diff options
Diffstat (limited to 'include/linux/mlx4')
| -rw-r--r-- | include/linux/mlx4/cmd.h | 26 | ||||
| -rw-r--r-- | include/linux/mlx4/device.h | 40 | ||||
| -rw-r--r-- | include/linux/mlx4/qp.h | 20 |
3 files changed, 73 insertions, 13 deletions
diff --git a/include/linux/mlx4/cmd.h b/include/linux/mlx4/cmd.h index 7b6d4e9ff603..f62e7cf227c6 100644 --- a/include/linux/mlx4/cmd.h +++ b/include/linux/mlx4/cmd.h | |||
| @@ -68,6 +68,8 @@ enum { | |||
| 68 | MLX4_CMD_UNMAP_ICM_AUX = 0xffb, | 68 | MLX4_CMD_UNMAP_ICM_AUX = 0xffb, |
| 69 | MLX4_CMD_SET_ICM_SIZE = 0xffd, | 69 | MLX4_CMD_SET_ICM_SIZE = 0xffd, |
| 70 | MLX4_CMD_ACCESS_REG = 0x3b, | 70 | MLX4_CMD_ACCESS_REG = 0x3b, |
| 71 | MLX4_CMD_ALLOCATE_VPP = 0x80, | ||
| 72 | MLX4_CMD_SET_VPORT_QOS = 0x81, | ||
| 71 | 73 | ||
| 72 | /*master notify fw on finish for slave's flr*/ | 74 | /*master notify fw on finish for slave's flr*/ |
| 73 | MLX4_CMD_INFORM_FLR_DONE = 0x5b, | 75 | MLX4_CMD_INFORM_FLR_DONE = 0x5b, |
| @@ -163,6 +165,9 @@ enum { | |||
| 163 | MLX4_QP_FLOW_STEERING_ATTACH = 0x65, | 165 | MLX4_QP_FLOW_STEERING_ATTACH = 0x65, |
| 164 | MLX4_QP_FLOW_STEERING_DETACH = 0x66, | 166 | MLX4_QP_FLOW_STEERING_DETACH = 0x66, |
| 165 | MLX4_FLOW_STEERING_IB_UC_QP_RANGE = 0x64, | 167 | MLX4_FLOW_STEERING_IB_UC_QP_RANGE = 0x64, |
| 168 | |||
| 169 | /* Update and read QCN parameters */ | ||
| 170 | MLX4_CMD_CONGESTION_CTRL_OPCODE = 0x68, | ||
| 166 | }; | 171 | }; |
| 167 | 172 | ||
| 168 | enum { | 173 | enum { |
| @@ -183,7 +188,14 @@ enum { | |||
| 183 | }; | 188 | }; |
| 184 | 189 | ||
| 185 | enum { | 190 | enum { |
| 186 | /* set port opcode modifiers */ | 191 | /* Set port opcode modifiers */ |
| 192 | MLX4_SET_PORT_IB_OPCODE = 0x0, | ||
| 193 | MLX4_SET_PORT_ETH_OPCODE = 0x1, | ||
| 194 | MLX4_SET_PORT_BEACON_OPCODE = 0x4, | ||
| 195 | }; | ||
| 196 | |||
| 197 | enum { | ||
| 198 | /* Set port Ethernet input modifiers */ | ||
| 187 | MLX4_SET_PORT_GENERAL = 0x0, | 199 | MLX4_SET_PORT_GENERAL = 0x0, |
| 188 | MLX4_SET_PORT_RQP_CALC = 0x1, | 200 | MLX4_SET_PORT_RQP_CALC = 0x1, |
| 189 | MLX4_SET_PORT_MAC_TABLE = 0x2, | 201 | MLX4_SET_PORT_MAC_TABLE = 0x2, |
| @@ -233,6 +245,16 @@ struct mlx4_config_dev_params { | |||
| 233 | u8 rx_csum_flags_port_2; | 245 | u8 rx_csum_flags_port_2; |
| 234 | }; | 246 | }; |
| 235 | 247 | ||
| 248 | enum mlx4_en_congestion_control_algorithm { | ||
| 249 | MLX4_CTRL_ALGO_802_1_QAU_REACTION_POINT = 0, | ||
| 250 | }; | ||
| 251 | |||
| 252 | enum mlx4_en_congestion_control_opmod { | ||
| 253 | MLX4_CONGESTION_CONTROL_GET_PARAMS, | ||
| 254 | MLX4_CONGESTION_CONTROL_GET_STATISTICS, | ||
| 255 | MLX4_CONGESTION_CONTROL_SET_PARAMS = 4, | ||
| 256 | }; | ||
| 257 | |||
| 236 | struct mlx4_dev; | 258 | struct mlx4_dev; |
| 237 | 259 | ||
| 238 | struct mlx4_cmd_mailbox { | 260 | struct mlx4_cmd_mailbox { |
| @@ -281,6 +303,8 @@ void mlx4_free_cmd_mailbox(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbo | |||
| 281 | u32 mlx4_comm_get_version(void); | 303 | u32 mlx4_comm_get_version(void); |
| 282 | int mlx4_set_vf_mac(struct mlx4_dev *dev, int port, int vf, u64 mac); | 304 | int mlx4_set_vf_mac(struct mlx4_dev *dev, int port, int vf, u64 mac); |
| 283 | int mlx4_set_vf_vlan(struct mlx4_dev *dev, int port, int vf, u16 vlan, u8 qos); | 305 | int mlx4_set_vf_vlan(struct mlx4_dev *dev, int port, int vf, u16 vlan, u8 qos); |
| 306 | int mlx4_set_vf_rate(struct mlx4_dev *dev, int port, int vf, int min_tx_rate, | ||
| 307 | int max_tx_rate); | ||
| 284 | int mlx4_set_vf_spoofchk(struct mlx4_dev *dev, int port, int vf, bool setting); | 308 | int mlx4_set_vf_spoofchk(struct mlx4_dev *dev, int port, int vf, bool setting); |
| 285 | int mlx4_get_vf_config(struct mlx4_dev *dev, int port, int vf, struct ifla_vf_info *ivf); | 309 | int mlx4_get_vf_config(struct mlx4_dev *dev, int port, int vf, struct ifla_vf_info *ivf); |
| 286 | int mlx4_set_vf_link_state(struct mlx4_dev *dev, int port, int vf, int link_state); | 310 | int mlx4_set_vf_link_state(struct mlx4_dev *dev, int port, int vf, int link_state); |
diff --git a/include/linux/mlx4/device.h b/include/linux/mlx4/device.h index e4ebff7e9d02..f9ce34bec45b 100644 --- a/include/linux/mlx4/device.h +++ b/include/linux/mlx4/device.h | |||
| @@ -49,8 +49,6 @@ | |||
| 49 | #define MSIX_LEGACY_SZ 4 | 49 | #define MSIX_LEGACY_SZ 4 |
| 50 | #define MIN_MSIX_P_PORT 5 | 50 | #define MIN_MSIX_P_PORT 5 |
| 51 | 51 | ||
| 52 | #define MLX4_NUM_UP 8 | ||
| 53 | #define MLX4_NUM_TC 8 | ||
| 54 | #define MLX4_MAX_100M_UNITS_VAL 255 /* | 52 | #define MLX4_MAX_100M_UNITS_VAL 255 /* |
| 55 | * work around: can't set values | 53 | * work around: can't set values |
| 56 | * greater then this value when | 54 | * greater then this value when |
| @@ -174,6 +172,7 @@ enum { | |||
| 174 | MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41, | 172 | MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41, |
| 175 | MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42, | 173 | MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42, |
| 176 | MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48, | 174 | MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48, |
| 175 | MLX4_DEV_CAP_FLAG_RSS_IP_FRAG = 1LL << 52, | ||
| 177 | MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53, | 176 | MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53, |
| 178 | MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55, | 177 | MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55, |
| 179 | MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59, | 178 | MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59, |
| @@ -203,7 +202,14 @@ enum { | |||
| 203 | MLX4_DEV_CAP_FLAG2_80_VFS = 1LL << 18, | 202 | MLX4_DEV_CAP_FLAG2_80_VFS = 1LL << 18, |
| 204 | MLX4_DEV_CAP_FLAG2_FS_A0 = 1LL << 19, | 203 | MLX4_DEV_CAP_FLAG2_FS_A0 = 1LL << 19, |
| 205 | MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT = 1LL << 20, | 204 | MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT = 1LL << 20, |
| 206 | MLX4_DEV_CAP_FLAG2_PORT_REMAP = 1LL << 21 | 205 | MLX4_DEV_CAP_FLAG2_PORT_REMAP = 1LL << 21, |
| 206 | MLX4_DEV_CAP_FLAG2_QCN = 1LL << 22, | ||
| 207 | MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT = 1LL << 23, | ||
| 208 | MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN = 1LL << 24, | ||
| 209 | MLX4_DEV_CAP_FLAG2_QOS_VPP = 1LL << 25, | ||
| 210 | MLX4_DEV_CAP_FLAG2_ETS_CFG = 1LL << 26, | ||
| 211 | MLX4_DEV_CAP_FLAG2_PORT_BEACON = 1LL << 27, | ||
| 212 | MLX4_DEV_CAP_FLAG2_IGNORE_FCS = 1LL << 28, | ||
| 207 | }; | 213 | }; |
| 208 | 214 | ||
| 209 | enum { | 215 | enum { |
| @@ -449,6 +455,21 @@ enum mlx4_module_id { | |||
| 449 | MLX4_MODULE_ID_QSFP28 = 0x11, | 455 | MLX4_MODULE_ID_QSFP28 = 0x11, |
| 450 | }; | 456 | }; |
| 451 | 457 | ||
| 458 | enum { /* rl */ | ||
| 459 | MLX4_QP_RATE_LIMIT_NONE = 0, | ||
| 460 | MLX4_QP_RATE_LIMIT_KBS = 1, | ||
| 461 | MLX4_QP_RATE_LIMIT_MBS = 2, | ||
| 462 | MLX4_QP_RATE_LIMIT_GBS = 3 | ||
| 463 | }; | ||
| 464 | |||
| 465 | struct mlx4_rate_limit_caps { | ||
| 466 | u16 num_rates; /* Number of different rates */ | ||
| 467 | u8 min_unit; | ||
| 468 | u16 min_val; | ||
| 469 | u8 max_unit; | ||
| 470 | u16 max_val; | ||
| 471 | }; | ||
| 472 | |||
| 452 | static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor) | 473 | static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor) |
| 453 | { | 474 | { |
| 454 | return (major << 32) | (minor << 16) | subminor; | 475 | return (major << 32) | (minor << 16) | subminor; |
| @@ -564,6 +585,7 @@ struct mlx4_caps { | |||
| 564 | u32 dmfs_high_rate_qpn_base; | 585 | u32 dmfs_high_rate_qpn_base; |
| 565 | u32 dmfs_high_rate_qpn_range; | 586 | u32 dmfs_high_rate_qpn_range; |
| 566 | u32 vf_caps; | 587 | u32 vf_caps; |
| 588 | struct mlx4_rate_limit_caps rl_caps; | ||
| 567 | }; | 589 | }; |
| 568 | 590 | ||
| 569 | struct mlx4_buf_list { | 591 | struct mlx4_buf_list { |
| @@ -982,6 +1004,11 @@ static inline int mlx4_is_slave(struct mlx4_dev *dev) | |||
| 982 | return dev->flags & MLX4_FLAG_SLAVE; | 1004 | return dev->flags & MLX4_FLAG_SLAVE; |
| 983 | } | 1005 | } |
| 984 | 1006 | ||
| 1007 | static inline int mlx4_is_eth(struct mlx4_dev *dev, int port) | ||
| 1008 | { | ||
| 1009 | return dev->caps.port_type[port] == MLX4_PORT_TYPE_IB ? 0 : 1; | ||
| 1010 | } | ||
| 1011 | |||
| 985 | int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct, | 1012 | int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct, |
| 986 | struct mlx4_buf *buf, gfp_t gfp); | 1013 | struct mlx4_buf *buf, gfp_t gfp); |
| 987 | void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf); | 1014 | void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf); |
| @@ -1282,14 +1309,13 @@ int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac); | |||
| 1282 | void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac); | 1309 | void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac); |
| 1283 | int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port); | 1310 | int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port); |
| 1284 | int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac); | 1311 | int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac); |
| 1285 | void mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap); | ||
| 1286 | int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu, | 1312 | int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu, |
| 1287 | u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx); | 1313 | u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx); |
| 1288 | int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn, | 1314 | int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn, |
| 1289 | u8 promisc); | 1315 | u8 promisc); |
| 1290 | int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc); | 1316 | int mlx4_SET_PORT_BEACON(struct mlx4_dev *dev, u8 port, u16 time); |
| 1291 | int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw, | 1317 | int mlx4_SET_PORT_fcs_check(struct mlx4_dev *dev, u8 port, |
| 1292 | u8 *pg, u16 *ratelimit); | 1318 | u8 ignore_fcs_value); |
| 1293 | int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering, int enable); | 1319 | int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering, int enable); |
| 1294 | int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx); | 1320 | int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx); |
| 1295 | int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx); | 1321 | int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx); |
diff --git a/include/linux/mlx4/qp.h b/include/linux/mlx4/qp.h index 2bbc62aa818a..6fed539e5456 100644 --- a/include/linux/mlx4/qp.h +++ b/include/linux/mlx4/qp.h | |||
| @@ -207,14 +207,17 @@ struct mlx4_qp_context { | |||
| 207 | __be32 msn; | 207 | __be32 msn; |
| 208 | __be16 rq_wqe_counter; | 208 | __be16 rq_wqe_counter; |
| 209 | __be16 sq_wqe_counter; | 209 | __be16 sq_wqe_counter; |
| 210 | u32 reserved3[2]; | 210 | u32 reserved3; |
| 211 | __be16 rate_limit_params; | ||
| 212 | u8 reserved4; | ||
| 213 | u8 qos_vport; | ||
| 211 | __be32 param3; | 214 | __be32 param3; |
| 212 | __be32 nummmcpeers_basemkey; | 215 | __be32 nummmcpeers_basemkey; |
| 213 | u8 log_page_size; | 216 | u8 log_page_size; |
| 214 | u8 reserved4[2]; | 217 | u8 reserved5[2]; |
| 215 | u8 mtt_base_addr_h; | 218 | u8 mtt_base_addr_h; |
| 216 | __be32 mtt_base_addr_l; | 219 | __be32 mtt_base_addr_l; |
| 217 | u32 reserved5[10]; | 220 | u32 reserved6[10]; |
| 218 | }; | 221 | }; |
| 219 | 222 | ||
| 220 | struct mlx4_update_qp_context { | 223 | struct mlx4_update_qp_context { |
| @@ -229,6 +232,8 @@ struct mlx4_update_qp_context { | |||
| 229 | enum { | 232 | enum { |
| 230 | MLX4_UPD_QP_MASK_PM_STATE = 32, | 233 | MLX4_UPD_QP_MASK_PM_STATE = 32, |
| 231 | MLX4_UPD_QP_MASK_VSD = 33, | 234 | MLX4_UPD_QP_MASK_VSD = 33, |
| 235 | MLX4_UPD_QP_MASK_QOS_VPP = 34, | ||
| 236 | MLX4_UPD_QP_MASK_RATE_LIMIT = 35, | ||
| 232 | }; | 237 | }; |
| 233 | 238 | ||
| 234 | enum { | 239 | enum { |
| @@ -427,8 +432,10 @@ struct mlx4_wqe_inline_seg { | |||
| 427 | 432 | ||
| 428 | enum mlx4_update_qp_attr { | 433 | enum mlx4_update_qp_attr { |
| 429 | MLX4_UPDATE_QP_SMAC = 1 << 0, | 434 | MLX4_UPDATE_QP_SMAC = 1 << 0, |
| 430 | MLX4_UPDATE_QP_VSD = 1 << 2, | 435 | MLX4_UPDATE_QP_VSD = 1 << 1, |
| 431 | MLX4_UPDATE_QP_SUPPORTED_ATTRS = (1 << 2) - 1 | 436 | MLX4_UPDATE_QP_RATE_LIMIT = 1 << 2, |
| 437 | MLX4_UPDATE_QP_QOS_VPORT = 1 << 3, | ||
| 438 | MLX4_UPDATE_QP_SUPPORTED_ATTRS = (1 << 4) - 1 | ||
| 432 | }; | 439 | }; |
| 433 | 440 | ||
| 434 | enum mlx4_update_qp_params_flags { | 441 | enum mlx4_update_qp_params_flags { |
| @@ -437,7 +444,10 @@ enum mlx4_update_qp_params_flags { | |||
| 437 | 444 | ||
| 438 | struct mlx4_update_qp_params { | 445 | struct mlx4_update_qp_params { |
| 439 | u8 smac_index; | 446 | u8 smac_index; |
| 447 | u8 qos_vport; | ||
| 440 | u32 flags; | 448 | u32 flags; |
| 449 | u16 rate_unit; | ||
| 450 | u16 rate_val; | ||
| 441 | }; | 451 | }; |
| 442 | 452 | ||
| 443 | int mlx4_update_qp(struct mlx4_dev *dev, u32 qpn, | 453 | int mlx4_update_qp(struct mlx4_dev *dev, u32 qpn, |
