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-rw-r--r--include/linux/mfd/abx500.h5
-rw-r--r--include/linux/mfd/abx500/ab5500.h140
-rw-r--r--include/linux/mfd/abx500/ab8500.h18
-rw-r--r--include/linux/mfd/anatop.h4
-rw-r--r--include/linux/mfd/asic3.h3
-rw-r--r--include/linux/mfd/da9052/da9052.h20
-rw-r--r--include/linux/mfd/db5500-prcmu.h105
-rw-r--r--include/linux/mfd/dbx500-prcmu.h242
-rw-r--r--include/linux/mfd/lm3533.h104
-rw-r--r--include/linux/mfd/lpc_ich.h48
-rw-r--r--include/linux/mfd/max77693-private.h227
-rw-r--r--include/linux/mfd/max77693.h36
-rw-r--r--include/linux/mfd/max8997.h23
-rw-r--r--include/linux/mfd/mc13xxx.h11
-rw-r--r--include/linux/mfd/palmas.h2620
-rw-r--r--include/linux/mfd/rc5t583.h31
-rw-r--r--include/linux/mfd/s5m87xx/s5m-core.h1
-rw-r--r--include/linux/mfd/s5m87xx/s5m-pmic.h29
-rw-r--r--include/linux/mfd/sta2x11-mfd.h324
-rw-r--r--include/linux/mfd/stmpe.h2
-rw-r--r--include/linux/mfd/tps65090.h13
-rw-r--r--include/linux/mfd/tps6586x.h1
-rw-r--r--include/linux/mfd/tps65910.h49
-rw-r--r--include/linux/mfd/twl6040.h2
-rw-r--r--include/linux/mfd/wm831x/core.h12
-rw-r--r--include/linux/mfd/wm831x/pdata.h2
-rw-r--r--include/linux/mfd/wm8350/core.h9
-rw-r--r--include/linux/mfd/wm8400-private.h14
-rw-r--r--include/linux/mfd/wm8994/core.h13
-rw-r--r--include/linux/mfd/wm8994/registers.h3
30 files changed, 3604 insertions, 507 deletions
diff --git a/include/linux/mfd/abx500.h b/include/linux/mfd/abx500.h
index ee96cd51d8b2..1318ca622633 100644
--- a/include/linux/mfd/abx500.h
+++ b/include/linux/mfd/abx500.h
@@ -6,7 +6,7 @@
6 * 6 *
7 * ABX500 core access functions. 7 * ABX500 core access functions.
8 * The abx500 interface is used for the Analog Baseband chip 8 * The abx500 interface is used for the Analog Baseband chip
9 * ab3100, ab5500, and ab8500. 9 * ab3100 and ab8500.
10 * 10 *
11 * Author: Mattias Wallin <mattias.wallin@stericsson.com> 11 * Author: Mattias Wallin <mattias.wallin@stericsson.com>
12 * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com> 12 * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
@@ -30,9 +30,6 @@ struct device;
30#define AB3100_P1G 0xc6 30#define AB3100_P1G 0xc6
31#define AB3100_R2A 0xc7 31#define AB3100_R2A 0xc7
32#define AB3100_R2B 0xc8 32#define AB3100_R2B 0xc8
33#define AB5500_1_0 0x20
34#define AB5500_1_1 0x21
35#define AB5500_2_0 0x24
36 33
37/* 34/*
38 * AB3100, EVENTA1, A2 and A3 event register flags 35 * AB3100, EVENTA1, A2 and A3 event register flags
diff --git a/include/linux/mfd/abx500/ab5500.h b/include/linux/mfd/abx500/ab5500.h
deleted file mode 100644
index 54f820ed73bb..000000000000
--- a/include/linux/mfd/abx500/ab5500.h
+++ /dev/null
@@ -1,140 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson 2011
3 *
4 * License Terms: GNU General Public License v2
5 */
6#ifndef MFD_AB5500_H
7#define MFD_AB5500_H
8
9struct device;
10
11enum ab5500_devid {
12 AB5500_DEVID_ADC,
13 AB5500_DEVID_LEDS,
14 AB5500_DEVID_POWER,
15 AB5500_DEVID_REGULATORS,
16 AB5500_DEVID_SIM,
17 AB5500_DEVID_RTC,
18 AB5500_DEVID_CHARGER,
19 AB5500_DEVID_FUELGAUGE,
20 AB5500_DEVID_VIBRATOR,
21 AB5500_DEVID_CODEC,
22 AB5500_DEVID_USB,
23 AB5500_DEVID_OTP,
24 AB5500_DEVID_VIDEO,
25 AB5500_DEVID_DBIECI,
26 AB5500_DEVID_ONSWA,
27 AB5500_NUM_DEVICES,
28};
29
30enum ab5500_banks {
31 AB5500_BANK_VIT_IO_I2C_CLK_TST_OTP = 0,
32 AB5500_BANK_VDDDIG_IO_I2C_CLK_TST = 1,
33 AB5500_BANK_VDENC = 2,
34 AB5500_BANK_SIM_USBSIM = 3,
35 AB5500_BANK_LED = 4,
36 AB5500_BANK_ADC = 5,
37 AB5500_BANK_RTC = 6,
38 AB5500_BANK_STARTUP = 7,
39 AB5500_BANK_DBI_ECI = 8,
40 AB5500_BANK_CHG = 9,
41 AB5500_BANK_FG_BATTCOM_ACC = 10,
42 AB5500_BANK_USB = 11,
43 AB5500_BANK_IT = 12,
44 AB5500_BANK_VIBRA = 13,
45 AB5500_BANK_AUDIO_HEADSETUSB = 14,
46 AB5500_NUM_BANKS = 15,
47};
48
49enum ab5500_banks_addr {
50 AB5500_ADDR_VIT_IO_I2C_CLK_TST_OTP = 0x4A,
51 AB5500_ADDR_VDDDIG_IO_I2C_CLK_TST = 0x4B,
52 AB5500_ADDR_VDENC = 0x06,
53 AB5500_ADDR_SIM_USBSIM = 0x04,
54 AB5500_ADDR_LED = 0x10,
55 AB5500_ADDR_ADC = 0x0A,
56 AB5500_ADDR_RTC = 0x0F,
57 AB5500_ADDR_STARTUP = 0x03,
58 AB5500_ADDR_DBI_ECI = 0x07,
59 AB5500_ADDR_CHG = 0x0B,
60 AB5500_ADDR_FG_BATTCOM_ACC = 0x0C,
61 AB5500_ADDR_USB = 0x05,
62 AB5500_ADDR_IT = 0x0E,
63 AB5500_ADDR_VIBRA = 0x02,
64 AB5500_ADDR_AUDIO_HEADSETUSB = 0x0D,
65};
66
67/*
68 * Interrupt register offsets
69 * Bank : 0x0E
70 */
71#define AB5500_IT_SOURCE0_REG 0x20
72#define AB5500_IT_SOURCE1_REG 0x21
73#define AB5500_IT_SOURCE2_REG 0x22
74#define AB5500_IT_SOURCE3_REG 0x23
75#define AB5500_IT_SOURCE4_REG 0x24
76#define AB5500_IT_SOURCE5_REG 0x25
77#define AB5500_IT_SOURCE6_REG 0x26
78#define AB5500_IT_SOURCE7_REG 0x27
79#define AB5500_IT_SOURCE8_REG 0x28
80#define AB5500_IT_SOURCE9_REG 0x29
81#define AB5500_IT_SOURCE10_REG 0x2A
82#define AB5500_IT_SOURCE11_REG 0x2B
83#define AB5500_IT_SOURCE12_REG 0x2C
84#define AB5500_IT_SOURCE13_REG 0x2D
85#define AB5500_IT_SOURCE14_REG 0x2E
86#define AB5500_IT_SOURCE15_REG 0x2F
87#define AB5500_IT_SOURCE16_REG 0x30
88#define AB5500_IT_SOURCE17_REG 0x31
89#define AB5500_IT_SOURCE18_REG 0x32
90#define AB5500_IT_SOURCE19_REG 0x33
91#define AB5500_IT_SOURCE20_REG 0x34
92#define AB5500_IT_SOURCE21_REG 0x35
93#define AB5500_IT_SOURCE22_REG 0x36
94#define AB5500_IT_SOURCE23_REG 0x37
95
96#define AB5500_NUM_IRQ_REGS 23
97
98/**
99 * struct ab5500
100 * @access_mutex: lock out concurrent accesses to the AB registers
101 * @dev: a pointer to the device struct for this chip driver
102 * @ab5500_irq: the analog baseband irq
103 * @irq_base: the platform configuration irq base for subdevices
104 * @chip_name: name of this chip variant
105 * @chip_id: 8 bit chip ID for this chip variant
106 * @irq_lock: a lock to protect the mask
107 * @abb_events: a local bit mask of the prcmu wakeup events
108 * @event_mask: a local copy of the mask event registers
109 * @last_event_mask: a copy of the last event_mask written to hardware
110 * @startup_events: a copy of the first reading of the event registers
111 * @startup_events_read: whether the first events have been read
112 */
113struct ab5500 {
114 struct mutex access_mutex;
115 struct device *dev;
116 unsigned int ab5500_irq;
117 unsigned int irq_base;
118 char chip_name[32];
119 u8 chip_id;
120 struct mutex irq_lock;
121 u32 abb_events;
122 u8 mask[AB5500_NUM_IRQ_REGS];
123 u8 oldmask[AB5500_NUM_IRQ_REGS];
124 u8 startup_events[AB5500_NUM_IRQ_REGS];
125 bool startup_events_read;
126#ifdef CONFIG_DEBUG_FS
127 unsigned int debug_bank;
128 unsigned int debug_address;
129#endif
130};
131
132struct ab5500_platform_data {
133 struct {unsigned int base; unsigned int count; } irq;
134 void *dev_data[AB5500_NUM_DEVICES];
135 struct abx500_init_settings *init_settings;
136 unsigned int init_settings_sz;
137 bool pm_power_off;
138};
139
140#endif /* MFD_AB5500_H */
diff --git a/include/linux/mfd/abx500/ab8500.h b/include/linux/mfd/abx500/ab8500.h
index fccc3002f271..91dd3ef63e99 100644
--- a/include/linux/mfd/abx500/ab8500.h
+++ b/include/linux/mfd/abx500/ab8500.h
@@ -7,6 +7,7 @@
7#ifndef MFD_AB8500_H 7#ifndef MFD_AB8500_H
8#define MFD_AB8500_H 8#define MFD_AB8500_H
9 9
10#include <linux/atomic.h>
10#include <linux/mutex.h> 11#include <linux/mutex.h>
11 12
12struct device; 13struct device;
@@ -194,6 +195,14 @@ enum ab8500_version {
194#define AB9540_INT_GPIO52F 123 195#define AB9540_INT_GPIO52F 123
195#define AB9540_INT_GPIO53F 124 196#define AB9540_INT_GPIO53F 124
196#define AB9540_INT_GPIO54F 125 /* not 8505 */ 197#define AB9540_INT_GPIO54F 125 /* not 8505 */
198/* ab8500_irq_regoffset[16] -> IT[Source|Latch|Mask]25 */
199#define AB8505_INT_KEYSTUCK 128
200#define AB8505_INT_IKR 129
201#define AB8505_INT_IKP 130
202#define AB8505_INT_KP 131
203#define AB8505_INT_KEYDEGLITCH 132
204#define AB8505_INT_MODPWRSTATUSF 134
205#define AB8505_INT_MODPWRSTATUSR 135
197 206
198/* 207/*
199 * AB8500_AB9540_NR_IRQS is used when configuring the IRQ numbers for the 208 * AB8500_AB9540_NR_IRQS is used when configuring the IRQ numbers for the
@@ -203,8 +212,8 @@ enum ab8500_version {
203 * which is larger. 212 * which is larger.
204 */ 213 */
205#define AB8500_NR_IRQS 112 214#define AB8500_NR_IRQS 112
206#define AB8505_NR_IRQS 128 215#define AB8505_NR_IRQS 136
207#define AB9540_NR_IRQS 128 216#define AB9540_NR_IRQS 136
208/* This is set to the roof of any AB8500 chip variant IRQ counts */ 217/* This is set to the roof of any AB8500 chip variant IRQ counts */
209#define AB8500_MAX_NR_IRQS AB9540_NR_IRQS 218#define AB8500_MAX_NR_IRQS AB9540_NR_IRQS
210 219
@@ -216,6 +225,7 @@ enum ab8500_version {
216 * @dev: parent device 225 * @dev: parent device
217 * @lock: read/write operations lock 226 * @lock: read/write operations lock
218 * @irq_lock: genirq bus lock 227 * @irq_lock: genirq bus lock
228 * @transfer_ongoing: 0 if no transfer ongoing
219 * @irq: irq line 229 * @irq: irq line
220 * @version: chip version id (e.g. ab8500 or ab9540) 230 * @version: chip version id (e.g. ab8500 or ab9540)
221 * @chip_id: chip revision id 231 * @chip_id: chip revision id
@@ -234,7 +244,7 @@ struct ab8500 {
234 struct device *dev; 244 struct device *dev;
235 struct mutex lock; 245 struct mutex lock;
236 struct mutex irq_lock; 246 struct mutex irq_lock;
237 247 atomic_t transfer_ongoing;
238 int irq_base; 248 int irq_base;
239 int irq; 249 int irq;
240 enum ab8500_version version; 250 enum ab8500_version version;
@@ -280,6 +290,8 @@ extern int __devinit ab8500_init(struct ab8500 *ab8500,
280 enum ab8500_version version); 290 enum ab8500_version version);
281extern int __devexit ab8500_exit(struct ab8500 *ab8500); 291extern int __devexit ab8500_exit(struct ab8500 *ab8500);
282 292
293extern int ab8500_suspend(struct ab8500 *ab8500);
294
283static inline int is_ab8500(struct ab8500 *ab) 295static inline int is_ab8500(struct ab8500 *ab)
284{ 296{
285 return ab->version == AB8500_VERSION_AB8500; 297 return ab->version == AB8500_VERSION_AB8500;
diff --git a/include/linux/mfd/anatop.h b/include/linux/mfd/anatop.h
index 22c1007d3ec5..7f92acf03d9e 100644
--- a/include/linux/mfd/anatop.h
+++ b/include/linux/mfd/anatop.h
@@ -34,7 +34,7 @@ struct anatop {
34 spinlock_t reglock; 34 spinlock_t reglock;
35}; 35};
36 36
37extern u32 anatop_get_bits(struct anatop *, u32, int, int); 37extern u32 anatop_read_reg(struct anatop *, u32);
38extern void anatop_set_bits(struct anatop *, u32, int, int, u32); 38extern void anatop_write_reg(struct anatop *, u32, u32, u32);
39 39
40#endif /* __LINUX_MFD_ANATOP_H */ 40#endif /* __LINUX_MFD_ANATOP_H */
diff --git a/include/linux/mfd/asic3.h b/include/linux/mfd/asic3.h
index ed793b77a1c5..e1148d037e7b 100644
--- a/include/linux/mfd/asic3.h
+++ b/include/linux/mfd/asic3.h
@@ -31,6 +31,8 @@ struct asic3_platform_data {
31 31
32 unsigned int gpio_base; 32 unsigned int gpio_base;
33 33
34 unsigned int clock_rate;
35
34 struct asic3_led *leds; 36 struct asic3_led *leds;
35}; 37};
36 38
@@ -138,6 +140,7 @@ struct asic3_platform_data {
138#define ASIC3_GPIOC13_nPWAIT ASIC3_CONFIG_GPIO(45, 1, 1, 0) 140#define ASIC3_GPIOC13_nPWAIT ASIC3_CONFIG_GPIO(45, 1, 1, 0)
139#define ASIC3_GPIOC14_nPIOIS16 ASIC3_CONFIG_GPIO(46, 1, 1, 0) 141#define ASIC3_GPIOC14_nPIOIS16 ASIC3_CONFIG_GPIO(46, 1, 1, 0)
140#define ASIC3_GPIOC15_nPIOR ASIC3_CONFIG_GPIO(47, 1, 0, 0) 142#define ASIC3_GPIOC15_nPIOR ASIC3_CONFIG_GPIO(47, 1, 0, 0)
143#define ASIC3_GPIOD4_CF_nCD ASIC3_CONFIG_GPIO(52, 1, 0, 0)
141#define ASIC3_GPIOD11_nCIOIS16 ASIC3_CONFIG_GPIO(59, 1, 0, 0) 144#define ASIC3_GPIOD11_nCIOIS16 ASIC3_CONFIG_GPIO(59, 1, 0, 0)
142#define ASIC3_GPIOD12_nCWAIT ASIC3_CONFIG_GPIO(60, 1, 0, 0) 145#define ASIC3_GPIOD12_nCWAIT ASIC3_CONFIG_GPIO(60, 1, 0, 0)
143#define ASIC3_GPIOD15_nPIOW ASIC3_CONFIG_GPIO(63, 1, 0, 0) 146#define ASIC3_GPIOD15_nPIOW ASIC3_CONFIG_GPIO(63, 1, 0, 0)
diff --git a/include/linux/mfd/da9052/da9052.h b/include/linux/mfd/da9052/da9052.h
index 7ffbd6e9e7fc..0507c4c21a7d 100644
--- a/include/linux/mfd/da9052/da9052.h
+++ b/include/linux/mfd/da9052/da9052.h
@@ -33,6 +33,18 @@
33 33
34#include <linux/mfd/da9052/reg.h> 34#include <linux/mfd/da9052/reg.h>
35 35
36/* Common - HWMON Channel Definations */
37#define DA9052_ADC_VDDOUT 0
38#define DA9052_ADC_ICH 1
39#define DA9052_ADC_TBAT 2
40#define DA9052_ADC_VBAT 3
41#define DA9052_ADC_IN4 4
42#define DA9052_ADC_IN5 5
43#define DA9052_ADC_IN6 6
44#define DA9052_ADC_TSI 7
45#define DA9052_ADC_TJUNC 8
46#define DA9052_ADC_VBBAT 9
47
36#define DA9052_IRQ_DCIN 0 48#define DA9052_IRQ_DCIN 0
37#define DA9052_IRQ_VBUS 1 49#define DA9052_IRQ_VBUS 1
38#define DA9052_IRQ_DCINREM 2 50#define DA9052_IRQ_DCINREM 2
@@ -79,12 +91,20 @@ struct da9052 {
79 struct device *dev; 91 struct device *dev;
80 struct regmap *regmap; 92 struct regmap *regmap;
81 93
94 struct mutex auxadc_lock;
95 struct completion done;
96
82 int irq_base; 97 int irq_base;
98 struct regmap_irq_chip_data *irq_data;
83 u8 chip_id; 99 u8 chip_id;
84 100
85 int chip_irq; 101 int chip_irq;
86}; 102};
87 103
104/* ADC API */
105int da9052_adc_manual_read(struct da9052 *da9052, unsigned char channel);
106int da9052_adc_read_temp(struct da9052 *da9052);
107
88/* Device I/O API */ 108/* Device I/O API */
89static inline int da9052_reg_read(struct da9052 *da9052, unsigned char reg) 109static inline int da9052_reg_read(struct da9052 *da9052, unsigned char reg)
90{ 110{
diff --git a/include/linux/mfd/db5500-prcmu.h b/include/linux/mfd/db5500-prcmu.h
deleted file mode 100644
index 5a049dfaf153..000000000000
--- a/include/linux/mfd/db5500-prcmu.h
+++ /dev/null
@@ -1,105 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License v2
5 *
6 * U5500 PRCMU API.
7 */
8#ifndef __MFD_DB5500_PRCMU_H
9#define __MFD_DB5500_PRCMU_H
10
11static inline int prcmu_resetout(u8 resoutn, u8 state)
12{
13 return 0;
14}
15
16static inline int db5500_prcmu_set_epod(u16 epod_id, u8 epod_state)
17{
18 return 0;
19}
20
21static inline int db5500_prcmu_request_clock(u8 clock, bool enable)
22{
23 return 0;
24}
25
26static inline int db5500_prcmu_set_power_state(u8 state, bool keep_ulp_clk,
27 bool keep_ap_pll)
28{
29 return 0;
30}
31
32static inline int db5500_prcmu_config_esram0_deep_sleep(u8 state)
33{
34 return 0;
35}
36
37static inline u16 db5500_prcmu_get_reset_code(void)
38{
39 return 0;
40}
41
42static inline bool db5500_prcmu_is_ac_wake_requested(void)
43{
44 return 0;
45}
46
47static inline int db5500_prcmu_set_arm_opp(u8 opp)
48{
49 return 0;
50}
51
52static inline int db5500_prcmu_get_arm_opp(void)
53{
54 return 0;
55}
56
57static inline void db5500_prcmu_config_abb_event_readout(u32 abb_events) {}
58
59static inline void db5500_prcmu_get_abb_event_buffer(void __iomem **buf) {}
60
61static inline void db5500_prcmu_system_reset(u16 reset_code) {}
62
63static inline void db5500_prcmu_enable_wakeups(u32 wakeups) {}
64
65#ifdef CONFIG_MFD_DB5500_PRCMU
66
67void db5500_prcmu_early_init(void);
68int db5500_prcmu_set_display_clocks(void);
69int db5500_prcmu_disable_dsipll(void);
70int db5500_prcmu_enable_dsipll(void);
71int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
72int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
73
74#else /* !CONFIG_UX500_SOC_DB5500 */
75
76static inline void db5500_prcmu_early_init(void) {}
77
78static inline int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
79{
80 return -ENOSYS;
81}
82
83static inline int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
84{
85 return -ENOSYS;
86}
87
88static inline int db5500_prcmu_set_display_clocks(void)
89{
90 return 0;
91}
92
93static inline int db5500_prcmu_disable_dsipll(void)
94{
95 return 0;
96}
97
98static inline int db5500_prcmu_enable_dsipll(void)
99{
100 return 0;
101}
102
103#endif /* CONFIG_MFD_DB5500_PRCMU */
104
105#endif /* __MFD_DB5500_PRCMU_H */
diff --git a/include/linux/mfd/dbx500-prcmu.h b/include/linux/mfd/dbx500-prcmu.h
index d7674eb7305f..5a13f93d8f1c 100644
--- a/include/linux/mfd/dbx500-prcmu.h
+++ b/include/linux/mfd/dbx500-prcmu.h
@@ -55,17 +55,6 @@ enum prcmu_wakeup_index {
55#define NUM_EPOD_ID 8 55#define NUM_EPOD_ID 8
56 56
57/* 57/*
58 * DB5500 EPODs
59 */
60#define DB5500_EPOD_ID_BASE 0x0100
61#define DB5500_EPOD_ID_SGA (DB5500_EPOD_ID_BASE + 0)
62#define DB5500_EPOD_ID_HVA (DB5500_EPOD_ID_BASE + 1)
63#define DB5500_EPOD_ID_SIA (DB5500_EPOD_ID_BASE + 2)
64#define DB5500_EPOD_ID_DISP (DB5500_EPOD_ID_BASE + 3)
65#define DB5500_EPOD_ID_ESRAM12 (DB5500_EPOD_ID_BASE + 6)
66#define DB5500_NUM_EPOD_ID 7
67
68/*
69 * state definition for EPOD (power domain) 58 * state definition for EPOD (power domain)
70 * - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged 59 * - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged
71 * - EPOD_STATE_OFF: The EPOD is switched off 60 * - EPOD_STATE_OFF: The EPOD is switched off
@@ -80,29 +69,6 @@ enum prcmu_wakeup_index {
80#define EPOD_STATE_ON_CLK_OFF 0x03 69#define EPOD_STATE_ON_CLK_OFF 0x03
81#define EPOD_STATE_ON 0x04 70#define EPOD_STATE_ON 0x04
82 71
83/* DB5500 CLKOUT IDs */
84enum {
85 DB5500_CLKOUT0 = 0,
86 DB5500_CLKOUT1,
87};
88
89/* DB5500 CLKOUTx sources */
90enum {
91 DB5500_CLKOUT_REF_CLK_SEL0,
92 DB5500_CLKOUT_RTC_CLK0_SEL0,
93 DB5500_CLKOUT_ULP_CLK_SEL0,
94 DB5500_CLKOUT_STATIC0,
95 DB5500_CLKOUT_REFCLK,
96 DB5500_CLKOUT_ULPCLK,
97 DB5500_CLKOUT_ARMCLK,
98 DB5500_CLKOUT_SYSACC0CLK,
99 DB5500_CLKOUT_SOC0PLLCLK,
100 DB5500_CLKOUT_SOC1PLLCLK,
101 DB5500_CLKOUT_DDRPLLCLK,
102 DB5500_CLKOUT_TVCLK,
103 DB5500_CLKOUT_IRDACLK,
104};
105
106/* 72/*
107 * CLKOUT sources 73 * CLKOUT sources
108 */ 74 */
@@ -248,101 +214,66 @@ enum ddr_pwrst {
248}; 214};
249 215
250#include <linux/mfd/db8500-prcmu.h> 216#include <linux/mfd/db8500-prcmu.h>
251#include <linux/mfd/db5500-prcmu.h>
252 217
253#if defined(CONFIG_UX500_SOC_DB8500) || defined(CONFIG_UX500_SOC_DB5500) 218#if defined(CONFIG_UX500_SOC_DB8500)
254 219
255#include <mach/id.h> 220#include <mach/id.h>
256 221
257static inline void __init prcmu_early_init(void) 222static inline void __init prcmu_early_init(void)
258{ 223{
259 if (cpu_is_u5500()) 224 return db8500_prcmu_early_init();
260 return db5500_prcmu_early_init();
261 else
262 return db8500_prcmu_early_init();
263} 225}
264 226
265static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk, 227static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
266 bool keep_ap_pll) 228 bool keep_ap_pll)
267{ 229{
268 if (cpu_is_u5500()) 230 return db8500_prcmu_set_power_state(state, keep_ulp_clk,
269 return db5500_prcmu_set_power_state(state, keep_ulp_clk, 231 keep_ap_pll);
270 keep_ap_pll);
271 else
272 return db8500_prcmu_set_power_state(state, keep_ulp_clk,
273 keep_ap_pll);
274} 232}
275 233
276static inline u8 prcmu_get_power_state_result(void) 234static inline u8 prcmu_get_power_state_result(void)
277{ 235{
278 if (cpu_is_u5500()) 236 return db8500_prcmu_get_power_state_result();
279 return -EINVAL;
280 else
281 return db8500_prcmu_get_power_state_result();
282} 237}
283 238
284static inline int prcmu_gic_decouple(void) 239static inline int prcmu_gic_decouple(void)
285{ 240{
286 if (cpu_is_u5500()) 241 return db8500_prcmu_gic_decouple();
287 return -EINVAL;
288 else
289 return db8500_prcmu_gic_decouple();
290} 242}
291 243
292static inline int prcmu_gic_recouple(void) 244static inline int prcmu_gic_recouple(void)
293{ 245{
294 if (cpu_is_u5500()) 246 return db8500_prcmu_gic_recouple();
295 return -EINVAL;
296 else
297 return db8500_prcmu_gic_recouple();
298} 247}
299 248
300static inline bool prcmu_gic_pending_irq(void) 249static inline bool prcmu_gic_pending_irq(void)
301{ 250{
302 if (cpu_is_u5500()) 251 return db8500_prcmu_gic_pending_irq();
303 return -EINVAL;
304 else
305 return db8500_prcmu_gic_pending_irq();
306} 252}
307 253
308static inline bool prcmu_is_cpu_in_wfi(int cpu) 254static inline bool prcmu_is_cpu_in_wfi(int cpu)
309{ 255{
310 if (cpu_is_u5500()) 256 return db8500_prcmu_is_cpu_in_wfi(cpu);
311 return -EINVAL;
312 else
313 return db8500_prcmu_is_cpu_in_wfi(cpu);
314} 257}
315 258
316static inline int prcmu_copy_gic_settings(void) 259static inline int prcmu_copy_gic_settings(void)
317{ 260{
318 if (cpu_is_u5500()) 261 return db8500_prcmu_copy_gic_settings();
319 return -EINVAL;
320 else
321 return db8500_prcmu_copy_gic_settings();
322} 262}
323 263
324static inline bool prcmu_pending_irq(void) 264static inline bool prcmu_pending_irq(void)
325{ 265{
326 if (cpu_is_u5500()) 266 return db8500_prcmu_pending_irq();
327 return -EINVAL;
328 else
329 return db8500_prcmu_pending_irq();
330} 267}
331 268
332static inline int prcmu_set_epod(u16 epod_id, u8 epod_state) 269static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
333{ 270{
334 if (cpu_is_u5500()) 271 return db8500_prcmu_set_epod(epod_id, epod_state);
335 return -EINVAL;
336 else
337 return db8500_prcmu_set_epod(epod_id, epod_state);
338} 272}
339 273
340static inline void prcmu_enable_wakeups(u32 wakeups) 274static inline void prcmu_enable_wakeups(u32 wakeups)
341{ 275{
342 if (cpu_is_u5500()) 276 db8500_prcmu_enable_wakeups(wakeups);
343 db5500_prcmu_enable_wakeups(wakeups);
344 else
345 db8500_prcmu_enable_wakeups(wakeups);
346} 277}
347 278
348static inline void prcmu_disable_wakeups(void) 279static inline void prcmu_disable_wakeups(void)
@@ -352,18 +283,12 @@ static inline void prcmu_disable_wakeups(void)
352 283
353static inline void prcmu_config_abb_event_readout(u32 abb_events) 284static inline void prcmu_config_abb_event_readout(u32 abb_events)
354{ 285{
355 if (cpu_is_u5500()) 286 db8500_prcmu_config_abb_event_readout(abb_events);
356 db5500_prcmu_config_abb_event_readout(abb_events);
357 else
358 db8500_prcmu_config_abb_event_readout(abb_events);
359} 287}
360 288
361static inline void prcmu_get_abb_event_buffer(void __iomem **buf) 289static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
362{ 290{
363 if (cpu_is_u5500()) 291 db8500_prcmu_get_abb_event_buffer(buf);
364 db5500_prcmu_get_abb_event_buffer(buf);
365 else
366 db8500_prcmu_get_abb_event_buffer(buf);
367} 292}
368 293
369int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size); 294int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
@@ -374,10 +299,7 @@ int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
374 299
375static inline int prcmu_request_clock(u8 clock, bool enable) 300static inline int prcmu_request_clock(u8 clock, bool enable)
376{ 301{
377 if (cpu_is_u5500()) 302 return db8500_prcmu_request_clock(clock, enable);
378 return db5500_prcmu_request_clock(clock, enable);
379 else
380 return db8500_prcmu_request_clock(clock, enable);
381} 303}
382 304
383unsigned long prcmu_clock_rate(u8 clock); 305unsigned long prcmu_clock_rate(u8 clock);
@@ -386,211 +308,133 @@ int prcmu_set_clock_rate(u8 clock, unsigned long rate);
386 308
387static inline int prcmu_set_ddr_opp(u8 opp) 309static inline int prcmu_set_ddr_opp(u8 opp)
388{ 310{
389 if (cpu_is_u5500()) 311 return db8500_prcmu_set_ddr_opp(opp);
390 return -EINVAL;
391 else
392 return db8500_prcmu_set_ddr_opp(opp);
393} 312}
394static inline int prcmu_get_ddr_opp(void) 313static inline int prcmu_get_ddr_opp(void)
395{ 314{
396 if (cpu_is_u5500()) 315 return db8500_prcmu_get_ddr_opp();
397 return -EINVAL;
398 else
399 return db8500_prcmu_get_ddr_opp();
400} 316}
401 317
402static inline int prcmu_set_arm_opp(u8 opp) 318static inline int prcmu_set_arm_opp(u8 opp)
403{ 319{
404 if (cpu_is_u5500()) 320 return db8500_prcmu_set_arm_opp(opp);
405 return -EINVAL;
406 else
407 return db8500_prcmu_set_arm_opp(opp);
408} 321}
409 322
410static inline int prcmu_get_arm_opp(void) 323static inline int prcmu_get_arm_opp(void)
411{ 324{
412 if (cpu_is_u5500()) 325 return db8500_prcmu_get_arm_opp();
413 return -EINVAL;
414 else
415 return db8500_prcmu_get_arm_opp();
416} 326}
417 327
418static inline int prcmu_set_ape_opp(u8 opp) 328static inline int prcmu_set_ape_opp(u8 opp)
419{ 329{
420 if (cpu_is_u5500()) 330 return db8500_prcmu_set_ape_opp(opp);
421 return -EINVAL;
422 else
423 return db8500_prcmu_set_ape_opp(opp);
424} 331}
425 332
426static inline int prcmu_get_ape_opp(void) 333static inline int prcmu_get_ape_opp(void)
427{ 334{
428 if (cpu_is_u5500()) 335 return db8500_prcmu_get_ape_opp();
429 return -EINVAL;
430 else
431 return db8500_prcmu_get_ape_opp();
432} 336}
433 337
434static inline void prcmu_system_reset(u16 reset_code) 338static inline void prcmu_system_reset(u16 reset_code)
435{ 339{
436 if (cpu_is_u5500()) 340 return db8500_prcmu_system_reset(reset_code);
437 return db5500_prcmu_system_reset(reset_code);
438 else
439 return db8500_prcmu_system_reset(reset_code);
440} 341}
441 342
442static inline u16 prcmu_get_reset_code(void) 343static inline u16 prcmu_get_reset_code(void)
443{ 344{
444 if (cpu_is_u5500()) 345 return db8500_prcmu_get_reset_code();
445 return db5500_prcmu_get_reset_code();
446 else
447 return db8500_prcmu_get_reset_code();
448} 346}
449 347
450void prcmu_ac_wake_req(void); 348void prcmu_ac_wake_req(void);
451void prcmu_ac_sleep_req(void); 349void prcmu_ac_sleep_req(void);
452static inline void prcmu_modem_reset(void) 350static inline void prcmu_modem_reset(void)
453{ 351{
454 if (cpu_is_u5500()) 352 return db8500_prcmu_modem_reset();
455 return;
456 else
457 return db8500_prcmu_modem_reset();
458} 353}
459 354
460static inline bool prcmu_is_ac_wake_requested(void) 355static inline bool prcmu_is_ac_wake_requested(void)
461{ 356{
462 if (cpu_is_u5500()) 357 return db8500_prcmu_is_ac_wake_requested();
463 return db5500_prcmu_is_ac_wake_requested();
464 else
465 return db8500_prcmu_is_ac_wake_requested();
466} 358}
467 359
468static inline int prcmu_set_display_clocks(void) 360static inline int prcmu_set_display_clocks(void)
469{ 361{
470 if (cpu_is_u5500()) 362 return db8500_prcmu_set_display_clocks();
471 return db5500_prcmu_set_display_clocks();
472 else
473 return db8500_prcmu_set_display_clocks();
474} 363}
475 364
476static inline int prcmu_disable_dsipll(void) 365static inline int prcmu_disable_dsipll(void)
477{ 366{
478 if (cpu_is_u5500()) 367 return db8500_prcmu_disable_dsipll();
479 return db5500_prcmu_disable_dsipll();
480 else
481 return db8500_prcmu_disable_dsipll();
482} 368}
483 369
484static inline int prcmu_enable_dsipll(void) 370static inline int prcmu_enable_dsipll(void)
485{ 371{
486 if (cpu_is_u5500()) 372 return db8500_prcmu_enable_dsipll();
487 return db5500_prcmu_enable_dsipll();
488 else
489 return db8500_prcmu_enable_dsipll();
490} 373}
491 374
492static inline int prcmu_config_esram0_deep_sleep(u8 state) 375static inline int prcmu_config_esram0_deep_sleep(u8 state)
493{ 376{
494 if (cpu_is_u5500()) 377 return db8500_prcmu_config_esram0_deep_sleep(state);
495 return -EINVAL;
496 else
497 return db8500_prcmu_config_esram0_deep_sleep(state);
498} 378}
499 379
500static inline int prcmu_config_hotdog(u8 threshold) 380static inline int prcmu_config_hotdog(u8 threshold)
501{ 381{
502 if (cpu_is_u5500()) 382 return db8500_prcmu_config_hotdog(threshold);
503 return -EINVAL;
504 else
505 return db8500_prcmu_config_hotdog(threshold);
506} 383}
507 384
508static inline int prcmu_config_hotmon(u8 low, u8 high) 385static inline int prcmu_config_hotmon(u8 low, u8 high)
509{ 386{
510 if (cpu_is_u5500()) 387 return db8500_prcmu_config_hotmon(low, high);
511 return -EINVAL;
512 else
513 return db8500_prcmu_config_hotmon(low, high);
514} 388}
515 389
516static inline int prcmu_start_temp_sense(u16 cycles32k) 390static inline int prcmu_start_temp_sense(u16 cycles32k)
517{ 391{
518 if (cpu_is_u5500()) 392 return db8500_prcmu_start_temp_sense(cycles32k);
519 return -EINVAL;
520 else
521 return db8500_prcmu_start_temp_sense(cycles32k);
522} 393}
523 394
524static inline int prcmu_stop_temp_sense(void) 395static inline int prcmu_stop_temp_sense(void)
525{ 396{
526 if (cpu_is_u5500()) 397 return db8500_prcmu_stop_temp_sense();
527 return -EINVAL;
528 else
529 return db8500_prcmu_stop_temp_sense();
530} 398}
531 399
532static inline u32 prcmu_read(unsigned int reg) 400static inline u32 prcmu_read(unsigned int reg)
533{ 401{
534 if (cpu_is_u5500()) 402 return db8500_prcmu_read(reg);
535 return -EINVAL;
536 else
537 return db8500_prcmu_read(reg);
538} 403}
539 404
540static inline void prcmu_write(unsigned int reg, u32 value) 405static inline void prcmu_write(unsigned int reg, u32 value)
541{ 406{
542 if (cpu_is_u5500()) 407 db8500_prcmu_write(reg, value);
543 return;
544 else
545 db8500_prcmu_write(reg, value);
546} 408}
547 409
548static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) 410static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
549{ 411{
550 if (cpu_is_u5500()) 412 db8500_prcmu_write_masked(reg, mask, value);
551 return;
552 else
553 db8500_prcmu_write_masked(reg, mask, value);
554} 413}
555 414
556static inline int prcmu_enable_a9wdog(u8 id) 415static inline int prcmu_enable_a9wdog(u8 id)
557{ 416{
558 if (cpu_is_u5500()) 417 return db8500_prcmu_enable_a9wdog(id);
559 return -EINVAL;
560 else
561 return db8500_prcmu_enable_a9wdog(id);
562} 418}
563 419
564static inline int prcmu_disable_a9wdog(u8 id) 420static inline int prcmu_disable_a9wdog(u8 id)
565{ 421{
566 if (cpu_is_u5500()) 422 return db8500_prcmu_disable_a9wdog(id);
567 return -EINVAL;
568 else
569 return db8500_prcmu_disable_a9wdog(id);
570} 423}
571 424
572static inline int prcmu_kick_a9wdog(u8 id) 425static inline int prcmu_kick_a9wdog(u8 id)
573{ 426{
574 if (cpu_is_u5500()) 427 return db8500_prcmu_kick_a9wdog(id);
575 return -EINVAL;
576 else
577 return db8500_prcmu_kick_a9wdog(id);
578} 428}
579 429
580static inline int prcmu_load_a9wdog(u8 id, u32 timeout) 430static inline int prcmu_load_a9wdog(u8 id, u32 timeout)
581{ 431{
582 if (cpu_is_u5500()) 432 return db8500_prcmu_load_a9wdog(id, timeout);
583 return -EINVAL;
584 else
585 return db8500_prcmu_load_a9wdog(id, timeout);
586} 433}
587 434
588static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off) 435static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
589{ 436{
590 if (cpu_is_u5500()) 437 return db8500_prcmu_config_a9wdog(num, sleep_auto_off);
591 return -EINVAL;
592 else
593 return db8500_prcmu_config_a9wdog(num, sleep_auto_off);
594} 438}
595#else 439#else
596 440
@@ -768,7 +612,7 @@ static inline void prcmu_clear(unsigned int reg, u32 bits)
768 prcmu_write_masked(reg, bits, 0); 612 prcmu_write_masked(reg, bits, 0);
769} 613}
770 614
771#if defined(CONFIG_UX500_SOC_DB8500) || defined(CONFIG_UX500_SOC_DB5500) 615#if defined(CONFIG_UX500_SOC_DB8500)
772 616
773/** 617/**
774 * prcmu_enable_spi2 - Enables pin muxing for SPI2 on OtherAlternateC1. 618 * prcmu_enable_spi2 - Enables pin muxing for SPI2 on OtherAlternateC1.
diff --git a/include/linux/mfd/lm3533.h b/include/linux/mfd/lm3533.h
new file mode 100644
index 000000000000..594bc591f256
--- /dev/null
+++ b/include/linux/mfd/lm3533.h
@@ -0,0 +1,104 @@
1/*
2 * lm3533.h -- LM3533 interface
3 *
4 * Copyright (C) 2011-2012 Texas Instruments
5 *
6 * Author: Johan Hovold <jhovold@gmail.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#ifndef __LINUX_MFD_LM3533_H
15#define __LINUX_MFD_LM3533_H
16
17#define LM3533_ATTR_RO(_name) \
18 DEVICE_ATTR(_name, S_IRUGO, show_##_name, NULL)
19#define LM3533_ATTR_RW(_name) \
20 DEVICE_ATTR(_name, S_IRUGO | S_IWUSR , show_##_name, store_##_name)
21
22struct device;
23struct regmap;
24
25struct lm3533 {
26 struct device *dev;
27
28 struct regmap *regmap;
29
30 int gpio_hwen;
31 int irq;
32
33 unsigned have_als:1;
34 unsigned have_backlights:1;
35 unsigned have_leds:1;
36};
37
38struct lm3533_ctrlbank {
39 struct lm3533 *lm3533;
40 struct device *dev;
41 int id;
42};
43
44struct lm3533_als_platform_data {
45 unsigned pwm_mode:1; /* PWM input mode (default analog) */
46 u8 r_select; /* 1 - 127 (ignored in PWM-mode) */
47};
48
49struct lm3533_bl_platform_data {
50 char *name;
51 u16 max_current; /* 5000 - 29800 uA (800 uA step) */
52 u8 default_brightness; /* 0 - 255 */
53 u8 pwm; /* 0 - 0x3f */
54};
55
56struct lm3533_led_platform_data {
57 char *name;
58 const char *default_trigger;
59 u16 max_current; /* 5000 - 29800 uA (800 uA step) */
60 u8 pwm; /* 0 - 0x3f */
61};
62
63enum lm3533_boost_freq {
64 LM3533_BOOST_FREQ_500KHZ,
65 LM3533_BOOST_FREQ_1000KHZ,
66};
67
68enum lm3533_boost_ovp {
69 LM3533_BOOST_OVP_16V,
70 LM3533_BOOST_OVP_24V,
71 LM3533_BOOST_OVP_32V,
72 LM3533_BOOST_OVP_40V,
73};
74
75struct lm3533_platform_data {
76 int gpio_hwen;
77
78 enum lm3533_boost_ovp boost_ovp;
79 enum lm3533_boost_freq boost_freq;
80
81 struct lm3533_als_platform_data *als;
82
83 struct lm3533_bl_platform_data *backlights;
84 int num_backlights;
85
86 struct lm3533_led_platform_data *leds;
87 int num_leds;
88};
89
90extern int lm3533_ctrlbank_enable(struct lm3533_ctrlbank *cb);
91extern int lm3533_ctrlbank_disable(struct lm3533_ctrlbank *cb);
92
93extern int lm3533_ctrlbank_set_brightness(struct lm3533_ctrlbank *cb, u8 val);
94extern int lm3533_ctrlbank_get_brightness(struct lm3533_ctrlbank *cb, u8 *val);
95extern int lm3533_ctrlbank_set_max_current(struct lm3533_ctrlbank *cb,
96 u16 imax);
97extern int lm3533_ctrlbank_set_pwm(struct lm3533_ctrlbank *cb, u8 val);
98extern int lm3533_ctrlbank_get_pwm(struct lm3533_ctrlbank *cb, u8 *val);
99
100extern int lm3533_read(struct lm3533 *lm3533, u8 reg, u8 *val);
101extern int lm3533_write(struct lm3533 *lm3533, u8 reg, u8 val);
102extern int lm3533_update(struct lm3533 *lm3533, u8 reg, u8 val, u8 mask);
103
104#endif /* __LINUX_MFD_LM3533_H */
diff --git a/include/linux/mfd/lpc_ich.h b/include/linux/mfd/lpc_ich.h
new file mode 100644
index 000000000000..fec5256c3f5d
--- /dev/null
+++ b/include/linux/mfd/lpc_ich.h
@@ -0,0 +1,48 @@
1/*
2 * linux/drivers/mfd/lpc_ich.h
3 *
4 * Copyright (c) 2012 Extreme Engineering Solution, Inc.
5 * Author: Aaron Sierra <asierra@xes-inc.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License 2 as published
9 * by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; see the file COPYING. If not, write to
18 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20#ifndef LPC_ICH_H
21#define LPC_ICH_H
22
23/* Watchdog resources */
24#define ICH_RES_IO_TCO 0
25#define ICH_RES_IO_SMI 1
26#define ICH_RES_MEM_OFF 2
27#define ICH_RES_MEM_GCS 0
28
29/* GPIO resources */
30#define ICH_RES_GPIO 0
31#define ICH_RES_GPE0 1
32
33/* GPIO compatibility */
34#define ICH_I3100_GPIO 0x401
35#define ICH_V5_GPIO 0x501
36#define ICH_V6_GPIO 0x601
37#define ICH_V7_GPIO 0x701
38#define ICH_V9_GPIO 0x801
39#define ICH_V10CORP_GPIO 0xa01
40#define ICH_V10CONS_GPIO 0xa11
41
42struct lpc_ich_info {
43 char name[32];
44 unsigned int iTCO_version;
45 unsigned int gpio_version;
46};
47
48#endif
diff --git a/include/linux/mfd/max77693-private.h b/include/linux/mfd/max77693-private.h
new file mode 100644
index 000000000000..68263c5fa53c
--- /dev/null
+++ b/include/linux/mfd/max77693-private.h
@@ -0,0 +1,227 @@
1/*
2 * max77693-private.h - Voltage regulator driver for the Maxim 77693
3 *
4 * Copyright (C) 2012 Samsung Electrnoics
5 * SangYoung Son <hello.son@samsung.com>
6 *
7 * This program is not provided / owned by Maxim Integrated Products.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#ifndef __LINUX_MFD_MAX77693_PRIV_H
25#define __LINUX_MFD_MAX77693_PRIV_H
26
27#include <linux/i2c.h>
28
29#define MAX77693_NUM_IRQ_MUIC_REGS 3
30#define MAX77693_REG_INVALID (0xff)
31
32/* Slave addr = 0xCC: PMIC, Charger, Flash LED */
33enum max77693_pmic_reg {
34 MAX77693_LED_REG_IFLASH1 = 0x00,
35 MAX77693_LED_REG_IFLASH2 = 0x01,
36 MAX77693_LED_REG_ITORCH = 0x02,
37 MAX77693_LED_REG_ITORCHTIMER = 0x03,
38 MAX77693_LED_REG_FLASH_TIMER = 0x04,
39 MAX77693_LED_REG_FLASH_EN = 0x05,
40 MAX77693_LED_REG_MAX_FLASH1 = 0x06,
41 MAX77693_LED_REG_MAX_FLASH2 = 0x07,
42 MAX77693_LED_REG_MAX_FLASH3 = 0x08,
43 MAX77693_LED_REG_MAX_FLASH4 = 0x09,
44 MAX77693_LED_REG_VOUT_CNTL = 0x0A,
45 MAX77693_LED_REG_VOUT_FLASH1 = 0x0B,
46 MAX77693_LED_REG_VOUT_FLASH2 = 0x0C,
47 MAX77693_LED_REG_FLASH_INT = 0x0E,
48 MAX77693_LED_REG_FLASH_INT_MASK = 0x0F,
49 MAX77693_LED_REG_FLASH_INT_STATUS = 0x10,
50
51 MAX77693_PMIC_REG_PMIC_ID1 = 0x20,
52 MAX77693_PMIC_REG_PMIC_ID2 = 0x21,
53 MAX77693_PMIC_REG_INTSRC = 0x22,
54 MAX77693_PMIC_REG_INTSRC_MASK = 0x23,
55 MAX77693_PMIC_REG_TOPSYS_INT = 0x24,
56 MAX77693_PMIC_REG_TOPSYS_INT_MASK = 0x26,
57 MAX77693_PMIC_REG_TOPSYS_STAT = 0x28,
58 MAX77693_PMIC_REG_MAINCTRL1 = 0x2A,
59 MAX77693_PMIC_REG_LSCNFG = 0x2B,
60
61 MAX77693_CHG_REG_CHG_INT = 0xB0,
62 MAX77693_CHG_REG_CHG_INT_MASK = 0xB1,
63 MAX77693_CHG_REG_CHG_INT_OK = 0xB2,
64 MAX77693_CHG_REG_CHG_DETAILS_00 = 0xB3,
65 MAX77693_CHG_REG_CHG_DETAILS_01 = 0xB4,
66 MAX77693_CHG_REG_CHG_DETAILS_02 = 0xB5,
67 MAX77693_CHG_REG_CHG_DETAILS_03 = 0xB6,
68 MAX77693_CHG_REG_CHG_CNFG_00 = 0xB7,
69 MAX77693_CHG_REG_CHG_CNFG_01 = 0xB8,
70 MAX77693_CHG_REG_CHG_CNFG_02 = 0xB9,
71 MAX77693_CHG_REG_CHG_CNFG_03 = 0xBA,
72 MAX77693_CHG_REG_CHG_CNFG_04 = 0xBB,
73 MAX77693_CHG_REG_CHG_CNFG_05 = 0xBC,
74 MAX77693_CHG_REG_CHG_CNFG_06 = 0xBD,
75 MAX77693_CHG_REG_CHG_CNFG_07 = 0xBE,
76 MAX77693_CHG_REG_CHG_CNFG_08 = 0xBF,
77 MAX77693_CHG_REG_CHG_CNFG_09 = 0xC0,
78 MAX77693_CHG_REG_CHG_CNFG_10 = 0xC1,
79 MAX77693_CHG_REG_CHG_CNFG_11 = 0xC2,
80 MAX77693_CHG_REG_CHG_CNFG_12 = 0xC3,
81 MAX77693_CHG_REG_CHG_CNFG_13 = 0xC4,
82 MAX77693_CHG_REG_CHG_CNFG_14 = 0xC5,
83 MAX77693_CHG_REG_SAFEOUT_CTRL = 0xC6,
84
85 MAX77693_PMIC_REG_END,
86};
87
88/* Slave addr = 0x4A: MUIC */
89enum max77693_muic_reg {
90 MAX77693_MUIC_REG_ID = 0x00,
91 MAX77693_MUIC_REG_INT1 = 0x01,
92 MAX77693_MUIC_REG_INT2 = 0x02,
93 MAX77693_MUIC_REG_INT3 = 0x03,
94 MAX77693_MUIC_REG_STATUS1 = 0x04,
95 MAX77693_MUIC_REG_STATUS2 = 0x05,
96 MAX77693_MUIC_REG_STATUS3 = 0x06,
97 MAX77693_MUIC_REG_INTMASK1 = 0x07,
98 MAX77693_MUIC_REG_INTMASK2 = 0x08,
99 MAX77693_MUIC_REG_INTMASK3 = 0x09,
100 MAX77693_MUIC_REG_CDETCTRL1 = 0x0A,
101 MAX77693_MUIC_REG_CDETCTRL2 = 0x0B,
102 MAX77693_MUIC_REG_CTRL1 = 0x0C,
103 MAX77693_MUIC_REG_CTRL2 = 0x0D,
104 MAX77693_MUIC_REG_CTRL3 = 0x0E,
105
106 MAX77693_MUIC_REG_END,
107};
108
109/* Slave addr = 0x90: Haptic */
110enum max77693_haptic_reg {
111 MAX77693_HAPTIC_REG_STATUS = 0x00,
112 MAX77693_HAPTIC_REG_CONFIG1 = 0x01,
113 MAX77693_HAPTIC_REG_CONFIG2 = 0x02,
114 MAX77693_HAPTIC_REG_CONFIG_CHNL = 0x03,
115 MAX77693_HAPTIC_REG_CONFG_CYC1 = 0x04,
116 MAX77693_HAPTIC_REG_CONFG_CYC2 = 0x05,
117 MAX77693_HAPTIC_REG_CONFIG_PER1 = 0x06,
118 MAX77693_HAPTIC_REG_CONFIG_PER2 = 0x07,
119 MAX77693_HAPTIC_REG_CONFIG_PER3 = 0x08,
120 MAX77693_HAPTIC_REG_CONFIG_PER4 = 0x09,
121 MAX77693_HAPTIC_REG_CONFIG_DUTY1 = 0x0A,
122 MAX77693_HAPTIC_REG_CONFIG_DUTY2 = 0x0B,
123 MAX77693_HAPTIC_REG_CONFIG_PWM1 = 0x0C,
124 MAX77693_HAPTIC_REG_CONFIG_PWM2 = 0x0D,
125 MAX77693_HAPTIC_REG_CONFIG_PWM3 = 0x0E,
126 MAX77693_HAPTIC_REG_CONFIG_PWM4 = 0x0F,
127 MAX77693_HAPTIC_REG_REV = 0x10,
128
129 MAX77693_HAPTIC_REG_END,
130};
131
132enum max77693_irq_source {
133 LED_INT = 0,
134 TOPSYS_INT,
135 CHG_INT,
136 MUIC_INT1,
137 MUIC_INT2,
138 MUIC_INT3,
139
140 MAX77693_IRQ_GROUP_NR,
141};
142
143enum max77693_irq {
144 /* PMIC - FLASH */
145 MAX77693_LED_IRQ_FLED2_OPEN,
146 MAX77693_LED_IRQ_FLED2_SHORT,
147 MAX77693_LED_IRQ_FLED1_OPEN,
148 MAX77693_LED_IRQ_FLED1_SHORT,
149 MAX77693_LED_IRQ_MAX_FLASH,
150
151 /* PMIC - TOPSYS */
152 MAX77693_TOPSYS_IRQ_T120C_INT,
153 MAX77693_TOPSYS_IRQ_T140C_INT,
154 MAX77693_TOPSYS_IRQ_LOWSYS_INT,
155
156 /* PMIC - Charger */
157 MAX77693_CHG_IRQ_BYP_I,
158 MAX77693_CHG_IRQ_THM_I,
159 MAX77693_CHG_IRQ_BAT_I,
160 MAX77693_CHG_IRQ_CHG_I,
161 MAX77693_CHG_IRQ_CHGIN_I,
162
163 /* MUIC INT1 */
164 MAX77693_MUIC_IRQ_INT1_ADC,
165 MAX77693_MUIC_IRQ_INT1_ADC_LOW,
166 MAX77693_MUIC_IRQ_INT1_ADC_ERR,
167 MAX77693_MUIC_IRQ_INT1_ADC1K,
168
169 /* MUIC INT2 */
170 MAX77693_MUIC_IRQ_INT2_CHGTYP,
171 MAX77693_MUIC_IRQ_INT2_CHGDETREUN,
172 MAX77693_MUIC_IRQ_INT2_DCDTMR,
173 MAX77693_MUIC_IRQ_INT2_DXOVP,
174 MAX77693_MUIC_IRQ_INT2_VBVOLT,
175 MAX77693_MUIC_IRQ_INT2_VIDRM,
176
177 /* MUIC INT3 */
178 MAX77693_MUIC_IRQ_INT3_EOC,
179 MAX77693_MUIC_IRQ_INT3_CGMBC,
180 MAX77693_MUIC_IRQ_INT3_OVP,
181 MAX77693_MUIC_IRQ_INT3_MBCCHG_ERR,
182 MAX77693_MUIC_IRQ_INT3_CHG_ENABLED,
183 MAX77693_MUIC_IRQ_INT3_BAT_DET,
184
185 MAX77693_IRQ_NR,
186};
187
188struct max77693_dev {
189 struct device *dev;
190 struct i2c_client *i2c; /* 0xCC , PMIC, Charger, Flash LED */
191 struct i2c_client *muic; /* 0x4A , MUIC */
192 struct i2c_client *haptic; /* 0x90 , Haptic */
193 struct mutex iolock;
194
195 int type;
196
197 struct regmap *regmap;
198 struct regmap *regmap_muic;
199 struct regmap *regmap_haptic;
200
201 struct irq_domain *irq_domain;
202
203 int irq;
204 int irq_gpio;
205 bool wakeup;
206 struct mutex irqlock;
207 int irq_masks_cur[MAX77693_IRQ_GROUP_NR];
208 int irq_masks_cache[MAX77693_IRQ_GROUP_NR];
209};
210
211enum max77693_types {
212 TYPE_MAX77693,
213};
214
215extern int max77693_read_reg(struct regmap *map, u8 reg, u8 *dest);
216extern int max77693_bulk_read(struct regmap *map, u8 reg, int count,
217 u8 *buf);
218extern int max77693_write_reg(struct regmap *map, u8 reg, u8 value);
219extern int max77693_bulk_write(struct regmap *map, u8 reg, int count,
220 u8 *buf);
221extern int max77693_update_reg(struct regmap *map, u8 reg, u8 val, u8 mask);
222
223extern int max77693_irq_init(struct max77693_dev *max77686);
224extern void max77693_irq_exit(struct max77693_dev *max77686);
225extern int max77693_irq_resume(struct max77693_dev *max77686);
226
227#endif /* __LINUX_MFD_MAX77693_PRIV_H */
diff --git a/include/linux/mfd/max77693.h b/include/linux/mfd/max77693.h
new file mode 100644
index 000000000000..1d28ae90384e
--- /dev/null
+++ b/include/linux/mfd/max77693.h
@@ -0,0 +1,36 @@
1/*
2 * max77693.h - Driver for the Maxim 77693
3 *
4 * Copyright (C) 2012 Samsung Electrnoics
5 * SangYoung Son <hello.son@samsung.com>
6 *
7 * This program is not provided / owned by Maxim Integrated Products.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 * This driver is based on max8997.h
24 *
25 * MAX77693 has PMIC, Charger, Flash LED, Haptic, MUIC devices.
26 * The devices share the same I2C bus and included in
27 * this mfd driver.
28 */
29
30#ifndef __LINUX_MFD_MAX77693_H
31#define __LINUX_MFD_MAX77693_H
32
33struct max77693_platform_data {
34 int wakeup;
35};
36#endif /* __LINUX_MFD_MAX77693_H */
diff --git a/include/linux/mfd/max8997.h b/include/linux/mfd/max8997.h
index 28726dd540f2..b40c08cd30bc 100644
--- a/include/linux/mfd/max8997.h
+++ b/include/linux/mfd/max8997.h
@@ -99,34 +99,11 @@ struct max8997_muic_reg_data {
99 99
100/** 100/**
101 * struct max8997_muic_platform_data 101 * struct max8997_muic_platform_data
102 * @usb_callback: callback function for USB
103 * inform callee of USB type (HOST or DEVICE)
104 * and attached state(true or false)
105 * @charger_callback: callback function for charger
106 * inform callee of charger_type
107 * and attached state(true or false)
108 * @deskdock_callback: callback function for desk dock
109 * inform callee of attached state(true or false)
110 * @cardock_callback: callback function for car dock
111 * inform callee of attached state(true or false)
112 * @mhl_callback: callback function for MHL (Mobile High-definition Link)
113 * inform callee of attached state(true or false)
114 * @uart_callback: callback function for JIG UART
115 * inform callee of attached state(true or false)
116 * @init_data: array of max8997_muic_reg_data 102 * @init_data: array of max8997_muic_reg_data
117 * used for initializing registers of MAX8997 MUIC device 103 * used for initializing registers of MAX8997 MUIC device
118 * @num_init_data: array size of init_data 104 * @num_init_data: array size of init_data
119 */ 105 */
120struct max8997_muic_platform_data { 106struct max8997_muic_platform_data {
121 void (*usb_callback)(enum max8997_muic_usb_type usb_type,
122 bool attached);
123 void (*charger_callback)(bool attached,
124 enum max8997_muic_charger_type charger_type);
125 void (*deskdock_callback) (bool attached);
126 void (*cardock_callback) (bool attached);
127 void (*mhl_callback) (bool attached);
128 void (*uart_callback) (bool attached);
129
130 struct max8997_muic_reg_data *init_data; 107 struct max8997_muic_reg_data *init_data;
131 int num_init_data; 108 int num_init_data;
132}; 109};
diff --git a/include/linux/mfd/mc13xxx.h b/include/linux/mfd/mc13xxx.h
index 10e038bac8dd..bf070755982e 100644
--- a/include/linux/mfd/mc13xxx.h
+++ b/include/linux/mfd/mc13xxx.h
@@ -170,6 +170,16 @@ struct mc13xxx_ts_platform_data {
170 bool atox; 170 bool atox;
171}; 171};
172 172
173enum mc13783_ssi_port {
174 MC13783_SSI1_PORT,
175 MC13783_SSI2_PORT,
176};
177
178struct mc13xxx_codec_platform_data {
179 enum mc13783_ssi_port adc_ssi_port;
180 enum mc13783_ssi_port dac_ssi_port;
181};
182
173struct mc13xxx_platform_data { 183struct mc13xxx_platform_data {
174#define MC13XXX_USE_TOUCHSCREEN (1 << 0) 184#define MC13XXX_USE_TOUCHSCREEN (1 << 0)
175#define MC13XXX_USE_CODEC (1 << 1) 185#define MC13XXX_USE_CODEC (1 << 1)
@@ -181,6 +191,7 @@ struct mc13xxx_platform_data {
181 struct mc13xxx_leds_platform_data *leds; 191 struct mc13xxx_leds_platform_data *leds;
182 struct mc13xxx_buttons_platform_data *buttons; 192 struct mc13xxx_buttons_platform_data *buttons;
183 struct mc13xxx_ts_platform_data touch; 193 struct mc13xxx_ts_platform_data touch;
194 struct mc13xxx_codec_platform_data *codec;
184}; 195};
185 196
186#define MC13XXX_ADC_MODE_TS 1 197#define MC13XXX_ADC_MODE_TS 1
diff --git a/include/linux/mfd/palmas.h b/include/linux/mfd/palmas.h
new file mode 100644
index 000000000000..9cbc642d40ad
--- /dev/null
+++ b/include/linux/mfd/palmas.h
@@ -0,0 +1,2620 @@
1/*
2 * TI Palmas
3 *
4 * Copyright 2011 Texas Instruments Inc.
5 *
6 * Author: Graeme Gregory <gg@slimlogic.co.uk>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#ifndef __LINUX_MFD_PALMAS_H
16#define __LINUX_MFD_PALMAS_H
17
18#include <linux/usb/otg.h>
19#include <linux/leds.h>
20#include <linux/regmap.h>
21#include <linux/regulator/driver.h>
22
23#define PALMAS_NUM_CLIENTS 3
24
25struct palmas_pmic;
26
27struct palmas {
28 struct device *dev;
29
30 struct i2c_client *i2c_clients[PALMAS_NUM_CLIENTS];
31 struct regmap *regmap[PALMAS_NUM_CLIENTS];
32
33 /* Stored chip id */
34 int id;
35
36 /* IRQ Data */
37 int irq;
38 u32 irq_mask;
39 struct mutex irq_lock;
40 struct regmap_irq_chip_data *irq_data;
41
42 /* Child Devices */
43 struct palmas_pmic *pmic;
44
45 /* GPIO MUXing */
46 u8 gpio_muxed;
47 u8 led_muxed;
48 u8 pwm_muxed;
49};
50
51struct palmas_reg_init {
52 /* warm_rest controls the voltage levels after a warm reset
53 *
54 * 0: reload default values from OTP on warm reset
55 * 1: maintain voltage from VSEL on warm reset
56 */
57 int warm_reset;
58
59 /* roof_floor controls whether the regulator uses the i2c style
60 * of DVS or uses the method where a GPIO or other control method is
61 * attached to the NSLEEP/ENABLE1/ENABLE2 pins
62 *
63 * For SMPS
64 *
65 * 0: i2c selection of voltage
66 * 1: pin selection of voltage.
67 *
68 * For LDO unused
69 */
70 int roof_floor;
71
72 /* sleep_mode is the mode loaded to MODE_SLEEP bits as defined in
73 * the data sheet.
74 *
75 * For SMPS
76 *
77 * 0: Off
78 * 1: AUTO
79 * 2: ECO
80 * 3: Forced PWM
81 *
82 * For LDO
83 *
84 * 0: Off
85 * 1: On
86 */
87 int mode_sleep;
88
89 /* tstep is the timestep loaded to the TSTEP register
90 *
91 * For SMPS
92 *
93 * 0: Jump (no slope control)
94 * 1: 10mV/us
95 * 2: 5mV/us
96 * 3: 2.5mV/us
97 *
98 * For LDO unused
99 */
100 int tstep;
101
102 /* voltage_sel is the bitfield loaded onto the SMPSX_VOLTAGE
103 * register. Set this is the default voltage set in OTP needs
104 * to be overridden.
105 */
106 u8 vsel;
107
108};
109
110struct palmas_pmic_platform_data {
111 /* An array of pointers to regulator init data indexed by regulator
112 * ID
113 */
114 struct regulator_init_data **reg_data;
115
116 /* An array of pointers to structures containing sleep mode and DVS
117 * configuration for regulators indexed by ID
118 */
119 struct palmas_reg_init **reg_init;
120
121 /* use LDO6 for vibrator control */
122 int ldo6_vibrator;
123
124
125};
126
127struct palmas_platform_data {
128 int gpio_base;
129
130 /* bit value to be loaded to the POWER_CTRL register */
131 u8 power_ctrl;
132
133 /*
134 * boolean to select if we want to configure muxing here
135 * then the two value to load into the registers if true
136 */
137 int mux_from_pdata;
138 u8 pad1, pad2;
139
140 struct palmas_pmic_platform_data *pmic_pdata;
141};
142
143/* Define the palmas IRQ numbers */
144enum palmas_irqs {
145 /* INT1 registers */
146 PALMAS_CHARG_DET_N_VBUS_OVV_IRQ,
147 PALMAS_PWRON_IRQ,
148 PALMAS_LONG_PRESS_KEY_IRQ,
149 PALMAS_RPWRON_IRQ,
150 PALMAS_PWRDOWN_IRQ,
151 PALMAS_HOTDIE_IRQ,
152 PALMAS_VSYS_MON_IRQ,
153 PALMAS_VBAT_MON_IRQ,
154 /* INT2 registers */
155 PALMAS_RTC_ALARM_IRQ,
156 PALMAS_RTC_TIMER_IRQ,
157 PALMAS_WDT_IRQ,
158 PALMAS_BATREMOVAL_IRQ,
159 PALMAS_RESET_IN_IRQ,
160 PALMAS_FBI_BB_IRQ,
161 PALMAS_SHORT_IRQ,
162 PALMAS_VAC_ACOK_IRQ,
163 /* INT3 registers */
164 PALMAS_GPADC_AUTO_0_IRQ,
165 PALMAS_GPADC_AUTO_1_IRQ,
166 PALMAS_GPADC_EOC_SW_IRQ,
167 PALMAS_GPADC_EOC_RT_IRQ,
168 PALMAS_ID_OTG_IRQ,
169 PALMAS_ID_IRQ,
170 PALMAS_VBUS_OTG_IRQ,
171 PALMAS_VBUS_IRQ,
172 /* INT4 registers */
173 PALMAS_GPIO_0_IRQ,
174 PALMAS_GPIO_1_IRQ,
175 PALMAS_GPIO_2_IRQ,
176 PALMAS_GPIO_3_IRQ,
177 PALMAS_GPIO_4_IRQ,
178 PALMAS_GPIO_5_IRQ,
179 PALMAS_GPIO_6_IRQ,
180 PALMAS_GPIO_7_IRQ,
181 /* Total Number IRQs */
182 PALMAS_NUM_IRQ,
183};
184
185enum palmas_regulators {
186 /* SMPS regulators */
187 PALMAS_REG_SMPS12,
188 PALMAS_REG_SMPS123,
189 PALMAS_REG_SMPS3,
190 PALMAS_REG_SMPS45,
191 PALMAS_REG_SMPS457,
192 PALMAS_REG_SMPS6,
193 PALMAS_REG_SMPS7,
194 PALMAS_REG_SMPS8,
195 PALMAS_REG_SMPS9,
196 PALMAS_REG_SMPS10,
197 /* LDO regulators */
198 PALMAS_REG_LDO1,
199 PALMAS_REG_LDO2,
200 PALMAS_REG_LDO3,
201 PALMAS_REG_LDO4,
202 PALMAS_REG_LDO5,
203 PALMAS_REG_LDO6,
204 PALMAS_REG_LDO7,
205 PALMAS_REG_LDO8,
206 PALMAS_REG_LDO9,
207 PALMAS_REG_LDOLN,
208 PALMAS_REG_LDOUSB,
209 /* Total number of regulators */
210 PALMAS_NUM_REGS,
211};
212
213struct palmas_pmic {
214 struct palmas *palmas;
215 struct device *dev;
216 struct regulator_desc desc[PALMAS_NUM_REGS];
217 struct regulator_dev *rdev[PALMAS_NUM_REGS];
218 struct mutex mutex;
219
220 int smps123;
221 int smps457;
222
223 int range[PALMAS_REG_SMPS10];
224};
225
226/* defines so we can store the mux settings */
227#define PALMAS_GPIO_0_MUXED (1 << 0)
228#define PALMAS_GPIO_1_MUXED (1 << 1)
229#define PALMAS_GPIO_2_MUXED (1 << 2)
230#define PALMAS_GPIO_3_MUXED (1 << 3)
231#define PALMAS_GPIO_4_MUXED (1 << 4)
232#define PALMAS_GPIO_5_MUXED (1 << 5)
233#define PALMAS_GPIO_6_MUXED (1 << 6)
234#define PALMAS_GPIO_7_MUXED (1 << 7)
235
236#define PALMAS_LED1_MUXED (1 << 0)
237#define PALMAS_LED2_MUXED (1 << 1)
238
239#define PALMAS_PWM1_MUXED (1 << 0)
240#define PALMAS_PWM2_MUXED (1 << 1)
241
242/* helper macro to get correct slave number */
243#define PALMAS_BASE_TO_SLAVE(x) ((x >> 8) - 1)
244#define PALMAS_BASE_TO_REG(x, y) ((x & 0xff) + y)
245
246/* Base addresses of IP blocks in Palmas */
247#define PALMAS_SMPS_DVS_BASE 0x20
248#define PALMAS_RTC_BASE 0x100
249#define PALMAS_VALIDITY_BASE 0x118
250#define PALMAS_SMPS_BASE 0x120
251#define PALMAS_LDO_BASE 0x150
252#define PALMAS_DVFS_BASE 0x180
253#define PALMAS_PMU_CONTROL_BASE 0x1A0
254#define PALMAS_RESOURCE_BASE 0x1D4
255#define PALMAS_PU_PD_OD_BASE 0x1F4
256#define PALMAS_LED_BASE 0x200
257#define PALMAS_INTERRUPT_BASE 0x210
258#define PALMAS_USB_OTG_BASE 0x250
259#define PALMAS_VIBRATOR_BASE 0x270
260#define PALMAS_GPIO_BASE 0x280
261#define PALMAS_USB_BASE 0x290
262#define PALMAS_GPADC_BASE 0x2C0
263#define PALMAS_TRIM_GPADC_BASE 0x3CD
264
265/* Registers for function RTC */
266#define PALMAS_SECONDS_REG 0x0
267#define PALMAS_MINUTES_REG 0x1
268#define PALMAS_HOURS_REG 0x2
269#define PALMAS_DAYS_REG 0x3
270#define PALMAS_MONTHS_REG 0x4
271#define PALMAS_YEARS_REG 0x5
272#define PALMAS_WEEKS_REG 0x6
273#define PALMAS_ALARM_SECONDS_REG 0x8
274#define PALMAS_ALARM_MINUTES_REG 0x9
275#define PALMAS_ALARM_HOURS_REG 0xA
276#define PALMAS_ALARM_DAYS_REG 0xB
277#define PALMAS_ALARM_MONTHS_REG 0xC
278#define PALMAS_ALARM_YEARS_REG 0xD
279#define PALMAS_RTC_CTRL_REG 0x10
280#define PALMAS_RTC_STATUS_REG 0x11
281#define PALMAS_RTC_INTERRUPTS_REG 0x12
282#define PALMAS_RTC_COMP_LSB_REG 0x13
283#define PALMAS_RTC_COMP_MSB_REG 0x14
284#define PALMAS_RTC_RES_PROG_REG 0x15
285#define PALMAS_RTC_RESET_STATUS_REG 0x16
286
287/* Bit definitions for SECONDS_REG */
288#define PALMAS_SECONDS_REG_SEC1_MASK 0x70
289#define PALMAS_SECONDS_REG_SEC1_SHIFT 4
290#define PALMAS_SECONDS_REG_SEC0_MASK 0x0f
291#define PALMAS_SECONDS_REG_SEC0_SHIFT 0
292
293/* Bit definitions for MINUTES_REG */
294#define PALMAS_MINUTES_REG_MIN1_MASK 0x70
295#define PALMAS_MINUTES_REG_MIN1_SHIFT 4
296#define PALMAS_MINUTES_REG_MIN0_MASK 0x0f
297#define PALMAS_MINUTES_REG_MIN0_SHIFT 0
298
299/* Bit definitions for HOURS_REG */
300#define PALMAS_HOURS_REG_PM_NAM 0x80
301#define PALMAS_HOURS_REG_PM_NAM_SHIFT 7
302#define PALMAS_HOURS_REG_HOUR1_MASK 0x30
303#define PALMAS_HOURS_REG_HOUR1_SHIFT 4
304#define PALMAS_HOURS_REG_HOUR0_MASK 0x0f
305#define PALMAS_HOURS_REG_HOUR0_SHIFT 0
306
307/* Bit definitions for DAYS_REG */
308#define PALMAS_DAYS_REG_DAY1_MASK 0x30
309#define PALMAS_DAYS_REG_DAY1_SHIFT 4
310#define PALMAS_DAYS_REG_DAY0_MASK 0x0f
311#define PALMAS_DAYS_REG_DAY0_SHIFT 0
312
313/* Bit definitions for MONTHS_REG */
314#define PALMAS_MONTHS_REG_MONTH1 0x10
315#define PALMAS_MONTHS_REG_MONTH1_SHIFT 4
316#define PALMAS_MONTHS_REG_MONTH0_MASK 0x0f
317#define PALMAS_MONTHS_REG_MONTH0_SHIFT 0
318
319/* Bit definitions for YEARS_REG */
320#define PALMAS_YEARS_REG_YEAR1_MASK 0xf0
321#define PALMAS_YEARS_REG_YEAR1_SHIFT 4
322#define PALMAS_YEARS_REG_YEAR0_MASK 0x0f
323#define PALMAS_YEARS_REG_YEAR0_SHIFT 0
324
325/* Bit definitions for WEEKS_REG */
326#define PALMAS_WEEKS_REG_WEEK_MASK 0x07
327#define PALMAS_WEEKS_REG_WEEK_SHIFT 0
328
329/* Bit definitions for ALARM_SECONDS_REG */
330#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_MASK 0x70
331#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_SHIFT 4
332#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_MASK 0x0f
333#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_SHIFT 0
334
335/* Bit definitions for ALARM_MINUTES_REG */
336#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_MASK 0x70
337#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_SHIFT 4
338#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_MASK 0x0f
339#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_SHIFT 0
340
341/* Bit definitions for ALARM_HOURS_REG */
342#define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM 0x80
343#define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM_SHIFT 7
344#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_MASK 0x30
345#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_SHIFT 4
346#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_MASK 0x0f
347#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_SHIFT 0
348
349/* Bit definitions for ALARM_DAYS_REG */
350#define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_MASK 0x30
351#define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_SHIFT 4
352#define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_MASK 0x0f
353#define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_SHIFT 0
354
355/* Bit definitions for ALARM_MONTHS_REG */
356#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1 0x10
357#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1_SHIFT 4
358#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_MASK 0x0f
359#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_SHIFT 0
360
361/* Bit definitions for ALARM_YEARS_REG */
362#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_MASK 0xf0
363#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_SHIFT 4
364#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_MASK 0x0f
365#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_SHIFT 0
366
367/* Bit definitions for RTC_CTRL_REG */
368#define PALMAS_RTC_CTRL_REG_RTC_V_OPT 0x80
369#define PALMAS_RTC_CTRL_REG_RTC_V_OPT_SHIFT 7
370#define PALMAS_RTC_CTRL_REG_GET_TIME 0x40
371#define PALMAS_RTC_CTRL_REG_GET_TIME_SHIFT 6
372#define PALMAS_RTC_CTRL_REG_SET_32_COUNTER 0x20
373#define PALMAS_RTC_CTRL_REG_SET_32_COUNTER_SHIFT 5
374#define PALMAS_RTC_CTRL_REG_TEST_MODE 0x10
375#define PALMAS_RTC_CTRL_REG_TEST_MODE_SHIFT 4
376#define PALMAS_RTC_CTRL_REG_MODE_12_24 0x08
377#define PALMAS_RTC_CTRL_REG_MODE_12_24_SHIFT 3
378#define PALMAS_RTC_CTRL_REG_AUTO_COMP 0x04
379#define PALMAS_RTC_CTRL_REG_AUTO_COMP_SHIFT 2
380#define PALMAS_RTC_CTRL_REG_ROUND_30S 0x02
381#define PALMAS_RTC_CTRL_REG_ROUND_30S_SHIFT 1
382#define PALMAS_RTC_CTRL_REG_STOP_RTC 0x01
383#define PALMAS_RTC_CTRL_REG_STOP_RTC_SHIFT 0
384
385/* Bit definitions for RTC_STATUS_REG */
386#define PALMAS_RTC_STATUS_REG_POWER_UP 0x80
387#define PALMAS_RTC_STATUS_REG_POWER_UP_SHIFT 7
388#define PALMAS_RTC_STATUS_REG_ALARM 0x40
389#define PALMAS_RTC_STATUS_REG_ALARM_SHIFT 6
390#define PALMAS_RTC_STATUS_REG_EVENT_1D 0x20
391#define PALMAS_RTC_STATUS_REG_EVENT_1D_SHIFT 5
392#define PALMAS_RTC_STATUS_REG_EVENT_1H 0x10
393#define PALMAS_RTC_STATUS_REG_EVENT_1H_SHIFT 4
394#define PALMAS_RTC_STATUS_REG_EVENT_1M 0x08
395#define PALMAS_RTC_STATUS_REG_EVENT_1M_SHIFT 3
396#define PALMAS_RTC_STATUS_REG_EVENT_1S 0x04
397#define PALMAS_RTC_STATUS_REG_EVENT_1S_SHIFT 2
398#define PALMAS_RTC_STATUS_REG_RUN 0x02
399#define PALMAS_RTC_STATUS_REG_RUN_SHIFT 1
400
401/* Bit definitions for RTC_INTERRUPTS_REG */
402#define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN 0x10
403#define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN_SHIFT 4
404#define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM 0x08
405#define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM_SHIFT 3
406#define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER 0x04
407#define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER_SHIFT 2
408#define PALMAS_RTC_INTERRUPTS_REG_EVERY_MASK 0x03
409#define PALMAS_RTC_INTERRUPTS_REG_EVERY_SHIFT 0
410
411/* Bit definitions for RTC_COMP_LSB_REG */
412#define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_MASK 0xff
413#define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_SHIFT 0
414
415/* Bit definitions for RTC_COMP_MSB_REG */
416#define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_MASK 0xff
417#define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_SHIFT 0
418
419/* Bit definitions for RTC_RES_PROG_REG */
420#define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_MASK 0x3f
421#define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_SHIFT 0
422
423/* Bit definitions for RTC_RESET_STATUS_REG */
424#define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS 0x01
425#define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS_SHIFT 0
426
427/* Registers for function BACKUP */
428#define PALMAS_BACKUP0 0x0
429#define PALMAS_BACKUP1 0x1
430#define PALMAS_BACKUP2 0x2
431#define PALMAS_BACKUP3 0x3
432#define PALMAS_BACKUP4 0x4
433#define PALMAS_BACKUP5 0x5
434#define PALMAS_BACKUP6 0x6
435#define PALMAS_BACKUP7 0x7
436
437/* Bit definitions for BACKUP0 */
438#define PALMAS_BACKUP0_BACKUP_MASK 0xff
439#define PALMAS_BACKUP0_BACKUP_SHIFT 0
440
441/* Bit definitions for BACKUP1 */
442#define PALMAS_BACKUP1_BACKUP_MASK 0xff
443#define PALMAS_BACKUP1_BACKUP_SHIFT 0
444
445/* Bit definitions for BACKUP2 */
446#define PALMAS_BACKUP2_BACKUP_MASK 0xff
447#define PALMAS_BACKUP2_BACKUP_SHIFT 0
448
449/* Bit definitions for BACKUP3 */
450#define PALMAS_BACKUP3_BACKUP_MASK 0xff
451#define PALMAS_BACKUP3_BACKUP_SHIFT 0
452
453/* Bit definitions for BACKUP4 */
454#define PALMAS_BACKUP4_BACKUP_MASK 0xff
455#define PALMAS_BACKUP4_BACKUP_SHIFT 0
456
457/* Bit definitions for BACKUP5 */
458#define PALMAS_BACKUP5_BACKUP_MASK 0xff
459#define PALMAS_BACKUP5_BACKUP_SHIFT 0
460
461/* Bit definitions for BACKUP6 */
462#define PALMAS_BACKUP6_BACKUP_MASK 0xff
463#define PALMAS_BACKUP6_BACKUP_SHIFT 0
464
465/* Bit definitions for BACKUP7 */
466#define PALMAS_BACKUP7_BACKUP_MASK 0xff
467#define PALMAS_BACKUP7_BACKUP_SHIFT 0
468
469/* Registers for function SMPS */
470#define PALMAS_SMPS12_CTRL 0x0
471#define PALMAS_SMPS12_TSTEP 0x1
472#define PALMAS_SMPS12_FORCE 0x2
473#define PALMAS_SMPS12_VOLTAGE 0x3
474#define PALMAS_SMPS3_CTRL 0x4
475#define PALMAS_SMPS3_VOLTAGE 0x7
476#define PALMAS_SMPS45_CTRL 0x8
477#define PALMAS_SMPS45_TSTEP 0x9
478#define PALMAS_SMPS45_FORCE 0xA
479#define PALMAS_SMPS45_VOLTAGE 0xB
480#define PALMAS_SMPS6_CTRL 0xC
481#define PALMAS_SMPS6_TSTEP 0xD
482#define PALMAS_SMPS6_FORCE 0xE
483#define PALMAS_SMPS6_VOLTAGE 0xF
484#define PALMAS_SMPS7_CTRL 0x10
485#define PALMAS_SMPS7_VOLTAGE 0x13
486#define PALMAS_SMPS8_CTRL 0x14
487#define PALMAS_SMPS8_TSTEP 0x15
488#define PALMAS_SMPS8_FORCE 0x16
489#define PALMAS_SMPS8_VOLTAGE 0x17
490#define PALMAS_SMPS9_CTRL 0x18
491#define PALMAS_SMPS9_VOLTAGE 0x1B
492#define PALMAS_SMPS10_CTRL 0x1C
493#define PALMAS_SMPS10_STATUS 0x1F
494#define PALMAS_SMPS_CTRL 0x24
495#define PALMAS_SMPS_PD_CTRL 0x25
496#define PALMAS_SMPS_DITHER_EN 0x26
497#define PALMAS_SMPS_THERMAL_EN 0x27
498#define PALMAS_SMPS_THERMAL_STATUS 0x28
499#define PALMAS_SMPS_SHORT_STATUS 0x29
500#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN 0x2A
501#define PALMAS_SMPS_POWERGOOD_MASK1 0x2B
502#define PALMAS_SMPS_POWERGOOD_MASK2 0x2C
503
504/* Bit definitions for SMPS12_CTRL */
505#define PALMAS_SMPS12_CTRL_WR_S 0x80
506#define PALMAS_SMPS12_CTRL_WR_S_SHIFT 7
507#define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN 0x40
508#define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN_SHIFT 6
509#define PALMAS_SMPS12_CTRL_STATUS_MASK 0x30
510#define PALMAS_SMPS12_CTRL_STATUS_SHIFT 4
511#define PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK 0x0c
512#define PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT 2
513#define PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK 0x03
514#define PALMAS_SMPS12_CTRL_MODE_ACTIVE_SHIFT 0
515
516/* Bit definitions for SMPS12_TSTEP */
517#define PALMAS_SMPS12_TSTEP_TSTEP_MASK 0x03
518#define PALMAS_SMPS12_TSTEP_TSTEP_SHIFT 0
519
520/* Bit definitions for SMPS12_FORCE */
521#define PALMAS_SMPS12_FORCE_CMD 0x80
522#define PALMAS_SMPS12_FORCE_CMD_SHIFT 7
523#define PALMAS_SMPS12_FORCE_VSEL_MASK 0x7f
524#define PALMAS_SMPS12_FORCE_VSEL_SHIFT 0
525
526/* Bit definitions for SMPS12_VOLTAGE */
527#define PALMAS_SMPS12_VOLTAGE_RANGE 0x80
528#define PALMAS_SMPS12_VOLTAGE_RANGE_SHIFT 7
529#define PALMAS_SMPS12_VOLTAGE_VSEL_MASK 0x7f
530#define PALMAS_SMPS12_VOLTAGE_VSEL_SHIFT 0
531
532/* Bit definitions for SMPS3_CTRL */
533#define PALMAS_SMPS3_CTRL_WR_S 0x80
534#define PALMAS_SMPS3_CTRL_WR_S_SHIFT 7
535#define PALMAS_SMPS3_CTRL_STATUS_MASK 0x30
536#define PALMAS_SMPS3_CTRL_STATUS_SHIFT 4
537#define PALMAS_SMPS3_CTRL_MODE_SLEEP_MASK 0x0c
538#define PALMAS_SMPS3_CTRL_MODE_SLEEP_SHIFT 2
539#define PALMAS_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03
540#define PALMAS_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0
541
542/* Bit definitions for SMPS3_VOLTAGE */
543#define PALMAS_SMPS3_VOLTAGE_RANGE 0x80
544#define PALMAS_SMPS3_VOLTAGE_RANGE_SHIFT 7
545#define PALMAS_SMPS3_VOLTAGE_VSEL_MASK 0x7f
546#define PALMAS_SMPS3_VOLTAGE_VSEL_SHIFT 0
547
548/* Bit definitions for SMPS45_CTRL */
549#define PALMAS_SMPS45_CTRL_WR_S 0x80
550#define PALMAS_SMPS45_CTRL_WR_S_SHIFT 7
551#define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN 0x40
552#define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN_SHIFT 6
553#define PALMAS_SMPS45_CTRL_STATUS_MASK 0x30
554#define PALMAS_SMPS45_CTRL_STATUS_SHIFT 4
555#define PALMAS_SMPS45_CTRL_MODE_SLEEP_MASK 0x0c
556#define PALMAS_SMPS45_CTRL_MODE_SLEEP_SHIFT 2
557#define PALMAS_SMPS45_CTRL_MODE_ACTIVE_MASK 0x03
558#define PALMAS_SMPS45_CTRL_MODE_ACTIVE_SHIFT 0
559
560/* Bit definitions for SMPS45_TSTEP */
561#define PALMAS_SMPS45_TSTEP_TSTEP_MASK 0x03
562#define PALMAS_SMPS45_TSTEP_TSTEP_SHIFT 0
563
564/* Bit definitions for SMPS45_FORCE */
565#define PALMAS_SMPS45_FORCE_CMD 0x80
566#define PALMAS_SMPS45_FORCE_CMD_SHIFT 7
567#define PALMAS_SMPS45_FORCE_VSEL_MASK 0x7f
568#define PALMAS_SMPS45_FORCE_VSEL_SHIFT 0
569
570/* Bit definitions for SMPS45_VOLTAGE */
571#define PALMAS_SMPS45_VOLTAGE_RANGE 0x80
572#define PALMAS_SMPS45_VOLTAGE_RANGE_SHIFT 7
573#define PALMAS_SMPS45_VOLTAGE_VSEL_MASK 0x7f
574#define PALMAS_SMPS45_VOLTAGE_VSEL_SHIFT 0
575
576/* Bit definitions for SMPS6_CTRL */
577#define PALMAS_SMPS6_CTRL_WR_S 0x80
578#define PALMAS_SMPS6_CTRL_WR_S_SHIFT 7
579#define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN 0x40
580#define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN_SHIFT 6
581#define PALMAS_SMPS6_CTRL_STATUS_MASK 0x30
582#define PALMAS_SMPS6_CTRL_STATUS_SHIFT 4
583#define PALMAS_SMPS6_CTRL_MODE_SLEEP_MASK 0x0c
584#define PALMAS_SMPS6_CTRL_MODE_SLEEP_SHIFT 2
585#define PALMAS_SMPS6_CTRL_MODE_ACTIVE_MASK 0x03
586#define PALMAS_SMPS6_CTRL_MODE_ACTIVE_SHIFT 0
587
588/* Bit definitions for SMPS6_TSTEP */
589#define PALMAS_SMPS6_TSTEP_TSTEP_MASK 0x03
590#define PALMAS_SMPS6_TSTEP_TSTEP_SHIFT 0
591
592/* Bit definitions for SMPS6_FORCE */
593#define PALMAS_SMPS6_FORCE_CMD 0x80
594#define PALMAS_SMPS6_FORCE_CMD_SHIFT 7
595#define PALMAS_SMPS6_FORCE_VSEL_MASK 0x7f
596#define PALMAS_SMPS6_FORCE_VSEL_SHIFT 0
597
598/* Bit definitions for SMPS6_VOLTAGE */
599#define PALMAS_SMPS6_VOLTAGE_RANGE 0x80
600#define PALMAS_SMPS6_VOLTAGE_RANGE_SHIFT 7
601#define PALMAS_SMPS6_VOLTAGE_VSEL_MASK 0x7f
602#define PALMAS_SMPS6_VOLTAGE_VSEL_SHIFT 0
603
604/* Bit definitions for SMPS7_CTRL */
605#define PALMAS_SMPS7_CTRL_WR_S 0x80
606#define PALMAS_SMPS7_CTRL_WR_S_SHIFT 7
607#define PALMAS_SMPS7_CTRL_STATUS_MASK 0x30
608#define PALMAS_SMPS7_CTRL_STATUS_SHIFT 4
609#define PALMAS_SMPS7_CTRL_MODE_SLEEP_MASK 0x0c
610#define PALMAS_SMPS7_CTRL_MODE_SLEEP_SHIFT 2
611#define PALMAS_SMPS7_CTRL_MODE_ACTIVE_MASK 0x03
612#define PALMAS_SMPS7_CTRL_MODE_ACTIVE_SHIFT 0
613
614/* Bit definitions for SMPS7_VOLTAGE */
615#define PALMAS_SMPS7_VOLTAGE_RANGE 0x80
616#define PALMAS_SMPS7_VOLTAGE_RANGE_SHIFT 7
617#define PALMAS_SMPS7_VOLTAGE_VSEL_MASK 0x7f
618#define PALMAS_SMPS7_VOLTAGE_VSEL_SHIFT 0
619
620/* Bit definitions for SMPS8_CTRL */
621#define PALMAS_SMPS8_CTRL_WR_S 0x80
622#define PALMAS_SMPS8_CTRL_WR_S_SHIFT 7
623#define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN 0x40
624#define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN_SHIFT 6
625#define PALMAS_SMPS8_CTRL_STATUS_MASK 0x30
626#define PALMAS_SMPS8_CTRL_STATUS_SHIFT 4
627#define PALMAS_SMPS8_CTRL_MODE_SLEEP_MASK 0x0c
628#define PALMAS_SMPS8_CTRL_MODE_SLEEP_SHIFT 2
629#define PALMAS_SMPS8_CTRL_MODE_ACTIVE_MASK 0x03
630#define PALMAS_SMPS8_CTRL_MODE_ACTIVE_SHIFT 0
631
632/* Bit definitions for SMPS8_TSTEP */
633#define PALMAS_SMPS8_TSTEP_TSTEP_MASK 0x03
634#define PALMAS_SMPS8_TSTEP_TSTEP_SHIFT 0
635
636/* Bit definitions for SMPS8_FORCE */
637#define PALMAS_SMPS8_FORCE_CMD 0x80
638#define PALMAS_SMPS8_FORCE_CMD_SHIFT 7
639#define PALMAS_SMPS8_FORCE_VSEL_MASK 0x7f
640#define PALMAS_SMPS8_FORCE_VSEL_SHIFT 0
641
642/* Bit definitions for SMPS8_VOLTAGE */
643#define PALMAS_SMPS8_VOLTAGE_RANGE 0x80
644#define PALMAS_SMPS8_VOLTAGE_RANGE_SHIFT 7
645#define PALMAS_SMPS8_VOLTAGE_VSEL_MASK 0x7f
646#define PALMAS_SMPS8_VOLTAGE_VSEL_SHIFT 0
647
648/* Bit definitions for SMPS9_CTRL */
649#define PALMAS_SMPS9_CTRL_WR_S 0x80
650#define PALMAS_SMPS9_CTRL_WR_S_SHIFT 7
651#define PALMAS_SMPS9_CTRL_STATUS_MASK 0x30
652#define PALMAS_SMPS9_CTRL_STATUS_SHIFT 4
653#define PALMAS_SMPS9_CTRL_MODE_SLEEP_MASK 0x0c
654#define PALMAS_SMPS9_CTRL_MODE_SLEEP_SHIFT 2
655#define PALMAS_SMPS9_CTRL_MODE_ACTIVE_MASK 0x03
656#define PALMAS_SMPS9_CTRL_MODE_ACTIVE_SHIFT 0
657
658/* Bit definitions for SMPS9_VOLTAGE */
659#define PALMAS_SMPS9_VOLTAGE_RANGE 0x80
660#define PALMAS_SMPS9_VOLTAGE_RANGE_SHIFT 7
661#define PALMAS_SMPS9_VOLTAGE_VSEL_MASK 0x7f
662#define PALMAS_SMPS9_VOLTAGE_VSEL_SHIFT 0
663
664/* Bit definitions for SMPS10_CTRL */
665#define PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK 0xf0
666#define PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT 4
667#define PALMAS_SMPS10_CTRL_MODE_ACTIVE_MASK 0x0f
668#define PALMAS_SMPS10_CTRL_MODE_ACTIVE_SHIFT 0
669
670/* Bit definitions for SMPS10_STATUS */
671#define PALMAS_SMPS10_STATUS_STATUS_MASK 0x0f
672#define PALMAS_SMPS10_STATUS_STATUS_SHIFT 0
673
674/* Bit definitions for SMPS_CTRL */
675#define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN 0x20
676#define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN_SHIFT 5
677#define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN 0x10
678#define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN_SHIFT 4
679#define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_MASK 0x0c
680#define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_SHIFT 2
681#define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_MASK 0x03
682#define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_SHIFT 0
683
684/* Bit definitions for SMPS_PD_CTRL */
685#define PALMAS_SMPS_PD_CTRL_SMPS9 0x40
686#define PALMAS_SMPS_PD_CTRL_SMPS9_SHIFT 6
687#define PALMAS_SMPS_PD_CTRL_SMPS8 0x20
688#define PALMAS_SMPS_PD_CTRL_SMPS8_SHIFT 5
689#define PALMAS_SMPS_PD_CTRL_SMPS7 0x10
690#define PALMAS_SMPS_PD_CTRL_SMPS7_SHIFT 4
691#define PALMAS_SMPS_PD_CTRL_SMPS6 0x08
692#define PALMAS_SMPS_PD_CTRL_SMPS6_SHIFT 3
693#define PALMAS_SMPS_PD_CTRL_SMPS45 0x04
694#define PALMAS_SMPS_PD_CTRL_SMPS45_SHIFT 2
695#define PALMAS_SMPS_PD_CTRL_SMPS3 0x02
696#define PALMAS_SMPS_PD_CTRL_SMPS3_SHIFT 1
697#define PALMAS_SMPS_PD_CTRL_SMPS12 0x01
698#define PALMAS_SMPS_PD_CTRL_SMPS12_SHIFT 0
699
700/* Bit definitions for SMPS_THERMAL_EN */
701#define PALMAS_SMPS_THERMAL_EN_SMPS9 0x40
702#define PALMAS_SMPS_THERMAL_EN_SMPS9_SHIFT 6
703#define PALMAS_SMPS_THERMAL_EN_SMPS8 0x20
704#define PALMAS_SMPS_THERMAL_EN_SMPS8_SHIFT 5
705#define PALMAS_SMPS_THERMAL_EN_SMPS6 0x08
706#define PALMAS_SMPS_THERMAL_EN_SMPS6_SHIFT 3
707#define PALMAS_SMPS_THERMAL_EN_SMPS457 0x04
708#define PALMAS_SMPS_THERMAL_EN_SMPS457_SHIFT 2
709#define PALMAS_SMPS_THERMAL_EN_SMPS123 0x01
710#define PALMAS_SMPS_THERMAL_EN_SMPS123_SHIFT 0
711
712/* Bit definitions for SMPS_THERMAL_STATUS */
713#define PALMAS_SMPS_THERMAL_STATUS_SMPS9 0x40
714#define PALMAS_SMPS_THERMAL_STATUS_SMPS9_SHIFT 6
715#define PALMAS_SMPS_THERMAL_STATUS_SMPS8 0x20
716#define PALMAS_SMPS_THERMAL_STATUS_SMPS8_SHIFT 5
717#define PALMAS_SMPS_THERMAL_STATUS_SMPS6 0x08
718#define PALMAS_SMPS_THERMAL_STATUS_SMPS6_SHIFT 3
719#define PALMAS_SMPS_THERMAL_STATUS_SMPS457 0x04
720#define PALMAS_SMPS_THERMAL_STATUS_SMPS457_SHIFT 2
721#define PALMAS_SMPS_THERMAL_STATUS_SMPS123 0x01
722#define PALMAS_SMPS_THERMAL_STATUS_SMPS123_SHIFT 0
723
724/* Bit definitions for SMPS_SHORT_STATUS */
725#define PALMAS_SMPS_SHORT_STATUS_SMPS10 0x80
726#define PALMAS_SMPS_SHORT_STATUS_SMPS10_SHIFT 7
727#define PALMAS_SMPS_SHORT_STATUS_SMPS9 0x40
728#define PALMAS_SMPS_SHORT_STATUS_SMPS9_SHIFT 6
729#define PALMAS_SMPS_SHORT_STATUS_SMPS8 0x20
730#define PALMAS_SMPS_SHORT_STATUS_SMPS8_SHIFT 5
731#define PALMAS_SMPS_SHORT_STATUS_SMPS7 0x10
732#define PALMAS_SMPS_SHORT_STATUS_SMPS7_SHIFT 4
733#define PALMAS_SMPS_SHORT_STATUS_SMPS6 0x08
734#define PALMAS_SMPS_SHORT_STATUS_SMPS6_SHIFT 3
735#define PALMAS_SMPS_SHORT_STATUS_SMPS45 0x04
736#define PALMAS_SMPS_SHORT_STATUS_SMPS45_SHIFT 2
737#define PALMAS_SMPS_SHORT_STATUS_SMPS3 0x02
738#define PALMAS_SMPS_SHORT_STATUS_SMPS3_SHIFT 1
739#define PALMAS_SMPS_SHORT_STATUS_SMPS12 0x01
740#define PALMAS_SMPS_SHORT_STATUS_SMPS12_SHIFT 0
741
742/* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */
743#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9 0x40
744#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9_SHIFT 6
745#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8 0x20
746#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8_SHIFT 5
747#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7 0x10
748#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7_SHIFT 4
749#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6 0x08
750#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6_SHIFT 3
751#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45 0x04
752#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45_SHIFT 2
753#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x02
754#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 1
755#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12 0x01
756#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12_SHIFT 0
757
758/* Bit definitions for SMPS_POWERGOOD_MASK1 */
759#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10 0x80
760#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10_SHIFT 7
761#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9 0x40
762#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9_SHIFT 6
763#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8 0x20
764#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8_SHIFT 5
765#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7 0x10
766#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7_SHIFT 4
767#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6 0x08
768#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6_SHIFT 3
769#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45 0x04
770#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45_SHIFT 2
771#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3 0x02
772#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 1
773#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12 0x01
774#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12_SHIFT 0
775
776/* Bit definitions for SMPS_POWERGOOD_MASK2 */
777#define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80
778#define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 7
779#define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7 0x04
780#define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7_SHIFT 2
781#define PALMAS_SMPS_POWERGOOD_MASK2_VBUS 0x02
782#define PALMAS_SMPS_POWERGOOD_MASK2_VBUS_SHIFT 1
783#define PALMAS_SMPS_POWERGOOD_MASK2_ACOK 0x01
784#define PALMAS_SMPS_POWERGOOD_MASK2_ACOK_SHIFT 0
785
786/* Registers for function LDO */
787#define PALMAS_LDO1_CTRL 0x0
788#define PALMAS_LDO1_VOLTAGE 0x1
789#define PALMAS_LDO2_CTRL 0x2
790#define PALMAS_LDO2_VOLTAGE 0x3
791#define PALMAS_LDO3_CTRL 0x4
792#define PALMAS_LDO3_VOLTAGE 0x5
793#define PALMAS_LDO4_CTRL 0x6
794#define PALMAS_LDO4_VOLTAGE 0x7
795#define PALMAS_LDO5_CTRL 0x8
796#define PALMAS_LDO5_VOLTAGE 0x9
797#define PALMAS_LDO6_CTRL 0xA
798#define PALMAS_LDO6_VOLTAGE 0xB
799#define PALMAS_LDO7_CTRL 0xC
800#define PALMAS_LDO7_VOLTAGE 0xD
801#define PALMAS_LDO8_CTRL 0xE
802#define PALMAS_LDO8_VOLTAGE 0xF
803#define PALMAS_LDO9_CTRL 0x10
804#define PALMAS_LDO9_VOLTAGE 0x11
805#define PALMAS_LDOLN_CTRL 0x12
806#define PALMAS_LDOLN_VOLTAGE 0x13
807#define PALMAS_LDOUSB_CTRL 0x14
808#define PALMAS_LDOUSB_VOLTAGE 0x15
809#define PALMAS_LDO_CTRL 0x1A
810#define PALMAS_LDO_PD_CTRL1 0x1B
811#define PALMAS_LDO_PD_CTRL2 0x1C
812#define PALMAS_LDO_SHORT_STATUS1 0x1D
813#define PALMAS_LDO_SHORT_STATUS2 0x1E
814
815/* Bit definitions for LDO1_CTRL */
816#define PALMAS_LDO1_CTRL_WR_S 0x80
817#define PALMAS_LDO1_CTRL_WR_S_SHIFT 7
818#define PALMAS_LDO1_CTRL_STATUS 0x10
819#define PALMAS_LDO1_CTRL_STATUS_SHIFT 4
820#define PALMAS_LDO1_CTRL_MODE_SLEEP 0x04
821#define PALMAS_LDO1_CTRL_MODE_SLEEP_SHIFT 2
822#define PALMAS_LDO1_CTRL_MODE_ACTIVE 0x01
823#define PALMAS_LDO1_CTRL_MODE_ACTIVE_SHIFT 0
824
825/* Bit definitions for LDO1_VOLTAGE */
826#define PALMAS_LDO1_VOLTAGE_VSEL_MASK 0x3f
827#define PALMAS_LDO1_VOLTAGE_VSEL_SHIFT 0
828
829/* Bit definitions for LDO2_CTRL */
830#define PALMAS_LDO2_CTRL_WR_S 0x80
831#define PALMAS_LDO2_CTRL_WR_S_SHIFT 7
832#define PALMAS_LDO2_CTRL_STATUS 0x10
833#define PALMAS_LDO2_CTRL_STATUS_SHIFT 4
834#define PALMAS_LDO2_CTRL_MODE_SLEEP 0x04
835#define PALMAS_LDO2_CTRL_MODE_SLEEP_SHIFT 2
836#define PALMAS_LDO2_CTRL_MODE_ACTIVE 0x01
837#define PALMAS_LDO2_CTRL_MODE_ACTIVE_SHIFT 0
838
839/* Bit definitions for LDO2_VOLTAGE */
840#define PALMAS_LDO2_VOLTAGE_VSEL_MASK 0x3f
841#define PALMAS_LDO2_VOLTAGE_VSEL_SHIFT 0
842
843/* Bit definitions for LDO3_CTRL */
844#define PALMAS_LDO3_CTRL_WR_S 0x80
845#define PALMAS_LDO3_CTRL_WR_S_SHIFT 7
846#define PALMAS_LDO3_CTRL_STATUS 0x10
847#define PALMAS_LDO3_CTRL_STATUS_SHIFT 4
848#define PALMAS_LDO3_CTRL_MODE_SLEEP 0x04
849#define PALMAS_LDO3_CTRL_MODE_SLEEP_SHIFT 2
850#define PALMAS_LDO3_CTRL_MODE_ACTIVE 0x01
851#define PALMAS_LDO3_CTRL_MODE_ACTIVE_SHIFT 0
852
853/* Bit definitions for LDO3_VOLTAGE */
854#define PALMAS_LDO3_VOLTAGE_VSEL_MASK 0x3f
855#define PALMAS_LDO3_VOLTAGE_VSEL_SHIFT 0
856
857/* Bit definitions for LDO4_CTRL */
858#define PALMAS_LDO4_CTRL_WR_S 0x80
859#define PALMAS_LDO4_CTRL_WR_S_SHIFT 7
860#define PALMAS_LDO4_CTRL_STATUS 0x10
861#define PALMAS_LDO4_CTRL_STATUS_SHIFT 4
862#define PALMAS_LDO4_CTRL_MODE_SLEEP 0x04
863#define PALMAS_LDO4_CTRL_MODE_SLEEP_SHIFT 2
864#define PALMAS_LDO4_CTRL_MODE_ACTIVE 0x01
865#define PALMAS_LDO4_CTRL_MODE_ACTIVE_SHIFT 0
866
867/* Bit definitions for LDO4_VOLTAGE */
868#define PALMAS_LDO4_VOLTAGE_VSEL_MASK 0x3f
869#define PALMAS_LDO4_VOLTAGE_VSEL_SHIFT 0
870
871/* Bit definitions for LDO5_CTRL */
872#define PALMAS_LDO5_CTRL_WR_S 0x80
873#define PALMAS_LDO5_CTRL_WR_S_SHIFT 7
874#define PALMAS_LDO5_CTRL_STATUS 0x10
875#define PALMAS_LDO5_CTRL_STATUS_SHIFT 4
876#define PALMAS_LDO5_CTRL_MODE_SLEEP 0x04
877#define PALMAS_LDO5_CTRL_MODE_SLEEP_SHIFT 2
878#define PALMAS_LDO5_CTRL_MODE_ACTIVE 0x01
879#define PALMAS_LDO5_CTRL_MODE_ACTIVE_SHIFT 0
880
881/* Bit definitions for LDO5_VOLTAGE */
882#define PALMAS_LDO5_VOLTAGE_VSEL_MASK 0x3f
883#define PALMAS_LDO5_VOLTAGE_VSEL_SHIFT 0
884
885/* Bit definitions for LDO6_CTRL */
886#define PALMAS_LDO6_CTRL_WR_S 0x80
887#define PALMAS_LDO6_CTRL_WR_S_SHIFT 7
888#define PALMAS_LDO6_CTRL_LDO_VIB_EN 0x40
889#define PALMAS_LDO6_CTRL_LDO_VIB_EN_SHIFT 6
890#define PALMAS_LDO6_CTRL_STATUS 0x10
891#define PALMAS_LDO6_CTRL_STATUS_SHIFT 4
892#define PALMAS_LDO6_CTRL_MODE_SLEEP 0x04
893#define PALMAS_LDO6_CTRL_MODE_SLEEP_SHIFT 2
894#define PALMAS_LDO6_CTRL_MODE_ACTIVE 0x01
895#define PALMAS_LDO6_CTRL_MODE_ACTIVE_SHIFT 0
896
897/* Bit definitions for LDO6_VOLTAGE */
898#define PALMAS_LDO6_VOLTAGE_VSEL_MASK 0x3f
899#define PALMAS_LDO6_VOLTAGE_VSEL_SHIFT 0
900
901/* Bit definitions for LDO7_CTRL */
902#define PALMAS_LDO7_CTRL_WR_S 0x80
903#define PALMAS_LDO7_CTRL_WR_S_SHIFT 7
904#define PALMAS_LDO7_CTRL_STATUS 0x10
905#define PALMAS_LDO7_CTRL_STATUS_SHIFT 4
906#define PALMAS_LDO7_CTRL_MODE_SLEEP 0x04
907#define PALMAS_LDO7_CTRL_MODE_SLEEP_SHIFT 2
908#define PALMAS_LDO7_CTRL_MODE_ACTIVE 0x01
909#define PALMAS_LDO7_CTRL_MODE_ACTIVE_SHIFT 0
910
911/* Bit definitions for LDO7_VOLTAGE */
912#define PALMAS_LDO7_VOLTAGE_VSEL_MASK 0x3f
913#define PALMAS_LDO7_VOLTAGE_VSEL_SHIFT 0
914
915/* Bit definitions for LDO8_CTRL */
916#define PALMAS_LDO8_CTRL_WR_S 0x80
917#define PALMAS_LDO8_CTRL_WR_S_SHIFT 7
918#define PALMAS_LDO8_CTRL_LDO_TRACKING_EN 0x40
919#define PALMAS_LDO8_CTRL_LDO_TRACKING_EN_SHIFT 6
920#define PALMAS_LDO8_CTRL_STATUS 0x10
921#define PALMAS_LDO8_CTRL_STATUS_SHIFT 4
922#define PALMAS_LDO8_CTRL_MODE_SLEEP 0x04
923#define PALMAS_LDO8_CTRL_MODE_SLEEP_SHIFT 2
924#define PALMAS_LDO8_CTRL_MODE_ACTIVE 0x01
925#define PALMAS_LDO8_CTRL_MODE_ACTIVE_SHIFT 0
926
927/* Bit definitions for LDO8_VOLTAGE */
928#define PALMAS_LDO8_VOLTAGE_VSEL_MASK 0x3f
929#define PALMAS_LDO8_VOLTAGE_VSEL_SHIFT 0
930
931/* Bit definitions for LDO9_CTRL */
932#define PALMAS_LDO9_CTRL_WR_S 0x80
933#define PALMAS_LDO9_CTRL_WR_S_SHIFT 7
934#define PALMAS_LDO9_CTRL_LDO_BYPASS_EN 0x40
935#define PALMAS_LDO9_CTRL_LDO_BYPASS_EN_SHIFT 6
936#define PALMAS_LDO9_CTRL_STATUS 0x10
937#define PALMAS_LDO9_CTRL_STATUS_SHIFT 4
938#define PALMAS_LDO9_CTRL_MODE_SLEEP 0x04
939#define PALMAS_LDO9_CTRL_MODE_SLEEP_SHIFT 2
940#define PALMAS_LDO9_CTRL_MODE_ACTIVE 0x01
941#define PALMAS_LDO9_CTRL_MODE_ACTIVE_SHIFT 0
942
943/* Bit definitions for LDO9_VOLTAGE */
944#define PALMAS_LDO9_VOLTAGE_VSEL_MASK 0x3f
945#define PALMAS_LDO9_VOLTAGE_VSEL_SHIFT 0
946
947/* Bit definitions for LDOLN_CTRL */
948#define PALMAS_LDOLN_CTRL_WR_S 0x80
949#define PALMAS_LDOLN_CTRL_WR_S_SHIFT 7
950#define PALMAS_LDOLN_CTRL_STATUS 0x10
951#define PALMAS_LDOLN_CTRL_STATUS_SHIFT 4
952#define PALMAS_LDOLN_CTRL_MODE_SLEEP 0x04
953#define PALMAS_LDOLN_CTRL_MODE_SLEEP_SHIFT 2
954#define PALMAS_LDOLN_CTRL_MODE_ACTIVE 0x01
955#define PALMAS_LDOLN_CTRL_MODE_ACTIVE_SHIFT 0
956
957/* Bit definitions for LDOLN_VOLTAGE */
958#define PALMAS_LDOLN_VOLTAGE_VSEL_MASK 0x3f
959#define PALMAS_LDOLN_VOLTAGE_VSEL_SHIFT 0
960
961/* Bit definitions for LDOUSB_CTRL */
962#define PALMAS_LDOUSB_CTRL_WR_S 0x80
963#define PALMAS_LDOUSB_CTRL_WR_S_SHIFT 7
964#define PALMAS_LDOUSB_CTRL_STATUS 0x10
965#define PALMAS_LDOUSB_CTRL_STATUS_SHIFT 4
966#define PALMAS_LDOUSB_CTRL_MODE_SLEEP 0x04
967#define PALMAS_LDOUSB_CTRL_MODE_SLEEP_SHIFT 2
968#define PALMAS_LDOUSB_CTRL_MODE_ACTIVE 0x01
969#define PALMAS_LDOUSB_CTRL_MODE_ACTIVE_SHIFT 0
970
971/* Bit definitions for LDOUSB_VOLTAGE */
972#define PALMAS_LDOUSB_VOLTAGE_VSEL_MASK 0x3f
973#define PALMAS_LDOUSB_VOLTAGE_VSEL_SHIFT 0
974
975/* Bit definitions for LDO_CTRL */
976#define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS 0x01
977#define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_SHIFT 0
978
979/* Bit definitions for LDO_PD_CTRL1 */
980#define PALMAS_LDO_PD_CTRL1_LDO8 0x80
981#define PALMAS_LDO_PD_CTRL1_LDO8_SHIFT 7
982#define PALMAS_LDO_PD_CTRL1_LDO7 0x40
983#define PALMAS_LDO_PD_CTRL1_LDO7_SHIFT 6
984#define PALMAS_LDO_PD_CTRL1_LDO6 0x20
985#define PALMAS_LDO_PD_CTRL1_LDO6_SHIFT 5
986#define PALMAS_LDO_PD_CTRL1_LDO5 0x10
987#define PALMAS_LDO_PD_CTRL1_LDO5_SHIFT 4
988#define PALMAS_LDO_PD_CTRL1_LDO4 0x08
989#define PALMAS_LDO_PD_CTRL1_LDO4_SHIFT 3
990#define PALMAS_LDO_PD_CTRL1_LDO3 0x04
991#define PALMAS_LDO_PD_CTRL1_LDO3_SHIFT 2
992#define PALMAS_LDO_PD_CTRL1_LDO2 0x02
993#define PALMAS_LDO_PD_CTRL1_LDO2_SHIFT 1
994#define PALMAS_LDO_PD_CTRL1_LDO1 0x01
995#define PALMAS_LDO_PD_CTRL1_LDO1_SHIFT 0
996
997/* Bit definitions for LDO_PD_CTRL2 */
998#define PALMAS_LDO_PD_CTRL2_LDOUSB 0x04
999#define PALMAS_LDO_PD_CTRL2_LDOUSB_SHIFT 2
1000#define PALMAS_LDO_PD_CTRL2_LDOLN 0x02
1001#define PALMAS_LDO_PD_CTRL2_LDOLN_SHIFT 1
1002#define PALMAS_LDO_PD_CTRL2_LDO9 0x01
1003#define PALMAS_LDO_PD_CTRL2_LDO9_SHIFT 0
1004
1005/* Bit definitions for LDO_SHORT_STATUS1 */
1006#define PALMAS_LDO_SHORT_STATUS1_LDO8 0x80
1007#define PALMAS_LDO_SHORT_STATUS1_LDO8_SHIFT 7
1008#define PALMAS_LDO_SHORT_STATUS1_LDO7 0x40
1009#define PALMAS_LDO_SHORT_STATUS1_LDO7_SHIFT 6
1010#define PALMAS_LDO_SHORT_STATUS1_LDO6 0x20
1011#define PALMAS_LDO_SHORT_STATUS1_LDO6_SHIFT 5
1012#define PALMAS_LDO_SHORT_STATUS1_LDO5 0x10
1013#define PALMAS_LDO_SHORT_STATUS1_LDO5_SHIFT 4
1014#define PALMAS_LDO_SHORT_STATUS1_LDO4 0x08
1015#define PALMAS_LDO_SHORT_STATUS1_LDO4_SHIFT 3
1016#define PALMAS_LDO_SHORT_STATUS1_LDO3 0x04
1017#define PALMAS_LDO_SHORT_STATUS1_LDO3_SHIFT 2
1018#define PALMAS_LDO_SHORT_STATUS1_LDO2 0x02
1019#define PALMAS_LDO_SHORT_STATUS1_LDO2_SHIFT 1
1020#define PALMAS_LDO_SHORT_STATUS1_LDO1 0x01
1021#define PALMAS_LDO_SHORT_STATUS1_LDO1_SHIFT 0
1022
1023/* Bit definitions for LDO_SHORT_STATUS2 */
1024#define PALMAS_LDO_SHORT_STATUS2_LDOVANA 0x08
1025#define PALMAS_LDO_SHORT_STATUS2_LDOVANA_SHIFT 3
1026#define PALMAS_LDO_SHORT_STATUS2_LDOUSB 0x04
1027#define PALMAS_LDO_SHORT_STATUS2_LDOUSB_SHIFT 2
1028#define PALMAS_LDO_SHORT_STATUS2_LDOLN 0x02
1029#define PALMAS_LDO_SHORT_STATUS2_LDOLN_SHIFT 1
1030#define PALMAS_LDO_SHORT_STATUS2_LDO9 0x01
1031#define PALMAS_LDO_SHORT_STATUS2_LDO9_SHIFT 0
1032
1033/* Registers for function PMU_CONTROL */
1034#define PALMAS_DEV_CTRL 0x0
1035#define PALMAS_POWER_CTRL 0x1
1036#define PALMAS_VSYS_LO 0x2
1037#define PALMAS_VSYS_MON 0x3
1038#define PALMAS_VBAT_MON 0x4
1039#define PALMAS_WATCHDOG 0x5
1040#define PALMAS_BOOT_STATUS 0x6
1041#define PALMAS_BATTERY_BOUNCE 0x7
1042#define PALMAS_BACKUP_BATTERY_CTRL 0x8
1043#define PALMAS_LONG_PRESS_KEY 0x9
1044#define PALMAS_OSC_THERM_CTRL 0xA
1045#define PALMAS_BATDEBOUNCING 0xB
1046#define PALMAS_SWOFF_HWRST 0xF
1047#define PALMAS_SWOFF_COLDRST 0x10
1048#define PALMAS_SWOFF_STATUS 0x11
1049#define PALMAS_PMU_CONFIG 0x12
1050#define PALMAS_SPARE 0x14
1051#define PALMAS_PMU_SECONDARY_INT 0x15
1052#define PALMAS_SW_REVISION 0x17
1053#define PALMAS_EXT_CHRG_CTRL 0x18
1054#define PALMAS_PMU_SECONDARY_INT2 0x19
1055
1056/* Bit definitions for DEV_CTRL */
1057#define PALMAS_DEV_CTRL_DEV_STATUS_MASK 0x0c
1058#define PALMAS_DEV_CTRL_DEV_STATUS_SHIFT 2
1059#define PALMAS_DEV_CTRL_SW_RST 0x02
1060#define PALMAS_DEV_CTRL_SW_RST_SHIFT 1
1061#define PALMAS_DEV_CTRL_DEV_ON 0x01
1062#define PALMAS_DEV_CTRL_DEV_ON_SHIFT 0
1063
1064/* Bit definitions for POWER_CTRL */
1065#define PALMAS_POWER_CTRL_ENABLE2_MASK 0x04
1066#define PALMAS_POWER_CTRL_ENABLE2_MASK_SHIFT 2
1067#define PALMAS_POWER_CTRL_ENABLE1_MASK 0x02
1068#define PALMAS_POWER_CTRL_ENABLE1_MASK_SHIFT 1
1069#define PALMAS_POWER_CTRL_NSLEEP_MASK 0x01
1070#define PALMAS_POWER_CTRL_NSLEEP_MASK_SHIFT 0
1071
1072/* Bit definitions for VSYS_LO */
1073#define PALMAS_VSYS_LO_THRESHOLD_MASK 0x1f
1074#define PALMAS_VSYS_LO_THRESHOLD_SHIFT 0
1075
1076/* Bit definitions for VSYS_MON */
1077#define PALMAS_VSYS_MON_ENABLE 0x80
1078#define PALMAS_VSYS_MON_ENABLE_SHIFT 7
1079#define PALMAS_VSYS_MON_THRESHOLD_MASK 0x3f
1080#define PALMAS_VSYS_MON_THRESHOLD_SHIFT 0
1081
1082/* Bit definitions for VBAT_MON */
1083#define PALMAS_VBAT_MON_ENABLE 0x80
1084#define PALMAS_VBAT_MON_ENABLE_SHIFT 7
1085#define PALMAS_VBAT_MON_THRESHOLD_MASK 0x3f
1086#define PALMAS_VBAT_MON_THRESHOLD_SHIFT 0
1087
1088/* Bit definitions for WATCHDOG */
1089#define PALMAS_WATCHDOG_LOCK 0x20
1090#define PALMAS_WATCHDOG_LOCK_SHIFT 5
1091#define PALMAS_WATCHDOG_ENABLE 0x10
1092#define PALMAS_WATCHDOG_ENABLE_SHIFT 4
1093#define PALMAS_WATCHDOG_MODE 0x08
1094#define PALMAS_WATCHDOG_MODE_SHIFT 3
1095#define PALMAS_WATCHDOG_TIMER_MASK 0x07
1096#define PALMAS_WATCHDOG_TIMER_SHIFT 0
1097
1098/* Bit definitions for BOOT_STATUS */
1099#define PALMAS_BOOT_STATUS_BOOT1 0x02
1100#define PALMAS_BOOT_STATUS_BOOT1_SHIFT 1
1101#define PALMAS_BOOT_STATUS_BOOT0 0x01
1102#define PALMAS_BOOT_STATUS_BOOT0_SHIFT 0
1103
1104/* Bit definitions for BATTERY_BOUNCE */
1105#define PALMAS_BATTERY_BOUNCE_BB_DELAY_MASK 0x3f
1106#define PALMAS_BATTERY_BOUNCE_BB_DELAY_SHIFT 0
1107
1108/* Bit definitions for BACKUP_BATTERY_CTRL */
1109#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15 0x80
1110#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15_SHIFT 7
1111#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP 0x40
1112#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP_SHIFT 6
1113#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF 0x20
1114#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF_SHIFT 5
1115#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN 0x10
1116#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN_SHIFT 4
1117#define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG 0x08
1118#define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG_SHIFT 3
1119#define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_MASK 0x06
1120#define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_SHIFT 1
1121#define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN 0x01
1122#define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN_SHIFT 0
1123
1124/* Bit definitions for LONG_PRESS_KEY */
1125#define PALMAS_LONG_PRESS_KEY_LPK_LOCK 0x80
1126#define PALMAS_LONG_PRESS_KEY_LPK_LOCK_SHIFT 7
1127#define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR 0x10
1128#define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR_SHIFT 4
1129#define PALMAS_LONG_PRESS_KEY_LPK_TIME_MASK 0x0c
1130#define PALMAS_LONG_PRESS_KEY_LPK_TIME_SHIFT 2
1131#define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_MASK 0x03
1132#define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_SHIFT 0
1133
1134/* Bit definitions for OSC_THERM_CTRL */
1135#define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP 0x80
1136#define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP_SHIFT 7
1137#define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP 0x40
1138#define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP_SHIFT 6
1139#define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP 0x20
1140#define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP_SHIFT 5
1141#define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP 0x10
1142#define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP_SHIFT 4
1143#define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_MASK 0x0c
1144#define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_SHIFT 2
1145#define PALMAS_OSC_THERM_CTRL_OSC_BYPASS 0x02
1146#define PALMAS_OSC_THERM_CTRL_OSC_BYPASS_SHIFT 1
1147#define PALMAS_OSC_THERM_CTRL_OSC_HPMODE 0x01
1148#define PALMAS_OSC_THERM_CTRL_OSC_HPMODE_SHIFT 0
1149
1150/* Bit definitions for BATDEBOUNCING */
1151#define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS 0x80
1152#define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS_SHIFT 7
1153#define PALMAS_BATDEBOUNCING_BINS_DEB_MASK 0x78
1154#define PALMAS_BATDEBOUNCING_BINS_DEB_SHIFT 3
1155#define PALMAS_BATDEBOUNCING_BEXT_DEB_MASK 0x07
1156#define PALMAS_BATDEBOUNCING_BEXT_DEB_SHIFT 0
1157
1158/* Bit definitions for SWOFF_HWRST */
1159#define PALMAS_SWOFF_HWRST_PWRON_LPK 0x80
1160#define PALMAS_SWOFF_HWRST_PWRON_LPK_SHIFT 7
1161#define PALMAS_SWOFF_HWRST_PWRDOWN 0x40
1162#define PALMAS_SWOFF_HWRST_PWRDOWN_SHIFT 6
1163#define PALMAS_SWOFF_HWRST_WTD 0x20
1164#define PALMAS_SWOFF_HWRST_WTD_SHIFT 5
1165#define PALMAS_SWOFF_HWRST_TSHUT 0x10
1166#define PALMAS_SWOFF_HWRST_TSHUT_SHIFT 4
1167#define PALMAS_SWOFF_HWRST_RESET_IN 0x08
1168#define PALMAS_SWOFF_HWRST_RESET_IN_SHIFT 3
1169#define PALMAS_SWOFF_HWRST_SW_RST 0x04
1170#define PALMAS_SWOFF_HWRST_SW_RST_SHIFT 2
1171#define PALMAS_SWOFF_HWRST_VSYS_LO 0x02
1172#define PALMAS_SWOFF_HWRST_VSYS_LO_SHIFT 1
1173#define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN 0x01
1174#define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN_SHIFT 0
1175
1176/* Bit definitions for SWOFF_COLDRST */
1177#define PALMAS_SWOFF_COLDRST_PWRON_LPK 0x80
1178#define PALMAS_SWOFF_COLDRST_PWRON_LPK_SHIFT 7
1179#define PALMAS_SWOFF_COLDRST_PWRDOWN 0x40
1180#define PALMAS_SWOFF_COLDRST_PWRDOWN_SHIFT 6
1181#define PALMAS_SWOFF_COLDRST_WTD 0x20
1182#define PALMAS_SWOFF_COLDRST_WTD_SHIFT 5
1183#define PALMAS_SWOFF_COLDRST_TSHUT 0x10
1184#define PALMAS_SWOFF_COLDRST_TSHUT_SHIFT 4
1185#define PALMAS_SWOFF_COLDRST_RESET_IN 0x08
1186#define PALMAS_SWOFF_COLDRST_RESET_IN_SHIFT 3
1187#define PALMAS_SWOFF_COLDRST_SW_RST 0x04
1188#define PALMAS_SWOFF_COLDRST_SW_RST_SHIFT 2
1189#define PALMAS_SWOFF_COLDRST_VSYS_LO 0x02
1190#define PALMAS_SWOFF_COLDRST_VSYS_LO_SHIFT 1
1191#define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN 0x01
1192#define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN_SHIFT 0
1193
1194/* Bit definitions for SWOFF_STATUS */
1195#define PALMAS_SWOFF_STATUS_PWRON_LPK 0x80
1196#define PALMAS_SWOFF_STATUS_PWRON_LPK_SHIFT 7
1197#define PALMAS_SWOFF_STATUS_PWRDOWN 0x40
1198#define PALMAS_SWOFF_STATUS_PWRDOWN_SHIFT 6
1199#define PALMAS_SWOFF_STATUS_WTD 0x20
1200#define PALMAS_SWOFF_STATUS_WTD_SHIFT 5
1201#define PALMAS_SWOFF_STATUS_TSHUT 0x10
1202#define PALMAS_SWOFF_STATUS_TSHUT_SHIFT 4
1203#define PALMAS_SWOFF_STATUS_RESET_IN 0x08
1204#define PALMAS_SWOFF_STATUS_RESET_IN_SHIFT 3
1205#define PALMAS_SWOFF_STATUS_SW_RST 0x04
1206#define PALMAS_SWOFF_STATUS_SW_RST_SHIFT 2
1207#define PALMAS_SWOFF_STATUS_VSYS_LO 0x02
1208#define PALMAS_SWOFF_STATUS_VSYS_LO_SHIFT 1
1209#define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN 0x01
1210#define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN_SHIFT 0
1211
1212/* Bit definitions for PMU_CONFIG */
1213#define PALMAS_PMU_CONFIG_MULTI_CELL_EN 0x40
1214#define PALMAS_PMU_CONFIG_MULTI_CELL_EN_SHIFT 6
1215#define PALMAS_PMU_CONFIG_SPARE_MASK 0x30
1216#define PALMAS_PMU_CONFIG_SPARE_SHIFT 4
1217#define PALMAS_PMU_CONFIG_SWOFF_DLY_MASK 0x0c
1218#define PALMAS_PMU_CONFIG_SWOFF_DLY_SHIFT 2
1219#define PALMAS_PMU_CONFIG_GATE_RESET_OUT 0x02
1220#define PALMAS_PMU_CONFIG_GATE_RESET_OUT_SHIFT 1
1221#define PALMAS_PMU_CONFIG_AUTODEVON 0x01
1222#define PALMAS_PMU_CONFIG_AUTODEVON_SHIFT 0
1223
1224/* Bit definitions for SPARE */
1225#define PALMAS_SPARE_SPARE_MASK 0xf8
1226#define PALMAS_SPARE_SPARE_SHIFT 3
1227#define PALMAS_SPARE_REGEN3_OD 0x04
1228#define PALMAS_SPARE_REGEN3_OD_SHIFT 2
1229#define PALMAS_SPARE_REGEN2_OD 0x02
1230#define PALMAS_SPARE_REGEN2_OD_SHIFT 1
1231#define PALMAS_SPARE_REGEN1_OD 0x01
1232#define PALMAS_SPARE_REGEN1_OD_SHIFT 0
1233
1234/* Bit definitions for PMU_SECONDARY_INT */
1235#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC 0x80
1236#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC_SHIFT 7
1237#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC 0x40
1238#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC_SHIFT 6
1239#define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC 0x20
1240#define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC_SHIFT 5
1241#define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC 0x10
1242#define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC_SHIFT 4
1243#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK 0x08
1244#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK_SHIFT 3
1245#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK 0x04
1246#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK_SHIFT 2
1247#define PALMAS_PMU_SECONDARY_INT_BB_MASK 0x02
1248#define PALMAS_PMU_SECONDARY_INT_BB_MASK_SHIFT 1
1249#define PALMAS_PMU_SECONDARY_INT_FBI_MASK 0x01
1250#define PALMAS_PMU_SECONDARY_INT_FBI_MASK_SHIFT 0
1251
1252/* Bit definitions for SW_REVISION */
1253#define PALMAS_SW_REVISION_SW_REVISION_MASK 0xff
1254#define PALMAS_SW_REVISION_SW_REVISION_SHIFT 0
1255
1256/* Bit definitions for EXT_CHRG_CTRL */
1257#define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS 0x80
1258#define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS_SHIFT 7
1259#define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS 0x40
1260#define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS_SHIFT 6
1261#define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY 0x08
1262#define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY_SHIFT 3
1263#define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N 0x04
1264#define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N_SHIFT 2
1265#define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN 0x02
1266#define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN_SHIFT 1
1267#define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN 0x01
1268#define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN_SHIFT 0
1269
1270/* Bit definitions for PMU_SECONDARY_INT2 */
1271#define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC 0x20
1272#define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC_SHIFT 5
1273#define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC 0x10
1274#define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC_SHIFT 4
1275#define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK 0x02
1276#define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK_SHIFT 1
1277#define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK 0x01
1278#define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK_SHIFT 0
1279
1280/* Registers for function RESOURCE */
1281#define PALMAS_CLK32KG_CTRL 0x0
1282#define PALMAS_CLK32KGAUDIO_CTRL 0x1
1283#define PALMAS_REGEN1_CTRL 0x2
1284#define PALMAS_REGEN2_CTRL 0x3
1285#define PALMAS_SYSEN1_CTRL 0x4
1286#define PALMAS_SYSEN2_CTRL 0x5
1287#define PALMAS_NSLEEP_RES_ASSIGN 0x6
1288#define PALMAS_NSLEEP_SMPS_ASSIGN 0x7
1289#define PALMAS_NSLEEP_LDO_ASSIGN1 0x8
1290#define PALMAS_NSLEEP_LDO_ASSIGN2 0x9
1291#define PALMAS_ENABLE1_RES_ASSIGN 0xA
1292#define PALMAS_ENABLE1_SMPS_ASSIGN 0xB
1293#define PALMAS_ENABLE1_LDO_ASSIGN1 0xC
1294#define PALMAS_ENABLE1_LDO_ASSIGN2 0xD
1295#define PALMAS_ENABLE2_RES_ASSIGN 0xE
1296#define PALMAS_ENABLE2_SMPS_ASSIGN 0xF
1297#define PALMAS_ENABLE2_LDO_ASSIGN1 0x10
1298#define PALMAS_ENABLE2_LDO_ASSIGN2 0x11
1299#define PALMAS_REGEN3_CTRL 0x12
1300
1301/* Bit definitions for CLK32KG_CTRL */
1302#define PALMAS_CLK32KG_CTRL_STATUS 0x10
1303#define PALMAS_CLK32KG_CTRL_STATUS_SHIFT 4
1304#define PALMAS_CLK32KG_CTRL_MODE_SLEEP 0x04
1305#define PALMAS_CLK32KG_CTRL_MODE_SLEEP_SHIFT 2
1306#define PALMAS_CLK32KG_CTRL_MODE_ACTIVE 0x01
1307#define PALMAS_CLK32KG_CTRL_MODE_ACTIVE_SHIFT 0
1308
1309/* Bit definitions for CLK32KGAUDIO_CTRL */
1310#define PALMAS_CLK32KGAUDIO_CTRL_STATUS 0x10
1311#define PALMAS_CLK32KGAUDIO_CTRL_STATUS_SHIFT 4
1312#define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3 0x08
1313#define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3_SHIFT 3
1314#define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP 0x04
1315#define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP_SHIFT 2
1316#define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE 0x01
1317#define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE_SHIFT 0
1318
1319/* Bit definitions for REGEN1_CTRL */
1320#define PALMAS_REGEN1_CTRL_STATUS 0x10
1321#define PALMAS_REGEN1_CTRL_STATUS_SHIFT 4
1322#define PALMAS_REGEN1_CTRL_MODE_SLEEP 0x04
1323#define PALMAS_REGEN1_CTRL_MODE_SLEEP_SHIFT 2
1324#define PALMAS_REGEN1_CTRL_MODE_ACTIVE 0x01
1325#define PALMAS_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0
1326
1327/* Bit definitions for REGEN2_CTRL */
1328#define PALMAS_REGEN2_CTRL_STATUS 0x10
1329#define PALMAS_REGEN2_CTRL_STATUS_SHIFT 4
1330#define PALMAS_REGEN2_CTRL_MODE_SLEEP 0x04
1331#define PALMAS_REGEN2_CTRL_MODE_SLEEP_SHIFT 2
1332#define PALMAS_REGEN2_CTRL_MODE_ACTIVE 0x01
1333#define PALMAS_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0
1334
1335/* Bit definitions for SYSEN1_CTRL */
1336#define PALMAS_SYSEN1_CTRL_STATUS 0x10
1337#define PALMAS_SYSEN1_CTRL_STATUS_SHIFT 4
1338#define PALMAS_SYSEN1_CTRL_MODE_SLEEP 0x04
1339#define PALMAS_SYSEN1_CTRL_MODE_SLEEP_SHIFT 2
1340#define PALMAS_SYSEN1_CTRL_MODE_ACTIVE 0x01
1341#define PALMAS_SYSEN1_CTRL_MODE_ACTIVE_SHIFT 0
1342
1343/* Bit definitions for SYSEN2_CTRL */
1344#define PALMAS_SYSEN2_CTRL_STATUS 0x10
1345#define PALMAS_SYSEN2_CTRL_STATUS_SHIFT 4
1346#define PALMAS_SYSEN2_CTRL_MODE_SLEEP 0x04
1347#define PALMAS_SYSEN2_CTRL_MODE_SLEEP_SHIFT 2
1348#define PALMAS_SYSEN2_CTRL_MODE_ACTIVE 0x01
1349#define PALMAS_SYSEN2_CTRL_MODE_ACTIVE_SHIFT 0
1350
1351/* Bit definitions for NSLEEP_RES_ASSIGN */
1352#define PALMAS_NSLEEP_RES_ASSIGN_REGEN3 0x40
1353#define PALMAS_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 6
1354#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO 0x20
1355#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO_SHIFT 5
1356#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG 0x10
1357#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG_SHIFT 4
1358#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2 0x08
1359#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2_SHIFT 3
1360#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1 0x04
1361#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1_SHIFT 2
1362#define PALMAS_NSLEEP_RES_ASSIGN_REGEN2 0x02
1363#define PALMAS_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 1
1364#define PALMAS_NSLEEP_RES_ASSIGN_REGEN1 0x01
1365#define PALMAS_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0
1366
1367/* Bit definitions for NSLEEP_SMPS_ASSIGN */
1368#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10 0x80
1369#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10_SHIFT 7
1370#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9 0x40
1371#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9_SHIFT 6
1372#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8 0x20
1373#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8_SHIFT 5
1374#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7 0x10
1375#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7_SHIFT 4
1376#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6 0x08
1377#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6_SHIFT 3
1378#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45 0x04
1379#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45_SHIFT 2
1380#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3 0x02
1381#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 1
1382#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12 0x01
1383#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12_SHIFT 0
1384
1385/* Bit definitions for NSLEEP_LDO_ASSIGN1 */
1386#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8 0x80
1387#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8_SHIFT 7
1388#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7 0x40
1389#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7_SHIFT 6
1390#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6 0x20
1391#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6_SHIFT 5
1392#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5 0x10
1393#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5_SHIFT 4
1394#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4 0x08
1395#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 3
1396#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3 0x04
1397#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3_SHIFT 2
1398#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2 0x02
1399#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 1
1400#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1 0x01
1401#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0
1402
1403/* Bit definitions for NSLEEP_LDO_ASSIGN2 */
1404#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB 0x04
1405#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB_SHIFT 2
1406#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN 0x02
1407#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN_SHIFT 1
1408#define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9 0x01
1409#define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9_SHIFT 0
1410
1411/* Bit definitions for ENABLE1_RES_ASSIGN */
1412#define PALMAS_ENABLE1_RES_ASSIGN_REGEN3 0x40
1413#define PALMAS_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 6
1414#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO 0x20
1415#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO_SHIFT 5
1416#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG 0x10
1417#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG_SHIFT 4
1418#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2 0x08
1419#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2_SHIFT 3
1420#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1 0x04
1421#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1_SHIFT 2
1422#define PALMAS_ENABLE1_RES_ASSIGN_REGEN2 0x02
1423#define PALMAS_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 1
1424#define PALMAS_ENABLE1_RES_ASSIGN_REGEN1 0x01
1425#define PALMAS_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0
1426
1427/* Bit definitions for ENABLE1_SMPS_ASSIGN */
1428#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10 0x80
1429#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10_SHIFT 7
1430#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9 0x40
1431#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9_SHIFT 6
1432#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8 0x20
1433#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8_SHIFT 5
1434#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7 0x10
1435#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7_SHIFT 4
1436#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6 0x08
1437#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6_SHIFT 3
1438#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45 0x04
1439#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45_SHIFT 2
1440#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3 0x02
1441#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 1
1442#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12 0x01
1443#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12_SHIFT 0
1444
1445/* Bit definitions for ENABLE1_LDO_ASSIGN1 */
1446#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8 0x80
1447#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8_SHIFT 7
1448#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7 0x40
1449#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7_SHIFT 6
1450#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6 0x20
1451#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6_SHIFT 5
1452#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5 0x10
1453#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5_SHIFT 4
1454#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4 0x08
1455#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 3
1456#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3 0x04
1457#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3_SHIFT 2
1458#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2 0x02
1459#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 1
1460#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1 0x01
1461#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0
1462
1463/* Bit definitions for ENABLE1_LDO_ASSIGN2 */
1464#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB 0x04
1465#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB_SHIFT 2
1466#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN 0x02
1467#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN_SHIFT 1
1468#define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9 0x01
1469#define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9_SHIFT 0
1470
1471/* Bit definitions for ENABLE2_RES_ASSIGN */
1472#define PALMAS_ENABLE2_RES_ASSIGN_REGEN3 0x40
1473#define PALMAS_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 6
1474#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO 0x20
1475#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO_SHIFT 5
1476#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG 0x10
1477#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG_SHIFT 4
1478#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2 0x08
1479#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2_SHIFT 3
1480#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1 0x04
1481#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1_SHIFT 2
1482#define PALMAS_ENABLE2_RES_ASSIGN_REGEN2 0x02
1483#define PALMAS_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 1
1484#define PALMAS_ENABLE2_RES_ASSIGN_REGEN1 0x01
1485#define PALMAS_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0
1486
1487/* Bit definitions for ENABLE2_SMPS_ASSIGN */
1488#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10 0x80
1489#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10_SHIFT 7
1490#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9 0x40
1491#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9_SHIFT 6
1492#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8 0x20
1493#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8_SHIFT 5
1494#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7 0x10
1495#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7_SHIFT 4
1496#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6 0x08
1497#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6_SHIFT 3
1498#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45 0x04
1499#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45_SHIFT 2
1500#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3 0x02
1501#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 1
1502#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12 0x01
1503#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12_SHIFT 0
1504
1505/* Bit definitions for ENABLE2_LDO_ASSIGN1 */
1506#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8 0x80
1507#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8_SHIFT 7
1508#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7 0x40
1509#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7_SHIFT 6
1510#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6 0x20
1511#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6_SHIFT 5
1512#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5 0x10
1513#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5_SHIFT 4
1514#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4 0x08
1515#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 3
1516#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3 0x04
1517#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3_SHIFT 2
1518#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2 0x02
1519#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 1
1520#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1 0x01
1521#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0
1522
1523/* Bit definitions for ENABLE2_LDO_ASSIGN2 */
1524#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB 0x04
1525#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB_SHIFT 2
1526#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN 0x02
1527#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN_SHIFT 1
1528#define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9 0x01
1529#define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9_SHIFT 0
1530
1531/* Bit definitions for REGEN3_CTRL */
1532#define PALMAS_REGEN3_CTRL_STATUS 0x10
1533#define PALMAS_REGEN3_CTRL_STATUS_SHIFT 4
1534#define PALMAS_REGEN3_CTRL_MODE_SLEEP 0x04
1535#define PALMAS_REGEN3_CTRL_MODE_SLEEP_SHIFT 2
1536#define PALMAS_REGEN3_CTRL_MODE_ACTIVE 0x01
1537#define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0
1538
1539/* Registers for function PAD_CONTROL */
1540#define PALMAS_PU_PD_INPUT_CTRL1 0x0
1541#define PALMAS_PU_PD_INPUT_CTRL2 0x1
1542#define PALMAS_PU_PD_INPUT_CTRL3 0x2
1543#define PALMAS_OD_OUTPUT_CTRL 0x4
1544#define PALMAS_POLARITY_CTRL 0x5
1545#define PALMAS_PRIMARY_SECONDARY_PAD1 0x6
1546#define PALMAS_PRIMARY_SECONDARY_PAD2 0x7
1547#define PALMAS_I2C_SPI 0x8
1548#define PALMAS_PU_PD_INPUT_CTRL4 0x9
1549#define PALMAS_PRIMARY_SECONDARY_PAD3 0xA
1550
1551/* Bit definitions for PU_PD_INPUT_CTRL1 */
1552#define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD 0x40
1553#define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD_SHIFT 6
1554#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU 0x20
1555#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU_SHIFT 5
1556#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD 0x10
1557#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD_SHIFT 4
1558#define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD 0x04
1559#define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD_SHIFT 2
1560#define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU 0x02
1561#define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU_SHIFT 1
1562
1563/* Bit definitions for PU_PD_INPUT_CTRL2 */
1564#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU 0x20
1565#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU_SHIFT 5
1566#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD 0x10
1567#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD_SHIFT 4
1568#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU 0x08
1569#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU_SHIFT 3
1570#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD 0x04
1571#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD_SHIFT 2
1572#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU 0x02
1573#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU_SHIFT 1
1574#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD 0x01
1575#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD_SHIFT 0
1576
1577/* Bit definitions for PU_PD_INPUT_CTRL3 */
1578#define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD 0x40
1579#define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD_SHIFT 6
1580#define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD 0x10
1581#define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD_SHIFT 4
1582#define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD 0x04
1583#define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD_SHIFT 2
1584#define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD 0x01
1585#define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD_SHIFT 0
1586
1587/* Bit definitions for OD_OUTPUT_CTRL */
1588#define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD 0x80
1589#define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD_SHIFT 7
1590#define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD 0x40
1591#define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD_SHIFT 6
1592#define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD 0x20
1593#define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD_SHIFT 5
1594#define PALMAS_OD_OUTPUT_CTRL_INT_OD 0x08
1595#define PALMAS_OD_OUTPUT_CTRL_INT_OD_SHIFT 3
1596
1597/* Bit definitions for POLARITY_CTRL */
1598#define PALMAS_POLARITY_CTRL_INT_POLARITY 0x80
1599#define PALMAS_POLARITY_CTRL_INT_POLARITY_SHIFT 7
1600#define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY 0x40
1601#define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY_SHIFT 6
1602#define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY 0x20
1603#define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY_SHIFT 5
1604#define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY 0x10
1605#define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY_SHIFT 4
1606#define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY 0x08
1607#define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY_SHIFT 3
1608#define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY 0x04
1609#define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY_SHIFT 2
1610#define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY 0x02
1611#define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY_SHIFT 1
1612#define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY 0x01
1613#define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY_SHIFT 0
1614
1615/* Bit definitions for PRIMARY_SECONDARY_PAD1 */
1616#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3 0x80
1617#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3_SHIFT 7
1618#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK 0x60
1619#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT 5
1620#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK 0x18
1621#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT 3
1622#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0 0x04
1623#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0_SHIFT 2
1624#define PALMAS_PRIMARY_SECONDARY_PAD1_VAC 0x02
1625#define PALMAS_PRIMARY_SECONDARY_PAD1_VAC_SHIFT 1
1626#define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD 0x01
1627#define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD_SHIFT 0
1628
1629/* Bit definitions for PRIMARY_SECONDARY_PAD2 */
1630#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK 0x30
1631#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_SHIFT 4
1632#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6 0x08
1633#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6_SHIFT 3
1634#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK 0x06
1635#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT 1
1636#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4 0x01
1637#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_SHIFT 0
1638
1639/* Bit definitions for I2C_SPI */
1640#define PALMAS_I2C_SPI_I2C2OTP_EN 0x80
1641#define PALMAS_I2C_SPI_I2C2OTP_EN_SHIFT 7
1642#define PALMAS_I2C_SPI_I2C2OTP_PAGESEL 0x40
1643#define PALMAS_I2C_SPI_I2C2OTP_PAGESEL_SHIFT 6
1644#define PALMAS_I2C_SPI_ID_I2C2 0x20
1645#define PALMAS_I2C_SPI_ID_I2C2_SHIFT 5
1646#define PALMAS_I2C_SPI_I2C_SPI 0x10
1647#define PALMAS_I2C_SPI_I2C_SPI_SHIFT 4
1648#define PALMAS_I2C_SPI_ID_I2C1_MASK 0x0f
1649#define PALMAS_I2C_SPI_ID_I2C1_SHIFT 0
1650
1651/* Bit definitions for PU_PD_INPUT_CTRL4 */
1652#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD 0x40
1653#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD_SHIFT 6
1654#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD 0x10
1655#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD_SHIFT 4
1656#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD 0x04
1657#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD_SHIFT 2
1658#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD 0x01
1659#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD_SHIFT 0
1660
1661/* Bit definitions for PRIMARY_SECONDARY_PAD3 */
1662#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2 0x02
1663#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2_SHIFT 1
1664#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1 0x01
1665#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1_SHIFT 0
1666
1667/* Registers for function LED_PWM */
1668#define PALMAS_LED_PERIOD_CTRL 0x0
1669#define PALMAS_LED_CTRL 0x1
1670#define PALMAS_PWM_CTRL1 0x2
1671#define PALMAS_PWM_CTRL2 0x3
1672
1673/* Bit definitions for LED_PERIOD_CTRL */
1674#define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_MASK 0x38
1675#define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_SHIFT 3
1676#define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_MASK 0x07
1677#define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_SHIFT 0
1678
1679/* Bit definitions for LED_CTRL */
1680#define PALMAS_LED_CTRL_LED_2_SEQ 0x20
1681#define PALMAS_LED_CTRL_LED_2_SEQ_SHIFT 5
1682#define PALMAS_LED_CTRL_LED_1_SEQ 0x10
1683#define PALMAS_LED_CTRL_LED_1_SEQ_SHIFT 4
1684#define PALMAS_LED_CTRL_LED_2_ON_TIME_MASK 0x0c
1685#define PALMAS_LED_CTRL_LED_2_ON_TIME_SHIFT 2
1686#define PALMAS_LED_CTRL_LED_1_ON_TIME_MASK 0x03
1687#define PALMAS_LED_CTRL_LED_1_ON_TIME_SHIFT 0
1688
1689/* Bit definitions for PWM_CTRL1 */
1690#define PALMAS_PWM_CTRL1_PWM_FREQ_EN 0x02
1691#define PALMAS_PWM_CTRL1_PWM_FREQ_EN_SHIFT 1
1692#define PALMAS_PWM_CTRL1_PWM_FREQ_SEL 0x01
1693#define PALMAS_PWM_CTRL1_PWM_FREQ_SEL_SHIFT 0
1694
1695/* Bit definitions for PWM_CTRL2 */
1696#define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_MASK 0xff
1697#define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_SHIFT 0
1698
1699/* Registers for function INTERRUPT */
1700#define PALMAS_INT1_STATUS 0x0
1701#define PALMAS_INT1_MASK 0x1
1702#define PALMAS_INT1_LINE_STATE 0x2
1703#define PALMAS_INT1_EDGE_DETECT1_RESERVED 0x3
1704#define PALMAS_INT1_EDGE_DETECT2_RESERVED 0x4
1705#define PALMAS_INT2_STATUS 0x5
1706#define PALMAS_INT2_MASK 0x6
1707#define PALMAS_INT2_LINE_STATE 0x7
1708#define PALMAS_INT2_EDGE_DETECT1_RESERVED 0x8
1709#define PALMAS_INT2_EDGE_DETECT2_RESERVED 0x9
1710#define PALMAS_INT3_STATUS 0xA
1711#define PALMAS_INT3_MASK 0xB
1712#define PALMAS_INT3_LINE_STATE 0xC
1713#define PALMAS_INT3_EDGE_DETECT1_RESERVED 0xD
1714#define PALMAS_INT3_EDGE_DETECT2_RESERVED 0xE
1715#define PALMAS_INT4_STATUS 0xF
1716#define PALMAS_INT4_MASK 0x10
1717#define PALMAS_INT4_LINE_STATE 0x11
1718#define PALMAS_INT4_EDGE_DETECT1 0x12
1719#define PALMAS_INT4_EDGE_DETECT2 0x13
1720#define PALMAS_INT_CTRL 0x14
1721
1722/* Bit definitions for INT1_STATUS */
1723#define PALMAS_INT1_STATUS_VBAT_MON 0x80
1724#define PALMAS_INT1_STATUS_VBAT_MON_SHIFT 7
1725#define PALMAS_INT1_STATUS_VSYS_MON 0x40
1726#define PALMAS_INT1_STATUS_VSYS_MON_SHIFT 6
1727#define PALMAS_INT1_STATUS_HOTDIE 0x20
1728#define PALMAS_INT1_STATUS_HOTDIE_SHIFT 5
1729#define PALMAS_INT1_STATUS_PWRDOWN 0x10
1730#define PALMAS_INT1_STATUS_PWRDOWN_SHIFT 4
1731#define PALMAS_INT1_STATUS_RPWRON 0x08
1732#define PALMAS_INT1_STATUS_RPWRON_SHIFT 3
1733#define PALMAS_INT1_STATUS_LONG_PRESS_KEY 0x04
1734#define PALMAS_INT1_STATUS_LONG_PRESS_KEY_SHIFT 2
1735#define PALMAS_INT1_STATUS_PWRON 0x02
1736#define PALMAS_INT1_STATUS_PWRON_SHIFT 1
1737#define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV 0x01
1738#define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV_SHIFT 0
1739
1740/* Bit definitions for INT1_MASK */
1741#define PALMAS_INT1_MASK_VBAT_MON 0x80
1742#define PALMAS_INT1_MASK_VBAT_MON_SHIFT 7
1743#define PALMAS_INT1_MASK_VSYS_MON 0x40
1744#define PALMAS_INT1_MASK_VSYS_MON_SHIFT 6
1745#define PALMAS_INT1_MASK_HOTDIE 0x20
1746#define PALMAS_INT1_MASK_HOTDIE_SHIFT 5
1747#define PALMAS_INT1_MASK_PWRDOWN 0x10
1748#define PALMAS_INT1_MASK_PWRDOWN_SHIFT 4
1749#define PALMAS_INT1_MASK_RPWRON 0x08
1750#define PALMAS_INT1_MASK_RPWRON_SHIFT 3
1751#define PALMAS_INT1_MASK_LONG_PRESS_KEY 0x04
1752#define PALMAS_INT1_MASK_LONG_PRESS_KEY_SHIFT 2
1753#define PALMAS_INT1_MASK_PWRON 0x02
1754#define PALMAS_INT1_MASK_PWRON_SHIFT 1
1755#define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV 0x01
1756#define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV_SHIFT 0
1757
1758/* Bit definitions for INT1_LINE_STATE */
1759#define PALMAS_INT1_LINE_STATE_VBAT_MON 0x80
1760#define PALMAS_INT1_LINE_STATE_VBAT_MON_SHIFT 7
1761#define PALMAS_INT1_LINE_STATE_VSYS_MON 0x40
1762#define PALMAS_INT1_LINE_STATE_VSYS_MON_SHIFT 6
1763#define PALMAS_INT1_LINE_STATE_HOTDIE 0x20
1764#define PALMAS_INT1_LINE_STATE_HOTDIE_SHIFT 5
1765#define PALMAS_INT1_LINE_STATE_PWRDOWN 0x10
1766#define PALMAS_INT1_LINE_STATE_PWRDOWN_SHIFT 4
1767#define PALMAS_INT1_LINE_STATE_RPWRON 0x08
1768#define PALMAS_INT1_LINE_STATE_RPWRON_SHIFT 3
1769#define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY 0x04
1770#define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 2
1771#define PALMAS_INT1_LINE_STATE_PWRON 0x02
1772#define PALMAS_INT1_LINE_STATE_PWRON_SHIFT 1
1773#define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV 0x01
1774#define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV_SHIFT 0
1775
1776/* Bit definitions for INT2_STATUS */
1777#define PALMAS_INT2_STATUS_VAC_ACOK 0x80
1778#define PALMAS_INT2_STATUS_VAC_ACOK_SHIFT 7
1779#define PALMAS_INT2_STATUS_SHORT 0x40
1780#define PALMAS_INT2_STATUS_SHORT_SHIFT 6
1781#define PALMAS_INT2_STATUS_FBI_BB 0x20
1782#define PALMAS_INT2_STATUS_FBI_BB_SHIFT 5
1783#define PALMAS_INT2_STATUS_RESET_IN 0x10
1784#define PALMAS_INT2_STATUS_RESET_IN_SHIFT 4
1785#define PALMAS_INT2_STATUS_BATREMOVAL 0x08
1786#define PALMAS_INT2_STATUS_BATREMOVAL_SHIFT 3
1787#define PALMAS_INT2_STATUS_WDT 0x04
1788#define PALMAS_INT2_STATUS_WDT_SHIFT 2
1789#define PALMAS_INT2_STATUS_RTC_TIMER 0x02
1790#define PALMAS_INT2_STATUS_RTC_TIMER_SHIFT 1
1791#define PALMAS_INT2_STATUS_RTC_ALARM 0x01
1792#define PALMAS_INT2_STATUS_RTC_ALARM_SHIFT 0
1793
1794/* Bit definitions for INT2_MASK */
1795#define PALMAS_INT2_MASK_VAC_ACOK 0x80
1796#define PALMAS_INT2_MASK_VAC_ACOK_SHIFT 7
1797#define PALMAS_INT2_MASK_SHORT 0x40
1798#define PALMAS_INT2_MASK_SHORT_SHIFT 6
1799#define PALMAS_INT2_MASK_FBI_BB 0x20
1800#define PALMAS_INT2_MASK_FBI_BB_SHIFT 5
1801#define PALMAS_INT2_MASK_RESET_IN 0x10
1802#define PALMAS_INT2_MASK_RESET_IN_SHIFT 4
1803#define PALMAS_INT2_MASK_BATREMOVAL 0x08
1804#define PALMAS_INT2_MASK_BATREMOVAL_SHIFT 3
1805#define PALMAS_INT2_MASK_WDT 0x04
1806#define PALMAS_INT2_MASK_WDT_SHIFT 2
1807#define PALMAS_INT2_MASK_RTC_TIMER 0x02
1808#define PALMAS_INT2_MASK_RTC_TIMER_SHIFT 1
1809#define PALMAS_INT2_MASK_RTC_ALARM 0x01
1810#define PALMAS_INT2_MASK_RTC_ALARM_SHIFT 0
1811
1812/* Bit definitions for INT2_LINE_STATE */
1813#define PALMAS_INT2_LINE_STATE_VAC_ACOK 0x80
1814#define PALMAS_INT2_LINE_STATE_VAC_ACOK_SHIFT 7
1815#define PALMAS_INT2_LINE_STATE_SHORT 0x40
1816#define PALMAS_INT2_LINE_STATE_SHORT_SHIFT 6
1817#define PALMAS_INT2_LINE_STATE_FBI_BB 0x20
1818#define PALMAS_INT2_LINE_STATE_FBI_BB_SHIFT 5
1819#define PALMAS_INT2_LINE_STATE_RESET_IN 0x10
1820#define PALMAS_INT2_LINE_STATE_RESET_IN_SHIFT 4
1821#define PALMAS_INT2_LINE_STATE_BATREMOVAL 0x08
1822#define PALMAS_INT2_LINE_STATE_BATREMOVAL_SHIFT 3
1823#define PALMAS_INT2_LINE_STATE_WDT 0x04
1824#define PALMAS_INT2_LINE_STATE_WDT_SHIFT 2
1825#define PALMAS_INT2_LINE_STATE_RTC_TIMER 0x02
1826#define PALMAS_INT2_LINE_STATE_RTC_TIMER_SHIFT 1
1827#define PALMAS_INT2_LINE_STATE_RTC_ALARM 0x01
1828#define PALMAS_INT2_LINE_STATE_RTC_ALARM_SHIFT 0
1829
1830/* Bit definitions for INT3_STATUS */
1831#define PALMAS_INT3_STATUS_VBUS 0x80
1832#define PALMAS_INT3_STATUS_VBUS_SHIFT 7
1833#define PALMAS_INT3_STATUS_VBUS_OTG 0x40
1834#define PALMAS_INT3_STATUS_VBUS_OTG_SHIFT 6
1835#define PALMAS_INT3_STATUS_ID 0x20
1836#define PALMAS_INT3_STATUS_ID_SHIFT 5
1837#define PALMAS_INT3_STATUS_ID_OTG 0x10
1838#define PALMAS_INT3_STATUS_ID_OTG_SHIFT 4
1839#define PALMAS_INT3_STATUS_GPADC_EOC_RT 0x08
1840#define PALMAS_INT3_STATUS_GPADC_EOC_RT_SHIFT 3
1841#define PALMAS_INT3_STATUS_GPADC_EOC_SW 0x04
1842#define PALMAS_INT3_STATUS_GPADC_EOC_SW_SHIFT 2
1843#define PALMAS_INT3_STATUS_GPADC_AUTO_1 0x02
1844#define PALMAS_INT3_STATUS_GPADC_AUTO_1_SHIFT 1
1845#define PALMAS_INT3_STATUS_GPADC_AUTO_0 0x01
1846#define PALMAS_INT3_STATUS_GPADC_AUTO_0_SHIFT 0
1847
1848/* Bit definitions for INT3_MASK */
1849#define PALMAS_INT3_MASK_VBUS 0x80
1850#define PALMAS_INT3_MASK_VBUS_SHIFT 7
1851#define PALMAS_INT3_MASK_VBUS_OTG 0x40
1852#define PALMAS_INT3_MASK_VBUS_OTG_SHIFT 6
1853#define PALMAS_INT3_MASK_ID 0x20
1854#define PALMAS_INT3_MASK_ID_SHIFT 5
1855#define PALMAS_INT3_MASK_ID_OTG 0x10
1856#define PALMAS_INT3_MASK_ID_OTG_SHIFT 4
1857#define PALMAS_INT3_MASK_GPADC_EOC_RT 0x08
1858#define PALMAS_INT3_MASK_GPADC_EOC_RT_SHIFT 3
1859#define PALMAS_INT3_MASK_GPADC_EOC_SW 0x04
1860#define PALMAS_INT3_MASK_GPADC_EOC_SW_SHIFT 2
1861#define PALMAS_INT3_MASK_GPADC_AUTO_1 0x02
1862#define PALMAS_INT3_MASK_GPADC_AUTO_1_SHIFT 1
1863#define PALMAS_INT3_MASK_GPADC_AUTO_0 0x01
1864#define PALMAS_INT3_MASK_GPADC_AUTO_0_SHIFT 0
1865
1866/* Bit definitions for INT3_LINE_STATE */
1867#define PALMAS_INT3_LINE_STATE_VBUS 0x80
1868#define PALMAS_INT3_LINE_STATE_VBUS_SHIFT 7
1869#define PALMAS_INT3_LINE_STATE_VBUS_OTG 0x40
1870#define PALMAS_INT3_LINE_STATE_VBUS_OTG_SHIFT 6
1871#define PALMAS_INT3_LINE_STATE_ID 0x20
1872#define PALMAS_INT3_LINE_STATE_ID_SHIFT 5
1873#define PALMAS_INT3_LINE_STATE_ID_OTG 0x10
1874#define PALMAS_INT3_LINE_STATE_ID_OTG_SHIFT 4
1875#define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT 0x08
1876#define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT_SHIFT 3
1877#define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW 0x04
1878#define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 2
1879#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1 0x02
1880#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 1
1881#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0 0x01
1882#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0
1883
1884/* Bit definitions for INT4_STATUS */
1885#define PALMAS_INT4_STATUS_GPIO_7 0x80
1886#define PALMAS_INT4_STATUS_GPIO_7_SHIFT 7
1887#define PALMAS_INT4_STATUS_GPIO_6 0x40
1888#define PALMAS_INT4_STATUS_GPIO_6_SHIFT 6
1889#define PALMAS_INT4_STATUS_GPIO_5 0x20
1890#define PALMAS_INT4_STATUS_GPIO_5_SHIFT 5
1891#define PALMAS_INT4_STATUS_GPIO_4 0x10
1892#define PALMAS_INT4_STATUS_GPIO_4_SHIFT 4
1893#define PALMAS_INT4_STATUS_GPIO_3 0x08
1894#define PALMAS_INT4_STATUS_GPIO_3_SHIFT 3
1895#define PALMAS_INT4_STATUS_GPIO_2 0x04
1896#define PALMAS_INT4_STATUS_GPIO_2_SHIFT 2
1897#define PALMAS_INT4_STATUS_GPIO_1 0x02
1898#define PALMAS_INT4_STATUS_GPIO_1_SHIFT 1
1899#define PALMAS_INT4_STATUS_GPIO_0 0x01
1900#define PALMAS_INT4_STATUS_GPIO_0_SHIFT 0
1901
1902/* Bit definitions for INT4_MASK */
1903#define PALMAS_INT4_MASK_GPIO_7 0x80
1904#define PALMAS_INT4_MASK_GPIO_7_SHIFT 7
1905#define PALMAS_INT4_MASK_GPIO_6 0x40
1906#define PALMAS_INT4_MASK_GPIO_6_SHIFT 6
1907#define PALMAS_INT4_MASK_GPIO_5 0x20
1908#define PALMAS_INT4_MASK_GPIO_5_SHIFT 5
1909#define PALMAS_INT4_MASK_GPIO_4 0x10
1910#define PALMAS_INT4_MASK_GPIO_4_SHIFT 4
1911#define PALMAS_INT4_MASK_GPIO_3 0x08
1912#define PALMAS_INT4_MASK_GPIO_3_SHIFT 3
1913#define PALMAS_INT4_MASK_GPIO_2 0x04
1914#define PALMAS_INT4_MASK_GPIO_2_SHIFT 2
1915#define PALMAS_INT4_MASK_GPIO_1 0x02
1916#define PALMAS_INT4_MASK_GPIO_1_SHIFT 1
1917#define PALMAS_INT4_MASK_GPIO_0 0x01
1918#define PALMAS_INT4_MASK_GPIO_0_SHIFT 0
1919
1920/* Bit definitions for INT4_LINE_STATE */
1921#define PALMAS_INT4_LINE_STATE_GPIO_7 0x80
1922#define PALMAS_INT4_LINE_STATE_GPIO_7_SHIFT 7
1923#define PALMAS_INT4_LINE_STATE_GPIO_6 0x40
1924#define PALMAS_INT4_LINE_STATE_GPIO_6_SHIFT 6
1925#define PALMAS_INT4_LINE_STATE_GPIO_5 0x20
1926#define PALMAS_INT4_LINE_STATE_GPIO_5_SHIFT 5
1927#define PALMAS_INT4_LINE_STATE_GPIO_4 0x10
1928#define PALMAS_INT4_LINE_STATE_GPIO_4_SHIFT 4
1929#define PALMAS_INT4_LINE_STATE_GPIO_3 0x08
1930#define PALMAS_INT4_LINE_STATE_GPIO_3_SHIFT 3
1931#define PALMAS_INT4_LINE_STATE_GPIO_2 0x04
1932#define PALMAS_INT4_LINE_STATE_GPIO_2_SHIFT 2
1933#define PALMAS_INT4_LINE_STATE_GPIO_1 0x02
1934#define PALMAS_INT4_LINE_STATE_GPIO_1_SHIFT 1
1935#define PALMAS_INT4_LINE_STATE_GPIO_0 0x01
1936#define PALMAS_INT4_LINE_STATE_GPIO_0_SHIFT 0
1937
1938/* Bit definitions for INT4_EDGE_DETECT1 */
1939#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80
1940#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 7
1941#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40
1942#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 6
1943#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20
1944#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 5
1945#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10
1946#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 4
1947#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08
1948#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 3
1949#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04
1950#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 2
1951#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02
1952#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 1
1953#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01
1954#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0
1955
1956/* Bit definitions for INT4_EDGE_DETECT2 */
1957#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING 0x80
1958#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING_SHIFT 7
1959#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING 0x40
1960#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING_SHIFT 6
1961#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20
1962#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 5
1963#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10
1964#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 4
1965#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08
1966#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 3
1967#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04
1968#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 2
1969#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02
1970#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 1
1971#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01
1972#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0
1973
1974/* Bit definitions for INT_CTRL */
1975#define PALMAS_INT_CTRL_INT_PENDING 0x04
1976#define PALMAS_INT_CTRL_INT_PENDING_SHIFT 2
1977#define PALMAS_INT_CTRL_INT_CLEAR 0x01
1978#define PALMAS_INT_CTRL_INT_CLEAR_SHIFT 0
1979
1980/* Registers for function USB_OTG */
1981#define PALMAS_USB_WAKEUP 0x3
1982#define PALMAS_USB_VBUS_CTRL_SET 0x4
1983#define PALMAS_USB_VBUS_CTRL_CLR 0x5
1984#define PALMAS_USB_ID_CTRL_SET 0x6
1985#define PALMAS_USB_ID_CTRL_CLEAR 0x7
1986#define PALMAS_USB_VBUS_INT_SRC 0x8
1987#define PALMAS_USB_VBUS_INT_LATCH_SET 0x9
1988#define PALMAS_USB_VBUS_INT_LATCH_CLR 0xA
1989#define PALMAS_USB_VBUS_INT_EN_LO_SET 0xB
1990#define PALMAS_USB_VBUS_INT_EN_LO_CLR 0xC
1991#define PALMAS_USB_VBUS_INT_EN_HI_SET 0xD
1992#define PALMAS_USB_VBUS_INT_EN_HI_CLR 0xE
1993#define PALMAS_USB_ID_INT_SRC 0xF
1994#define PALMAS_USB_ID_INT_LATCH_SET 0x10
1995#define PALMAS_USB_ID_INT_LATCH_CLR 0x11
1996#define PALMAS_USB_ID_INT_EN_LO_SET 0x12
1997#define PALMAS_USB_ID_INT_EN_LO_CLR 0x13
1998#define PALMAS_USB_ID_INT_EN_HI_SET 0x14
1999#define PALMAS_USB_ID_INT_EN_HI_CLR 0x15
2000#define PALMAS_USB_OTG_ADP_CTRL 0x16
2001#define PALMAS_USB_OTG_ADP_HIGH 0x17
2002#define PALMAS_USB_OTG_ADP_LOW 0x18
2003#define PALMAS_USB_OTG_ADP_RISE 0x19
2004#define PALMAS_USB_OTG_REVISION 0x1A
2005
2006/* Bit definitions for USB_WAKEUP */
2007#define PALMAS_USB_WAKEUP_ID_WK_UP_COMP 0x01
2008#define PALMAS_USB_WAKEUP_ID_WK_UP_COMP_SHIFT 0
2009
2010/* Bit definitions for USB_VBUS_CTRL_SET */
2011#define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS 0x80
2012#define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS_SHIFT 7
2013#define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG 0x20
2014#define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG_SHIFT 5
2015#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC 0x10
2016#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC_SHIFT 4
2017#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK 0x08
2018#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK_SHIFT 3
2019#define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP 0x04
2020#define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP_SHIFT 2
2021
2022/* Bit definitions for USB_VBUS_CTRL_CLR */
2023#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS 0x80
2024#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS_SHIFT 7
2025#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG 0x20
2026#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG_SHIFT 5
2027#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC 0x10
2028#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC_SHIFT 4
2029#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK 0x08
2030#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK_SHIFT 3
2031#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP 0x04
2032#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP_SHIFT 2
2033
2034/* Bit definitions for USB_ID_CTRL_SET */
2035#define PALMAS_USB_ID_CTRL_SET_ID_PU_220K 0x80
2036#define PALMAS_USB_ID_CTRL_SET_ID_PU_220K_SHIFT 7
2037#define PALMAS_USB_ID_CTRL_SET_ID_PU_100K 0x40
2038#define PALMAS_USB_ID_CTRL_SET_ID_PU_100K_SHIFT 6
2039#define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV 0x20
2040#define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV_SHIFT 5
2041#define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U 0x10
2042#define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U_SHIFT 4
2043#define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U 0x08
2044#define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U_SHIFT 3
2045#define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP 0x04
2046#define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP_SHIFT 2
2047
2048/* Bit definitions for USB_ID_CTRL_CLEAR */
2049#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K 0x80
2050#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K_SHIFT 7
2051#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K 0x40
2052#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K_SHIFT 6
2053#define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV 0x20
2054#define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV_SHIFT 5
2055#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U 0x10
2056#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U_SHIFT 4
2057#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U 0x08
2058#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U_SHIFT 3
2059#define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP 0x04
2060#define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP_SHIFT 2
2061
2062/* Bit definitions for USB_VBUS_INT_SRC */
2063#define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD 0x80
2064#define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD_SHIFT 7
2065#define PALMAS_USB_VBUS_INT_SRC_VADP_PRB 0x40
2066#define PALMAS_USB_VBUS_INT_SRC_VADP_PRB_SHIFT 6
2067#define PALMAS_USB_VBUS_INT_SRC_VADP_SNS 0x20
2068#define PALMAS_USB_VBUS_INT_SRC_VADP_SNS_SHIFT 5
2069#define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD 0x08
2070#define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD_SHIFT 3
2071#define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD 0x04
2072#define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD_SHIFT 2
2073#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD 0x02
2074#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD_SHIFT 1
2075#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END 0x01
2076#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END_SHIFT 0
2077
2078/* Bit definitions for USB_VBUS_INT_LATCH_SET */
2079#define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD 0x80
2080#define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD_SHIFT 7
2081#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB 0x40
2082#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB_SHIFT 6
2083#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS 0x20
2084#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS_SHIFT 5
2085#define PALMAS_USB_VBUS_INT_LATCH_SET_ADP 0x10
2086#define PALMAS_USB_VBUS_INT_LATCH_SET_ADP_SHIFT 4
2087#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD 0x08
2088#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD_SHIFT 3
2089#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD 0x04
2090#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD_SHIFT 2
2091#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD 0x02
2092#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD_SHIFT 1
2093#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END 0x01
2094#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END_SHIFT 0
2095
2096/* Bit definitions for USB_VBUS_INT_LATCH_CLR */
2097#define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD 0x80
2098#define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD_SHIFT 7
2099#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB 0x40
2100#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB_SHIFT 6
2101#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS 0x20
2102#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS_SHIFT 5
2103#define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP 0x10
2104#define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP_SHIFT 4
2105#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD 0x08
2106#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD_SHIFT 3
2107#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD 0x04
2108#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD_SHIFT 2
2109#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD 0x02
2110#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD_SHIFT 1
2111#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END 0x01
2112#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END_SHIFT 0
2113
2114/* Bit definitions for USB_VBUS_INT_EN_LO_SET */
2115#define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD 0x80
2116#define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD_SHIFT 7
2117#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB 0x40
2118#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB_SHIFT 6
2119#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS 0x20
2120#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS_SHIFT 5
2121#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD 0x08
2122#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD_SHIFT 3
2123#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD 0x04
2124#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD_SHIFT 2
2125#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD 0x02
2126#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD_SHIFT 1
2127#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END 0x01
2128#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END_SHIFT 0
2129
2130/* Bit definitions for USB_VBUS_INT_EN_LO_CLR */
2131#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD 0x80
2132#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD_SHIFT 7
2133#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB 0x40
2134#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB_SHIFT 6
2135#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS 0x20
2136#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS_SHIFT 5
2137#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD 0x08
2138#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD_SHIFT 3
2139#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD 0x04
2140#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD_SHIFT 2
2141#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD 0x02
2142#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD_SHIFT 1
2143#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END 0x01
2144#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END_SHIFT 0
2145
2146/* Bit definitions for USB_VBUS_INT_EN_HI_SET */
2147#define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD 0x80
2148#define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD_SHIFT 7
2149#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB 0x40
2150#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB_SHIFT 6
2151#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS 0x20
2152#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS_SHIFT 5
2153#define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP 0x10
2154#define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP_SHIFT 4
2155#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD 0x08
2156#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD_SHIFT 3
2157#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD 0x04
2158#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD_SHIFT 2
2159#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD 0x02
2160#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD_SHIFT 1
2161#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END 0x01
2162#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END_SHIFT 0
2163
2164/* Bit definitions for USB_VBUS_INT_EN_HI_CLR */
2165#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD 0x80
2166#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD_SHIFT 7
2167#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB 0x40
2168#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB_SHIFT 6
2169#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS 0x20
2170#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS_SHIFT 5
2171#define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP 0x10
2172#define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP_SHIFT 4
2173#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD 0x08
2174#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD_SHIFT 3
2175#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD 0x04
2176#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD_SHIFT 2
2177#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD 0x02
2178#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD_SHIFT 1
2179#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END 0x01
2180#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END_SHIFT 0
2181
2182/* Bit definitions for USB_ID_INT_SRC */
2183#define PALMAS_USB_ID_INT_SRC_ID_FLOAT 0x10
2184#define PALMAS_USB_ID_INT_SRC_ID_FLOAT_SHIFT 4
2185#define PALMAS_USB_ID_INT_SRC_ID_A 0x08
2186#define PALMAS_USB_ID_INT_SRC_ID_A_SHIFT 3
2187#define PALMAS_USB_ID_INT_SRC_ID_B 0x04
2188#define PALMAS_USB_ID_INT_SRC_ID_B_SHIFT 2
2189#define PALMAS_USB_ID_INT_SRC_ID_C 0x02
2190#define PALMAS_USB_ID_INT_SRC_ID_C_SHIFT 1
2191#define PALMAS_USB_ID_INT_SRC_ID_GND 0x01
2192#define PALMAS_USB_ID_INT_SRC_ID_GND_SHIFT 0
2193
2194/* Bit definitions for USB_ID_INT_LATCH_SET */
2195#define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT 0x10
2196#define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT_SHIFT 4
2197#define PALMAS_USB_ID_INT_LATCH_SET_ID_A 0x08
2198#define PALMAS_USB_ID_INT_LATCH_SET_ID_A_SHIFT 3
2199#define PALMAS_USB_ID_INT_LATCH_SET_ID_B 0x04
2200#define PALMAS_USB_ID_INT_LATCH_SET_ID_B_SHIFT 2
2201#define PALMAS_USB_ID_INT_LATCH_SET_ID_C 0x02
2202#define PALMAS_USB_ID_INT_LATCH_SET_ID_C_SHIFT 1
2203#define PALMAS_USB_ID_INT_LATCH_SET_ID_GND 0x01
2204#define PALMAS_USB_ID_INT_LATCH_SET_ID_GND_SHIFT 0
2205
2206/* Bit definitions for USB_ID_INT_LATCH_CLR */
2207#define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT 0x10
2208#define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT_SHIFT 4
2209#define PALMAS_USB_ID_INT_LATCH_CLR_ID_A 0x08
2210#define PALMAS_USB_ID_INT_LATCH_CLR_ID_A_SHIFT 3
2211#define PALMAS_USB_ID_INT_LATCH_CLR_ID_B 0x04
2212#define PALMAS_USB_ID_INT_LATCH_CLR_ID_B_SHIFT 2
2213#define PALMAS_USB_ID_INT_LATCH_CLR_ID_C 0x02
2214#define PALMAS_USB_ID_INT_LATCH_CLR_ID_C_SHIFT 1
2215#define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND 0x01
2216#define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND_SHIFT 0
2217
2218/* Bit definitions for USB_ID_INT_EN_LO_SET */
2219#define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT 0x10
2220#define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT_SHIFT 4
2221#define PALMAS_USB_ID_INT_EN_LO_SET_ID_A 0x08
2222#define PALMAS_USB_ID_INT_EN_LO_SET_ID_A_SHIFT 3
2223#define PALMAS_USB_ID_INT_EN_LO_SET_ID_B 0x04
2224#define PALMAS_USB_ID_INT_EN_LO_SET_ID_B_SHIFT 2
2225#define PALMAS_USB_ID_INT_EN_LO_SET_ID_C 0x02
2226#define PALMAS_USB_ID_INT_EN_LO_SET_ID_C_SHIFT 1
2227#define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND 0x01
2228#define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND_SHIFT 0
2229
2230/* Bit definitions for USB_ID_INT_EN_LO_CLR */
2231#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT 0x10
2232#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT_SHIFT 4
2233#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A 0x08
2234#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A_SHIFT 3
2235#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B 0x04
2236#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B_SHIFT 2
2237#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C 0x02
2238#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C_SHIFT 1
2239#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND 0x01
2240#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND_SHIFT 0
2241
2242/* Bit definitions for USB_ID_INT_EN_HI_SET */
2243#define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT 0x10
2244#define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT_SHIFT 4
2245#define PALMAS_USB_ID_INT_EN_HI_SET_ID_A 0x08
2246#define PALMAS_USB_ID_INT_EN_HI_SET_ID_A_SHIFT 3
2247#define PALMAS_USB_ID_INT_EN_HI_SET_ID_B 0x04
2248#define PALMAS_USB_ID_INT_EN_HI_SET_ID_B_SHIFT 2
2249#define PALMAS_USB_ID_INT_EN_HI_SET_ID_C 0x02
2250#define PALMAS_USB_ID_INT_EN_HI_SET_ID_C_SHIFT 1
2251#define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND 0x01
2252#define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND_SHIFT 0
2253
2254/* Bit definitions for USB_ID_INT_EN_HI_CLR */
2255#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT 0x10
2256#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT_SHIFT 4
2257#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A 0x08
2258#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A_SHIFT 3
2259#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B 0x04
2260#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B_SHIFT 2
2261#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C 0x02
2262#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C_SHIFT 1
2263#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND 0x01
2264#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND_SHIFT 0
2265
2266/* Bit definitions for USB_OTG_ADP_CTRL */
2267#define PALMAS_USB_OTG_ADP_CTRL_ADP_EN 0x04
2268#define PALMAS_USB_OTG_ADP_CTRL_ADP_EN_SHIFT 2
2269#define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_MASK 0x03
2270#define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_SHIFT 0
2271
2272/* Bit definitions for USB_OTG_ADP_HIGH */
2273#define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_MASK 0xff
2274#define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_SHIFT 0
2275
2276/* Bit definitions for USB_OTG_ADP_LOW */
2277#define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_MASK 0xff
2278#define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_SHIFT 0
2279
2280/* Bit definitions for USB_OTG_ADP_RISE */
2281#define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_MASK 0xff
2282#define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_SHIFT 0
2283
2284/* Bit definitions for USB_OTG_REVISION */
2285#define PALMAS_USB_OTG_REVISION_OTG_REV 0x01
2286#define PALMAS_USB_OTG_REVISION_OTG_REV_SHIFT 0
2287
2288/* Registers for function VIBRATOR */
2289#define PALMAS_VIBRA_CTRL 0x0
2290
2291/* Bit definitions for VIBRA_CTRL */
2292#define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_MASK 0x06
2293#define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_SHIFT 1
2294#define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL 0x01
2295#define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL_SHIFT 0
2296
2297/* Registers for function GPIO */
2298#define PALMAS_GPIO_DATA_IN 0x0
2299#define PALMAS_GPIO_DATA_DIR 0x1
2300#define PALMAS_GPIO_DATA_OUT 0x2
2301#define PALMAS_GPIO_DEBOUNCE_EN 0x3
2302#define PALMAS_GPIO_CLEAR_DATA_OUT 0x4
2303#define PALMAS_GPIO_SET_DATA_OUT 0x5
2304#define PALMAS_PU_PD_GPIO_CTRL1 0x6
2305#define PALMAS_PU_PD_GPIO_CTRL2 0x7
2306#define PALMAS_OD_OUTPUT_GPIO_CTRL 0x8
2307
2308/* Bit definitions for GPIO_DATA_IN */
2309#define PALMAS_GPIO_DATA_IN_GPIO_7_IN 0x80
2310#define PALMAS_GPIO_DATA_IN_GPIO_7_IN_SHIFT 7
2311#define PALMAS_GPIO_DATA_IN_GPIO_6_IN 0x40
2312#define PALMAS_GPIO_DATA_IN_GPIO_6_IN_SHIFT 6
2313#define PALMAS_GPIO_DATA_IN_GPIO_5_IN 0x20
2314#define PALMAS_GPIO_DATA_IN_GPIO_5_IN_SHIFT 5
2315#define PALMAS_GPIO_DATA_IN_GPIO_4_IN 0x10
2316#define PALMAS_GPIO_DATA_IN_GPIO_4_IN_SHIFT 4
2317#define PALMAS_GPIO_DATA_IN_GPIO_3_IN 0x08
2318#define PALMAS_GPIO_DATA_IN_GPIO_3_IN_SHIFT 3
2319#define PALMAS_GPIO_DATA_IN_GPIO_2_IN 0x04
2320#define PALMAS_GPIO_DATA_IN_GPIO_2_IN_SHIFT 2
2321#define PALMAS_GPIO_DATA_IN_GPIO_1_IN 0x02
2322#define PALMAS_GPIO_DATA_IN_GPIO_1_IN_SHIFT 1
2323#define PALMAS_GPIO_DATA_IN_GPIO_0_IN 0x01
2324#define PALMAS_GPIO_DATA_IN_GPIO_0_IN_SHIFT 0
2325
2326/* Bit definitions for GPIO_DATA_DIR */
2327#define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR 0x80
2328#define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR_SHIFT 7
2329#define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR 0x40
2330#define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR_SHIFT 6
2331#define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR 0x20
2332#define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR_SHIFT 5
2333#define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR 0x10
2334#define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR_SHIFT 4
2335#define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR 0x08
2336#define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR_SHIFT 3
2337#define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR 0x04
2338#define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR_SHIFT 2
2339#define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR 0x02
2340#define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR_SHIFT 1
2341#define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR 0x01
2342#define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR_SHIFT 0
2343
2344/* Bit definitions for GPIO_DATA_OUT */
2345#define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT 0x80
2346#define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT_SHIFT 7
2347#define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT 0x40
2348#define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT_SHIFT 6
2349#define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT 0x20
2350#define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT_SHIFT 5
2351#define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT 0x10
2352#define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT_SHIFT 4
2353#define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT 0x08
2354#define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT_SHIFT 3
2355#define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT 0x04
2356#define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT_SHIFT 2
2357#define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT 0x02
2358#define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT_SHIFT 1
2359#define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT 0x01
2360#define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT_SHIFT 0
2361
2362/* Bit definitions for GPIO_DEBOUNCE_EN */
2363#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN 0x80
2364#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN_SHIFT 7
2365#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN 0x40
2366#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN_SHIFT 6
2367#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN 0x20
2368#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN_SHIFT 5
2369#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN 0x10
2370#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN_SHIFT 4
2371#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN 0x08
2372#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN_SHIFT 3
2373#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN 0x04
2374#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN_SHIFT 2
2375#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN 0x02
2376#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN_SHIFT 1
2377#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN 0x01
2378#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN_SHIFT 0
2379
2380/* Bit definitions for GPIO_CLEAR_DATA_OUT */
2381#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT 0x80
2382#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT_SHIFT 7
2383#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT 0x40
2384#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT_SHIFT 6
2385#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT 0x20
2386#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT_SHIFT 5
2387#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT 0x10
2388#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT_SHIFT 4
2389#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT 0x08
2390#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT_SHIFT 3
2391#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT 0x04
2392#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT_SHIFT 2
2393#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT 0x02
2394#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT_SHIFT 1
2395#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT 0x01
2396#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT_SHIFT 0
2397
2398/* Bit definitions for GPIO_SET_DATA_OUT */
2399#define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT 0x80
2400#define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT_SHIFT 7
2401#define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT 0x40
2402#define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT_SHIFT 6
2403#define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT 0x20
2404#define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT_SHIFT 5
2405#define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT 0x10
2406#define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT_SHIFT 4
2407#define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT 0x08
2408#define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT_SHIFT 3
2409#define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT 0x04
2410#define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT_SHIFT 2
2411#define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT 0x02
2412#define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT_SHIFT 1
2413#define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT 0x01
2414#define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT_SHIFT 0
2415
2416/* Bit definitions for PU_PD_GPIO_CTRL1 */
2417#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD 0x40
2418#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD_SHIFT 6
2419#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU 0x20
2420#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU_SHIFT 5
2421#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD 0x10
2422#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD_SHIFT 4
2423#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU 0x08
2424#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU_SHIFT 3
2425#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD 0x04
2426#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD_SHIFT 2
2427#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD 0x01
2428#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD_SHIFT 0
2429
2430/* Bit definitions for PU_PD_GPIO_CTRL2 */
2431#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD 0x40
2432#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD_SHIFT 6
2433#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU 0x20
2434#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU_SHIFT 5
2435#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD 0x10
2436#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD_SHIFT 4
2437#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU 0x08
2438#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU_SHIFT 3
2439#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD 0x04
2440#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD_SHIFT 2
2441#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU 0x02
2442#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU_SHIFT 1
2443#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD 0x01
2444#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD_SHIFT 0
2445
2446/* Bit definitions for OD_OUTPUT_GPIO_CTRL */
2447#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD 0x20
2448#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD_SHIFT 5
2449#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD 0x04
2450#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD_SHIFT 2
2451#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD 0x02
2452#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD_SHIFT 1
2453
2454/* Registers for function GPADC */
2455#define PALMAS_GPADC_CTRL1 0x0
2456#define PALMAS_GPADC_CTRL2 0x1
2457#define PALMAS_GPADC_RT_CTRL 0x2
2458#define PALMAS_GPADC_AUTO_CTRL 0x3
2459#define PALMAS_GPADC_STATUS 0x4
2460#define PALMAS_GPADC_RT_SELECT 0x5
2461#define PALMAS_GPADC_RT_CONV0_LSB 0x6
2462#define PALMAS_GPADC_RT_CONV0_MSB 0x7
2463#define PALMAS_GPADC_AUTO_SELECT 0x8
2464#define PALMAS_GPADC_AUTO_CONV0_LSB 0x9
2465#define PALMAS_GPADC_AUTO_CONV0_MSB 0xA
2466#define PALMAS_GPADC_AUTO_CONV1_LSB 0xB
2467#define PALMAS_GPADC_AUTO_CONV1_MSB 0xC
2468#define PALMAS_GPADC_SW_SELECT 0xD
2469#define PALMAS_GPADC_SW_CONV0_LSB 0xE
2470#define PALMAS_GPADC_SW_CONV0_MSB 0xF
2471#define PALMAS_GPADC_THRES_CONV0_LSB 0x10
2472#define PALMAS_GPADC_THRES_CONV0_MSB 0x11
2473#define PALMAS_GPADC_THRES_CONV1_LSB 0x12
2474#define PALMAS_GPADC_THRES_CONV1_MSB 0x13
2475#define PALMAS_GPADC_SMPS_ILMONITOR_EN 0x14
2476#define PALMAS_GPADC_SMPS_VSEL_MONITORING 0x15
2477
2478/* Bit definitions for GPADC_CTRL1 */
2479#define PALMAS_GPADC_CTRL1_RESERVED_MASK 0xc0
2480#define PALMAS_GPADC_CTRL1_RESERVED_SHIFT 6
2481#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK 0x30
2482#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT 4
2483#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK 0x0c
2484#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT 2
2485#define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET 0x02
2486#define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET_SHIFT 1
2487#define PALMAS_GPADC_CTRL1_GPADC_FORCE 0x01
2488#define PALMAS_GPADC_CTRL1_GPADC_FORCE_SHIFT 0
2489
2490/* Bit definitions for GPADC_CTRL2 */
2491#define PALMAS_GPADC_CTRL2_RESERVED_MASK 0x06
2492#define PALMAS_GPADC_CTRL2_RESERVED_SHIFT 1
2493
2494/* Bit definitions for GPADC_RT_CTRL */
2495#define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY 0x02
2496#define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT 1
2497#define PALMAS_GPADC_RT_CTRL_START_POLARITY 0x01
2498#define PALMAS_GPADC_RT_CTRL_START_POLARITY_SHIFT 0
2499
2500/* Bit definitions for GPADC_AUTO_CTRL */
2501#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1 0x80
2502#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1_SHIFT 7
2503#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0 0x40
2504#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0_SHIFT 6
2505#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN 0x20
2506#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN_SHIFT 5
2507#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN 0x10
2508#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN_SHIFT 4
2509#define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK 0x0f
2510#define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_SHIFT 0
2511
2512/* Bit definitions for GPADC_STATUS */
2513#define PALMAS_GPADC_STATUS_GPADC_AVAILABLE 0x10
2514#define PALMAS_GPADC_STATUS_GPADC_AVAILABLE_SHIFT 4
2515
2516/* Bit definitions for GPADC_RT_SELECT */
2517#define PALMAS_GPADC_RT_SELECT_RT_CONV_EN 0x80
2518#define PALMAS_GPADC_RT_SELECT_RT_CONV_EN_SHIFT 7
2519#define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_MASK 0x0f
2520#define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_SHIFT 0
2521
2522/* Bit definitions for GPADC_RT_CONV0_LSB */
2523#define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_MASK 0xff
2524#define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_SHIFT 0
2525
2526/* Bit definitions for GPADC_RT_CONV0_MSB */
2527#define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_MASK 0x0f
2528#define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_SHIFT 0
2529
2530/* Bit definitions for GPADC_AUTO_SELECT */
2531#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_MASK 0xf0
2532#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_SHIFT 4
2533#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_MASK 0x0f
2534#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_SHIFT 0
2535
2536/* Bit definitions for GPADC_AUTO_CONV0_LSB */
2537#define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_MASK 0xff
2538#define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_SHIFT 0
2539
2540/* Bit definitions for GPADC_AUTO_CONV0_MSB */
2541#define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_MASK 0x0f
2542#define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_SHIFT 0
2543
2544/* Bit definitions for GPADC_AUTO_CONV1_LSB */
2545#define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_MASK 0xff
2546#define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_SHIFT 0
2547
2548/* Bit definitions for GPADC_AUTO_CONV1_MSB */
2549#define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_MASK 0x0f
2550#define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_SHIFT 0
2551
2552/* Bit definitions for GPADC_SW_SELECT */
2553#define PALMAS_GPADC_SW_SELECT_SW_CONV_EN 0x80
2554#define PALMAS_GPADC_SW_SELECT_SW_CONV_EN_SHIFT 7
2555#define PALMAS_GPADC_SW_SELECT_SW_START_CONV0 0x10
2556#define PALMAS_GPADC_SW_SELECT_SW_START_CONV0_SHIFT 4
2557#define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK 0x0f
2558#define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_SHIFT 0
2559
2560/* Bit definitions for GPADC_SW_CONV0_LSB */
2561#define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_MASK 0xff
2562#define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_SHIFT 0
2563
2564/* Bit definitions for GPADC_SW_CONV0_MSB */
2565#define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_MASK 0x0f
2566#define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_SHIFT 0
2567
2568/* Bit definitions for GPADC_THRES_CONV0_LSB */
2569#define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_MASK 0xff
2570#define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_SHIFT 0
2571
2572/* Bit definitions for GPADC_THRES_CONV0_MSB */
2573#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL 0x80
2574#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL_SHIFT 7
2575#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_MASK 0x0f
2576#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_SHIFT 0
2577
2578/* Bit definitions for GPADC_THRES_CONV1_LSB */
2579#define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_MASK 0xff
2580#define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_SHIFT 0
2581
2582/* Bit definitions for GPADC_THRES_CONV1_MSB */
2583#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL 0x80
2584#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL_SHIFT 7
2585#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_MASK 0x0f
2586#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_SHIFT 0
2587
2588/* Bit definitions for GPADC_SMPS_ILMONITOR_EN */
2589#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN 0x20
2590#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN_SHIFT 5
2591#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT 0x10
2592#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT_SHIFT 4
2593#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_MASK 0x0f
2594#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_SHIFT 0
2595
2596/* Bit definitions for GPADC_SMPS_VSEL_MONITORING */
2597#define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE 0x80
2598#define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE_SHIFT 7
2599#define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_MASK 0x7f
2600#define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_SHIFT 0
2601
2602/* Registers for function GPADC */
2603#define PALMAS_GPADC_TRIM1 0x0
2604#define PALMAS_GPADC_TRIM2 0x1
2605#define PALMAS_GPADC_TRIM3 0x2
2606#define PALMAS_GPADC_TRIM4 0x3
2607#define PALMAS_GPADC_TRIM5 0x4
2608#define PALMAS_GPADC_TRIM6 0x5
2609#define PALMAS_GPADC_TRIM7 0x6
2610#define PALMAS_GPADC_TRIM8 0x7
2611#define PALMAS_GPADC_TRIM9 0x8
2612#define PALMAS_GPADC_TRIM10 0x9
2613#define PALMAS_GPADC_TRIM11 0xA
2614#define PALMAS_GPADC_TRIM12 0xB
2615#define PALMAS_GPADC_TRIM13 0xC
2616#define PALMAS_GPADC_TRIM14 0xD
2617#define PALMAS_GPADC_TRIM15 0xE
2618#define PALMAS_GPADC_TRIM16 0xF
2619
2620#endif /* __LINUX_MFD_PALMAS_H */
diff --git a/include/linux/mfd/rc5t583.h b/include/linux/mfd/rc5t583.h
index 0b64b19d81ab..3661c59aa1e9 100644
--- a/include/linux/mfd/rc5t583.h
+++ b/include/linux/mfd/rc5t583.h
@@ -250,6 +250,26 @@ enum {
250 RC5T583_EXT_PWRREQ2_CONTROL = 0x2, 250 RC5T583_EXT_PWRREQ2_CONTROL = 0x2,
251}; 251};
252 252
253enum {
254 RC5T583_REGULATOR_DC0,
255 RC5T583_REGULATOR_DC1,
256 RC5T583_REGULATOR_DC2,
257 RC5T583_REGULATOR_DC3,
258 RC5T583_REGULATOR_LDO0,
259 RC5T583_REGULATOR_LDO1,
260 RC5T583_REGULATOR_LDO2,
261 RC5T583_REGULATOR_LDO3,
262 RC5T583_REGULATOR_LDO4,
263 RC5T583_REGULATOR_LDO5,
264 RC5T583_REGULATOR_LDO6,
265 RC5T583_REGULATOR_LDO7,
266 RC5T583_REGULATOR_LDO8,
267 RC5T583_REGULATOR_LDO9,
268
269 /* Should be last entry */
270 RC5T583_REGULATOR_MAX,
271};
272
253struct rc5t583 { 273struct rc5t583 {
254 struct device *dev; 274 struct device *dev;
255 struct regmap *regmap; 275 struct regmap *regmap;
@@ -272,12 +292,23 @@ struct rc5t583 {
272 * rc5t583_platform_data: Platform data for ricoh rc5t583 pmu. 292 * rc5t583_platform_data: Platform data for ricoh rc5t583 pmu.
273 * The board specific data is provided through this structure. 293 * The board specific data is provided through this structure.
274 * @irq_base: Irq base number on which this device registers their interrupts. 294 * @irq_base: Irq base number on which this device registers their interrupts.
295 * @gpio_base: GPIO base from which gpio of this device will start.
275 * @enable_shutdown: Enable shutdown through the input pin "shutdown". 296 * @enable_shutdown: Enable shutdown through the input pin "shutdown".
297 * @regulator_deepsleep_slot: The slot number on which device goes to sleep
298 * in device sleep mode.
299 * @regulator_ext_pwr_control: External power request regulator control. The
300 * regulator output enable/disable is controlled by the external
301 * power request input state.
302 * @reg_init_data: Regulator init data.
276 */ 303 */
277 304
278struct rc5t583_platform_data { 305struct rc5t583_platform_data {
279 int irq_base; 306 int irq_base;
307 int gpio_base;
280 bool enable_shutdown; 308 bool enable_shutdown;
309 int regulator_deepsleep_slot[RC5T583_REGULATOR_MAX];
310 unsigned long regulator_ext_pwr_control[RC5T583_REGULATOR_MAX];
311 struct regulator_init_data *reg_init_data[RC5T583_REGULATOR_MAX];
281}; 312};
282 313
283static inline int rc5t583_write(struct device *dev, uint8_t reg, uint8_t val) 314static inline int rc5t583_write(struct device *dev, uint8_t reg, uint8_t val)
diff --git a/include/linux/mfd/s5m87xx/s5m-core.h b/include/linux/mfd/s5m87xx/s5m-core.h
index a7480b57f92d..21603b42f22f 100644
--- a/include/linux/mfd/s5m87xx/s5m-core.h
+++ b/include/linux/mfd/s5m87xx/s5m-core.h
@@ -335,6 +335,7 @@ extern int s5m_reg_update(struct s5m87xx_dev *s5m87xx, u8 reg, u8 val, u8 mask);
335 335
336struct s5m_platform_data { 336struct s5m_platform_data {
337 struct s5m_regulator_data *regulators; 337 struct s5m_regulator_data *regulators;
338 struct s5m_opmode_data *opmode;
338 int device_type; 339 int device_type;
339 int num_regulators; 340 int num_regulators;
340 341
diff --git a/include/linux/mfd/s5m87xx/s5m-pmic.h b/include/linux/mfd/s5m87xx/s5m-pmic.h
index a72a5d27e62e..7c719f20f58a 100644
--- a/include/linux/mfd/s5m87xx/s5m-pmic.h
+++ b/include/linux/mfd/s5m87xx/s5m-pmic.h
@@ -58,6 +58,8 @@ enum s5m8767_regulators {
58 S5M8767_REG_MAX, 58 S5M8767_REG_MAX,
59}; 59};
60 60
61#define S5M8767_ENCTRL_SHIFT 6
62
61/* S5M8763 regulator ids */ 63/* S5M8763 regulator ids */
62enum s5m8763_regulators { 64enum s5m8763_regulators {
63 S5M8763_LDO1, 65 S5M8763_LDO1,
@@ -97,4 +99,31 @@ struct s5m_regulator_data {
97 struct regulator_init_data *initdata; 99 struct regulator_init_data *initdata;
98}; 100};
99 101
102/*
103 * s5m_opmode_data - regulator operation mode data
104 * @id: regulator id
105 * @mode: regulator operation mode
106 */
107struct s5m_opmode_data {
108 int id;
109 int mode;
110};
111
112/*
113 * s5m regulator operation mode
114 * S5M_OPMODE_OFF Regulator always OFF
115 * S5M_OPMODE_ON Regulator always ON
116 * S5M_OPMODE_LOWPOWER Regulator is on in low-power mode
117 * S5M_OPMODE_SUSPEND Regulator is changed by PWREN pin
118 * If PWREN is high, regulator is on
119 * If PWREN is low, regulator is off
120 */
121
122enum s5m_opmode {
123 S5M_OPMODE_OFF,
124 S5M_OPMODE_ON,
125 S5M_OPMODE_LOWPOWER,
126 S5M_OPMODE_SUSPEND,
127};
128
100#endif /* __LINUX_MFD_S5M_PMIC_H */ 129#endif /* __LINUX_MFD_S5M_PMIC_H */
diff --git a/include/linux/mfd/sta2x11-mfd.h b/include/linux/mfd/sta2x11-mfd.h
new file mode 100644
index 000000000000..d179227e866f
--- /dev/null
+++ b/include/linux/mfd/sta2x11-mfd.h
@@ -0,0 +1,324 @@
1/*
2 * Copyright (c) 2009-2011 Wind River Systems, Inc.
3 * Copyright (c) 2011 ST Microelectronics (Alessandro Rubini)
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
12 * See the GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 *
18 * The STMicroelectronics ConneXt (STA2X11) chip has several unrelated
19 * functions in one PCI endpoint functions. This driver simply
20 * registers the platform devices in this iomemregion and exports a few
21 * functions to access common registers
22 */
23
24#ifndef __STA2X11_MFD_H
25#define __STA2X11_MFD_H
26#include <linux/types.h>
27#include <linux/pci.h>
28
29/*
30 * The MFD PCI block includes the GPIO peripherals and other register blocks.
31 * For GPIO, we have 32*4 bits (I use "gsta" for "gpio sta2x11".)
32 */
33#define GSTA_GPIO_PER_BLOCK 32
34#define GSTA_NR_BLOCKS 4
35#define GSTA_NR_GPIO (GSTA_GPIO_PER_BLOCK * GSTA_NR_BLOCKS)
36
37/* Pinconfig is set by the board definition: altfunc, pull-up, pull-down */
38struct sta2x11_gpio_pdata {
39 unsigned pinconfig[GSTA_NR_GPIO];
40};
41
42/* Macros below lifted from sh_pfc.h, with minor differences */
43#define PINMUX_TYPE_NONE 0
44#define PINMUX_TYPE_FUNCTION 1
45#define PINMUX_TYPE_OUTPUT_LOW 2
46#define PINMUX_TYPE_OUTPUT_HIGH 3
47#define PINMUX_TYPE_INPUT 4
48#define PINMUX_TYPE_INPUT_PULLUP 5
49#define PINMUX_TYPE_INPUT_PULLDOWN 6
50
51/* Give names to GPIO pins, like PXA does, taken from the manual */
52#define STA2X11_GPIO0 0
53#define STA2X11_GPIO1 1
54#define STA2X11_GPIO2 2
55#define STA2X11_GPIO3 3
56#define STA2X11_GPIO4 4
57#define STA2X11_GPIO5 5
58#define STA2X11_GPIO6 6
59#define STA2X11_GPIO7 7
60#define STA2X11_GPIO8_RGBOUT_RED7 8
61#define STA2X11_GPIO9_RGBOUT_RED6 9
62#define STA2X11_GPIO10_RGBOUT_RED5 10
63#define STA2X11_GPIO11_RGBOUT_RED4 11
64#define STA2X11_GPIO12_RGBOUT_RED3 12
65#define STA2X11_GPIO13_RGBOUT_RED2 13
66#define STA2X11_GPIO14_RGBOUT_RED1 14
67#define STA2X11_GPIO15_RGBOUT_RED0 15
68#define STA2X11_GPIO16_RGBOUT_GREEN7 16
69#define STA2X11_GPIO17_RGBOUT_GREEN6 17
70#define STA2X11_GPIO18_RGBOUT_GREEN5 18
71#define STA2X11_GPIO19_RGBOUT_GREEN4 19
72#define STA2X11_GPIO20_RGBOUT_GREEN3 20
73#define STA2X11_GPIO21_RGBOUT_GREEN2 21
74#define STA2X11_GPIO22_RGBOUT_GREEN1 22
75#define STA2X11_GPIO23_RGBOUT_GREEN0 23
76#define STA2X11_GPIO24_RGBOUT_BLUE7 24
77#define STA2X11_GPIO25_RGBOUT_BLUE6 25
78#define STA2X11_GPIO26_RGBOUT_BLUE5 26
79#define STA2X11_GPIO27_RGBOUT_BLUE4 27
80#define STA2X11_GPIO28_RGBOUT_BLUE3 28
81#define STA2X11_GPIO29_RGBOUT_BLUE2 29
82#define STA2X11_GPIO30_RGBOUT_BLUE1 30
83#define STA2X11_GPIO31_RGBOUT_BLUE0 31
84#define STA2X11_GPIO32_RGBOUT_VSYNCH 32
85#define STA2X11_GPIO33_RGBOUT_HSYNCH 33
86#define STA2X11_GPIO34_RGBOUT_DEN 34
87#define STA2X11_GPIO35_ETH_CRS_DV 35
88#define STA2X11_GPIO36_ETH_TXD1 36
89#define STA2X11_GPIO37_ETH_TXD0 37
90#define STA2X11_GPIO38_ETH_TX_EN 38
91#define STA2X11_GPIO39_MDIO 39
92#define STA2X11_GPIO40_ETH_REF_CLK 40
93#define STA2X11_GPIO41_ETH_RXD1 41
94#define STA2X11_GPIO42_ETH_RXD0 42
95#define STA2X11_GPIO43_MDC 43
96#define STA2X11_GPIO44_CAN_TX 44
97#define STA2X11_GPIO45_CAN_RX 45
98#define STA2X11_GPIO46_MLB_DAT 46
99#define STA2X11_GPIO47_MLB_SIG 47
100#define STA2X11_GPIO48_SPI0_CLK 48
101#define STA2X11_GPIO49_SPI0_TXD 49
102#define STA2X11_GPIO50_SPI0_RXD 50
103#define STA2X11_GPIO51_SPI0_FRM 51
104#define STA2X11_GPIO52_SPI1_CLK 52
105#define STA2X11_GPIO53_SPI1_TXD 53
106#define STA2X11_GPIO54_SPI1_RXD 54
107#define STA2X11_GPIO55_SPI1_FRM 55
108#define STA2X11_GPIO56_SPI2_CLK 56
109#define STA2X11_GPIO57_SPI2_TXD 57
110#define STA2X11_GPIO58_SPI2_RXD 58
111#define STA2X11_GPIO59_SPI2_FRM 59
112#define STA2X11_GPIO60_I2C0_SCL 60
113#define STA2X11_GPIO61_I2C0_SDA 61
114#define STA2X11_GPIO62_I2C1_SCL 62
115#define STA2X11_GPIO63_I2C1_SDA 63
116#define STA2X11_GPIO64_I2C2_SCL 64
117#define STA2X11_GPIO65_I2C2_SDA 65
118#define STA2X11_GPIO66_I2C3_SCL 66
119#define STA2X11_GPIO67_I2C3_SDA 67
120#define STA2X11_GPIO68_MSP0_RCK 68
121#define STA2X11_GPIO69_MSP0_RXD 69
122#define STA2X11_GPIO70_MSP0_RFS 70
123#define STA2X11_GPIO71_MSP0_TCK 71
124#define STA2X11_GPIO72_MSP0_TXD 72
125#define STA2X11_GPIO73_MSP0_TFS 73
126#define STA2X11_GPIO74_MSP0_SCK 74
127#define STA2X11_GPIO75_MSP1_CK 75
128#define STA2X11_GPIO76_MSP1_RXD 76
129#define STA2X11_GPIO77_MSP1_FS 77
130#define STA2X11_GPIO78_MSP1_TXD 78
131#define STA2X11_GPIO79_MSP2_CK 79
132#define STA2X11_GPIO80_MSP2_RXD 80
133#define STA2X11_GPIO81_MSP2_FS 81
134#define STA2X11_GPIO82_MSP2_TXD 82
135#define STA2X11_GPIO83_MSP3_CK 83
136#define STA2X11_GPIO84_MSP3_RXD 84
137#define STA2X11_GPIO85_MSP3_FS 85
138#define STA2X11_GPIO86_MSP3_TXD 86
139#define STA2X11_GPIO87_MSP4_CK 87
140#define STA2X11_GPIO88_MSP4_RXD 88
141#define STA2X11_GPIO89_MSP4_FS 89
142#define STA2X11_GPIO90_MSP4_TXD 90
143#define STA2X11_GPIO91_MSP5_CK 91
144#define STA2X11_GPIO92_MSP5_RXD 92
145#define STA2X11_GPIO93_MSP5_FS 93
146#define STA2X11_GPIO94_MSP5_TXD 94
147#define STA2X11_GPIO95_SDIO3_DAT3 95
148#define STA2X11_GPIO96_SDIO3_DAT2 96
149#define STA2X11_GPIO97_SDIO3_DAT1 97
150#define STA2X11_GPIO98_SDIO3_DAT0 98
151#define STA2X11_GPIO99_SDIO3_CLK 99
152#define STA2X11_GPIO100_SDIO3_CMD 100
153#define STA2X11_GPIO101 101
154#define STA2X11_GPIO102 102
155#define STA2X11_GPIO103 103
156#define STA2X11_GPIO104 104
157#define STA2X11_GPIO105_SDIO2_DAT3 105
158#define STA2X11_GPIO106_SDIO2_DAT2 106
159#define STA2X11_GPIO107_SDIO2_DAT1 107
160#define STA2X11_GPIO108_SDIO2_DAT0 108
161#define STA2X11_GPIO109_SDIO2_CLK 109
162#define STA2X11_GPIO110_SDIO2_CMD 110
163#define STA2X11_GPIO111 111
164#define STA2X11_GPIO112 112
165#define STA2X11_GPIO113 113
166#define STA2X11_GPIO114 114
167#define STA2X11_GPIO115_SDIO1_DAT3 115
168#define STA2X11_GPIO116_SDIO1_DAT2 116
169#define STA2X11_GPIO117_SDIO1_DAT1 117
170#define STA2X11_GPIO118_SDIO1_DAT0 118
171#define STA2X11_GPIO119_SDIO1_CLK 119
172#define STA2X11_GPIO120_SDIO1_CMD 120
173#define STA2X11_GPIO121 121
174#define STA2X11_GPIO122 122
175#define STA2X11_GPIO123 123
176#define STA2X11_GPIO124 124
177#define STA2X11_GPIO125_UART2_TXD 125
178#define STA2X11_GPIO126_UART2_RXD 126
179#define STA2X11_GPIO127_UART3_TXD 127
180
181/*
182 * The APB bridge has its own registers, needed by our users as well.
183 * They are accessed with the following read/mask/write function.
184 */
185u32 sta2x11_apbreg_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val);
186
187/* CAN and MLB */
188#define APBREG_BSR 0x00 /* Bridge Status Reg */
189#define APBREG_PAER 0x08 /* Peripherals Address Error Reg */
190#define APBREG_PWAC 0x20 /* Peripheral Write Access Control reg */
191#define APBREG_PRAC 0x40 /* Peripheral Read Access Control reg */
192#define APBREG_PCG 0x60 /* Peripheral Clock Gating Reg */
193#define APBREG_PUR 0x80 /* Peripheral Under Reset Reg */
194#define APBREG_EMU_PCG 0xA0 /* Emulator Peripheral Clock Gating Reg */
195
196#define APBREG_CAN (1 << 1)
197#define APBREG_MLB (1 << 3)
198
199/* SARAC */
200#define APBREG_BSR_SARAC 0x100 /* Bridge Status Reg */
201#define APBREG_PAER_SARAC 0x108 /* Peripherals Address Error Reg */
202#define APBREG_PWAC_SARAC 0x120 /* Peripheral Write Access Control reg */
203#define APBREG_PRAC_SARAC 0x140 /* Peripheral Read Access Control reg */
204#define APBREG_PCG_SARAC 0x160 /* Peripheral Clock Gating Reg */
205#define APBREG_PUR_SARAC 0x180 /* Peripheral Under Reset Reg */
206#define APBREG_EMU_PCG_SARAC 0x1A0 /* Emulator Peripheral Clock Gating Reg */
207
208#define APBREG_SARAC (1 << 2)
209
210/*
211 * The system controller has its own registers. Some of these are accessed
212 * by out users as well, using the following read/mask/write/function
213 */
214u32 sta2x11_sctl_mask(struct pci_dev *pdev, u32 reg, u32 mask, u32 val);
215
216#define SCTL_SCCTL 0x00 /* System controller control register */
217#define SCTL_ARMCFG 0x04 /* ARM configuration register */
218#define SCTL_SCPLLCTL 0x08 /* PLL control status register */
219#define SCTL_SCPLLFCTRL 0x0c /* PLL frequency control register */
220#define SCTL_SCRESFRACT 0x10 /* PLL fractional input register */
221#define SCTL_SCRESCTRL1 0x14 /* Peripheral reset control 1 */
222#define SCTL_SCRESXTRL2 0x18 /* Peripheral reset control 2 */
223#define SCTL_SCPEREN0 0x1c /* Peripheral clock enable register 0 */
224#define SCTL_SCPEREN1 0x20 /* Peripheral clock enable register 1 */
225#define SCTL_SCPEREN2 0x24 /* Peripheral clock enable register 2 */
226#define SCTL_SCGRST 0x28 /* Peripheral global reset */
227#define SCTL_SCPCIPMCR1 0x30 /* PCI power management control 1 */
228#define SCTL_SCPCIPMCR2 0x34 /* PCI power management control 2 */
229#define SCTL_SCPCIPMSR1 0x38 /* PCI power management status 1 */
230#define SCTL_SCPCIPMSR2 0x3c /* PCI power management status 2 */
231#define SCTL_SCPCIPMSR3 0x40 /* PCI power management status 3 */
232#define SCTL_SCINTREN 0x44 /* Interrupt enable */
233#define SCTL_SCRISR 0x48 /* RAW interrupt status */
234#define SCTL_SCCLKSTAT0 0x4c /* Peripheral clocks status 0 */
235#define SCTL_SCCLKSTAT1 0x50 /* Peripheral clocks status 1 */
236#define SCTL_SCCLKSTAT2 0x54 /* Peripheral clocks status 2 */
237#define SCTL_SCRSTSTA 0x58 /* Reset status register */
238
239#define SCTL_SCRESCTRL1_USB_PHY_POR (1 << 0)
240#define SCTL_SCRESCTRL1_USB_OTG (1 << 1)
241#define SCTL_SCRESCTRL1_USB_HRST (1 << 2)
242#define SCTL_SCRESCTRL1_USB_PHY_HOST (1 << 3)
243#define SCTL_SCRESCTRL1_SATAII (1 << 4)
244#define SCTL_SCRESCTRL1_VIP (1 << 5)
245#define SCTL_SCRESCTRL1_PER_MMC0 (1 << 6)
246#define SCTL_SCRESCTRL1_PER_MMC1 (1 << 7)
247#define SCTL_SCRESCTRL1_PER_GPIO0 (1 << 8)
248#define SCTL_SCRESCTRL1_PER_GPIO1 (1 << 9)
249#define SCTL_SCRESCTRL1_PER_GPIO2 (1 << 10)
250#define SCTL_SCRESCTRL1_PER_GPIO3 (1 << 11)
251#define SCTL_SCRESCTRL1_PER_MTU0 (1 << 12)
252#define SCTL_SCRESCTRL1_KER_SPI0 (1 << 13)
253#define SCTL_SCRESCTRL1_KER_SPI1 (1 << 14)
254#define SCTL_SCRESCTRL1_KER_SPI2 (1 << 15)
255#define SCTL_SCRESCTRL1_KER_MCI0 (1 << 16)
256#define SCTL_SCRESCTRL1_KER_MCI1 (1 << 17)
257#define SCTL_SCRESCTRL1_PRE_HSI2C0 (1 << 18)
258#define SCTL_SCRESCTRL1_PER_HSI2C1 (1 << 19)
259#define SCTL_SCRESCTRL1_PER_HSI2C2 (1 << 20)
260#define SCTL_SCRESCTRL1_PER_HSI2C3 (1 << 21)
261#define SCTL_SCRESCTRL1_PER_MSP0 (1 << 22)
262#define SCTL_SCRESCTRL1_PER_MSP1 (1 << 23)
263#define SCTL_SCRESCTRL1_PER_MSP2 (1 << 24)
264#define SCTL_SCRESCTRL1_PER_MSP3 (1 << 25)
265#define SCTL_SCRESCTRL1_PER_MSP4 (1 << 26)
266#define SCTL_SCRESCTRL1_PER_MSP5 (1 << 27)
267#define SCTL_SCRESCTRL1_PER_MMC (1 << 28)
268#define SCTL_SCRESCTRL1_KER_MSP0 (1 << 29)
269#define SCTL_SCRESCTRL1_KER_MSP1 (1 << 30)
270#define SCTL_SCRESCTRL1_KER_MSP2 (1 << 31)
271
272#define SCTL_SCPEREN0_UART0 (1 << 0)
273#define SCTL_SCPEREN0_UART1 (1 << 1)
274#define SCTL_SCPEREN0_UART2 (1 << 2)
275#define SCTL_SCPEREN0_UART3 (1 << 3)
276#define SCTL_SCPEREN0_MSP0 (1 << 4)
277#define SCTL_SCPEREN0_MSP1 (1 << 5)
278#define SCTL_SCPEREN0_MSP2 (1 << 6)
279#define SCTL_SCPEREN0_MSP3 (1 << 7)
280#define SCTL_SCPEREN0_MSP4 (1 << 8)
281#define SCTL_SCPEREN0_MSP5 (1 << 9)
282#define SCTL_SCPEREN0_SPI0 (1 << 10)
283#define SCTL_SCPEREN0_SPI1 (1 << 11)
284#define SCTL_SCPEREN0_SPI2 (1 << 12)
285#define SCTL_SCPEREN0_I2C0 (1 << 13)
286#define SCTL_SCPEREN0_I2C1 (1 << 14)
287#define SCTL_SCPEREN0_I2C2 (1 << 15)
288#define SCTL_SCPEREN0_I2C3 (1 << 16)
289#define SCTL_SCPEREN0_SVDO_LVDS (1 << 17)
290#define SCTL_SCPEREN0_USB_HOST (1 << 18)
291#define SCTL_SCPEREN0_USB_OTG (1 << 19)
292#define SCTL_SCPEREN0_MCI0 (1 << 20)
293#define SCTL_SCPEREN0_MCI1 (1 << 21)
294#define SCTL_SCPEREN0_MCI2 (1 << 22)
295#define SCTL_SCPEREN0_MCI3 (1 << 23)
296#define SCTL_SCPEREN0_SATA (1 << 24)
297#define SCTL_SCPEREN0_ETHERNET (1 << 25)
298#define SCTL_SCPEREN0_VIC (1 << 26)
299#define SCTL_SCPEREN0_DMA_AUDIO (1 << 27)
300#define SCTL_SCPEREN0_DMA_SOC (1 << 28)
301#define SCTL_SCPEREN0_RAM (1 << 29)
302#define SCTL_SCPEREN0_VIP (1 << 30)
303#define SCTL_SCPEREN0_ARM (1 << 31)
304
305#define SCTL_SCPEREN1_UART0 (1 << 0)
306#define SCTL_SCPEREN1_UART1 (1 << 1)
307#define SCTL_SCPEREN1_UART2 (1 << 2)
308#define SCTL_SCPEREN1_UART3 (1 << 3)
309#define SCTL_SCPEREN1_MSP0 (1 << 4)
310#define SCTL_SCPEREN1_MSP1 (1 << 5)
311#define SCTL_SCPEREN1_MSP2 (1 << 6)
312#define SCTL_SCPEREN1_MSP3 (1 << 7)
313#define SCTL_SCPEREN1_MSP4 (1 << 8)
314#define SCTL_SCPEREN1_MSP5 (1 << 9)
315#define SCTL_SCPEREN1_SPI0 (1 << 10)
316#define SCTL_SCPEREN1_SPI1 (1 << 11)
317#define SCTL_SCPEREN1_SPI2 (1 << 12)
318#define SCTL_SCPEREN1_I2C0 (1 << 13)
319#define SCTL_SCPEREN1_I2C1 (1 << 14)
320#define SCTL_SCPEREN1_I2C2 (1 << 15)
321#define SCTL_SCPEREN1_I2C3 (1 << 16)
322#define SCTL_SCPEREN1_USB_PHY (1 << 17)
323
324#endif /* __STA2X11_MFD_H */
diff --git a/include/linux/mfd/stmpe.h b/include/linux/mfd/stmpe.h
index 8516fd1eaabc..f8d5b4d5843f 100644
--- a/include/linux/mfd/stmpe.h
+++ b/include/linux/mfd/stmpe.h
@@ -117,7 +117,7 @@ struct matrix_keymap_data;
117 * @no_autorepeat: disable key autorepeat 117 * @no_autorepeat: disable key autorepeat
118 */ 118 */
119struct stmpe_keypad_platform_data { 119struct stmpe_keypad_platform_data {
120 struct matrix_keymap_data *keymap_data; 120 const struct matrix_keymap_data *keymap_data;
121 unsigned int debounce_ms; 121 unsigned int debounce_ms;
122 unsigned int scan_count; 122 unsigned int scan_count;
123 bool no_autorepeat; 123 bool no_autorepeat;
diff --git a/include/linux/mfd/tps65090.h b/include/linux/mfd/tps65090.h
index 38e31c55adbb..6bc31d854626 100644
--- a/include/linux/mfd/tps65090.h
+++ b/include/linux/mfd/tps65090.h
@@ -22,6 +22,19 @@
22#ifndef __LINUX_MFD_TPS65090_H 22#ifndef __LINUX_MFD_TPS65090_H
23#define __LINUX_MFD_TPS65090_H 23#define __LINUX_MFD_TPS65090_H
24 24
25#include <linux/irq.h>
26
27struct tps65090 {
28 struct mutex lock;
29 struct device *dev;
30 struct i2c_client *client;
31 struct regmap *rmap;
32 struct irq_chip irq_chip;
33 struct mutex irq_lock;
34 int irq_base;
35 unsigned int id;
36};
37
25struct tps65090_subdev_info { 38struct tps65090_subdev_info {
26 int id; 39 int id;
27 const char *name; 40 const char *name;
diff --git a/include/linux/mfd/tps6586x.h b/include/linux/mfd/tps6586x.h
index b19176eab44d..f350fd0ba1df 100644
--- a/include/linux/mfd/tps6586x.h
+++ b/include/linux/mfd/tps6586x.h
@@ -68,6 +68,7 @@ struct tps6586x_subdev_info {
68 int id; 68 int id;
69 const char *name; 69 const char *name;
70 void *platform_data; 70 void *platform_data;
71 struct device_node *of_node;
71}; 72};
72 73
73struct tps6586x_platform_data { 74struct tps6586x_platform_data {
diff --git a/include/linux/mfd/tps65910.h b/include/linux/mfd/tps65910.h
index 1c6c2860d1a6..dd8dc0a6c462 100644
--- a/include/linux/mfd/tps65910.h
+++ b/include/linux/mfd/tps65910.h
@@ -18,6 +18,7 @@
18#define __LINUX_MFD_TPS65910_H 18#define __LINUX_MFD_TPS65910_H
19 19
20#include <linux/gpio.h> 20#include <linux/gpio.h>
21#include <linux/regmap.h>
21 22
22/* TPS chip id list */ 23/* TPS chip id list */
23#define TPS65910 0 24#define TPS65910 0
@@ -783,6 +784,18 @@
783#define TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3 0x4 784#define TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3 0x4
784#define TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP 0x8 785#define TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP 0x8
785 786
787/*
788 * Sleep keepon data: Maintains the state in sleep mode
789 * @therm_keepon: Keep on the thermal monitoring in sleep state.
790 * @clkout32k_keepon: Keep on the 32KHz clock output in sleep state.
791 * @i2chs_keepon: Keep on high speed internal clock in sleep state.
792 */
793struct tps65910_sleep_keepon_data {
794 unsigned therm_keepon:1;
795 unsigned clkout32k_keepon:1;
796 unsigned i2chs_keepon:1;
797};
798
786/** 799/**
787 * struct tps65910_board 800 * struct tps65910_board
788 * Board platform data may be used to initialize regulators. 801 * Board platform data may be used to initialize regulators.
@@ -794,6 +807,8 @@ struct tps65910_board {
794 int irq_base; 807 int irq_base;
795 int vmbch_threshold; 808 int vmbch_threshold;
796 int vmbch2_threshold; 809 int vmbch2_threshold;
810 bool en_dev_slp;
811 struct tps65910_sleep_keepon_data *slp_keepon;
797 bool en_gpio_sleep[TPS6591X_MAX_NUM_GPIO]; 812 bool en_gpio_sleep[TPS6591X_MAX_NUM_GPIO];
798 unsigned long regulator_ext_sleep_control[TPS65910_NUM_REGS]; 813 unsigned long regulator_ext_sleep_control[TPS65910_NUM_REGS];
799 struct regulator_init_data *tps65910_pmic_init_data[TPS65910_NUM_REGS]; 814 struct regulator_init_data *tps65910_pmic_init_data[TPS65910_NUM_REGS];
@@ -809,16 +824,14 @@ struct tps65910 {
809 struct regmap *regmap; 824 struct regmap *regmap;
810 struct mutex io_mutex; 825 struct mutex io_mutex;
811 unsigned int id; 826 unsigned int id;
812 int (*read)(struct tps65910 *tps65910, u8 reg, int size, void *dest);
813 int (*write)(struct tps65910 *tps65910, u8 reg, int size, void *src);
814 827
815 /* Client devices */ 828 /* Client devices */
816 struct tps65910_pmic *pmic; 829 struct tps65910_pmic *pmic;
817 struct tps65910_rtc *rtc; 830 struct tps65910_rtc *rtc;
818 struct tps65910_power *power; 831 struct tps65910_power *power;
819 832
820 /* GPIO Handling */ 833 /* Device node parsed board data */
821 struct gpio_chip gpio; 834 struct tps65910_board *of_plat_data;
822 835
823 /* IRQ Handling */ 836 /* IRQ Handling */
824 struct mutex irq_lock; 837 struct mutex irq_lock;
@@ -826,6 +839,7 @@ struct tps65910 {
826 int irq_base; 839 int irq_base;
827 int irq_num; 840 int irq_num;
828 u32 irq_mask; 841 u32 irq_mask;
842 struct irq_domain *domain;
829}; 843};
830 844
831struct tps65910_platform_data { 845struct tps65910_platform_data {
@@ -833,9 +847,6 @@ struct tps65910_platform_data {
833 int irq_base; 847 int irq_base;
834}; 848};
835 849
836int tps65910_set_bits(struct tps65910 *tps65910, u8 reg, u8 mask);
837int tps65910_clear_bits(struct tps65910 *tps65910, u8 reg, u8 mask);
838void tps65910_gpio_init(struct tps65910 *tps65910, int gpio_base);
839int tps65910_irq_init(struct tps65910 *tps65910, int irq, 850int tps65910_irq_init(struct tps65910 *tps65910, int irq,
840 struct tps65910_platform_data *pdata); 851 struct tps65910_platform_data *pdata);
841int tps65910_irq_exit(struct tps65910 *tps65910); 852int tps65910_irq_exit(struct tps65910 *tps65910);
@@ -845,4 +856,28 @@ static inline int tps65910_chip_id(struct tps65910 *tps65910)
845 return tps65910->id; 856 return tps65910->id;
846} 857}
847 858
859static inline int tps65910_reg_read(struct tps65910 *tps65910, u8 reg,
860 unsigned int *val)
861{
862 return regmap_read(tps65910->regmap, reg, val);
863}
864
865static inline int tps65910_reg_write(struct tps65910 *tps65910, u8 reg,
866 unsigned int val)
867{
868 return regmap_write(tps65910->regmap, reg, val);
869}
870
871static inline int tps65910_reg_set_bits(struct tps65910 *tps65910, u8 reg,
872 u8 mask)
873{
874 return regmap_update_bits(tps65910->regmap, reg, mask, mask);
875}
876
877static inline int tps65910_reg_clear_bits(struct tps65910 *tps65910, u8 reg,
878 u8 mask)
879{
880 return regmap_update_bits(tps65910->regmap, reg, mask, 0);
881}
882
848#endif /* __LINUX_MFD_TPS65910_H */ 883#endif /* __LINUX_MFD_TPS65910_H */
diff --git a/include/linux/mfd/twl6040.h b/include/linux/mfd/twl6040.h
index b15b5f03f5c4..6659487c31e7 100644
--- a/include/linux/mfd/twl6040.h
+++ b/include/linux/mfd/twl6040.h
@@ -27,6 +27,7 @@
27 27
28#include <linux/interrupt.h> 28#include <linux/interrupt.h>
29#include <linux/mfd/core.h> 29#include <linux/mfd/core.h>
30#include <linux/regulator/consumer.h>
30 31
31#define TWL6040_REG_ASICID 0x01 32#define TWL6040_REG_ASICID 0x01
32#define TWL6040_REG_ASICREV 0x02 33#define TWL6040_REG_ASICREV 0x02
@@ -203,6 +204,7 @@ struct regmap;
203struct twl6040 { 204struct twl6040 {
204 struct device *dev; 205 struct device *dev;
205 struct regmap *regmap; 206 struct regmap *regmap;
207 struct regulator_bulk_data supplies[2]; /* supplies for vio, v2v1 */
206 struct mutex mutex; 208 struct mutex mutex;
207 struct mutex io_mutex; 209 struct mutex io_mutex;
208 struct mutex irq_mutex; 210 struct mutex irq_mutex;
diff --git a/include/linux/mfd/wm831x/core.h b/include/linux/mfd/wm831x/core.h
index 4b1211859f74..4a3b83a77614 100644
--- a/include/linux/mfd/wm831x/core.h
+++ b/include/linux/mfd/wm831x/core.h
@@ -17,6 +17,7 @@
17 17
18#include <linux/completion.h> 18#include <linux/completion.h>
19#include <linux/interrupt.h> 19#include <linux/interrupt.h>
20#include <linux/irqdomain.h>
20#include <linux/list.h> 21#include <linux/list.h>
21#include <linux/regmap.h> 22#include <linux/regmap.h>
22 23
@@ -338,6 +339,7 @@
338#define WM831X_FLL_CLK_SRC_WIDTH 2 /* FLL_CLK_SRC - [1:0] */ 339#define WM831X_FLL_CLK_SRC_WIDTH 2 /* FLL_CLK_SRC - [1:0] */
339 340
340struct regulator_dev; 341struct regulator_dev;
342struct irq_domain;
341 343
342#define WM831X_NUM_IRQ_REGS 5 344#define WM831X_NUM_IRQ_REGS 5
343#define WM831X_NUM_GPIO_REGS 16 345#define WM831X_NUM_GPIO_REGS 16
@@ -367,7 +369,7 @@ struct wm831x {
367 369
368 int irq; /* Our chip IRQ */ 370 int irq; /* Our chip IRQ */
369 struct mutex irq_lock; 371 struct mutex irq_lock;
370 int irq_base; 372 struct irq_domain *irq_domain;
371 int irq_masks_cur[WM831X_NUM_IRQ_REGS]; /* Currently active value */ 373 int irq_masks_cur[WM831X_NUM_IRQ_REGS]; /* Currently active value */
372 int irq_masks_cache[WM831X_NUM_IRQ_REGS]; /* Cached hardware value */ 374 int irq_masks_cache[WM831X_NUM_IRQ_REGS]; /* Cached hardware value */
373 375
@@ -382,7 +384,8 @@ struct wm831x {
382 384
383 /* Used by the interrupt controller code to post writes */ 385 /* Used by the interrupt controller code to post writes */
384 int gpio_update[WM831X_NUM_GPIO_REGS]; 386 int gpio_update[WM831X_NUM_GPIO_REGS];
385 bool gpio_level[WM831X_NUM_GPIO_REGS]; 387 bool gpio_level_high[WM831X_NUM_GPIO_REGS];
388 bool gpio_level_low[WM831X_NUM_GPIO_REGS];
386 389
387 struct mutex auxadc_lock; 390 struct mutex auxadc_lock;
388 struct list_head auxadc_pending; 391 struct list_head auxadc_pending;
@@ -417,6 +420,11 @@ int wm831x_irq_init(struct wm831x *wm831x, int irq);
417void wm831x_irq_exit(struct wm831x *wm831x); 420void wm831x_irq_exit(struct wm831x *wm831x);
418void wm831x_auxadc_init(struct wm831x *wm831x); 421void wm831x_auxadc_init(struct wm831x *wm831x);
419 422
423static inline int wm831x_irq(struct wm831x *wm831x, int irq)
424{
425 return irq_create_mapping(wm831x->irq_domain, irq);
426}
427
420extern struct regmap_config wm831x_regmap_config; 428extern struct regmap_config wm831x_regmap_config;
421 429
422#endif 430#endif
diff --git a/include/linux/mfd/wm831x/pdata.h b/include/linux/mfd/wm831x/pdata.h
index 1d7a3f7b3b5d..dcc9631b3052 100644
--- a/include/linux/mfd/wm831x/pdata.h
+++ b/include/linux/mfd/wm831x/pdata.h
@@ -26,7 +26,7 @@ struct wm831x_backlight_pdata {
26struct wm831x_backup_pdata { 26struct wm831x_backup_pdata {
27 int charger_enable; 27 int charger_enable;
28 int no_constant_voltage; /** Disable constant voltage charging */ 28 int no_constant_voltage; /** Disable constant voltage charging */
29 int vlim; /** Voltage limit in milivolts */ 29 int vlim; /** Voltage limit in millivolts */
30 int ilim; /** Current limit in microamps */ 30 int ilim; /** Current limit in microamps */
31}; 31};
32 32
diff --git a/include/linux/mfd/wm8350/core.h b/include/linux/mfd/wm8350/core.h
index 98fcc977e82b..9192b6404a73 100644
--- a/include/linux/mfd/wm8350/core.h
+++ b/include/linux/mfd/wm8350/core.h
@@ -602,6 +602,7 @@ extern const u16 wm8352_mode2_defaults[];
602extern const u16 wm8352_mode3_defaults[]; 602extern const u16 wm8352_mode3_defaults[];
603 603
604struct wm8350; 604struct wm8350;
605struct regmap;
605 606
606struct wm8350_hwmon { 607struct wm8350_hwmon {
607 struct platform_device *pdev; 608 struct platform_device *pdev;
@@ -612,13 +613,7 @@ struct wm8350 {
612 struct device *dev; 613 struct device *dev;
613 614
614 /* device IO */ 615 /* device IO */
615 union { 616 struct regmap *regmap;
616 struct i2c_client *i2c_client;
617 struct spi_device *spi_device;
618 };
619 int (*read_dev)(struct wm8350 *wm8350, char reg, int size, void *dest);
620 int (*write_dev)(struct wm8350 *wm8350, char reg, int size,
621 void *src);
622 u16 *reg_cache; 617 u16 *reg_cache;
623 618
624 struct mutex auxadc_mutex; 619 struct mutex auxadc_mutex;
diff --git a/include/linux/mfd/wm8400-private.h b/include/linux/mfd/wm8400-private.h
index 0147b6968510..2de565b94d0c 100644
--- a/include/linux/mfd/wm8400-private.h
+++ b/include/linux/mfd/wm8400-private.h
@@ -24,19 +24,14 @@
24#include <linux/mfd/wm8400.h> 24#include <linux/mfd/wm8400.h>
25#include <linux/mutex.h> 25#include <linux/mutex.h>
26#include <linux/platform_device.h> 26#include <linux/platform_device.h>
27 27#include <linux/regmap.h>
28struct regmap;
29 28
30#define WM8400_REGISTER_COUNT 0x55 29#define WM8400_REGISTER_COUNT 0x55
31 30
32struct wm8400 { 31struct wm8400 {
33 struct device *dev; 32 struct device *dev;
34
35 struct mutex io_lock;
36 struct regmap *regmap; 33 struct regmap *regmap;
37 34
38 u16 reg_cache[WM8400_REGISTER_COUNT];
39
40 struct platform_device regulators[6]; 35 struct platform_device regulators[6];
41}; 36};
42 37
@@ -930,6 +925,11 @@ struct wm8400 {
930 925
931u16 wm8400_reg_read(struct wm8400 *wm8400, u8 reg); 926u16 wm8400_reg_read(struct wm8400 *wm8400, u8 reg);
932int wm8400_block_read(struct wm8400 *wm8400, u8 reg, int count, u16 *data); 927int wm8400_block_read(struct wm8400 *wm8400, u8 reg, int count, u16 *data);
933int wm8400_set_bits(struct wm8400 *wm8400, u8 reg, u16 mask, u16 val); 928
929static inline int wm8400_set_bits(struct wm8400 *wm8400, u8 reg,
930 u16 mask, u16 val)
931{
932 return regmap_update_bits(wm8400->regmap, reg, mask, val);
933}
934 934
935#endif 935#endif
diff --git a/include/linux/mfd/wm8994/core.h b/include/linux/mfd/wm8994/core.h
index 9eff2a351ec5..1f173306bf05 100644
--- a/include/linux/mfd/wm8994/core.h
+++ b/include/linux/mfd/wm8994/core.h
@@ -17,6 +17,7 @@
17 17
18#include <linux/mutex.h> 18#include <linux/mutex.h>
19#include <linux/interrupt.h> 19#include <linux/interrupt.h>
20#include <linux/regmap.h>
20 21
21enum wm8994_type { 22enum wm8994_type {
22 WM8994 = 0, 23 WM8994 = 0,
@@ -26,7 +27,6 @@ enum wm8994_type {
26 27
27struct regulator_dev; 28struct regulator_dev;
28struct regulator_bulk_data; 29struct regulator_bulk_data;
29struct regmap;
30 30
31#define WM8994_NUM_GPIO_REGS 11 31#define WM8994_NUM_GPIO_REGS 11
32#define WM8994_NUM_LDO_REGS 2 32#define WM8994_NUM_LDO_REGS 2
@@ -57,6 +57,7 @@ struct wm8994 {
57 57
58 enum wm8994_type type; 58 enum wm8994_type type;
59 int revision; 59 int revision;
60 int cust_id;
60 61
61 struct device *dev; 62 struct device *dev;
62 struct regmap *regmap; 63 struct regmap *regmap;
@@ -94,17 +95,17 @@ static inline int wm8994_request_irq(struct wm8994 *wm8994, int irq,
94 irq_handler_t handler, const char *name, 95 irq_handler_t handler, const char *name,
95 void *data) 96 void *data)
96{ 97{
97 if (!wm8994->irq_base) 98 if (!wm8994->irq_data)
98 return -EINVAL; 99 return -EINVAL;
99 return request_threaded_irq(wm8994->irq_base + irq, NULL, handler, 100 return request_threaded_irq(regmap_irq_get_virq(wm8994->irq_data, irq),
100 IRQF_TRIGGER_RISING, name, 101 NULL, handler, IRQF_TRIGGER_RISING, name,
101 data); 102 data);
102} 103}
103static inline void wm8994_free_irq(struct wm8994 *wm8994, int irq, void *data) 104static inline void wm8994_free_irq(struct wm8994 *wm8994, int irq, void *data)
104{ 105{
105 if (!wm8994->irq_base) 106 if (!wm8994->irq_data)
106 return; 107 return;
107 free_irq(wm8994->irq_base + irq, data); 108 free_irq(regmap_irq_get_virq(wm8994->irq_data, irq), data);
108} 109}
109 110
110int wm8994_irq_init(struct wm8994 *wm8994); 111int wm8994_irq_init(struct wm8994 *wm8994);
diff --git a/include/linux/mfd/wm8994/registers.h b/include/linux/mfd/wm8994/registers.h
index 86e6a032a078..053548961c15 100644
--- a/include/linux/mfd/wm8994/registers.h
+++ b/include/linux/mfd/wm8994/registers.h
@@ -2212,6 +2212,9 @@
2212/* 2212/*
2213 * R256 (0x100) - Chip Revision 2213 * R256 (0x100) - Chip Revision
2214 */ 2214 */
2215#define WM8994_CUST_ID_MASK 0xFF00 /* CUST_ID - [15:8] */
2216#define WM8994_CUST_ID_SHIFT 8 /* CUST_ID - [15:8] */
2217#define WM8994_CUST_ID_WIDTH 8 /* CUST_ID - [15:8] */
2215#define WM8994_CHIP_REV_MASK 0x000F /* CHIP_REV - [3:0] */ 2218#define WM8994_CHIP_REV_MASK 0x000F /* CHIP_REV - [3:0] */
2216#define WM8994_CHIP_REV_SHIFT 0 /* CHIP_REV - [3:0] */ 2219#define WM8994_CHIP_REV_SHIFT 0 /* CHIP_REV - [3:0] */
2217#define WM8994_CHIP_REV_WIDTH 4 /* CHIP_REV - [3:0] */ 2220#define WM8994_CHIP_REV_WIDTH 4 /* CHIP_REV - [3:0] */
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-03 23:17:27 -0400