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-rw-r--r--include/linux/mfd/88pm860x.h48
-rw-r--r--include/linux/mfd/ab3100.h129
-rw-r--r--include/linux/mfd/abx500.h117
-rw-r--r--include/linux/mfd/abx500/ab8500.h2
-rw-r--r--include/linux/mfd/anatop.h40
-rw-r--r--include/linux/mfd/da9055/core.h94
-rw-r--r--include/linux/mfd/da9055/pdata.h32
-rw-r--r--include/linux/mfd/da9055/reg.h699
-rw-r--r--include/linux/mfd/lp8788-isink.h52
-rw-r--r--include/linux/mfd/lp8788.h364
-rw-r--r--include/linux/mfd/lpc_ich.h1
-rw-r--r--include/linux/mfd/max8907.h252
-rw-r--r--include/linux/mfd/max8925.h26
-rw-r--r--include/linux/mfd/palmas.h232
-rw-r--r--include/linux/mfd/smsc.h109
-rw-r--r--include/linux/mfd/syscon.h23
-rw-r--r--include/linux/mfd/syscon/imx6q-iomuxc-gpr.h319
-rw-r--r--include/linux/mfd/tc3589x.h1
-rw-r--r--include/linux/mfd/tps65217.h18
-rw-r--r--include/linux/mfd/tps6586x.h1
-rw-r--r--include/linux/mfd/tps65910.h3
-rw-r--r--include/linux/mfd/twl6040.h11
22 files changed, 2351 insertions, 222 deletions
diff --git a/include/linux/mfd/88pm860x.h b/include/linux/mfd/88pm860x.h
index 7b24943779fa..ef3e6b701179 100644
--- a/include/linux/mfd/88pm860x.h
+++ b/include/linux/mfd/88pm860x.h
@@ -34,22 +34,6 @@ enum {
34 PM8606_ID_MAX, 34 PM8606_ID_MAX,
35}; 35};
36 36
37enum {
38 PM8606_BACKLIGHT1 = 0,
39 PM8606_BACKLIGHT2,
40 PM8606_BACKLIGHT3,
41};
42
43enum {
44 PM8606_LED1_RED = 0,
45 PM8606_LED1_GREEN,
46 PM8606_LED1_BLUE,
47 PM8606_LED2_RED,
48 PM8606_LED2_GREEN,
49 PM8606_LED2_BLUE,
50 PM8607_LED_VIBRATOR,
51};
52
53 37
54/* 8606 Registers */ 38/* 8606 Registers */
55#define PM8606_DCM_BOOST (0x00) 39#define PM8606_DCM_BOOST (0x00)
@@ -322,7 +306,7 @@ struct pm860x_chip {
322 struct regmap *regmap_companion; 306 struct regmap *regmap_companion;
323 307
324 int buck3_double; /* DVC ramp slope double */ 308 int buck3_double; /* DVC ramp slope double */
325 unsigned short companion_addr; 309 int companion_addr;
326 unsigned short osc_vote; 310 unsigned short osc_vote;
327 int id; 311 int id;
328 int irq_mode; 312 int irq_mode;
@@ -340,16 +324,12 @@ enum {
340}; 324};
341 325
342struct pm860x_backlight_pdata { 326struct pm860x_backlight_pdata {
343 int id;
344 int pwm; 327 int pwm;
345 int iset; 328 int iset;
346 unsigned long flags;
347}; 329};
348 330
349struct pm860x_led_pdata { 331struct pm860x_led_pdata {
350 int id;
351 int iset; 332 int iset;
352 unsigned long flags;
353}; 333};
354 334
355struct pm860x_rtc_pdata { 335struct pm860x_rtc_pdata {
@@ -379,15 +359,29 @@ struct pm860x_platform_data {
379 struct pm860x_rtc_pdata *rtc; 359 struct pm860x_rtc_pdata *rtc;
380 struct pm860x_touch_pdata *touch; 360 struct pm860x_touch_pdata *touch;
381 struct pm860x_power_pdata *power; 361 struct pm860x_power_pdata *power;
382 struct regulator_init_data *regulator; 362 struct regulator_init_data *buck1;
383 363 struct regulator_init_data *buck2;
384 unsigned short companion_addr; /* I2C address of companion chip */ 364 struct regulator_init_data *buck3;
365 struct regulator_init_data *ldo1;
366 struct regulator_init_data *ldo2;
367 struct regulator_init_data *ldo3;
368 struct regulator_init_data *ldo4;
369 struct regulator_init_data *ldo5;
370 struct regulator_init_data *ldo6;
371 struct regulator_init_data *ldo7;
372 struct regulator_init_data *ldo8;
373 struct regulator_init_data *ldo9;
374 struct regulator_init_data *ldo10;
375 struct regulator_init_data *ldo12;
376 struct regulator_init_data *ldo_vibrator;
377 struct regulator_init_data *ldo14;
378
379 int companion_addr; /* I2C address of companion chip */
385 int i2c_port; /* Controlled by GI2C or PI2C */ 380 int i2c_port; /* Controlled by GI2C or PI2C */
386 int irq_mode; /* Clear interrupt by read/write(0/1) */ 381 int irq_mode; /* Clear interrupt by read/write(0/1) */
387 int irq_base; /* IRQ base number of 88pm860x */ 382 int irq_base; /* IRQ base number of 88pm860x */
388 int num_leds; 383 int num_leds;
389 int num_backlights; 384 int num_backlights;
390 int num_regulators;
391}; 385};
392 386
393extern int pm8606_osc_enable(struct pm860x_chip *, unsigned short); 387extern int pm8606_osc_enable(struct pm860x_chip *, unsigned short);
@@ -408,8 +402,4 @@ extern int pm860x_page_bulk_write(struct i2c_client *, int, int,
408extern int pm860x_page_set_bits(struct i2c_client *, int, unsigned char, 402extern int pm860x_page_set_bits(struct i2c_client *, int, unsigned char,
409 unsigned char); 403 unsigned char);
410 404
411extern int pm860x_device_init(struct pm860x_chip *chip,
412 struct pm860x_platform_data *pdata) __devinit ;
413extern void pm860x_device_exit(struct pm860x_chip *chip) __devexit ;
414
415#endif /* __LINUX_MFD_88PM860X_H */ 405#endif /* __LINUX_MFD_88PM860X_H */
diff --git a/include/linux/mfd/ab3100.h b/include/linux/mfd/ab3100.h
new file mode 100644
index 000000000000..afd3080bde24
--- /dev/null
+++ b/include/linux/mfd/ab3100.h
@@ -0,0 +1,129 @@
1/*
2 * Copyright (C) 2007-2009 ST-Ericsson AB
3 * License terms: GNU General Public License (GPL) version 2
4 * AB3100 core access functions
5 * Author: Linus Walleij <linus.walleij@stericsson.com>
6 *
7 */
8
9#include <linux/regulator/machine.h>
10
11struct device;
12
13#ifndef MFD_AB3100_H
14#define MFD_AB3100_H
15
16
17#define AB3100_P1A 0xc0
18#define AB3100_P1B 0xc1
19#define AB3100_P1C 0xc2
20#define AB3100_P1D 0xc3
21#define AB3100_P1E 0xc4
22#define AB3100_P1F 0xc5
23#define AB3100_P1G 0xc6
24#define AB3100_R2A 0xc7
25#define AB3100_R2B 0xc8
26
27/*
28 * AB3100, EVENTA1, A2 and A3 event register flags
29 * these are catenated into a single 32-bit flag in the code
30 * for event notification broadcasts.
31 */
32#define AB3100_EVENTA1_ONSWA (0x01<<16)
33#define AB3100_EVENTA1_ONSWB (0x02<<16)
34#define AB3100_EVENTA1_ONSWC (0x04<<16)
35#define AB3100_EVENTA1_DCIO (0x08<<16)
36#define AB3100_EVENTA1_OVER_TEMP (0x10<<16)
37#define AB3100_EVENTA1_SIM_OFF (0x20<<16)
38#define AB3100_EVENTA1_VBUS (0x40<<16)
39#define AB3100_EVENTA1_VSET_USB (0x80<<16)
40
41#define AB3100_EVENTA2_READY_TX (0x01<<8)
42#define AB3100_EVENTA2_READY_RX (0x02<<8)
43#define AB3100_EVENTA2_OVERRUN_ERROR (0x04<<8)
44#define AB3100_EVENTA2_FRAMING_ERROR (0x08<<8)
45#define AB3100_EVENTA2_CHARG_OVERCURRENT (0x10<<8)
46#define AB3100_EVENTA2_MIDR (0x20<<8)
47#define AB3100_EVENTA2_BATTERY_REM (0x40<<8)
48#define AB3100_EVENTA2_ALARM (0x80<<8)
49
50#define AB3100_EVENTA3_ADC_TRIG5 (0x01)
51#define AB3100_EVENTA3_ADC_TRIG4 (0x02)
52#define AB3100_EVENTA3_ADC_TRIG3 (0x04)
53#define AB3100_EVENTA3_ADC_TRIG2 (0x08)
54#define AB3100_EVENTA3_ADC_TRIGVBAT (0x10)
55#define AB3100_EVENTA3_ADC_TRIGVTX (0x20)
56#define AB3100_EVENTA3_ADC_TRIG1 (0x40)
57#define AB3100_EVENTA3_ADC_TRIG0 (0x80)
58
59/* AB3100, STR register flags */
60#define AB3100_STR_ONSWA (0x01)
61#define AB3100_STR_ONSWB (0x02)
62#define AB3100_STR_ONSWC (0x04)
63#define AB3100_STR_DCIO (0x08)
64#define AB3100_STR_BOOT_MODE (0x10)
65#define AB3100_STR_SIM_OFF (0x20)
66#define AB3100_STR_BATT_REMOVAL (0x40)
67#define AB3100_STR_VBUS (0x80)
68
69/*
70 * AB3100 contains 8 regulators, one external regulator controller
71 * and a buck converter, further the LDO E and buck converter can
72 * have separate settings if they are in sleep mode, this is
73 * modeled as a separate regulator.
74 */
75#define AB3100_NUM_REGULATORS 10
76
77/**
78 * struct ab3100
79 * @access_mutex: lock out concurrent accesses to the AB3100 registers
80 * @dev: pointer to the containing device
81 * @i2c_client: I2C client for this chip
82 * @testreg_client: secondary client for test registers
83 * @chip_name: name of this chip variant
84 * @chip_id: 8 bit chip ID for this chip variant
85 * @event_subscribers: event subscribers are listed here
86 * @startup_events: a copy of the first reading of the event registers
87 * @startup_events_read: whether the first events have been read
88 *
89 * This struct is PRIVATE and devices using it should NOT
90 * access ANY fields. It is used as a token for calling the
91 * AB3100 functions.
92 */
93struct ab3100 {
94 struct mutex access_mutex;
95 struct device *dev;
96 struct i2c_client *i2c_client;
97 struct i2c_client *testreg_client;
98 char chip_name[32];
99 u8 chip_id;
100 struct blocking_notifier_head event_subscribers;
101 u8 startup_events[3];
102 bool startup_events_read;
103};
104
105/**
106 * struct ab3100_platform_data
107 * Data supplied to initialize board connections to the AB3100
108 * @reg_constraints: regulator constraints for target board
109 * the order of these constraints are: LDO A, C, D, E,
110 * F, G, H, K, EXT and BUCK.
111 * @reg_initvals: initial values for the regulator registers
112 * plus two sleep settings for LDO E and the BUCK converter.
113 * exactly AB3100_NUM_REGULATORS+2 values must be sent in.
114 * Order: LDO A, C, E, E sleep, F, G, H, K, EXT, BUCK,
115 * BUCK sleep, LDO D. (LDO D need to be initialized last.)
116 * @external_voltage: voltage level of the external regulator.
117 */
118struct ab3100_platform_data {
119 struct regulator_init_data reg_constraints[AB3100_NUM_REGULATORS];
120 u8 reg_initvals[AB3100_NUM_REGULATORS+2];
121 int external_voltage;
122};
123
124int ab3100_event_register(struct ab3100 *ab3100,
125 struct notifier_block *nb);
126int ab3100_event_unregister(struct ab3100 *ab3100,
127 struct notifier_block *nb);
128
129#endif /* MFD_AB3100_H */
diff --git a/include/linux/mfd/abx500.h b/include/linux/mfd/abx500.h
index 1318ca622633..5d5298d56026 100644
--- a/include/linux/mfd/abx500.h
+++ b/include/linux/mfd/abx500.h
@@ -1,12 +1,9 @@
1/* 1/*
2 * Copyright (C) 2007-2009 ST-Ericsson AB 2 * Copyright (C) 2007-2009 ST-Ericsson AB
3 * License terms: GNU General Public License (GPL) version 2 3 * License terms: GNU General Public License (GPL) version 2
4 * AB3100 core access functions
5 * Author: Linus Walleij <linus.walleij@stericsson.com>
6 * 4 *
7 * ABX500 core access functions. 5 * ABX500 core access functions.
8 * The abx500 interface is used for the Analog Baseband chip 6 * The abx500 interface is used for the Analog Baseband chips.
9 * ab3100 and ab8500.
10 * 7 *
11 * Author: Mattias Wallin <mattias.wallin@stericsson.com> 8 * Author: Mattias Wallin <mattias.wallin@stericsson.com>
12 * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com> 9 * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
@@ -21,118 +18,6 @@ struct device;
21#ifndef MFD_ABX500_H 18#ifndef MFD_ABX500_H
22#define MFD_ABX500_H 19#define MFD_ABX500_H
23 20
24#define AB3100_P1A 0xc0
25#define AB3100_P1B 0xc1
26#define AB3100_P1C 0xc2
27#define AB3100_P1D 0xc3
28#define AB3100_P1E 0xc4
29#define AB3100_P1F 0xc5
30#define AB3100_P1G 0xc6
31#define AB3100_R2A 0xc7
32#define AB3100_R2B 0xc8
33
34/*
35 * AB3100, EVENTA1, A2 and A3 event register flags
36 * these are catenated into a single 32-bit flag in the code
37 * for event notification broadcasts.
38 */
39#define AB3100_EVENTA1_ONSWA (0x01<<16)
40#define AB3100_EVENTA1_ONSWB (0x02<<16)
41#define AB3100_EVENTA1_ONSWC (0x04<<16)
42#define AB3100_EVENTA1_DCIO (0x08<<16)
43#define AB3100_EVENTA1_OVER_TEMP (0x10<<16)
44#define AB3100_EVENTA1_SIM_OFF (0x20<<16)
45#define AB3100_EVENTA1_VBUS (0x40<<16)
46#define AB3100_EVENTA1_VSET_USB (0x80<<16)
47
48#define AB3100_EVENTA2_READY_TX (0x01<<8)
49#define AB3100_EVENTA2_READY_RX (0x02<<8)
50#define AB3100_EVENTA2_OVERRUN_ERROR (0x04<<8)
51#define AB3100_EVENTA2_FRAMING_ERROR (0x08<<8)
52#define AB3100_EVENTA2_CHARG_OVERCURRENT (0x10<<8)
53#define AB3100_EVENTA2_MIDR (0x20<<8)
54#define AB3100_EVENTA2_BATTERY_REM (0x40<<8)
55#define AB3100_EVENTA2_ALARM (0x80<<8)
56
57#define AB3100_EVENTA3_ADC_TRIG5 (0x01)
58#define AB3100_EVENTA3_ADC_TRIG4 (0x02)
59#define AB3100_EVENTA3_ADC_TRIG3 (0x04)
60#define AB3100_EVENTA3_ADC_TRIG2 (0x08)
61#define AB3100_EVENTA3_ADC_TRIGVBAT (0x10)
62#define AB3100_EVENTA3_ADC_TRIGVTX (0x20)
63#define AB3100_EVENTA3_ADC_TRIG1 (0x40)
64#define AB3100_EVENTA3_ADC_TRIG0 (0x80)
65
66/* AB3100, STR register flags */
67#define AB3100_STR_ONSWA (0x01)
68#define AB3100_STR_ONSWB (0x02)
69#define AB3100_STR_ONSWC (0x04)
70#define AB3100_STR_DCIO (0x08)
71#define AB3100_STR_BOOT_MODE (0x10)
72#define AB3100_STR_SIM_OFF (0x20)
73#define AB3100_STR_BATT_REMOVAL (0x40)
74#define AB3100_STR_VBUS (0x80)
75
76/*
77 * AB3100 contains 8 regulators, one external regulator controller
78 * and a buck converter, further the LDO E and buck converter can
79 * have separate settings if they are in sleep mode, this is
80 * modeled as a separate regulator.
81 */
82#define AB3100_NUM_REGULATORS 10
83
84/**
85 * struct ab3100
86 * @access_mutex: lock out concurrent accesses to the AB3100 registers
87 * @dev: pointer to the containing device
88 * @i2c_client: I2C client for this chip
89 * @testreg_client: secondary client for test registers
90 * @chip_name: name of this chip variant
91 * @chip_id: 8 bit chip ID for this chip variant
92 * @event_subscribers: event subscribers are listed here
93 * @startup_events: a copy of the first reading of the event registers
94 * @startup_events_read: whether the first events have been read
95 *
96 * This struct is PRIVATE and devices using it should NOT
97 * access ANY fields. It is used as a token for calling the
98 * AB3100 functions.
99 */
100struct ab3100 {
101 struct mutex access_mutex;
102 struct device *dev;
103 struct i2c_client *i2c_client;
104 struct i2c_client *testreg_client;
105 char chip_name[32];
106 u8 chip_id;
107 struct blocking_notifier_head event_subscribers;
108 u8 startup_events[3];
109 bool startup_events_read;
110};
111
112/**
113 * struct ab3100_platform_data
114 * Data supplied to initialize board connections to the AB3100
115 * @reg_constraints: regulator constraints for target board
116 * the order of these constraints are: LDO A, C, D, E,
117 * F, G, H, K, EXT and BUCK.
118 * @reg_initvals: initial values for the regulator registers
119 * plus two sleep settings for LDO E and the BUCK converter.
120 * exactly AB3100_NUM_REGULATORS+2 values must be sent in.
121 * Order: LDO A, C, E, E sleep, F, G, H, K, EXT, BUCK,
122 * BUCK sleep, LDO D. (LDO D need to be initialized last.)
123 * @external_voltage: voltage level of the external regulator.
124 */
125struct ab3100_platform_data {
126 struct regulator_init_data reg_constraints[AB3100_NUM_REGULATORS];
127 u8 reg_initvals[AB3100_NUM_REGULATORS+2];
128 int external_voltage;
129};
130
131int ab3100_event_register(struct ab3100 *ab3100,
132 struct notifier_block *nb);
133int ab3100_event_unregister(struct ab3100 *ab3100,
134 struct notifier_block *nb);
135
136/** 21/**
137 * struct abx500_init_setting 22 * struct abx500_init_setting
138 * Initial value of the registers for driver to use during setup. 23 * Initial value of the registers for driver to use during setup.
diff --git a/include/linux/mfd/abx500/ab8500.h b/include/linux/mfd/abx500/ab8500.h
index 3764cb6759e3..1491044efa10 100644
--- a/include/linux/mfd/abx500/ab8500.h
+++ b/include/linux/mfd/abx500/ab8500.h
@@ -341,6 +341,4 @@ static inline int is_ab8500_2p0(struct ab8500 *ab)
341 return (is_ab8500(ab) && (ab->chip_id == AB8500_CUT2P0)); 341 return (is_ab8500(ab) && (ab->chip_id == AB8500_CUT2P0));
342} 342}
343 343
344int ab8500_irq_get_virq(struct ab8500 *ab8500, int irq);
345
346#endif /* MFD_AB8500_H */ 344#endif /* MFD_AB8500_H */
diff --git a/include/linux/mfd/anatop.h b/include/linux/mfd/anatop.h
deleted file mode 100644
index 7f92acf03d9e..000000000000
--- a/include/linux/mfd/anatop.h
+++ /dev/null
@@ -1,40 +0,0 @@
1/*
2 * anatop.h - Anatop MFD driver
3 *
4 * Copyright (C) 2012 Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
5 * Copyright (C) 2012 Linaro
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#ifndef __LINUX_MFD_ANATOP_H
23#define __LINUX_MFD_ANATOP_H
24
25#include <linux/spinlock.h>
26
27/**
28 * anatop - MFD data
29 * @ioreg: ioremap register
30 * @reglock: spinlock for register read/write
31 */
32struct anatop {
33 void *ioreg;
34 spinlock_t reglock;
35};
36
37extern u32 anatop_read_reg(struct anatop *, u32);
38extern void anatop_write_reg(struct anatop *, u32, u32, u32);
39
40#endif /* __LINUX_MFD_ANATOP_H */
diff --git a/include/linux/mfd/da9055/core.h b/include/linux/mfd/da9055/core.h
new file mode 100644
index 000000000000..c96ad682c59e
--- /dev/null
+++ b/include/linux/mfd/da9055/core.h
@@ -0,0 +1,94 @@
1/*
2 * da9055 declarations for DA9055 PMICs.
3 *
4 * Copyright(c) 2012 Dialog Semiconductor Ltd.
5 *
6 * Author: David Dajun Chen <dchen@diasemi.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 */
23
24#ifndef __DA9055_CORE_H
25#define __DA9055_CORE_H
26
27#include <linux/interrupt.h>
28#include <linux/regmap.h>
29
30/*
31 * PMIC IRQ
32 */
33#define DA9055_IRQ_ALARM 0x01
34#define DA9055_IRQ_TICK 0x02
35#define DA9055_IRQ_NONKEY 0x00
36#define DA9055_IRQ_REGULATOR 0x0B
37#define DA9055_IRQ_HWMON 0x03
38
39struct da9055_pdata;
40
41struct da9055 {
42 struct regmap *regmap;
43 struct regmap_irq_chip_data *irq_data;
44 struct device *dev;
45 struct i2c_client *i2c_client;
46
47 int irq_base;
48 int chip_irq;
49};
50
51/* Device I/O */
52static inline int da9055_reg_read(struct da9055 *da9055, unsigned char reg)
53{
54 int val, ret;
55
56 ret = regmap_read(da9055->regmap, reg, &val);
57 if (ret < 0)
58 return ret;
59
60 return val;
61}
62
63static inline int da9055_reg_write(struct da9055 *da9055, unsigned char reg,
64 unsigned char val)
65{
66 return regmap_write(da9055->regmap, reg, val);
67}
68
69static inline int da9055_group_read(struct da9055 *da9055, unsigned char reg,
70 unsigned reg_cnt, unsigned char *val)
71{
72 return regmap_bulk_read(da9055->regmap, reg, val, reg_cnt);
73}
74
75static inline int da9055_group_write(struct da9055 *da9055, unsigned char reg,
76 unsigned reg_cnt, unsigned char *val)
77{
78 return regmap_raw_write(da9055->regmap, reg, val, reg_cnt);
79}
80
81static inline int da9055_reg_update(struct da9055 *da9055, unsigned char reg,
82 unsigned char bit_mask,
83 unsigned char reg_val)
84{
85 return regmap_update_bits(da9055->regmap, reg, bit_mask, reg_val);
86}
87
88/* Generic Device API */
89int da9055_device_init(struct da9055 *da9055);
90void da9055_device_exit(struct da9055 *da9055);
91
92extern struct regmap_config da9055_regmap_config;
93
94#endif /* __DA9055_CORE_H */
diff --git a/include/linux/mfd/da9055/pdata.h b/include/linux/mfd/da9055/pdata.h
new file mode 100644
index 000000000000..147293b4471d
--- /dev/null
+++ b/include/linux/mfd/da9055/pdata.h
@@ -0,0 +1,32 @@
1/* Copyright (C) 2012 Dialog Semiconductor Ltd.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation; either version 2 of the License, or
6 * (at your option) any later version.
7 *
8 */
9#ifndef __DA9055_PDATA_H
10#define __DA9055_PDATA_H
11
12#define DA9055_MAX_REGULATORS 8
13
14struct da9055;
15
16enum gpio_select {
17 NO_GPIO = 0,
18 GPIO_1,
19 GPIO_2
20};
21
22struct da9055_pdata {
23 int (*init) (struct da9055 *da9055);
24 int irq_base;
25 int gpio_base;
26
27 struct regulator_init_data *regulators[DA9055_MAX_REGULATORS];
28 bool reset_enable; /* Enable RTC in RESET Mode */
29 enum gpio_select *gpio_rsel; /* Select regulator set thru GPIO 1/2 */
30 enum gpio_select *gpio_ren; /* Enable regulator thru GPIO 1/2 */
31};
32#endif /* __DA9055_PDATA_H */
diff --git a/include/linux/mfd/da9055/reg.h b/include/linux/mfd/da9055/reg.h
new file mode 100644
index 000000000000..df237ee54803
--- /dev/null
+++ b/include/linux/mfd/da9055/reg.h
@@ -0,0 +1,699 @@
1/*
2 * DA9055 declarations for DA9055 PMICs.
3 *
4 * Copyright(c) 2012 Dialog Semiconductor Ltd.
5 *
6 * Author: David Dajun Chen <dchen@diasemi.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 */
23
24#ifndef __DA9055_REG_H
25#define __DA9055_REG_H
26
27/*
28 * PMIC registers
29 */
30 /* PAGE0 */
31#define DA9055_REG_PAGE_CON 0x00
32
33/* System Control and Event Registers */
34#define DA9055_REG_STATUS_A 0x01
35#define DA9055_REG_STATUS_B 0x02
36#define DA9055_REG_FAULT_LOG 0x03
37#define DA9055_REG_EVENT_A 0x04
38#define DA9055_REG_EVENT_B 0x05
39#define DA9055_REG_EVENT_C 0x06
40#define DA9055_REG_IRQ_MASK_A 0x07
41#define DA9055_REG_IRQ_MASK_B 0x08
42#define DA9055_REG_IRQ_MASK_C 0x09
43#define DA9055_REG_CONTROL_A 0x0A
44#define DA9055_REG_CONTROL_B 0x0B
45#define DA9055_REG_CONTROL_C 0x0C
46#define DA9055_REG_CONTROL_D 0x0D
47#define DA9055_REG_CONTROL_E 0x0E
48#define DA9055_REG_PD_DIS 0x0F
49
50/* GPIO Control Registers */
51#define DA9055_REG_GPIO0_1 0x10
52#define DA9055_REG_GPIO2 0x11
53#define DA9055_REG_GPIO_MODE0_2 0x12
54
55/* Regulator Control Registers */
56#define DA9055_REG_BCORE_CONT 0x13
57#define DA9055_REG_BMEM_CONT 0x14
58#define DA9055_REG_LDO1_CONT 0x15
59#define DA9055_REG_LDO2_CONT 0x16
60#define DA9055_REG_LDO3_CONT 0x17
61#define DA9055_REG_LDO4_CONT 0x18
62#define DA9055_REG_LDO5_CONT 0x19
63#define DA9055_REG_LDO6_CONT 0x1A
64
65/* GP-ADC Control Registers */
66#define DA9055_REG_ADC_MAN 0x1B
67#define DA9055_REG_ADC_CONT 0x1C
68#define DA9055_REG_VSYS_MON 0x1D
69#define DA9055_REG_ADC_RES_L 0x1E
70#define DA9055_REG_ADC_RES_H 0x1F
71#define DA9055_REG_VSYS_RES 0x20
72#define DA9055_REG_ADCIN1_RES 0x21
73#define DA9055_REG_ADCIN2_RES 0x22
74#define DA9055_REG_ADCIN3_RES 0x23
75
76/* Sequencer Control Registers */
77#define DA9055_REG_EN_32K 0x35
78
79/* Regulator Setting Registers */
80#define DA9055_REG_BUCK_LIM 0x37
81#define DA9055_REG_BCORE_MODE 0x38
82#define DA9055_REG_VBCORE_A 0x39
83#define DA9055_REG_VBMEM_A 0x3A
84#define DA9055_REG_VLDO1_A 0x3B
85#define DA9055_REG_VLDO2_A 0x3C
86#define DA9055_REG_VLDO3_A 0x3D
87#define DA9055_REG_VLDO4_A 0x3E
88#define DA9055_REG_VLDO5_A 0x3F
89#define DA9055_REG_VLDO6_A 0x40
90#define DA9055_REG_VBCORE_B 0x41
91#define DA9055_REG_VBMEM_B 0x42
92#define DA9055_REG_VLDO1_B 0x43
93#define DA9055_REG_VLDO2_B 0x44
94#define DA9055_REG_VLDO3_B 0x45
95#define DA9055_REG_VLDO4_B 0x46
96#define DA9055_REG_VLDO5_B 0x47
97#define DA9055_REG_VLDO6_B 0x48
98
99/* GP-ADC Threshold Registers */
100#define DA9055_REG_AUTO1_HIGH 0x49
101#define DA9055_REG_AUTO1_LOW 0x4A
102#define DA9055_REG_AUTO2_HIGH 0x4B
103#define DA9055_REG_AUTO2_LOW 0x4C
104#define DA9055_REG_AUTO3_HIGH 0x4D
105#define DA9055_REG_AUTO3_LOW 0x4E
106
107/* OTP */
108#define DA9055_REG_OPT_COUNT 0x50
109#define DA9055_REG_OPT_ADDR 0x51
110#define DA9055_REG_OPT_DATA 0x52
111
112/* RTC Calendar and Alarm Registers */
113#define DA9055_REG_COUNT_S 0x53
114#define DA9055_REG_COUNT_MI 0x54
115#define DA9055_REG_COUNT_H 0x55
116#define DA9055_REG_COUNT_D 0x56
117#define DA9055_REG_COUNT_MO 0x57
118#define DA9055_REG_COUNT_Y 0x58
119#define DA9055_REG_ALARM_MI 0x59
120#define DA9055_REG_ALARM_H 0x5A
121#define DA9055_REG_ALARM_D 0x5B
122#define DA9055_REG_ALARM_MO 0x5C
123#define DA9055_REG_ALARM_Y 0x5D
124#define DA9055_REG_SECOND_A 0x5E
125#define DA9055_REG_SECOND_B 0x5F
126#define DA9055_REG_SECOND_C 0x60
127#define DA9055_REG_SECOND_D 0x61
128
129/* Customer Trim and Configuration */
130#define DA9055_REG_T_OFFSET 0x63
131#define DA9055_REG_INTERFACE 0x64
132#define DA9055_REG_CONFIG_A 0x65
133#define DA9055_REG_CONFIG_B 0x66
134#define DA9055_REG_CONFIG_C 0x67
135#define DA9055_REG_CONFIG_D 0x68
136#define DA9055_REG_CONFIG_E 0x69
137#define DA9055_REG_TRIM_CLDR 0x6F
138
139/* General Purpose Registers */
140#define DA9055_REG_GP_ID_0 0x70
141#define DA9055_REG_GP_ID_1 0x71
142#define DA9055_REG_GP_ID_2 0x72
143#define DA9055_REG_GP_ID_3 0x73
144#define DA9055_REG_GP_ID_4 0x74
145#define DA9055_REG_GP_ID_5 0x75
146#define DA9055_REG_GP_ID_6 0x76
147#define DA9055_REG_GP_ID_7 0x77
148#define DA9055_REG_GP_ID_8 0x78
149#define DA9055_REG_GP_ID_9 0x79
150#define DA9055_REG_GP_ID_10 0x7A
151#define DA9055_REG_GP_ID_11 0x7B
152#define DA9055_REG_GP_ID_12 0x7C
153#define DA9055_REG_GP_ID_13 0x7D
154#define DA9055_REG_GP_ID_14 0x7E
155#define DA9055_REG_GP_ID_15 0x7F
156#define DA9055_REG_GP_ID_16 0x80
157#define DA9055_REG_GP_ID_17 0x81
158#define DA9055_REG_GP_ID_18 0x82
159#define DA9055_REG_GP_ID_19 0x83
160
161#define DA9055_MAX_REGISTER_CNT DA9055_REG_GP_ID_19
162
163/*
164 * PMIC registers bits
165 */
166
167/* DA9055_REG_PAGE_CON (addr=0x00) */
168#define DA9055_PAGE_WRITE_MODE (0<<6)
169#define DA9055_REPEAT_WRITE_MODE (1<<6)
170
171/* DA9055_REG_STATUS_A (addr=0x01) */
172#define DA9055_NOKEY_STS 0x01
173#define DA9055_WAKE_STS 0x02
174#define DA9055_DVC_BUSY_STS 0x04
175#define DA9055_COMP1V2_STS 0x08
176#define DA9055_NJIG_STS 0x10
177#define DA9055_LDO5_LIM_STS 0x20
178#define DA9055_LDO6_LIM_STS 0x40
179
180/* DA9055_REG_STATUS_B (addr=0x02) */
181#define DA9055_GPI0_STS 0x01
182#define DA9055_GPI1_STS 0x02
183#define DA9055_GPI2_STS 0x04
184
185/* DA9055_REG_FAULT_LOG (addr=0x03) */
186#define DA9055_TWD_ERROR_FLG 0x01
187#define DA9055_POR_FLG 0x02
188#define DA9055_VDD_FAULT_FLG 0x04
189#define DA9055_VDD_START_FLG 0x08
190#define DA9055_TEMP_CRIT_FLG 0x10
191#define DA9055_KEY_RESET_FLG 0x20
192#define DA9055_WAIT_SHUT_FLG 0x80
193
194/* DA9055_REG_EVENT_A (addr=0x04) */
195#define DA9055_NOKEY_EINT 0x01
196#define DA9055_ALARM_EINT 0x02
197#define DA9055_TICK_EINT 0x04
198#define DA9055_ADC_RDY_EINT 0x08
199#define DA9055_SEQ_RDY_EINT 0x10
200#define DA9055_EVENTS_B_EINT 0x20
201#define DA9055_EVENTS_C_EINT 0x40
202
203/* DA9055_REG_EVENT_B (addr=0x05) */
204#define DA9055_E_WAKE_EINT 0x01
205#define DA9055_E_TEMP_EINT 0x02
206#define DA9055_E_COMP1V2_EINT 0x04
207#define DA9055_E_LDO_LIM_EINT 0x08
208#define DA9055_E_NJIG_EINT 0x20
209#define DA9055_E_VDD_MON_EINT 0x40
210#define DA9055_E_VDD_WARN_EINT 0x80
211
212/* DA9055_REG_EVENT_C (addr=0x06) */
213#define DA9055_E_GPI0_EINT 0x01
214#define DA9055_E_GPI1_EINT 0x02
215#define DA9055_E_GPI2_EINT 0x04
216
217/* DA9055_REG_IRQ_MASK_A (addr=0x07) */
218#define DA9055_M_NONKEY_EINT 0x01
219#define DA9055_M_ALARM_EINT 0x02
220#define DA9055_M_TICK_EINT 0x04
221#define DA9055_M_ADC_RDY_EINT 0x08
222#define DA9055_M_SEQ_RDY_EINT 0x10
223
224/* DA9055_REG_IRQ_MASK_B (addr=0x08) */
225#define DA9055_M_WAKE_EINT 0x01
226#define DA9055_M_TEMP_EINT 0x02
227#define DA9055_M_COMP_1V2_EINT 0x04
228#define DA9055_M_LDO_LIM_EINT 0x08
229#define DA9055_M_NJIG_EINT 0x20
230#define DA9055_M_VDD_MON_EINT 0x40
231#define DA9055_M_VDD_WARN_EINT 0x80
232
233/* DA9055_REG_IRQ_MASK_C (addr=0x09) */
234#define DA9055_M_GPI0_EINT 0x01
235#define DA9055_M_GPI1_EINT 0x02
236#define DA9055_M_GPI2_EINT 0x04
237
238/* DA9055_REG_CONTROL_A (addr=0xA) */
239#define DA9055_DEBOUNCING_SHIFT 0x00
240#define DA9055_DEBOUNCING_MASK 0x07
241#define DA9055_NRES_MODE_SHIFT 0x03
242#define DA9055_NRES_MODE_MASK 0x08
243#define DA9055_SLEW_RATE_SHIFT 0x04
244#define DA9055_SLEW_RATE_MASK 0x30
245#define DA9055_NOKEY_LOCK_SHIFT 0x06
246#define DA9055_NOKEY_LOCK_MASK 0x40
247
248/* DA9055_REG_CONTROL_B (addr=0xB) */
249#define DA9055_RTC_MODE_PD 0x01
250#define DA9055_RTC_MODE_SD_SHIFT 0x01
251#define DA9055_RTC_MODE_SD 0x02
252#define DA9055_RTC_EN 0x04
253#define DA9055_ECO_MODE_SHIFT 0x03
254#define DA9055_ECO_MODE_MASK 0x08
255#define DA9055_TWDSCALE_SHIFT 4
256#define DA9055_TWDSCALE_MASK 0x70
257#define DA9055_V_LOCK_SHIFT 0x07
258#define DA9055_V_LOCK_MASK 0x80
259
260/* DA9055_REG_CONTROL_C (addr=0xC) */
261#define DA9055_SYSTEM_EN_SHIFT 0x00
262#define DA9055_SYSTEM_EN_MASK 0x01
263#define DA9055_POWERN_EN_SHIFT 0x01
264#define DA9055_POWERN_EN_MASK 0x02
265#define DA9055_POWER1_EN_SHIFT 0x02
266#define DA9055_POWER1_EN_MASK 0x04
267
268/* DA9055_REG_CONTROL_D (addr=0xD) */
269#define DA9055_STANDBY_SHIFT 0x02
270#define DA9055_STANDBY_MASK 0x08
271#define DA9055_AUTO_BOOT_SHIFT 0x03
272#define DA9055_AUTO_BOOT_MASK 0x04
273
274/* DA9055_REG_CONTROL_E (addr=0xE) */
275#define DA9055_WATCHDOG_SHIFT 0x00
276#define DA9055_WATCHDOG_MASK 0x01
277#define DA9055_SHUTDOWN_SHIFT 0x01
278#define DA9055_SHUTDOWN_MASK 0x02
279#define DA9055_WAKE_UP_SHIFT 0x02
280#define DA9055_WAKE_UP_MASK 0x04
281
282/* DA9055_REG_GPIO (addr=0x10/0x11) */
283#define DA9055_GPIO0_PIN_SHIFT 0x00
284#define DA9055_GPIO0_PIN_MASK 0x03
285#define DA9055_GPIO0_TYPE_SHIFT 0x02
286#define DA9055_GPIO0_TYPE_MASK 0x04
287#define DA9055_GPIO0_WEN_SHIFT 0x03
288#define DA9055_GPIO0_WEN_MASK 0x08
289#define DA9055_GPIO1_PIN_SHIFT 0x04
290#define DA9055_GPIO1_PIN_MASK 0x30
291#define DA9055_GPIO1_TYPE_SHIFT 0x06
292#define DA9055_GPIO1_TYPE_MASK 0x40
293#define DA9055_GPIO1_WEN_SHIFT 0x07
294#define DA9055_GPIO1_WEN_MASK 0x80
295#define DA9055_GPIO2_PIN_SHIFT 0x00
296#define DA9055_GPIO2_PIN_MASK 0x30
297#define DA9055_GPIO2_TYPE_SHIFT 0x02
298#define DA9055_GPIO2_TYPE_MASK 0x04
299#define DA9055_GPIO2_WEN_SHIFT 0x03
300#define DA9055_GPIO2_WEN_MASK 0x08
301
302/* DA9055_REG_GPIO_MODE (addr=0x12) */
303#define DA9055_GPIO0_MODE_SHIFT 0x00
304#define DA9055_GPIO0_MODE_MASK 0x01
305#define DA9055_GPIO1_MODE_SHIFT 0x01
306#define DA9055_GPIO1_MODE_MASK 0x02
307#define DA9055_GPIO2_MODE_SHIFT 0x02
308#define DA9055_GPIO2_MODE_MASK 0x04
309
310/* DA9055_REG_BCORE_CONT (addr=0x13) */
311#define DA9055_BCORE_EN_SHIFT 0x00
312#define DA9055_BCORE_EN_MASK 0x01
313#define DA9055_BCORE_GPI_SHIFT 0x01
314#define DA9055_BCORE_GPI_MASK 0x02
315#define DA9055_BCORE_PD_DIS_SHIFT 0x03
316#define DA9055_BCORE_PD_DIS_MASK 0x04
317#define DA9055_VBCORE_SEL_SHIFT 0x04
318#define DA9055_SEL_REG_A 0x0
319#define DA9055_SEL_REG_B 0x10
320#define DA9055_VBCORE_SEL_MASK 0x10
321#define DA9055_V_GPI_MASK 0x60
322#define DA9055_V_GPI_SHIFT 0x05
323#define DA9055_E_GPI_MASK 0x06
324#define DA9055_E_GPI_SHIFT 0x01
325#define DA9055_VBCORE_GPI_SHIFT 0x05
326#define DA9055_VBCORE_GPI_MASK 0x60
327#define DA9055_BCORE_CONF_SHIFT 0x07
328#define DA9055_BCORE_CONF_MASK 0x80
329
330/* DA9055_REG_BMEM_CONT (addr=0x14) */
331#define DA9055_BMEM_EN_SHIFT 0x00
332#define DA9055_BMEM_EN_MASK 0x01
333#define DA9055_BMEM_GPI_SHIFT 0x01
334#define DA9055_BMEM_GPI_MASK 0x06
335#define DA9055_BMEM_PD_DIS_SHIFT 0x03
336#define DA9055_BMEM_PD_DIS_MASK 0x08
337#define DA9055_VBMEM_SEL_SHIT 0x04
338#define DA9055_VBMEM_SEL_VBMEM_A (0<<4)
339#define DA9055_VBMEM_SEL_VBMEM_B (1<<4)
340#define DA9055_VBMEM_SEL_MASK 0x10
341#define DA9055_VBMEM_GPI_SHIFT 0x05
342#define DA9055_VBMEM_GPI_MASK 0x60
343#define DA9055_BMEM_CONF_SHIFT 0x07
344#define DA9055_BMEM_CONF_MASK 0x80
345
346/* DA9055_REG_LDO_CONT (addr=0x15-0x1A) */
347#define DA9055_LDO_EN_SHIFT 0x00
348#define DA9055_LDO_EN_MASK 0x01
349#define DA9055_LDO_GPI_SHIFT 0x01
350#define DA9055_LDO_GPI_MASK 0x06
351#define DA9055_LDO_PD_DIS_SHIFT 0x03
352#define DA9055_LDO_PD_DIS_MASK 0x08
353#define DA9055_VLDO_SEL_SHIFT 0x04
354#define DA9055_VLDO_SEL_MASK 0x10
355#define DA9055_VLDO_SEL_VLDO_A 0x00
356#define DA9055_VLDO_SEL_VLDO_B 0x01
357#define DA9055_VLDO_GPI_SHIFT 0x05
358#define DA9055_VLDO_GPI_MASK 0x60
359#define DA9055_LDO_CONF_SHIFT 0x07
360#define DA9055_LDO_CONF_MASK 0x80
361#define DA9055_REGUALTOR_SET_A 0x00
362#define DA9055_REGUALTOR_SET_B 0x10
363
364/* DA9055_REG_ADC_MAN (addr=0x1B) */
365#define DA9055_ADC_MUX_SHIFT 0
366#define DA9055_ADC_MUX_MASK 0xF
367#define DA9055_ADC_MUX_VSYS 0x0
368#define DA9055_ADC_MUX_ADCIN1 0x01
369#define DA9055_ADC_MUX_ADCIN2 0x02
370#define DA9055_ADC_MUX_ADCIN3 0x03
371#define DA9055_ADC_MUX_T_SENSE 0x04
372#define DA9055_ADC_MAN_SHIFT 0x04
373#define DA9055_ADC_MAN_CONV 0x10
374#define DA9055_ADC_LSB_MASK 0X03
375#define DA9055_ADC_MODE_MASK 0x20
376#define DA9055_ADC_MODE_SHIFT 5
377#define DA9055_ADC_MODE_1MS (1<<5)
378#define DA9055_COMP1V2_EN_SHIFT 7
379
380/* DA9055_REG_ADC_CONT (addr=0x1C) */
381#define DA9055_ADC_AUTO_VSYS_EN_SHIFT 0
382#define DA9055_ADC_AUTO_AD1_EN_SHIFT 1
383#define DA9055_ADC_AUTO_AD2_EN_SHIFT 2
384#define DA9055_ADC_AUTO_AD3_EN_SHIFT 3
385#define DA9055_ADC_ISRC_EN_SHIFT 4
386#define DA9055_ADC_ADCIN1_DEB_SHIFT 5
387#define DA9055_ADC_ADCIN2_DEB_SHIFT 6
388#define DA9055_ADC_ADCIN3_DEB_SHIFT 7
389#define DA9055_AD1_ISRC_MASK 0x10
390#define DA9055_AD1_ISRC_SHIFT 4
391
392/* DA9055_REG_VSYS_MON (addr=0x1D) */
393#define DA9055_VSYS_VAL_SHIFT 0
394#define DA9055_VSYS_VAL_MASK 0xFF
395#define DA9055_VSYS_VAL_BASE 0x00
396#define DA9055_VSYS_VAL_MAX DA9055_VSYS_VAL_MASK
397#define DA9055_VSYS_VOLT_BASE 2500
398#define DA9055_VSYS_VOLT_INC 10
399#define DA9055_VSYS_STEPS 255
400#define DA9055_VSYS_VOLT_MIN 2500
401
402/* DA9044_REG_XXX_RES (addr=0x20-0x23) */
403#define DA9055_ADC_VAL_SHIFT 0
404#define DA9055_ADC_VAL_MASK 0xFF
405#define DA9055_ADC_VAL_BASE 0x00
406#define DA9055_ADC_VAL_MAX DA9055_ADC_VAL_MASK
407#define DA9055_ADC_VOLT_BASE 0
408#define DA9055_ADC_VSYS_VOLT_BASE 2500
409#define DA9055_ADC_VOLT_INC 10
410#define DA9055_ADC_VSYS_VOLT_INC 12
411#define DA9055_ADC_STEPS 255
412
413/* DA9055_REG_EN_32K (addr=0x35)*/
414#define DA9055_STARTUP_TIME_MASK 0x07
415#define DA9055_STARTUP_TIME_0S 0x0
416#define DA9055_STARTUP_TIME_0_52S 0x1
417#define DA9055_STARTUP_TIME_1S 0x2
418#define DA9055_CRYSTAL_EN 0x08
419#define DA9055_DELAY_MODE_EN 0x10
420#define DA9055_OUT_CLCK_GATED 0x20
421#define DA9055_RTC_CLOCK_GATED 0x40
422#define DA9055_EN_32KOUT_BUF 0x80
423
424/* DA9055_REG_RESET (addr=0x36) */
425/* Timer up to 31.744 ms */
426#define DA9055_RESET_TIMER_VAL_SHIFT 0
427#define DA9055_RESET_LOW_VAL_MASK 0x3F
428#define DA9055_RESET_LOW_VAL_BASE 0
429#define DA9055_RESET_LOW_VAL_MAX DA9055_RESET_LOW_VAL_MASK
430#define DA9055_RESET_US_LOW_BASE 1024 /* min val in units of us */
431#define DA9055_RESET_US_LOW_INC 1024 /* inc val in units of us */
432#define DA9055_RESET_US_LOW_STEP 30
433
434/* Timer up to 1048.576ms */
435#define DA9055_RESET_HIGH_VAL_MASK 0x3F
436#define DA9055_RESET_HIGH_VAL_BASE 0
437#define DA9055_RESET_HIGH_VAL_MAX DA9055_RESET_HIGH_VAL_MASK
438#define DA9055_RESET_US_HIGH_BASE 32768 /* min val in units of us */
439#define DA9055_RESET_US_HIGH_INC 32768 /* inv val in units of us */
440#define DA9055_RESET_US_HIGH_STEP 31
441
442/* DA9055_REG_BUCK_ILIM (addr=0x37)*/
443#define DA9055_BMEM_ILIM_SHIFT 0
444#define DA9055_ILIM_MASK 0x3
445#define DA9055_ILIM_500MA 0x0
446#define DA9055_ILIM_600MA 0x1
447#define DA9055_ILIM_700MA 0x2
448#define DA9055_ILIM_800MA 0x3
449#define DA9055_BCORE_ILIM_SHIFT 2
450
451/* DA9055_REG_BCORE_MODE (addr=0x38) */
452#define DA9055_BMEM_MODE_SHIFT 0
453#define DA9055_MODE_MASK 0x3
454#define DA9055_MODE_AB 0x0
455#define DA9055_MODE_SLEEP 0x1
456#define DA9055_MODE_SYNCHRO 0x2
457#define DA9055_MODE_AUTO 0x3
458#define DA9055_BCORE_MODE_SHIFT 2
459
460/* DA9055_REG_VBCORE_A/B (addr=0x39/0x41)*/
461#define DA9055_VBCORE_VAL_SHIFT 0
462#define DA9055_VBCORE_VAL_MASK 0x3F
463#define DA9055_VBCORE_VAL_BASE 0x09
464#define DA9055_VBCORE_VAL_MAX DA9055_VBCORE_VAL_MASK
465#define DA9055_VBCORE_VOLT_BASE 750
466#define DA9055_VBCORE_VOLT_INC 25
467#define DA9055_VBCORE_STEPS 53
468#define DA9055_VBCORE_VOLT_MIN DA9055_VBCORE_VOLT_BASE
469#define DA9055_BCORE_SL_SYNCHRO (0<<7)
470#define DA9055_BCORE_SL_SLEEP (1<<7)
471
472/* DA9055_REG_VBMEM_A/B (addr=0x3A/0x42)*/
473#define DA9055_VBMEM_VAL_SHIFT 0
474#define DA9055_VBMEM_VAL_MASK 0x3F
475#define DA9055_VBMEM_VAL_BASE 0x00
476#define DA9055_VBMEM_VAL_MAX DA9055_VBMEM_VAL_MASK
477#define DA9055_VBMEM_VOLT_BASE 925
478#define DA9055_VBMEM_VOLT_INC 25
479#define DA9055_VBMEM_STEPS 63
480#define DA9055_VBMEM_VOLT_MIN DA9055_VBMEM_VOLT_BASE
481#define DA9055_BCMEM_SL_SYNCHRO (0<<7)
482#define DA9055_BCMEM_SL_SLEEP (1<<7)
483
484
485/* DA9055_REG_VLDO (addr=0x3B-0x40/0x43-0x48)*/
486#define DA9055_VLDO_VAL_SHIFT 0
487#define DA9055_VLDO_VAL_MASK 0x3F
488#define DA9055_VLDO6_VAL_MASK 0x7F
489#define DA9055_VLDO_VAL_BASE 0x02
490#define DA9055_VLDO2_VAL_BASE 0x03
491#define DA9055_VLDO6_VAL_BASE 0x00
492#define DA9055_VLDO_VAL_MAX DA9055_VLDO_VAL_MASK
493#define DA9055_VLDO6_VAL_MAX DA9055_VLDO6_VAL_MASK
494#define DA9055_VLDO_VOLT_BASE 900
495#define DA9055_VLDO_VOLT_INC 50
496#define DA9055_VLDO6_VOLT_INC 20
497#define DA9055_VLDO_STEPS 48
498#define DA9055_VLDO5_STEPS 37
499#define DA9055_VLDO6_STEPS 120
500#define DA9055_VLDO_VOLT_MIN DA9055_VLDO_VOLT_BASE
501#define DA9055_LDO_MODE_SHIFT 7
502#define DA9055_LDO_SL_NORMAL 0
503#define DA9055_LDO_SL_SLEEP 1
504
505/* DA9055_REG_OTP_CONT (addr=0x50) */
506#define DA9055_OTP_TIM_NORMAL (0<<0)
507#define DA9055_OTP_TIM_MARGINAL (1<<0)
508#define DA9055_OTP_GP_RD_SHIFT 1
509#define DA9055_OTP_APPS_RD_SHIFT 2
510#define DA9055_PC_DONE_SHIFT 3
511#define DA9055_OTP_GP_LOCK_SHIFT 4
512#define DA9055_OTP_APPS_LOCK_SHIFT 5
513#define DA9055_OTP_CONF_LOCK_SHIFT 6
514#define DA9055_OTP_WRITE_DIS_SHIFT 7
515
516/* DA9055_REG_COUNT_S (addr=0x53) */
517#define DA9055_RTC_SEC 0x3F
518#define DA9055_RTC_MONITOR_EN 0x40
519#define DA9055_RTC_READ 0x80
520
521/* DA9055_REG_COUNT_MI (addr=0x54) */
522#define DA9055_RTC_MIN 0x3F
523
524/* DA9055_REG_COUNT_H (addr=0x55) */
525#define DA9055_RTC_HOUR 0x1F
526
527/* DA9055_REG_COUNT_D (addr=0x56) */
528#define DA9055_RTC_DAY 0x1F
529
530/* DA9055_REG_COUNT_MO (addr=0x57) */
531#define DA9055_RTC_MONTH 0x0F
532
533/* DA9055_REG_COUNT_Y (addr=0x58) */
534#define DA9055_RTC_YEAR 0x3F
535#define DA9055_RTC_YEAR_BASE 2000
536
537/* DA9055_REG_ALARM_MI (addr=0x59) */
538#define DA9055_RTC_ALM_MIN 0x3F
539#define DA9055_ALARM_STATUS_SHIFT 6
540#define DA9055_ALARM_STATUS_MASK 0x3
541#define DA9055_ALARM_STATUS_NO_ALARM 0x0
542#define DA9055_ALARM_STATUS_TICK 0x1
543#define DA9055_ALARM_STATUS_TIMER_ALARM 0x2
544#define DA9055_ALARM_STATUS_BOTH 0x3
545
546/* DA9055_REG_ALARM_H (addr=0x5A) */
547#define DA9055_RTC_ALM_HOUR 0x1F
548
549/* DA9055_REG_ALARM_D (addr=0x5B) */
550#define DA9055_RTC_ALM_DAY 0x1F
551
552/* DA9055_REG_ALARM_MO (addr=0x5C) */
553#define DA9055_RTC_ALM_MONTH 0x0F
554#define DA9055_RTC_TICK_WAKE_MASK 0x20
555#define DA9055_RTC_TICK_WAKE_SHIFT 5
556#define DA9055_RTC_TICK_TYPE 0x10
557#define DA9055_RTC_TICK_TYPE_SHIFT 0x4
558#define DA9055_RTC_TICK_SEC 0x0
559#define DA9055_RTC_TICK_MIN 0x1
560#define DA9055_ALARAM_TICK_WAKE 0x20
561
562/* DA9055_REG_ALARM_Y (addr=0x5D) */
563#define DA9055_RTC_TICK_EN 0x80
564#define DA9055_RTC_ALM_EN 0x40
565#define DA9055_RTC_TICK_ALM_MASK 0xC0
566#define DA9055_RTC_ALM_YEAR 0x3F
567
568/* DA9055_REG_TRIM_CLDR (addr=0x62) */
569#define DA9055_TRIM_32K_SHIFT 0
570#define DA9055_TRIM_32K_MASK 0x7F
571#define DA9055_TRIM_DECREMENT (1<<7)
572#define DA9055_TRIM_INCREMENT (0<<7)
573#define DA9055_TRIM_VAL_BASE 0x0
574#define DA9055_TRIM_PPM_BASE 0x0 /* min val in units of 0.1PPM */
575#define DA9055_TRIM_PPM_INC 19 /* min inc in units of 0.1PPM */
576#define DA9055_TRIM_STEPS 127
577
578/* DA9055_REG_CONFIG_A (addr=0x65) */
579#define DA9055_PM_I_V_VDDCORE (0<<0)
580#define DA9055_PM_I_V_VDD_IO (1<<0)
581#define DA9055_VDD_FAULT_TYPE_ACT_LOW (0<<1)
582#define DA9055_VDD_FAULT_TYPE_ACT_HIGH (1<<1)
583#define DA9055_PM_O_TYPE_PUSH_PULL (0<<2)
584#define DA9055_PM_O_TYPE_OPEN_DRAIN (1<<2)
585#define DA9055_IRQ_TYPE_ACT_LOW (0<<3)
586#define DA9055_IRQ_TYPE_ACT_HIGH (1<<3)
587#define DA9055_NIRQ_MODE_IMM (0<<4)
588#define DA9055_NIRQ_MODE_ACTIVE (1<<4)
589#define DA9055_GPI_V_VDDCORE (0<<5)
590#define DA9055_GPI_V_VDD_IO (1<<5)
591#define DA9055_PM_IF_V_VDDCORE (0<<6)
592#define DA9055_PM_IF_V_VDD_IO (1<<6)
593
594/* DA9055_REG_CONFIG_B (addr=0x66) */
595#define DA9055_VDD_FAULT_VAL_SHIFT 0
596#define DA9055_VDD_FAULT_VAL_MASK 0xF
597#define DA9055_VDD_FAULT_VAL_BASE 0x0
598#define DA9055_VDD_FAULT_VAL_MAX DA9055_VDD_FAULT_VAL_MASK
599#define DA9055_VDD_FAULT_VOLT_BASE 2500
600#define DA9055_VDD_FAULT_VOLT_INC 50
601#define DA9055_VDD_FAULT_STEPS 15
602
603#define DA9055_VDD_HYST_VAL_SHIFT 4
604#define DA9055_VDD_HYST_VAL_MASK 0x7
605#define DA9055_VDD_HYST_VAL_BASE 0x0
606#define DA9055_VDD_HYST_VAL_MAX DA9055_VDD_HYST_VAL_MASK
607#define DA9055_VDD_HYST_VOLT_BASE 100
608#define DA9055_VDD_HYST_VOLT_INC 50
609#define DA9055_VDD_HYST_STEPS 7
610#define DA9055_VDD_HYST_VOLT_MIN DA9055_VDD_HYST_VOLT_BASE
611
612#define DA9055_VDD_FAULT_EN_SHIFT 7
613
614/* DA9055_REG_CONFIG_C (addr=0x67) */
615#define DA9055_BCORE_CLK_INV_SHIFT 0
616#define DA9055_BMEM_CLK_INV_SHIFT 1
617#define DA9055_NFAULT_CONF_SHIFT 2
618#define DA9055_LDO_SD_SHIFT 4
619#define DA9055_LDO5_BYP_SHIFT 6
620#define DA9055_LDO6_BYP_SHIFT 7
621
622/* DA9055_REG_CONFIG_D (addr=0x68) */
623#define DA9055_NONKEY_PIN_SHIFT 0
624#define DA9055_NONKEY_PIN_MASK 0x3
625#define DA9055_NONKEY_PIN_PORT_MODE 0x0
626#define DA9055_NONKEY_PIN_KEY_MODE 0x1
627#define DA9055_NONKEY_PIN_MULTI_FUNC 0x2
628#define DA9055_NONKEY_PIN_DEDICT 0x3
629#define DA9055_NONKEY_SD_SHIFT 2
630#define DA9055_KEY_DELAY_SHIFT 3
631#define DA9055_KEY_DELAY_MASK 0x3
632#define DA9055_KEY_DELAY_4S 0x0
633#define DA9055_KEY_DELAY_6S 0x1
634#define DA9055_KEY_DELAY_8S 0x2
635#define DA9055_KEY_DELAY_10S 0x3
636
637/* DA9055_REG_CONFIG_E (addr=0x69) */
638#define DA9055_GPIO_PUPD_PULL_UP 0x0
639#define DA9055_GPIO_PUPD_OPEN_DRAIN 0x1
640#define DA9055_GPIO0_PUPD_SHIFT 0
641#define DA9055_GPIO1_PUPD_SHIFT 1
642#define DA9055_GPIO2_PUPD_SHIFT 2
643#define DA9055_UVOV_DELAY_SHIFT 4
644#define DA9055_UVOV_DELAY_MASK 0x3
645#define DA9055_RESET_DURATION_SHIFT 6
646#define DA9055_RESET_DURATION_MASK 0x3
647#define DA9055_RESET_DURATION_0MS 0x0
648#define DA9055_RESET_DURATION_100MS 0x1
649#define DA9055_RESET_DURATION_500MS 0x2
650#define DA9055_RESET_DURATION_1000MS 0x3
651
652/* DA9055_REG_MON_REG_1 (addr=0x6A) */
653#define DA9055_MON_THRES_SHIFT 0
654#define DA9055_MON_THRES_MASK 0x3
655#define DA9055_MON_RES_SHIFT 2
656#define DA9055_MON_DEB_SHIFT 3
657#define DA9055_MON_MODE_SHIFT 4
658#define DA9055_MON_MODE_MASK 0x3
659#define DA9055_START_MAX_SHIFT 6
660#define DA9055_START_MAX_MASK 0x3
661
662/* DA9055_REG_MON_REG_2 (addr=0x6B) */
663#define DA9055_LDO1_MON_EN_SHIFT 0
664#define DA9055_LDO2_MON_EN_SHIFT 1
665#define DA9055_LDO3_MON_EN_SHIFT 2
666#define DA9055_LDO4_MON_EN_SHIFT 3
667#define DA9055_LDO5_MON_EN_SHIFT 4
668#define DA9055_LDO6_MON_EN_SHIFT 5
669#define DA9055_BCORE_MON_EN_SHIFT 6
670#define DA9055_BMEM_MON_EN_SHIFT 7
671
672/* DA9055_REG_CONFIG_F (addr=0x6C) */
673#define DA9055_LDO1_DEF_SHIFT 0
674#define DA9055_LDO2_DEF_SHIFT 1
675#define DA9055_LDO3_DEF_SHIFT 2
676#define DA9055_LDO4_DEF_SHIFT 3
677#define DA9055_LDO5_DEF_SHIFT 4
678#define DA9055_LDO6_DEF_SHIFT 5
679#define DA9055_BCORE_DEF_SHIFT 6
680#define DA9055_BMEM_DEF_SHIFT 7
681
682/* DA9055_REG_MON_REG_4 (addr=0x6D) */
683#define DA9055_MON_A8_IDX_SHIFT 0
684#define DA9055_MON_A89_IDX_MASK 0x3
685#define DA9055_MON_A89_IDX_NONE 0x0
686#define DA9055_MON_A89_IDX_BUCKCORE 0x1
687#define DA9055_MON_A89_IDX_LDO3 0x2
688#define DA9055_MON_A9_IDX_SHIFT 5
689
690/* DA9055_REG_MON_REG_5 (addr=0x6E) */
691#define DA9055_MON_A10_IDX_SHIFT 0
692#define DA9055_MON_A10_IDX_MASK 0x3
693#define DA9055_MON_A10_IDX_NONE 0x0
694#define DA9055_MON_A10_IDX_LDO1 0x1
695#define DA9055_MON_A10_IDX_LDO2 0x2
696#define DA9055_MON_A10_IDX_LDO5 0x3
697#define DA9055_MON_A10_IDX_LDO6 0x4
698
699#endif /* __DA9055_REG_H */
diff --git a/include/linux/mfd/lp8788-isink.h b/include/linux/mfd/lp8788-isink.h
new file mode 100644
index 000000000000..f38262d21ff1
--- /dev/null
+++ b/include/linux/mfd/lp8788-isink.h
@@ -0,0 +1,52 @@
1/*
2 * TI LP8788 MFD - common definitions for current sinks
3 *
4 * Copyright 2012 Texas Instruments
5 *
6 * Author: Milo(Woogyom) Kim <milo.kim@ti.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13
14#ifndef __ISINK_LP8788_H__
15#define __ISINK_LP8788_H__
16
17/* register address */
18#define LP8788_ISINK_CTRL 0x99
19#define LP8788_ISINK12_IOUT 0x9A
20#define LP8788_ISINK3_IOUT 0x9B
21#define LP8788_ISINK1_PWM 0x9C
22#define LP8788_ISINK2_PWM 0x9D
23#define LP8788_ISINK3_PWM 0x9E
24
25/* mask bits */
26#define LP8788_ISINK1_IOUT_M 0x0F /* Addr 9Ah */
27#define LP8788_ISINK2_IOUT_M 0xF0
28#define LP8788_ISINK3_IOUT_M 0x0F /* Addr 9Bh */
29
30/* 6 bits used for PWM code : Addr 9C ~ 9Eh */
31#define LP8788_ISINK_MAX_PWM 63
32#define LP8788_ISINK_SCALE_OFFSET 3
33
34static const u8 lp8788_iout_addr[] = {
35 LP8788_ISINK12_IOUT,
36 LP8788_ISINK12_IOUT,
37 LP8788_ISINK3_IOUT,
38};
39
40static const u8 lp8788_iout_mask[] = {
41 LP8788_ISINK1_IOUT_M,
42 LP8788_ISINK2_IOUT_M,
43 LP8788_ISINK3_IOUT_M,
44};
45
46static const u8 lp8788_pwm_addr[] = {
47 LP8788_ISINK1_PWM,
48 LP8788_ISINK2_PWM,
49 LP8788_ISINK3_PWM,
50};
51
52#endif
diff --git a/include/linux/mfd/lp8788.h b/include/linux/mfd/lp8788.h
new file mode 100644
index 000000000000..cec364bdccfa
--- /dev/null
+++ b/include/linux/mfd/lp8788.h
@@ -0,0 +1,364 @@
1/*
2 * TI LP8788 MFD Device
3 *
4 * Copyright 2012 Texas Instruments
5 *
6 * Author: Milo(Woogyom) Kim <milo.kim@ti.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13
14#ifndef __MFD_LP8788_H__
15#define __MFD_LP8788_H__
16
17#include <linux/gpio.h>
18#include <linux/irqdomain.h>
19#include <linux/regmap.h>
20
21#define LP8788_DEV_BUCK "lp8788-buck"
22#define LP8788_DEV_DLDO "lp8788-dldo"
23#define LP8788_DEV_ALDO "lp8788-aldo"
24#define LP8788_DEV_CHARGER "lp8788-charger"
25#define LP8788_DEV_RTC "lp8788-rtc"
26#define LP8788_DEV_BACKLIGHT "lp8788-backlight"
27#define LP8788_DEV_VIBRATOR "lp8788-vibrator"
28#define LP8788_DEV_KEYLED "lp8788-keyled"
29#define LP8788_DEV_ADC "lp8788-adc"
30
31#define LP8788_NUM_BUCKS 4
32#define LP8788_NUM_DLDOS 12
33#define LP8788_NUM_ALDOS 10
34#define LP8788_NUM_BUCK2_DVS 2
35
36#define LP8788_CHG_IRQ "CHG_IRQ"
37#define LP8788_PRSW_IRQ "PRSW_IRQ"
38#define LP8788_BATT_IRQ "BATT_IRQ"
39#define LP8788_ALM_IRQ "ALARM_IRQ"
40
41enum lp8788_int_id {
42 /* interrup register 1 : Addr 00h */
43 LP8788_INT_TSDL,
44 LP8788_INT_TSDH,
45 LP8788_INT_UVLO,
46 LP8788_INT_FLAGMON,
47 LP8788_INT_PWRON_TIME,
48 LP8788_INT_PWRON,
49 LP8788_INT_COMP1,
50 LP8788_INT_COMP2,
51
52 /* interrupt register 2 : Addr 01h */
53 LP8788_INT_CHG_INPUT_STATE,
54 LP8788_INT_CHG_STATE,
55 LP8788_INT_EOC,
56 LP8788_INT_CHG_RESTART,
57 LP8788_INT_RESTART_TIMEOUT,
58 LP8788_INT_FULLCHG_TIMEOUT,
59 LP8788_INT_PRECHG_TIMEOUT,
60
61 /* interrupt register 3 : Addr 02h */
62 LP8788_INT_RTC_ALARM1 = 17,
63 LP8788_INT_RTC_ALARM2,
64 LP8788_INT_ENTER_SYS_SUPPORT,
65 LP8788_INT_EXIT_SYS_SUPPORT,
66 LP8788_INT_BATT_LOW,
67 LP8788_INT_NO_BATT,
68
69 LP8788_INT_MAX = 24,
70};
71
72enum lp8788_dvs_sel {
73 DVS_SEL_V0,
74 DVS_SEL_V1,
75 DVS_SEL_V2,
76 DVS_SEL_V3,
77};
78
79enum lp8788_ext_ldo_en_id {
80 EN_ALDO1,
81 EN_ALDO234,
82 EN_ALDO5,
83 EN_ALDO7,
84 EN_DLDO7,
85 EN_DLDO911,
86 EN_LDOS_MAX,
87};
88
89enum lp8788_charger_event {
90 NO_CHARGER,
91 CHARGER_DETECTED,
92};
93
94enum lp8788_bl_ctrl_mode {
95 LP8788_BL_REGISTER_ONLY,
96 LP8788_BL_COMB_PWM_BASED, /* PWM + I2C, changed by PWM input */
97 LP8788_BL_COMB_REGISTER_BASED, /* PWM + I2C, changed by I2C */
98};
99
100enum lp8788_bl_dim_mode {
101 LP8788_DIM_EXPONENTIAL,
102 LP8788_DIM_LINEAR,
103};
104
105enum lp8788_bl_full_scale_current {
106 LP8788_FULLSCALE_5000uA,
107 LP8788_FULLSCALE_8500uA,
108 LP8788_FULLSCALE_1200uA,
109 LP8788_FULLSCALE_1550uA,
110 LP8788_FULLSCALE_1900uA,
111 LP8788_FULLSCALE_2250uA,
112 LP8788_FULLSCALE_2600uA,
113 LP8788_FULLSCALE_2950uA,
114};
115
116enum lp8788_bl_ramp_step {
117 LP8788_RAMP_8us,
118 LP8788_RAMP_1024us,
119 LP8788_RAMP_2048us,
120 LP8788_RAMP_4096us,
121 LP8788_RAMP_8192us,
122 LP8788_RAMP_16384us,
123 LP8788_RAMP_32768us,
124 LP8788_RAMP_65538us,
125};
126
127enum lp8788_bl_pwm_polarity {
128 LP8788_PWM_ACTIVE_HIGH,
129 LP8788_PWM_ACTIVE_LOW,
130};
131
132enum lp8788_isink_scale {
133 LP8788_ISINK_SCALE_100mA,
134 LP8788_ISINK_SCALE_120mA,
135};
136
137enum lp8788_isink_number {
138 LP8788_ISINK_1,
139 LP8788_ISINK_2,
140 LP8788_ISINK_3,
141};
142
143enum lp8788_alarm_sel {
144 LP8788_ALARM_1,
145 LP8788_ALARM_2,
146 LP8788_ALARM_MAX,
147};
148
149enum lp8788_adc_id {
150 LPADC_VBATT_5P5,
151 LPADC_VIN_CHG,
152 LPADC_IBATT,
153 LPADC_IC_TEMP,
154 LPADC_VBATT_6P0,
155 LPADC_VBATT_5P0,
156 LPADC_ADC1,
157 LPADC_ADC2,
158 LPADC_VDD,
159 LPADC_VCOIN,
160 LPADC_VDD_LDO,
161 LPADC_ADC3,
162 LPADC_ADC4,
163 LPADC_MAX,
164};
165
166struct lp8788;
167
168/*
169 * lp8788_buck1_dvs
170 * @gpio : gpio pin number for dvs control
171 * @vsel : dvs selector for buck v1 register
172 */
173struct lp8788_buck1_dvs {
174 int gpio;
175 enum lp8788_dvs_sel vsel;
176};
177
178/*
179 * lp8788_buck2_dvs
180 * @gpio : two gpio pin numbers are used for dvs
181 * @vsel : dvs selector for buck v2 register
182 */
183struct lp8788_buck2_dvs {
184 int gpio[LP8788_NUM_BUCK2_DVS];
185 enum lp8788_dvs_sel vsel;
186};
187
188/*
189 * struct lp8788_ldo_enable_pin
190 *
191 * Basically, all LDOs are enabled through the I2C commands.
192 * But ALDO 1 ~ 5, 7, DLDO 7, 9, 11 can be enabled by external gpio pins.
193 *
194 * @gpio : gpio number which is used for enabling ldos
195 * @init_state : initial gpio state (ex. GPIOF_OUT_INIT_LOW)
196 */
197struct lp8788_ldo_enable_pin {
198 int gpio;
199 int init_state;
200};
201
202/*
203 * struct lp8788_chg_param
204 * @addr : charging control register address (range : 0x11 ~ 0x1C)
205 * @val : charging parameter value
206 */
207struct lp8788_chg_param {
208 u8 addr;
209 u8 val;
210};
211
212/*
213 * struct lp8788_charger_platform_data
214 * @vbatt_adc : adc selection id for battery voltage
215 * @batt_temp_adc : adc selection id for battery temperature
216 * @max_vbatt_mv : used for calculating battery capacity
217 * @chg_params : initial charging parameters
218 * @num_chg_params : numbers of charging parameters
219 * @charger_event : the charger event can be reported to the platform side
220 */
221struct lp8788_charger_platform_data {
222 enum lp8788_adc_id vbatt_adc;
223 enum lp8788_adc_id batt_temp_adc;
224 unsigned int max_vbatt_mv;
225 struct lp8788_chg_param *chg_params;
226 int num_chg_params;
227 void (*charger_event) (struct lp8788 *lp,
228 enum lp8788_charger_event event);
229};
230
231/*
232 * struct lp8788_bl_pwm_data
233 * @pwm_set_intensity : set duty of pwm
234 * @pwm_get_intensity : get current duty of pwm
235 */
236struct lp8788_bl_pwm_data {
237 void (*pwm_set_intensity) (int brightness, int max_brightness);
238 int (*pwm_get_intensity) (int max_brightness);
239};
240
241/*
242 * struct lp8788_backlight_platform_data
243 * @name : backlight driver name. (default: "lcd-backlight")
244 * @initial_brightness : initial value of backlight brightness
245 * @bl_mode : brightness control by pwm or lp8788 register
246 * @dim_mode : dimming mode selection
247 * @full_scale : full scale current setting
248 * @rise_time : brightness ramp up step time
249 * @fall_time : brightness ramp down step time
250 * @pwm_pol : pwm polarity setting when bl_mode is pwm based
251 * @pwm_data : platform specific pwm generation functions
252 * only valid when bl_mode is pwm based
253 */
254struct lp8788_backlight_platform_data {
255 char *name;
256 int initial_brightness;
257 enum lp8788_bl_ctrl_mode bl_mode;
258 enum lp8788_bl_dim_mode dim_mode;
259 enum lp8788_bl_full_scale_current full_scale;
260 enum lp8788_bl_ramp_step rise_time;
261 enum lp8788_bl_ramp_step fall_time;
262 enum lp8788_bl_pwm_polarity pwm_pol;
263 struct lp8788_bl_pwm_data pwm_data;
264};
265
266/*
267 * struct lp8788_led_platform_data
268 * @name : led driver name. (default: "keyboard-backlight")
269 * @scale : current scale
270 * @num : current sink number
271 * @iout_code : current output value (Addr 9Ah ~ 9Bh)
272 */
273struct lp8788_led_platform_data {
274 char *name;
275 enum lp8788_isink_scale scale;
276 enum lp8788_isink_number num;
277 int iout_code;
278};
279
280/*
281 * struct lp8788_vib_platform_data
282 * @name : vibrator driver name
283 * @scale : current scale
284 * @num : current sink number
285 * @iout_code : current output value (Addr 9Ah ~ 9Bh)
286 * @pwm_code : PWM code value (Addr 9Ch ~ 9Eh)
287 */
288struct lp8788_vib_platform_data {
289 char *name;
290 enum lp8788_isink_scale scale;
291 enum lp8788_isink_number num;
292 int iout_code;
293 int pwm_code;
294};
295
296/*
297 * struct lp8788_platform_data
298 * @init_func : used for initializing registers
299 * before mfd driver is registered
300 * @buck_data : regulator initial data for buck
301 * @dldo_data : regulator initial data for digital ldo
302 * @aldo_data : regulator initial data for analog ldo
303 * @buck1_dvs : gpio configurations for buck1 dvs
304 * @buck2_dvs : gpio configurations for buck2 dvs
305 * @ldo_pin : gpio configurations for enabling LDOs
306 * @chg_pdata : platform data for charger driver
307 * @alarm_sel : rtc alarm selection (1 or 2)
308 * @bl_pdata : configurable data for backlight driver
309 * @led_pdata : configurable data for led driver
310 * @vib_pdata : configurable data for vibrator driver
311 * @adc_pdata : iio map data for adc driver
312 */
313struct lp8788_platform_data {
314 /* general system information */
315 int (*init_func) (struct lp8788 *lp);
316
317 /* regulators */
318 struct regulator_init_data *buck_data[LP8788_NUM_BUCKS];
319 struct regulator_init_data *dldo_data[LP8788_NUM_DLDOS];
320 struct regulator_init_data *aldo_data[LP8788_NUM_ALDOS];
321 struct lp8788_buck1_dvs *buck1_dvs;
322 struct lp8788_buck2_dvs *buck2_dvs;
323 struct lp8788_ldo_enable_pin *ldo_pin[EN_LDOS_MAX];
324
325 /* charger */
326 struct lp8788_charger_platform_data *chg_pdata;
327
328 /* rtc alarm */
329 enum lp8788_alarm_sel alarm_sel;
330
331 /* backlight */
332 struct lp8788_backlight_platform_data *bl_pdata;
333
334 /* current sinks */
335 struct lp8788_led_platform_data *led_pdata;
336 struct lp8788_vib_platform_data *vib_pdata;
337
338 /* adc iio map data */
339 struct iio_map *adc_pdata;
340};
341
342/*
343 * struct lp8788
344 * @dev : parent device pointer
345 * @regmap : used for i2c communcation on accessing registers
346 * @irqdm : interrupt domain for handling nested interrupt
347 * @irq : pin number of IRQ_N
348 * @pdata : lp8788 platform specific data
349 */
350struct lp8788 {
351 struct device *dev;
352 struct regmap *regmap;
353 struct irq_domain *irqdm;
354 int irq;
355 struct lp8788_platform_data *pdata;
356};
357
358int lp8788_irq_init(struct lp8788 *lp, int chip_irq);
359void lp8788_irq_exit(struct lp8788 *lp);
360int lp8788_read_byte(struct lp8788 *lp, u8 reg, u8 *data);
361int lp8788_read_multi_bytes(struct lp8788 *lp, u8 reg, u8 *data, size_t count);
362int lp8788_write_byte(struct lp8788 *lp, u8 reg, u8 data);
363int lp8788_update_bits(struct lp8788 *lp, u8 reg, u8 mask, u8 data);
364#endif
diff --git a/include/linux/mfd/lpc_ich.h b/include/linux/mfd/lpc_ich.h
index fec5256c3f5d..3e1df644c407 100644
--- a/include/linux/mfd/lpc_ich.h
+++ b/include/linux/mfd/lpc_ich.h
@@ -43,6 +43,7 @@ struct lpc_ich_info {
43 char name[32]; 43 char name[32];
44 unsigned int iTCO_version; 44 unsigned int iTCO_version;
45 unsigned int gpio_version; 45 unsigned int gpio_version;
46 u8 use_gpio;
46}; 47};
47 48
48#endif 49#endif
diff --git a/include/linux/mfd/max8907.h b/include/linux/mfd/max8907.h
new file mode 100644
index 000000000000..b06f7a6a1e80
--- /dev/null
+++ b/include/linux/mfd/max8907.h
@@ -0,0 +1,252 @@
1/*
2 * Functions to access MAX8907 power management chip.
3 *
4 * Copyright (C) 2010 Gyungoh Yoo <jack.yoo@maxim-ic.com>
5 * Copyright (C) 2012, NVIDIA CORPORATION. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __LINUX_MFD_MAX8907_H
13#define __LINUX_MFD_MAX8907_H
14
15#include <linux/mutex.h>
16#include <linux/pm.h>
17
18#define MAX8907_GEN_I2C_ADDR (0x78 >> 1)
19#define MAX8907_ADC_I2C_ADDR (0x8e >> 1)
20#define MAX8907_RTC_I2C_ADDR (0xd0 >> 1)
21
22/* MAX8907 register map */
23#define MAX8907_REG_SYSENSEL 0x00
24#define MAX8907_REG_ON_OFF_IRQ1 0x01
25#define MAX8907_REG_ON_OFF_IRQ1_MASK 0x02
26#define MAX8907_REG_ON_OFF_STAT 0x03
27#define MAX8907_REG_SDCTL1 0x04
28#define MAX8907_REG_SDSEQCNT1 0x05
29#define MAX8907_REG_SDV1 0x06
30#define MAX8907_REG_SDCTL2 0x07
31#define MAX8907_REG_SDSEQCNT2 0x08
32#define MAX8907_REG_SDV2 0x09
33#define MAX8907_REG_SDCTL3 0x0A
34#define MAX8907_REG_SDSEQCNT3 0x0B
35#define MAX8907_REG_SDV3 0x0C
36#define MAX8907_REG_ON_OFF_IRQ2 0x0D
37#define MAX8907_REG_ON_OFF_IRQ2_MASK 0x0E
38#define MAX8907_REG_RESET_CNFG 0x0F
39#define MAX8907_REG_LDOCTL16 0x10
40#define MAX8907_REG_LDOSEQCNT16 0x11
41#define MAX8907_REG_LDO16VOUT 0x12
42#define MAX8907_REG_SDBYSEQCNT 0x13
43#define MAX8907_REG_LDOCTL17 0x14
44#define MAX8907_REG_LDOSEQCNT17 0x15
45#define MAX8907_REG_LDO17VOUT 0x16
46#define MAX8907_REG_LDOCTL1 0x18
47#define MAX8907_REG_LDOSEQCNT1 0x19
48#define MAX8907_REG_LDO1VOUT 0x1A
49#define MAX8907_REG_LDOCTL2 0x1C
50#define MAX8907_REG_LDOSEQCNT2 0x1D
51#define MAX8907_REG_LDO2VOUT 0x1E
52#define MAX8907_REG_LDOCTL3 0x20
53#define MAX8907_REG_LDOSEQCNT3 0x21
54#define MAX8907_REG_LDO3VOUT 0x22
55#define MAX8907_REG_LDOCTL4 0x24
56#define MAX8907_REG_LDOSEQCNT4 0x25
57#define MAX8907_REG_LDO4VOUT 0x26
58#define MAX8907_REG_LDOCTL5 0x28
59#define MAX8907_REG_LDOSEQCNT5 0x29
60#define MAX8907_REG_LDO5VOUT 0x2A
61#define MAX8907_REG_LDOCTL6 0x2C
62#define MAX8907_REG_LDOSEQCNT6 0x2D
63#define MAX8907_REG_LDO6VOUT 0x2E
64#define MAX8907_REG_LDOCTL7 0x30
65#define MAX8907_REG_LDOSEQCNT7 0x31
66#define MAX8907_REG_LDO7VOUT 0x32
67#define MAX8907_REG_LDOCTL8 0x34
68#define MAX8907_REG_LDOSEQCNT8 0x35
69#define MAX8907_REG_LDO8VOUT 0x36
70#define MAX8907_REG_LDOCTL9 0x38
71#define MAX8907_REG_LDOSEQCNT9 0x39
72#define MAX8907_REG_LDO9VOUT 0x3A
73#define MAX8907_REG_LDOCTL10 0x3C
74#define MAX8907_REG_LDOSEQCNT10 0x3D
75#define MAX8907_REG_LDO10VOUT 0x3E
76#define MAX8907_REG_LDOCTL11 0x40
77#define MAX8907_REG_LDOSEQCNT11 0x41
78#define MAX8907_REG_LDO11VOUT 0x42
79#define MAX8907_REG_LDOCTL12 0x44
80#define MAX8907_REG_LDOSEQCNT12 0x45
81#define MAX8907_REG_LDO12VOUT 0x46
82#define MAX8907_REG_LDOCTL13 0x48
83#define MAX8907_REG_LDOSEQCNT13 0x49
84#define MAX8907_REG_LDO13VOUT 0x4A
85#define MAX8907_REG_LDOCTL14 0x4C
86#define MAX8907_REG_LDOSEQCNT14 0x4D
87#define MAX8907_REG_LDO14VOUT 0x4E
88#define MAX8907_REG_LDOCTL15 0x50
89#define MAX8907_REG_LDOSEQCNT15 0x51
90#define MAX8907_REG_LDO15VOUT 0x52
91#define MAX8907_REG_OUT5VEN 0x54
92#define MAX8907_REG_OUT5VSEQ 0x55
93#define MAX8907_REG_OUT33VEN 0x58
94#define MAX8907_REG_OUT33VSEQ 0x59
95#define MAX8907_REG_LDOCTL19 0x5C
96#define MAX8907_REG_LDOSEQCNT19 0x5D
97#define MAX8907_REG_LDO19VOUT 0x5E
98#define MAX8907_REG_LBCNFG 0x60
99#define MAX8907_REG_SEQ1CNFG 0x64
100#define MAX8907_REG_SEQ2CNFG 0x65
101#define MAX8907_REG_SEQ3CNFG 0x66
102#define MAX8907_REG_SEQ4CNFG 0x67
103#define MAX8907_REG_SEQ5CNFG 0x68
104#define MAX8907_REG_SEQ6CNFG 0x69
105#define MAX8907_REG_SEQ7CNFG 0x6A
106#define MAX8907_REG_LDOCTL18 0x72
107#define MAX8907_REG_LDOSEQCNT18 0x73
108#define MAX8907_REG_LDO18VOUT 0x74
109#define MAX8907_REG_BBAT_CNFG 0x78
110#define MAX8907_REG_CHG_CNTL1 0x7C
111#define MAX8907_REG_CHG_CNTL2 0x7D
112#define MAX8907_REG_CHG_IRQ1 0x7E
113#define MAX8907_REG_CHG_IRQ2 0x7F
114#define MAX8907_REG_CHG_IRQ1_MASK 0x80
115#define MAX8907_REG_CHG_IRQ2_MASK 0x81
116#define MAX8907_REG_CHG_STAT 0x82
117#define MAX8907_REG_WLED_MODE_CNTL 0x84
118#define MAX8907_REG_ILED_CNTL 0x84
119#define MAX8907_REG_II1RR 0x8E
120#define MAX8907_REG_II2RR 0x8F
121#define MAX8907_REG_LDOCTL20 0x9C
122#define MAX8907_REG_LDOSEQCNT20 0x9D
123#define MAX8907_REG_LDO20VOUT 0x9E
124
125/* RTC register map */
126#define MAX8907_REG_RTC_SEC 0x00
127#define MAX8907_REG_RTC_MIN 0x01
128#define MAX8907_REG_RTC_HOURS 0x02
129#define MAX8907_REG_RTC_WEEKDAY 0x03
130#define MAX8907_REG_RTC_DATE 0x04
131#define MAX8907_REG_RTC_MONTH 0x05
132#define MAX8907_REG_RTC_YEAR1 0x06
133#define MAX8907_REG_RTC_YEAR2 0x07
134#define MAX8907_REG_ALARM0_SEC 0x08
135#define MAX8907_REG_ALARM0_MIN 0x09
136#define MAX8907_REG_ALARM0_HOURS 0x0A
137#define MAX8907_REG_ALARM0_WEEKDAY 0x0B
138#define MAX8907_REG_ALARM0_DATE 0x0C
139#define MAX8907_REG_ALARM0_MONTH 0x0D
140#define MAX8907_REG_ALARM0_YEAR1 0x0E
141#define MAX8907_REG_ALARM0_YEAR2 0x0F
142#define MAX8907_REG_ALARM1_SEC 0x10
143#define MAX8907_REG_ALARM1_MIN 0x11
144#define MAX8907_REG_ALARM1_HOURS 0x12
145#define MAX8907_REG_ALARM1_WEEKDAY 0x13
146#define MAX8907_REG_ALARM1_DATE 0x14
147#define MAX8907_REG_ALARM1_MONTH 0x15
148#define MAX8907_REG_ALARM1_YEAR1 0x16
149#define MAX8907_REG_ALARM1_YEAR2 0x17
150#define MAX8907_REG_ALARM0_CNTL 0x18
151#define MAX8907_REG_ALARM1_CNTL 0x19
152#define MAX8907_REG_RTC_STATUS 0x1A
153#define MAX8907_REG_RTC_CNTL 0x1B
154#define MAX8907_REG_RTC_IRQ 0x1C
155#define MAX8907_REG_RTC_IRQ_MASK 0x1D
156#define MAX8907_REG_MPL_CNTL 0x1E
157
158/* ADC and Touch Screen Controller register map */
159#define MAX8907_CTL 0
160#define MAX8907_SEQCNT 1
161#define MAX8907_VOUT 2
162
163/* mask bit fields */
164#define MAX8907_MASK_LDO_SEQ 0x1C
165#define MAX8907_MASK_LDO_EN 0x01
166#define MAX8907_MASK_VBBATTCV 0x03
167#define MAX8907_MASK_OUT5V_VINEN 0x10
168#define MAX8907_MASK_OUT5V_ENSRC 0x0E
169#define MAX8907_MASK_OUT5V_EN 0x01
170#define MAX8907_MASK_POWER_OFF 0x40
171
172/* Regulator IDs */
173#define MAX8907_MBATT 0
174#define MAX8907_SD1 1
175#define MAX8907_SD2 2
176#define MAX8907_SD3 3
177#define MAX8907_LDO1 4
178#define MAX8907_LDO2 5
179#define MAX8907_LDO3 6
180#define MAX8907_LDO4 7
181#define MAX8907_LDO5 8
182#define MAX8907_LDO6 9
183#define MAX8907_LDO7 10
184#define MAX8907_LDO8 11
185#define MAX8907_LDO9 12
186#define MAX8907_LDO10 13
187#define MAX8907_LDO11 14
188#define MAX8907_LDO12 15
189#define MAX8907_LDO13 16
190#define MAX8907_LDO14 17
191#define MAX8907_LDO15 18
192#define MAX8907_LDO16 19
193#define MAX8907_LDO17 20
194#define MAX8907_LDO18 21
195#define MAX8907_LDO19 22
196#define MAX8907_LDO20 23
197#define MAX8907_OUT5V 24
198#define MAX8907_OUT33V 25
199#define MAX8907_BBAT 26
200#define MAX8907_SDBY 27
201#define MAX8907_VRTC 28
202#define MAX8907_NUM_REGULATORS (MAX8907_VRTC + 1)
203
204/* IRQ definitions */
205enum {
206 MAX8907_IRQ_VCHG_DC_OVP = 0,
207 MAX8907_IRQ_VCHG_DC_F,
208 MAX8907_IRQ_VCHG_DC_R,
209 MAX8907_IRQ_VCHG_THM_OK_R,
210 MAX8907_IRQ_VCHG_THM_OK_F,
211 MAX8907_IRQ_VCHG_MBATTLOW_F,
212 MAX8907_IRQ_VCHG_MBATTLOW_R,
213 MAX8907_IRQ_VCHG_RST,
214 MAX8907_IRQ_VCHG_DONE,
215 MAX8907_IRQ_VCHG_TOPOFF,
216 MAX8907_IRQ_VCHG_TMR_FAULT,
217
218 MAX8907_IRQ_GPM_RSTIN = 0,
219 MAX8907_IRQ_GPM_MPL,
220 MAX8907_IRQ_GPM_SW_3SEC,
221 MAX8907_IRQ_GPM_EXTON_F,
222 MAX8907_IRQ_GPM_EXTON_R,
223 MAX8907_IRQ_GPM_SW_1SEC,
224 MAX8907_IRQ_GPM_SW_F,
225 MAX8907_IRQ_GPM_SW_R,
226 MAX8907_IRQ_GPM_SYSCKEN_F,
227 MAX8907_IRQ_GPM_SYSCKEN_R,
228
229 MAX8907_IRQ_RTC_ALARM1 = 0,
230 MAX8907_IRQ_RTC_ALARM0,
231};
232
233struct max8907_platform_data {
234 struct regulator_init_data *init_data[MAX8907_NUM_REGULATORS];
235 bool pm_off;
236};
237
238struct regmap_irq_chips_data;
239
240struct max8907 {
241 struct device *dev;
242 struct mutex irq_lock;
243 struct i2c_client *i2c_gen;
244 struct i2c_client *i2c_rtc;
245 struct regmap *regmap_gen;
246 struct regmap *regmap_rtc;
247 struct regmap_irq_chip_data *irqc_chg;
248 struct regmap_irq_chip_data *irqc_on_off;
249 struct regmap_irq_chip_data *irqc_rtc;
250};
251
252#endif
diff --git a/include/linux/mfd/max8925.h b/include/linux/mfd/max8925.h
index 15b2392a56fb..74d8e2969630 100644
--- a/include/linux/mfd/max8925.h
+++ b/include/linux/mfd/max8925.h
@@ -158,8 +158,6 @@ enum {
158#define TSC_IRQ_MASK (0x03) 158#define TSC_IRQ_MASK (0x03)
159#define RTC_IRQ_MASK (0x0c) 159#define RTC_IRQ_MASK (0x0c)
160 160
161#define MAX8925_MAX_REGULATOR (23)
162
163#define MAX8925_NAME_SIZE (32) 161#define MAX8925_NAME_SIZE (32)
164 162
165/* IRQ definitions */ 163/* IRQ definitions */
@@ -236,7 +234,29 @@ struct max8925_platform_data {
236 struct max8925_backlight_pdata *backlight; 234 struct max8925_backlight_pdata *backlight;
237 struct max8925_touch_pdata *touch; 235 struct max8925_touch_pdata *touch;
238 struct max8925_power_pdata *power; 236 struct max8925_power_pdata *power;
239 struct regulator_init_data *regulator[MAX8925_MAX_REGULATOR]; 237 struct regulator_init_data *sd1;
238 struct regulator_init_data *sd2;
239 struct regulator_init_data *sd3;
240 struct regulator_init_data *ldo1;
241 struct regulator_init_data *ldo2;
242 struct regulator_init_data *ldo3;
243 struct regulator_init_data *ldo4;
244 struct regulator_init_data *ldo5;
245 struct regulator_init_data *ldo6;
246 struct regulator_init_data *ldo7;
247 struct regulator_init_data *ldo8;
248 struct regulator_init_data *ldo9;
249 struct regulator_init_data *ldo10;
250 struct regulator_init_data *ldo11;
251 struct regulator_init_data *ldo12;
252 struct regulator_init_data *ldo13;
253 struct regulator_init_data *ldo14;
254 struct regulator_init_data *ldo15;
255 struct regulator_init_data *ldo16;
256 struct regulator_init_data *ldo17;
257 struct regulator_init_data *ldo18;
258 struct regulator_init_data *ldo19;
259 struct regulator_init_data *ldo20;
240 260
241 int irq_base; 261 int irq_base;
242 int tsc_irq; 262 int tsc_irq;
diff --git a/include/linux/mfd/palmas.h b/include/linux/mfd/palmas.h
index 9cbc642d40ad..29f6616e12f0 100644
--- a/include/linux/mfd/palmas.h
+++ b/include/linux/mfd/palmas.h
@@ -23,6 +23,9 @@
23#define PALMAS_NUM_CLIENTS 3 23#define PALMAS_NUM_CLIENTS 3
24 24
25struct palmas_pmic; 25struct palmas_pmic;
26struct palmas_gpadc;
27struct palmas_resource;
28struct palmas_usb;
26 29
27struct palmas { 30struct palmas {
28 struct device *dev; 31 struct device *dev;
@@ -41,6 +44,9 @@ struct palmas {
41 44
42 /* Child Devices */ 45 /* Child Devices */
43 struct palmas_pmic *pmic; 46 struct palmas_pmic *pmic;
47 struct palmas_gpadc *gpadc;
48 struct palmas_resource *resource;
49 struct palmas_usb *usb;
44 50
45 /* GPIO MUXing */ 51 /* GPIO MUXing */
46 u8 gpio_muxed; 52 u8 gpio_muxed;
@@ -48,6 +54,23 @@ struct palmas {
48 u8 pwm_muxed; 54 u8 pwm_muxed;
49}; 55};
50 56
57struct palmas_gpadc_platform_data {
58 /* Channel 3 current source is only enabled during conversion */
59 int ch3_current;
60
61 /* Channel 0 current source can be used for battery detection.
62 * If used for battery detection this will cause a permanent current
63 * consumption depending on current level set here.
64 */
65 int ch0_current;
66
67 /* default BAT_REMOVAL_DAT setting on device probe */
68 int bat_removal;
69
70 /* Sets the START_POLARITY bit in the RT_CTRL register */
71 int start_polarity;
72};
73
51struct palmas_reg_init { 74struct palmas_reg_init {
52 /* warm_rest controls the voltage levels after a warm reset 75 /* warm_rest controls the voltage levels after a warm reset
53 * 76 *
@@ -107,21 +130,94 @@ struct palmas_reg_init {
107 130
108}; 131};
109 132
133enum palmas_regulators {
134 /* SMPS regulators */
135 PALMAS_REG_SMPS12,
136 PALMAS_REG_SMPS123,
137 PALMAS_REG_SMPS3,
138 PALMAS_REG_SMPS45,
139 PALMAS_REG_SMPS457,
140 PALMAS_REG_SMPS6,
141 PALMAS_REG_SMPS7,
142 PALMAS_REG_SMPS8,
143 PALMAS_REG_SMPS9,
144 PALMAS_REG_SMPS10,
145 /* LDO regulators */
146 PALMAS_REG_LDO1,
147 PALMAS_REG_LDO2,
148 PALMAS_REG_LDO3,
149 PALMAS_REG_LDO4,
150 PALMAS_REG_LDO5,
151 PALMAS_REG_LDO6,
152 PALMAS_REG_LDO7,
153 PALMAS_REG_LDO8,
154 PALMAS_REG_LDO9,
155 PALMAS_REG_LDOLN,
156 PALMAS_REG_LDOUSB,
157 /* Total number of regulators */
158 PALMAS_NUM_REGS,
159};
160
110struct palmas_pmic_platform_data { 161struct palmas_pmic_platform_data {
111 /* An array of pointers to regulator init data indexed by regulator 162 /* An array of pointers to regulator init data indexed by regulator
112 * ID 163 * ID
113 */ 164 */
114 struct regulator_init_data **reg_data; 165 struct regulator_init_data *reg_data[PALMAS_NUM_REGS];
115 166
116 /* An array of pointers to structures containing sleep mode and DVS 167 /* An array of pointers to structures containing sleep mode and DVS
117 * configuration for regulators indexed by ID 168 * configuration for regulators indexed by ID
118 */ 169 */
119 struct palmas_reg_init **reg_init; 170 struct palmas_reg_init *reg_init[PALMAS_NUM_REGS];
120 171
121 /* use LDO6 for vibrator control */ 172 /* use LDO6 for vibrator control */
122 int ldo6_vibrator; 173 int ldo6_vibrator;
174};
123 175
176struct palmas_usb_platform_data {
177 /* Set this if platform wishes its own vbus control */
178 int no_control_vbus;
124 179
180 /* Do we enable the wakeup comparator on probe */
181 int wakeup;
182};
183
184struct palmas_resource_platform_data {
185 int regen1_mode_sleep;
186 int regen2_mode_sleep;
187 int sysen1_mode_sleep;
188 int sysen2_mode_sleep;
189
190 /* bitfield to be loaded to NSLEEP_RES_ASSIGN */
191 u8 nsleep_res;
192 /* bitfield to be loaded to NSLEEP_SMPS_ASSIGN */
193 u8 nsleep_smps;
194 /* bitfield to be loaded to NSLEEP_LDO_ASSIGN1 */
195 u8 nsleep_ldo1;
196 /* bitfield to be loaded to NSLEEP_LDO_ASSIGN2 */
197 u8 nsleep_ldo2;
198
199 /* bitfield to be loaded to ENABLE1_RES_ASSIGN */
200 u8 enable1_res;
201 /* bitfield to be loaded to ENABLE1_SMPS_ASSIGN */
202 u8 enable1_smps;
203 /* bitfield to be loaded to ENABLE1_LDO_ASSIGN1 */
204 u8 enable1_ldo1;
205 /* bitfield to be loaded to ENABLE1_LDO_ASSIGN2 */
206 u8 enable1_ldo2;
207
208 /* bitfield to be loaded to ENABLE2_RES_ASSIGN */
209 u8 enable2_res;
210 /* bitfield to be loaded to ENABLE2_SMPS_ASSIGN */
211 u8 enable2_smps;
212 /* bitfield to be loaded to ENABLE2_LDO_ASSIGN1 */
213 u8 enable2_ldo1;
214 /* bitfield to be loaded to ENABLE2_LDO_ASSIGN2 */
215 u8 enable2_ldo2;
216};
217
218struct palmas_clk_platform_data {
219 int clk32kg_mode_sleep;
220 int clk32kgaudio_mode_sleep;
125}; 221};
126 222
127struct palmas_platform_data { 223struct palmas_platform_data {
@@ -138,8 +234,49 @@ struct palmas_platform_data {
138 u8 pad1, pad2; 234 u8 pad1, pad2;
139 235
140 struct palmas_pmic_platform_data *pmic_pdata; 236 struct palmas_pmic_platform_data *pmic_pdata;
237 struct palmas_gpadc_platform_data *gpadc_pdata;
238 struct palmas_usb_platform_data *usb_pdata;
239 struct palmas_resource_platform_data *resource_pdata;
240 struct palmas_clk_platform_data *clk_pdata;
241};
242
243struct palmas_gpadc_calibration {
244 s32 gain;
245 s32 gain_error;
246 s32 offset_error;
141}; 247};
142 248
249struct palmas_gpadc {
250 struct device *dev;
251 struct palmas *palmas;
252
253 int ch3_current;
254 int ch0_current;
255
256 int gpadc_force;
257
258 int bat_removal;
259
260 struct mutex reading_lock;
261 struct completion irq_complete;
262
263 int eoc_sw_irq;
264
265 struct palmas_gpadc_calibration *palmas_cal_tbl;
266
267 int conv0_channel;
268 int conv1_channel;
269 int rt_channel;
270};
271
272struct palmas_gpadc_result {
273 s32 raw_code;
274 s32 corrected_code;
275 s32 result;
276};
277
278#define PALMAS_MAX_CHANNELS 16
279
143/* Define the palmas IRQ numbers */ 280/* Define the palmas IRQ numbers */
144enum palmas_irqs { 281enum palmas_irqs {
145 /* INT1 registers */ 282 /* INT1 registers */
@@ -182,34 +319,6 @@ enum palmas_irqs {
182 PALMAS_NUM_IRQ, 319 PALMAS_NUM_IRQ,
183}; 320};
184 321
185enum palmas_regulators {
186 /* SMPS regulators */
187 PALMAS_REG_SMPS12,
188 PALMAS_REG_SMPS123,
189 PALMAS_REG_SMPS3,
190 PALMAS_REG_SMPS45,
191 PALMAS_REG_SMPS457,
192 PALMAS_REG_SMPS6,
193 PALMAS_REG_SMPS7,
194 PALMAS_REG_SMPS8,
195 PALMAS_REG_SMPS9,
196 PALMAS_REG_SMPS10,
197 /* LDO regulators */
198 PALMAS_REG_LDO1,
199 PALMAS_REG_LDO2,
200 PALMAS_REG_LDO3,
201 PALMAS_REG_LDO4,
202 PALMAS_REG_LDO5,
203 PALMAS_REG_LDO6,
204 PALMAS_REG_LDO7,
205 PALMAS_REG_LDO8,
206 PALMAS_REG_LDO9,
207 PALMAS_REG_LDOLN,
208 PALMAS_REG_LDOUSB,
209 /* Total number of regulators */
210 PALMAS_NUM_REGS,
211};
212
213struct palmas_pmic { 322struct palmas_pmic {
214 struct palmas *palmas; 323 struct palmas *palmas;
215 struct device *dev; 324 struct device *dev;
@@ -223,6 +332,69 @@ struct palmas_pmic {
223 int range[PALMAS_REG_SMPS10]; 332 int range[PALMAS_REG_SMPS10];
224}; 333};
225 334
335struct palmas_resource {
336 struct palmas *palmas;
337 struct device *dev;
338};
339
340struct palmas_usb {
341 struct palmas *palmas;
342 struct device *dev;
343
344 /* for vbus reporting with irqs disabled */
345 spinlock_t lock;
346
347 struct regulator *vbus_reg;
348
349 /* used to set vbus, in atomic path */
350 struct work_struct set_vbus_work;
351
352 int irq1;
353 int irq2;
354 int irq3;
355 int irq4;
356
357 int vbus_enable;
358
359 u8 linkstat;
360};
361
362#define comparator_to_palmas(x) container_of((x), struct palmas_usb, comparator)
363
364enum usb_irq_events {
365 /* Wakeup events from INT3 */
366 PALMAS_USB_ID_WAKEPUP,
367 PALMAS_USB_VBUS_WAKEUP,
368
369 /* ID_OTG_EVENTS */
370 PALMAS_USB_ID_GND,
371 N_PALMAS_USB_ID_GND,
372 PALMAS_USB_ID_C,
373 N_PALMAS_USB_ID_C,
374 PALMAS_USB_ID_B,
375 N_PALMAS_USB_ID_B,
376 PALMAS_USB_ID_A,
377 N_PALMAS_USB_ID_A,
378 PALMAS_USB_ID_FLOAT,
379 N_PALMAS_USB_ID_FLOAT,
380
381 /* VBUS_OTG_EVENTS */
382 PALMAS_USB_VB_SESS_END,
383 N_PALMAS_USB_VB_SESS_END,
384 PALMAS_USB_VB_SESS_VLD,
385 N_PALMAS_USB_VB_SESS_VLD,
386 PALMAS_USB_VA_SESS_VLD,
387 N_PALMAS_USB_VA_SESS_VLD,
388 PALMAS_USB_VA_VBUS_VLD,
389 N_PALMAS_USB_VA_VBUS_VLD,
390 PALMAS_USB_VADP_SNS,
391 N_PALMAS_USB_VADP_SNS,
392 PALMAS_USB_VADP_PRB,
393 N_PALMAS_USB_VADP_PRB,
394 PALMAS_USB_VOTG_SESS_VLD,
395 N_PALMAS_USB_VOTG_SESS_VLD,
396};
397
226/* defines so we can store the mux settings */ 398/* defines so we can store the mux settings */
227#define PALMAS_GPIO_0_MUXED (1 << 0) 399#define PALMAS_GPIO_0_MUXED (1 << 0)
228#define PALMAS_GPIO_1_MUXED (1 << 1) 400#define PALMAS_GPIO_1_MUXED (1 << 1)
diff --git a/include/linux/mfd/smsc.h b/include/linux/mfd/smsc.h
new file mode 100644
index 000000000000..9747b29f356f
--- /dev/null
+++ b/include/linux/mfd/smsc.h
@@ -0,0 +1,109 @@
1/*
2 * SMSC ECE1099
3 *
4 * Copyright 2012 Texas Instruments Inc.
5 *
6 * Author: Sourav Poddar <sourav.poddar@ti.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 */
14
15#ifndef __LINUX_MFD_SMSC_H
16#define __LINUX_MFD_SMSC_H
17
18#include <linux/regmap.h>
19
20#define SMSC_ID_ECE1099 1
21#define SMSC_NUM_CLIENTS 2
22
23#define SMSC_BASE_ADDR 0x38
24#define OMAP_GPIO_SMSC_IRQ 151
25
26#define SMSC_MAXGPIO 32
27#define SMSC_BANK(offs) ((offs) >> 3)
28#define SMSC_BIT(offs) (1u << ((offs) & 0x7))
29
30struct smsc {
31 struct device *dev;
32 struct i2c_client *i2c_clients[SMSC_NUM_CLIENTS];
33 struct regmap *regmap;
34 int clk;
35 /* Stored chip id */
36 int id;
37};
38
39struct smsc_gpio;
40struct smsc_keypad;
41
42static inline int smsc_read(struct device *child, unsigned int reg,
43 unsigned int *dest)
44{
45 struct smsc *smsc = dev_get_drvdata(child->parent);
46
47 return regmap_read(smsc->regmap, reg, dest);
48}
49
50static inline int smsc_write(struct device *child, unsigned int reg,
51 unsigned int value)
52{
53 struct smsc *smsc = dev_get_drvdata(child->parent);
54
55 return regmap_write(smsc->regmap, reg, value);
56}
57
58/* Registers for SMSC */
59#define SMSC_RESET 0xF5
60#define SMSC_GRP_INT 0xF9
61#define SMSC_CLK_CTRL 0xFA
62#define SMSC_WKUP_CTRL 0xFB
63#define SMSC_DEV_ID 0xFC
64#define SMSC_DEV_REV 0xFD
65#define SMSC_VEN_ID_L 0xFE
66#define SMSC_VEN_ID_H 0xFF
67
68/* CLK VALUE */
69#define SMSC_CLK_VALUE 0x13
70
71/* Registers for function GPIO INPUT */
72#define SMSC_GPIO_DATA_IN_START 0x00
73
74/* Registers for function GPIO OUPUT */
75#define SMSC_GPIO_DATA_OUT_START 0x05
76
77/* Definitions for SMSC GPIO CONFIGURATION REGISTER*/
78#define SMSC_GPIO_INPUT_LOW 0x01
79#define SMSC_GPIO_INPUT_RISING 0x09
80#define SMSC_GPIO_INPUT_FALLING 0x11
81#define SMSC_GPIO_INPUT_BOTH_EDGE 0x19
82#define SMSC_GPIO_OUTPUT_PP 0x21
83#define SMSC_GPIO_OUTPUT_OP 0x31
84
85#define GRP_INT_STAT 0xf9
86#define SMSC_GPI_INT 0x0f
87#define SMSC_CFG_START 0x0A
88
89/* Registers for SMSC GPIO INTERRUPT STATUS REGISTER*/
90#define SMSC_GPIO_INT_STAT_START 0x32
91
92/* Registers for SMSC GPIO INTERRUPT MASK REGISTER*/
93#define SMSC_GPIO_INT_MASK_START 0x37
94
95/* Registers for SMSC function KEYPAD*/
96#define SMSC_KP_OUT 0x40
97#define SMSC_KP_IN 0x41
98#define SMSC_KP_INT_STAT 0x42
99#define SMSC_KP_INT_MASK 0x43
100
101/* Definitions for keypad */
102#define SMSC_KP_KSO 0x70
103#define SMSC_KP_KSI 0x51
104#define SMSC_KSO_ALL_LOW 0x20
105#define SMSC_KP_SET_LOW_PWR 0x0B
106#define SMSC_KP_SET_HIGH 0xFF
107#define SMSC_KSO_EVAL 0x00
108
109#endif /* __LINUX_MFD_SMSC_H */
diff --git a/include/linux/mfd/syscon.h b/include/linux/mfd/syscon.h
new file mode 100644
index 000000000000..6aeb6b8da64d
--- /dev/null
+++ b/include/linux/mfd/syscon.h
@@ -0,0 +1,23 @@
1/*
2 * System Control Driver
3 *
4 * Copyright (C) 2012 Freescale Semiconductor, Inc.
5 * Copyright (C) 2012 Linaro Ltd.
6 *
7 * Author: Dong Aisheng <dong.aisheng@linaro.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#ifndef __LINUX_MFD_SYSCON_H__
16#define __LINUX_MFD_SYSCON_H__
17
18extern struct regmap *syscon_node_to_regmap(struct device_node *np);
19extern struct regmap *syscon_regmap_lookup_by_compatible(const char *s);
20extern struct regmap *syscon_regmap_lookup_by_phandle(
21 struct device_node *np,
22 const char *property);
23#endif /* __LINUX_MFD_SYSCON_H__ */
diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
new file mode 100644
index 000000000000..dab34a1deb2c
--- /dev/null
+++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h
@@ -0,0 +1,319 @@
1/*
2 * Copyright (C) 2012 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef __LINUX_IMX6Q_IOMUXC_GPR_H
10#define __LINUX_IMX6Q_IOMUXC_GPR_H
11
12#include <linux/bitops.h>
13
14#define IOMUXC_GPR0 0x00
15#define IOMUXC_GPR1 0x04
16#define IOMUXC_GPR2 0x08
17#define IOMUXC_GPR3 0x0c
18#define IOMUXC_GPR4 0x10
19#define IOMUXC_GPR5 0x14
20#define IOMUXC_GPR6 0x18
21#define IOMUXC_GPR7 0x1c
22#define IOMUXC_GPR8 0x20
23#define IOMUXC_GPR9 0x24
24#define IOMUXC_GPR10 0x28
25#define IOMUXC_GPR11 0x2c
26#define IOMUXC_GPR12 0x30
27#define IOMUXC_GPR13 0x34
28
29#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_MASK (0x3 << 30)
30#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_AUDMUX_RXCLK_P7_MUXED (0x0 << 30)
31#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_AUDMUX_RXCLK_P7 (0x1 << 30)
32#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_SSI3_SSI_SRCK (0x2 << 30)
33#define IMX6Q_GPR0_CLOCK_8_MUX_SEL_SSI3_RX_BIT_CLK (0x3 << 30)
34#define IMX6Q_GPR0_CLOCK_0_MUX_SEL_MASK (0x3 << 28)
35#define IMX6Q_GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_IND_SCKR_MUXED (0x0 << 28)
36#define IMX6Q_GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_IND_SCKR (0x1 << 28)
37#define IMX6Q_GPR0_CLOCK_0_MUX_SEL_ESAI1_IPP_DO_SCKR (0x2 << 28)
38#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_MASK (0x3 << 26)
39#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_AUDMUX_TXCLK_P7_MUXED (0x0 << 26)
40#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_AUDMUX_TXCLK_P7 (0x1 << 26)
41#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_SSI3_SSI_STCK (0x2 << 26)
42#define IMX6Q_GPR0_CLOCK_B_MUX_SEL_SSI3_TX_BIT_CLK (0x3 << 26)
43#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_MASK (0x3 << 24)
44#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_AUDMUX_RXCLK_P7_MUXED (0x3 << 24)
45#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_AUDMUX_RXCLK_P7 (0x3 << 24)
46#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_SSI3_SSI_SRCK (0x3 << 24)
47#define IMX6Q_GPR0_CLOCK_3_MUX_SEL_SSI3_RX_BIT_CLK (0x3 << 24)
48#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_MASK (0x3 << 22)
49#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_AUDMUX_TXCLK_P2_MUXED (0x0 << 22)
50#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_AUDMUX_TXCLK_P2 (0x1 << 22)
51#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_SSI2_SSI_STCK (0x2 << 22)
52#define IMX6Q_GPR0_CLOCK_A_MUX_SEL_SSI2_TX_BIT_CLK (0x3 << 22)
53#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_MASK (0x3 << 20)
54#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_AUDMUX_RXCLK_P2_MUXED (0x0 << 20)
55#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_AUDMUX_RXCLK_P2 (0x1 << 20)
56#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_SSI2_SSI_SRCK (0x2 << 20)
57#define IMX6Q_GPR0_CLOCK_2_MUX_SEL_SSI2_RX_BIT_CLK (0x3 << 20)
58#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_MASK (0x3 << 18)
59#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_AUDMUX_TXCLK_P1_MUXED (0x0 << 18)
60#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_AUDMUX_TXCLK_P1 (0x1 << 18)
61#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_SSI1_SSI_STCK (0x2 << 18)
62#define IMX6Q_GPR0_CLOCK_9_MUX_SEL_SSI1_SSI_TX_BIT_CLK (0x3 << 18)
63#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_MASK (0x3 << 16)
64#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_AUDMUX_RXCLK_P1_MUXED (0x0 << 16)
65#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_AUDMUX_RXCLK_P1 (0x1 << 16)
66#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_SSI1_SSI_SRCK (0x2 << 16)
67#define IMX6Q_GPR0_CLOCK_1_MUX_SEL_SSI1_SSI_RX_BIT_CLK (0x3 << 16)
68#define IMX6Q_GPR0_TX_CLK2_MUX_SEL_MASK (0x3 << 14)
69#define IMX6Q_GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK1 (0x0 << 14)
70#define IMX6Q_GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK2 (0x1 << 14)
71#define IMX6Q_GPR0_TX_CLK2_MUX_SEL_ASRCK_CLK3 (0x2 << 14)
72#define IMX6Q_GPR0_DMAREQ_MUX_SEL7_MASK BIT(7)
73#define IMX6Q_GPR0_DMAREQ_MUX_SEL7_SPDIF 0x0
74#define IMX6Q_GPR0_DMAREQ_MUX_SEL7_IOMUX BIT(7)
75#define IMX6Q_GPR0_DMAREQ_MUX_SEL6_MASK BIT(6)
76#define IMX6Q_GPR0_DMAREQ_MUX_SEL6_ESAI 0x0
77#define IMX6Q_GPR0_DMAREQ_MUX_SEL6_I2C3 BIT(6)
78#define IMX6Q_GPR0_DMAREQ_MUX_SEL5_MASK BIT(5)
79#define IMX6Q_GPR0_DMAREQ_MUX_SEL5_ECSPI4 0x0
80#define IMX6Q_GPR0_DMAREQ_MUX_SEL5_EPIT2 BIT(5)
81#define IMX6Q_GPR0_DMAREQ_MUX_SEL4_MASK BIT(4)
82#define IMX6Q_GPR0_DMAREQ_MUX_SEL4_ECSPI4 0x0
83#define IMX6Q_GPR0_DMAREQ_MUX_SEL4_I2C1 BIT(4)
84#define IMX6Q_GPR0_DMAREQ_MUX_SEL3_MASK BIT(3)
85#define IMX6Q_GPR0_DMAREQ_MUX_SEL3_ECSPI2 0x0
86#define IMX6Q_GPR0_DMAREQ_MUX_SEL3_I2C1 BIT(3)
87#define IMX6Q_GPR0_DMAREQ_MUX_SEL2_MASK BIT(2)
88#define IMX6Q_GPR0_DMAREQ_MUX_SEL2_ECSPI1 0x0
89#define IMX6Q_GPR0_DMAREQ_MUX_SEL2_I2C2 BIT(2)
90#define IMX6Q_GPR0_DMAREQ_MUX_SEL1_MASK BIT(1)
91#define IMX6Q_GPR0_DMAREQ_MUX_SEL1_ECSPI1 0x0
92#define IMX6Q_GPR0_DMAREQ_MUX_SEL1_I2C3 BIT(1)
93#define IMX6Q_GPR0_DMAREQ_MUX_SEL0_MASK BIT(0)
94#define IMX6Q_GPR0_DMAREQ_MUX_SEL0_IPU1 0x0
95#define IMX6Q_GPR0_DMAREQ_MUX_SEL0_IOMUX BIT(0)
96
97#define IMX6Q_GPR1_PCIE_REQ_MASK (0x3 << 30)
98#define IMX6Q_GPR1_PCIE_EXIT_L1 BIT(28)
99#define IMX6Q_GPR1_PCIE_RDY_L23 BIT(27)
100#define IMX6Q_GPR1_PCIE_ENTER_L1 BIT(26)
101#define IMX6Q_GPR1_MIPI_COLOR_SW BIT(25)
102#define IMX6Q_GPR1_DPI_OFF BIT(24)
103#define IMX6Q_GPR1_EXC_MON_MASK BIT(22)
104#define IMX6Q_GPR1_EXC_MON_OKAY 0x0
105#define IMX6Q_GPR1_EXC_MON_SLVE BIT(22)
106#define IMX6Q_GPR1_MIPI_IPU2_SEL_MASK BIT(21)
107#define IMX6Q_GPR1_MIPI_IPU2_SEL_GASKET 0x0
108#define IMX6Q_GPR1_MIPI_IPU2_SEL_IOMUX BIT(21)
109#define IMX6Q_GPR1_MIPI_IPU1_MUX_MASK BIT(20)
110#define IMX6Q_GPR1_MIPI_IPU1_MUX_GASKET 0x0
111#define IMX6Q_GPR1_MIPI_IPU1_MUX_IOMUX BIT(20)
112#define IMX6Q_GPR1_MIPI_IPU2_MUX_MASK BIT(19)
113#define IMX6Q_GPR1_MIPI_IPU2_MUX_GASKET 0x0
114#define IMX6Q_GPR1_MIPI_IPU2_MUX_IOMUX BIT(19)
115#define IMX6Q_GPR1_PCIE_TEST_PD BIT(18)
116#define IMX6Q_GPR1_IPU_VPU_MUX_MASK BIT(17)
117#define IMX6Q_GPR1_IPU_VPU_MUX_IPU1 0x0
118#define IMX6Q_GPR1_IPU_VPU_MUX_IPU2 BIT(17)
119#define IMX6Q_GPR1_PCIE_REF_CLK_EN BIT(16)
120#define IMX6Q_GPR1_USB_EXP_MODE BIT(15)
121#define IMX6Q_GPR1_PCIE_INT BIT(14)
122#define IMX6Q_GPR1_USB_OTG_ID_SEL_MASK BIT(13)
123#define IMX6Q_GPR1_USB_OTG_ID_SEL_ENET_RX_ER 0x0
124#define IMX6Q_GPR1_USB_OTG_ID_SEL_GPIO_1 BIT(13)
125#define IMX6Q_GPR1_GINT BIT(12)
126#define IMX6Q_GPR1_ADDRS3_MASK (0x3 << 10)
127#define IMX6Q_GPR1_ADDRS3_32MB (0x0 << 10)
128#define IMX6Q_GPR1_ADDRS3_64MB (0x1 << 10)
129#define IMX6Q_GPR1_ADDRS3_128MB (0x2 << 10)
130#define IMX6Q_GPR1_ACT_CS3 BIT(9)
131#define IMX6Q_GPR1_ADDRS2_MASK (0x3 << 7)
132#define IMX6Q_GPR1_ACT_CS2 BIT(6)
133#define IMX6Q_GPR1_ADDRS1_MASK (0x3 << 4)
134#define IMX6Q_GPR1_ACT_CS1 BIT(3)
135#define IMX6Q_GPR1_ADDRS0_MASK (0x3 << 1)
136#define IMX6Q_GPR1_ACT_CS0 BIT(0)
137
138#define IMX6Q_GPR2_COUNTER_RESET_VAL_MASK (0x3 << 20)
139#define IMX6Q_GPR2_COUNTER_RESET_VAL_5 (0x0 << 20)
140#define IMX6Q_GPR2_COUNTER_RESET_VAL_3 (0x1 << 20)
141#define IMX6Q_GPR2_COUNTER_RESET_VAL_4 (0x2 << 20)
142#define IMX6Q_GPR2_COUNTER_RESET_VAL_6 (0x3 << 20)
143#define IMX6Q_GPR2_LVDS_CLK_SHIFT_MASK (0x7 << 16)
144#define IMX6Q_GPR2_LVDS_CLK_SHIFT_0 (0x0 << 16)
145#define IMX6Q_GPR2_LVDS_CLK_SHIFT_1 (0x1 << 16)
146#define IMX6Q_GPR2_LVDS_CLK_SHIFT_2 (0x2 << 16)
147#define IMX6Q_GPR2_LVDS_CLK_SHIFT_3 (0x3 << 16)
148#define IMX6Q_GPR2_LVDS_CLK_SHIFT_4 (0x4 << 16)
149#define IMX6Q_GPR2_LVDS_CLK_SHIFT_5 (0x5 << 16)
150#define IMX6Q_GPR2_LVDS_CLK_SHIFT_6 (0x6 << 16)
151#define IMX6Q_GPR2_LVDS_CLK_SHIFT_7 (0x7 << 16)
152#define IMX6Q_GPR2_BGREF_RRMODE_MASK BIT(15)
153#define IMX6Q_GPR2_BGREF_RRMODE_EXT_RESISTOR 0x0
154#define IMX6Q_GPR2_BGREF_RRMODE_INT_RESISTOR BIT(15)
155#define IMX6Q_GPR2_DI1_VS_POLARITY_MASK BIT(10)
156#define IMX6Q_GPR2_DI1_VS_POLARITY_ACTIVE_H 0x0
157#define IMX6Q_GPR2_DI1_VS_POLARITY_ACTIVE_L BIT(10)
158#define IMX6Q_GPR2_DI0_VS_POLARITY_MASK BIT(9)
159#define IMX6Q_GPR2_DI0_VS_POLARITY_ACTIVE_H 0x0
160#define IMX6Q_GPR2_DI0_VS_POLARITY_ACTIVE_L BIT(9)
161#define IMX6Q_GPR2_BIT_MAPPING_CH1_MASK BIT(8)
162#define IMX6Q_GPR2_BIT_MAPPING_CH1_SPWG 0x0
163#define IMX6Q_GPR2_BIT_MAPPING_CH1_JEIDA BIT(8)
164#define IMX6Q_GPR2_DATA_WIDTH_CH1_MASK BIT(7)
165#define IMX6Q_GPR2_DATA_WIDTH_CH1_18BIT 0x0
166#define IMX6Q_GPR2_DATA_WIDTH_CH1_24BIT BIT(7)
167#define IMX6Q_GPR2_BIT_MAPPING_CH0_MASK BIT(6)
168#define IMX6Q_GPR2_BIT_MAPPING_CH0_SPWG 0x0
169#define IMX6Q_GPR2_BIT_MAPPING_CH0_JEIDA BIT(6)
170#define IMX6Q_GPR2_DATA_WIDTH_CH0_MASK BIT(5)
171#define IMX6Q_GPR2_DATA_WIDTH_CH0_18BIT 0x0
172#define IMX6Q_GPR2_DATA_WIDTH_CH0_24BIT BIT(5)
173#define IMX6Q_GPR2_SPLIT_MODE_EN BIT(4)
174#define IMX6Q_GPR2_CH1_MODE_MASK (0x3 << 2)
175#define IMX6Q_GPR2_CH1_MODE_DISABLE (0x0 << 2)
176#define IMX6Q_GPR2_CH1_MODE_EN_ROUTE_DI0 (0x1 << 2)
177#define IMX6Q_GPR2_CH1_MODE_EN_ROUTE_DI1 (0x3 << 2)
178#define IMX6Q_GPR2_CH0_MODE_MASK (0x3 << 0)
179#define IMX6Q_GPR2_CH0_MODE_DISABLE (0x0 << 0)
180#define IMX6Q_GPR2_CH0_MODE_EN_ROUTE_DI0 (0x1 << 0)
181#define IMX6Q_GPR2_CH0_MODE_EN_ROUTE_DI1 (0x3 << 0)
182
183#define IMX6Q_GPR3_GPU_DBG_MASK (0x3 << 29)
184#define IMX6Q_GPR3_GPU_DBG_GPU3D (0x0 << 29)
185#define IMX6Q_GPR3_GPU_DBG_GPU2D (0x1 << 29)
186#define IMX6Q_GPR3_GPU_DBG_OPENVG (0x2 << 29)
187#define IMX6Q_GPR3_BCH_WR_CACHE_CTL BIT(28)
188#define IMX6Q_GPR3_BCH_RD_CACHE_CTL BIT(27)
189#define IMX6Q_GPR3_USDHCX_WR_CACHE_CTL BIT(26)
190#define IMX6Q_GPR3_USDHCX_RD_CACHE_CTL BIT(25)
191#define IMX6Q_GPR3_OCRAM_CTL_MASK (0xf << 21)
192#define IMX6Q_GPR3_OCRAM_STATUS_MASK (0xf << 17)
193#define IMX6Q_GPR3_CORE3_DBG_ACK_EN BIT(16)
194#define IMX6Q_GPR3_CORE2_DBG_ACK_EN BIT(15)
195#define IMX6Q_GPR3_CORE1_DBG_ACK_EN BIT(14)
196#define IMX6Q_GPR3_CORE0_DBG_ACK_EN BIT(13)
197#define IMX6Q_GPR3_TZASC2_BOOT_LOCK BIT(12)
198#define IMX6Q_GPR3_TZASC1_BOOT_LOCK BIT(11)
199#define IMX6Q_GPR3_IPU_DIAG_MASK BIT(10)
200#define IMX6Q_GPR3_LVDS1_MUX_CTL_MASK (0x3 << 8)
201#define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU1_DI0 (0x0 << 8)
202#define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU1_DI1 (0x1 << 8)
203#define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU2_DI0 (0x2 << 8)
204#define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU2_DI1 (0x3 << 8)
205#define IMX6Q_GPR3_LVDS0_MUX_CTL_MASK (0x3 << 6)
206#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU1_DI0 (0x0 << 6)
207#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU1_DI1 (0x1 << 6)
208#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI0 (0x2 << 6)
209#define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI1 (0x3 << 6)
210#define IMX6Q_GPR3_MIPI_MUX_CTL_MASK (0x3 << 4)
211#define IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI0 (0x0 << 4)
212#define IMX6Q_GPR3_MIPI_MUX_CTL_IPU1_DI1 (0x1 << 4)
213#define IMX6Q_GPR3_MIPI_MUX_CTL_IPU2_DI0 (0x2 << 4)
214#define IMX6Q_GPR3_MIPI_MUX_CTL_IPU2_DI1 (0x3 << 4)
215#define IMX6Q_GPR3_HDMI_MUX_CTL_MASK (0x3 << 2)
216#define IMX6Q_GPR3_HDMI_MUX_CTL_IPU1_DI0 (0x0 << 2)
217#define IMX6Q_GPR3_HDMI_MUX_CTL_IPU1_DI1 (0x1 << 2)
218#define IMX6Q_GPR3_HDMI_MUX_CTL_IPU2_DI0 (0x2 << 2)
219#define IMX6Q_GPR3_HDMI_MUX_CTL_IPU2_DI1 (0x3 << 2)
220
221#define IMX6Q_GPR4_VDOA_WR_CACHE_SEL BIT(31)
222#define IMX6Q_GPR4_VDOA_RD_CACHE_SEL BIT(30)
223#define IMX6Q_GPR4_VDOA_WR_CACHE_VAL BIT(29)
224#define IMX6Q_GPR4_VDOA_RD_CACHE_VAL BIT(28)
225#define IMX6Q_GPR4_PCIE_WR_CACHE_SEL BIT(27)
226#define IMX6Q_GPR4_PCIE_RD_CACHE_SEL BIT(26)
227#define IMX6Q_GPR4_PCIE_WR_CACHE_VAL BIT(25)
228#define IMX6Q_GPR4_PCIE_RD_CACHE_VAL BIT(24)
229#define IMX6Q_GPR4_SDMA_STOP_ACK BIT(19)
230#define IMX6Q_GPR4_CAN2_STOP_ACK BIT(18)
231#define IMX6Q_GPR4_CAN1_STOP_ACK BIT(17)
232#define IMX6Q_GPR4_ENET_STOP_ACK BIT(16)
233#define IMX6Q_GPR4_SOC_VERSION_MASK (0xff << 8)
234#define IMX6Q_GPR4_SOC_VERSION_OFF 0x8
235#define IMX6Q_GPR4_VPU_WR_CACHE_SEL BIT(7)
236#define IMX6Q_GPR4_VPU_RD_CACHE_SEL BIT(6)
237#define IMX6Q_GPR4_VPU_P_WR_CACHE_VAL BIT(3)
238#define IMX6Q_GPR4_VPU_P_RD_CACHE_VAL_MASK BIT(2)
239#define IMX6Q_GPR4_IPU_WR_CACHE_CTL BIT(1)
240#define IMX6Q_GPR4_IPU_RD_CACHE_CTL BIT(0)
241
242#define IMX6Q_GPR5_L2_CLK_STOP BIT(8)
243
244#define IMX6Q_GPR9_TZASC2_BYP BIT(1)
245#define IMX6Q_GPR9_TZASC1_BYP BIT(0)
246
247#define IMX6Q_GPR10_LOCK_DBG_EN BIT(29)
248#define IMX6Q_GPR10_LOCK_DBG_CLK_EN BIT(28)
249#define IMX6Q_GPR10_LOCK_SEC_ERR_RESP BIT(27)
250#define IMX6Q_GPR10_LOCK_OCRAM_TZ_ADDR (0x3f << 21)
251#define IMX6Q_GPR10_LOCK_OCRAM_TZ_EN BIT(20)
252#define IMX6Q_GPR10_LOCK_DCIC2_MUX_MASK (0x3 << 18)
253#define IMX6Q_GPR10_LOCK_DCIC1_MUX_MASK (0x3 << 16)
254#define IMX6Q_GPR10_DBG_EN BIT(13)
255#define IMX6Q_GPR10_DBG_CLK_EN BIT(12)
256#define IMX6Q_GPR10_SEC_ERR_RESP_MASK BIT(11)
257#define IMX6Q_GPR10_SEC_ERR_RESP_OKEY 0x0
258#define IMX6Q_GPR10_SEC_ERR_RESP_SLVE BIT(11)
259#define IMX6Q_GPR10_OCRAM_TZ_ADDR_MASK (0x3f << 5)
260#define IMX6Q_GPR10_OCRAM_TZ_EN_MASK BIT(4)
261#define IMX6Q_GPR10_DCIC2_MUX_CTL_MASK (0x3 << 2)
262#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU1_DI0 (0x0 << 2)
263#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU1_DI1 (0x1 << 2)
264#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU2_DI0 (0x2 << 2)
265#define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU2_DI1 (0x3 << 2)
266#define IMX6Q_GPR10_DCIC1_MUX_CTL_MASK (0x3 << 0)
267#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU1_DI0 (0x0 << 0)
268#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU1_DI1 (0x1 << 0)
269#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU2_DI0 (0x2 << 0)
270#define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU2_DI1 (0x3 << 0)
271
272#define IMX6Q_GPR12_ARMP_IPG_CLK_EN BIT(27)
273#define IMX6Q_GPR12_ARMP_AHB_CLK_EN BIT(26)
274#define IMX6Q_GPR12_ARMP_ATB_CLK_EN BIT(25)
275#define IMX6Q_GPR12_ARMP_APB_CLK_EN BIT(24)
276#define IMX6Q_GPR12_PCIE_CTL_2 BIT(10)
277
278#define IMX6Q_GPR13_SDMA_STOP_REQ BIT(30)
279#define IMX6Q_GPR13_CAN2_STOP_REQ BIT(29)
280#define IMX6Q_GPR13_CAN1_STOP_REQ BIT(28)
281#define IMX6Q_GPR13_ENET_STOP_REQ BIT(27)
282#define IMX6Q_GPR13_SATA_PHY_8_MASK (0x7 << 24)
283#define IMX6Q_GPR13_SATA_PHY_8_0_5_DB (0x0 << 24)
284#define IMX6Q_GPR13_SATA_PHY_8_1_0_DB (0x1 << 24)
285#define IMX6Q_GPR13_SATA_PHY_8_1_5_DB (0x2 << 24)
286#define IMX6Q_GPR13_SATA_PHY_8_2_0_DB (0x3 << 24)
287#define IMX6Q_GPR13_SATA_PHY_8_2_5_DB (0x4 << 24)
288#define IMX6Q_GPR13_SATA_PHY_8_3_0_DB (0x5 << 24)
289#define IMX6Q_GPR13_SATA_PHY_8_3_5_DB (0x6 << 24)
290#define IMX6Q_GPR13_SATA_PHY_8_4_0_DB (0x7 << 24)
291#define IMX6Q_GPR13_SATA_PHY_7_MASK (0x1f << 19)
292#define IMX6Q_GPR13_SATA_PHY_7_SATA1I (0x10 << 19)
293#define IMX6Q_GPR13_SATA_PHY_7_SATA1M (0x10 << 19)
294#define IMX6Q_GPR13_SATA_PHY_7_SATA1X (0x1a << 19)
295#define IMX6Q_GPR13_SATA_PHY_7_SATA2I (0x12 << 19)
296#define IMX6Q_GPR13_SATA_PHY_7_SATA2M (0x12 << 19)
297#define IMX6Q_GPR13_SATA_PHY_7_SATA2X (0x1a << 19)
298#define IMX6Q_GPR13_SATA_PHY_6_MASK (0x7 << 16)
299#define IMX6Q_GPR13_SATA_SPEED_MASK BIT(15)
300#define IMX6Q_GPR13_SATA_SPEED_1P5G 0x0
301#define IMX6Q_GPR13_SATA_SPEED_3P0G BIT(15)
302#define IMX6Q_GPR13_SATA_PHY_5 BIT(14)
303#define IMX6Q_GPR13_SATA_PHY_4_MASK (0x7 << 11)
304#define IMX6Q_GPR13_SATA_PHY_4_16_16 (0x0 << 11)
305#define IMX6Q_GPR13_SATA_PHY_4_14_16 (0x1 << 11)
306#define IMX6Q_GPR13_SATA_PHY_4_12_16 (0x2 << 11)
307#define IMX6Q_GPR13_SATA_PHY_4_10_16 (0x3 << 11)
308#define IMX6Q_GPR13_SATA_PHY_4_9_16 (0x4 << 11)
309#define IMX6Q_GPR13_SATA_PHY_4_8_16 (0x5 << 11)
310#define IMX6Q_GPR13_SATA_PHY_3_MASK (0xf << 7)
311#define IMX6Q_GPR13_SATA_PHY_3_OFF 0x7
312#define IMX6Q_GPR13_SATA_PHY_2_MASK (0x1f << 2)
313#define IMX6Q_GPR13_SATA_PHY_2_OFF 0x2
314#define IMX6Q_GPR13_SATA_PHY_1_MASK (0x3 << 0)
315#define IMX6Q_GPR13_SATA_PHY_1_FAST (0x0 << 0)
316#define IMX6Q_GPR13_SATA_PHY_1_MED (0x1 << 0)
317#define IMX6Q_GPR13_SATA_PHY_1_SLOW (0x2 << 0)
318
319#endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */
diff --git a/include/linux/mfd/tc3589x.h b/include/linux/mfd/tc3589x.h
index 3acb3a8e3af5..6b8e1ff4672b 100644
--- a/include/linux/mfd/tc3589x.h
+++ b/include/linux/mfd/tc3589x.h
@@ -117,6 +117,7 @@ struct tc3589x {
117 struct mutex lock; 117 struct mutex lock;
118 struct device *dev; 118 struct device *dev;
119 struct i2c_client *i2c; 119 struct i2c_client *i2c;
120 struct irq_domain *domain;
120 121
121 int irq_base; 122 int irq_base;
122 int num_gpio; 123 int num_gpio;
diff --git a/include/linux/mfd/tps65217.h b/include/linux/mfd/tps65217.h
index 7cd83d826ed8..290762f93930 100644
--- a/include/linux/mfd/tps65217.h
+++ b/include/linux/mfd/tps65217.h
@@ -213,6 +213,23 @@ enum tps65217_regulator_id {
213/* Number of total regulators available */ 213/* Number of total regulators available */
214#define TPS65217_NUM_REGULATOR (TPS65217_NUM_DCDC + TPS65217_NUM_LDO) 214#define TPS65217_NUM_REGULATOR (TPS65217_NUM_DCDC + TPS65217_NUM_LDO)
215 215
216enum tps65217_bl_isel {
217 TPS65217_BL_ISET1 = 1,
218 TPS65217_BL_ISET2,
219};
220
221enum tps65217_bl_fdim {
222 TPS65217_BL_FDIM_100HZ,
223 TPS65217_BL_FDIM_200HZ,
224 TPS65217_BL_FDIM_500HZ,
225 TPS65217_BL_FDIM_1000HZ,
226};
227
228struct tps65217_bl_pdata {
229 enum tps65217_bl_isel isel;
230 enum tps65217_bl_fdim fdim;
231};
232
216/** 233/**
217 * struct tps65217_board - packages regulator init data 234 * struct tps65217_board - packages regulator init data
218 * @tps65217_regulator_data: regulator initialization values 235 * @tps65217_regulator_data: regulator initialization values
@@ -222,6 +239,7 @@ enum tps65217_regulator_id {
222struct tps65217_board { 239struct tps65217_board {
223 struct regulator_init_data *tps65217_init_data[TPS65217_NUM_REGULATOR]; 240 struct regulator_init_data *tps65217_init_data[TPS65217_NUM_REGULATOR];
224 struct device_node *of_node[TPS65217_NUM_REGULATOR]; 241 struct device_node *of_node[TPS65217_NUM_REGULATOR];
242 struct tps65217_bl_pdata *bl_pdata;
225}; 243};
226 244
227/** 245/**
diff --git a/include/linux/mfd/tps6586x.h b/include/linux/mfd/tps6586x.h
index 94514710a03f..2dd123194958 100644
--- a/include/linux/mfd/tps6586x.h
+++ b/include/linux/mfd/tps6586x.h
@@ -78,6 +78,7 @@ struct tps6586x_platform_data {
78 78
79 int gpio_base; 79 int gpio_base;
80 int irq_base; 80 int irq_base;
81 bool pm_off;
81}; 82};
82 83
83/* 84/*
diff --git a/include/linux/mfd/tps65910.h b/include/linux/mfd/tps65910.h
index 9bf8767818b4..ac772b36a1b1 100644
--- a/include/linux/mfd/tps65910.h
+++ b/include/linux/mfd/tps65910.h
@@ -366,6 +366,8 @@
366 366
367 367
368/*Register DEVCTRL (0x80) register.RegisterDescription */ 368/*Register DEVCTRL (0x80) register.RegisterDescription */
369#define DEVCTRL_PWR_OFF_MASK 0x80
370#define DEVCTRL_PWR_OFF_SHIFT 7
369#define DEVCTRL_RTC_PWDN_MASK 0x40 371#define DEVCTRL_RTC_PWDN_MASK 0x40
370#define DEVCTRL_RTC_PWDN_SHIFT 6 372#define DEVCTRL_RTC_PWDN_SHIFT 6
371#define DEVCTRL_CK32K_CTRL_MASK 0x20 373#define DEVCTRL_CK32K_CTRL_MASK 0x20
@@ -809,6 +811,7 @@ struct tps65910_board {
809 int vmbch2_threshold; 811 int vmbch2_threshold;
810 bool en_ck32k_xtal; 812 bool en_ck32k_xtal;
811 bool en_dev_slp; 813 bool en_dev_slp;
814 bool pm_off;
812 struct tps65910_sleep_keepon_data *slp_keepon; 815 struct tps65910_sleep_keepon_data *slp_keepon;
813 bool en_gpio_sleep[TPS6591X_MAX_NUM_GPIO]; 816 bool en_gpio_sleep[TPS6591X_MAX_NUM_GPIO];
814 unsigned long regulator_ext_sleep_control[TPS65910_NUM_REGS]; 817 unsigned long regulator_ext_sleep_control[TPS65910_NUM_REGS];
diff --git a/include/linux/mfd/twl6040.h b/include/linux/mfd/twl6040.h
index ba43d4806b83..a8eff4ad9be5 100644
--- a/include/linux/mfd/twl6040.h
+++ b/include/linux/mfd/twl6040.h
@@ -143,7 +143,7 @@
143 143
144#define TWL6040_GPO1 0x01 144#define TWL6040_GPO1 0x01
145#define TWL6040_GPO2 0x02 145#define TWL6040_GPO2 0x02
146#define TWL6040_GPO3 0x03 146#define TWL6040_GPO3 0x04
147 147
148/* ACCCTL (0x2D) fields */ 148/* ACCCTL (0x2D) fields */
149 149
@@ -158,7 +158,7 @@
158#define TWL6040_VIBROCDET 0x20 158#define TWL6040_VIBROCDET 0x20
159#define TWL6040_TSHUTDET 0x40 159#define TWL6040_TSHUTDET 0x40
160 160
161#define TWL6040_CELLS 2 161#define TWL6040_CELLS 3
162 162
163#define TWL6040_REV_ES1_0 0x00 163#define TWL6040_REV_ES1_0 0x00
164#define TWL6040_REV_ES1_1 0x01 /* Rev ES1.1 and ES1.2 */ 164#define TWL6040_REV_ES1_1 0x01 /* Rev ES1.1 and ES1.2 */
@@ -176,6 +176,8 @@
176#define TWL6040_SYSCLK_SEL_LPPLL 0 176#define TWL6040_SYSCLK_SEL_LPPLL 0
177#define TWL6040_SYSCLK_SEL_HPPLL 1 177#define TWL6040_SYSCLK_SEL_HPPLL 1
178 178
179#define TWL6040_GPO_MAX 3
180
179struct twl6040_codec_data { 181struct twl6040_codec_data {
180 u16 hs_left_step; 182 u16 hs_left_step;
181 u16 hs_right_step; 183 u16 hs_right_step;
@@ -192,11 +194,16 @@ struct twl6040_vibra_data {
192 int vddvibr_uV; /* VDDVIBR volt, set 0 for fixed reg */ 194 int vddvibr_uV; /* VDDVIBR volt, set 0 for fixed reg */
193}; 195};
194 196
197struct twl6040_gpo_data {
198 int gpio_base;
199};
200
195struct twl6040_platform_data { 201struct twl6040_platform_data {
196 int audpwron_gpio; /* audio power-on gpio */ 202 int audpwron_gpio; /* audio power-on gpio */
197 203
198 struct twl6040_codec_data *codec; 204 struct twl6040_codec_data *codec;
199 struct twl6040_vibra_data *vibra; 205 struct twl6040_vibra_data *vibra;
206 struct twl6040_gpo_data *gpo;
200}; 207};
201 208
202struct regmap; 209struct regmap;
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 15:18:19 -0500