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-rw-r--r--include/linux/mfd/88pm860x.h7
-rw-r--r--include/linux/mfd/ab4500.h262
-rw-r--r--include/linux/mfd/ab8500.h134
-rw-r--r--include/linux/mfd/abx500.h (renamed from include/linux/mfd/ab3100.h)134
-rw-r--r--include/linux/mfd/davinci_voicecodec.h126
-rw-r--r--include/linux/mfd/janz.h54
-rw-r--r--include/linux/mfd/max8998-private.h112
-rw-r--r--include/linux/mfd/max8998.h78
-rw-r--r--include/linux/mfd/mc13783-private.h220
-rw-r--r--include/linux/mfd/mc13783.h68
-rw-r--r--include/linux/mfd/pcf50633/backlight.h51
-rw-r--r--include/linux/mfd/pcf50633/core.h4
-rw-r--r--include/linux/mfd/rdc321x.h26
-rw-r--r--include/linux/mfd/sh_mobile_sdhi.h6
-rw-r--r--include/linux/mfd/stmpe.h201
-rw-r--r--include/linux/mfd/tc35892.h132
-rw-r--r--include/linux/mfd/tmio.h11
-rw-r--r--include/linux/mfd/tps6507x.h169
-rw-r--r--include/linux/mfd/tps6586x.h47
-rw-r--r--include/linux/mfd/wm831x/core.h5
-rw-r--r--include/linux/mfd/wm8350/audio.h2
-rw-r--r--include/linux/mfd/wm8994/core.h53
-rw-r--r--include/linux/mfd/wm8994/gpio.h4
-rw-r--r--include/linux/mfd/wm8994/pdata.h1
24 files changed, 1404 insertions, 503 deletions
diff --git a/include/linux/mfd/88pm860x.h b/include/linux/mfd/88pm860x.h
index 73f92c5feea2..bfd23bef7363 100644
--- a/include/linux/mfd/88pm860x.h
+++ b/include/linux/mfd/88pm860x.h
@@ -132,6 +132,7 @@ enum {
132 PM8607_ID_LDO9, 132 PM8607_ID_LDO9,
133 PM8607_ID_LDO10, 133 PM8607_ID_LDO10,
134 PM8607_ID_LDO12, 134 PM8607_ID_LDO12,
135 PM8607_ID_LDO13,
135 PM8607_ID_LDO14, 136 PM8607_ID_LDO14,
136 137
137 PM8607_ID_RG_MAX, 138 PM8607_ID_RG_MAX,
@@ -309,7 +310,7 @@ struct pm860x_chip {
309 310
310}; 311};
311 312
312#define PM8607_MAX_REGULATOR 15 /* 3 Bucks, 12 LDOs */ 313#define PM8607_MAX_REGULATOR PM8607_ID_RG_MAX /* 3 Bucks, 13 LDOs */
313 314
314enum { 315enum {
315 GI2C_PORT = 0, 316 GI2C_PORT = 0,
@@ -369,7 +370,7 @@ extern int pm860x_set_bits(struct i2c_client *, int, unsigned char,
369 unsigned char); 370 unsigned char);
370 371
371extern int pm860x_device_init(struct pm860x_chip *chip, 372extern int pm860x_device_init(struct pm860x_chip *chip,
372 struct pm860x_platform_data *pdata); 373 struct pm860x_platform_data *pdata) __devinit ;
373extern void pm860x_device_exit(struct pm860x_chip *chip); 374extern void pm860x_device_exit(struct pm860x_chip *chip) __devexit ;
374 375
375#endif /* __LINUX_MFD_88PM860X_H */ 376#endif /* __LINUX_MFD_88PM860X_H */
diff --git a/include/linux/mfd/ab4500.h b/include/linux/mfd/ab4500.h
deleted file mode 100644
index a42a7033ae53..000000000000
--- a/include/linux/mfd/ab4500.h
+++ /dev/null
@@ -1,262 +0,0 @@
1/*
2 * Copyright (C) 2009 ST-Ericsson
3 *
4 * Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2, as
8 * published by the Free Software Foundation.
9 *
10 * AB4500 device core funtions, for client access
11 */
12#ifndef MFD_AB4500_H
13#define MFD_AB4500_H
14
15#include <linux/device.h>
16
17/*
18 * AB4500 bank addresses
19 */
20#define AB4500_SYS_CTRL1_BLOCK 0x1
21#define AB4500_SYS_CTRL2_BLOCK 0x2
22#define AB4500_REGU_CTRL1 0x3
23#define AB4500_REGU_CTRL2 0x4
24#define AB4500_USB 0x5
25#define AB4500_TVOUT 0x6
26#define AB4500_DBI 0x7
27#define AB4500_ECI_AV_ACC 0x8
28#define AB4500_RESERVED 0x9
29#define AB4500_GPADC 0xA
30#define AB4500_CHARGER 0xB
31#define AB4500_GAS_GAUGE 0xC
32#define AB4500_AUDIO 0xD
33#define AB4500_INTERRUPT 0xE
34#define AB4500_RTC 0xF
35#define AB4500_MISC 0x10
36#define AB4500_DEBUG 0x12
37#define AB4500_PROD_TEST 0x13
38#define AB4500_OTP_EMUL 0x15
39
40/*
41 * System control 1 register offsets.
42 * Bank = 0x01
43 */
44#define AB4500_TURNON_STAT_REG 0x0100
45#define AB4500_RESET_STAT_REG 0x0101
46#define AB4500_PONKEY1_PRESS_STAT_REG 0x0102
47
48#define AB4500_FSM_STAT1_REG 0x0140
49#define AB4500_FSM_STAT2_REG 0x0141
50#define AB4500_SYSCLK_REQ_STAT_REG 0x0142
51#define AB4500_USB_STAT1_REG 0x0143
52#define AB4500_USB_STAT2_REG 0x0144
53#define AB4500_STATUS_SPARE1_REG 0x0145
54#define AB4500_STATUS_SPARE2_REG 0x0146
55
56#define AB4500_CTRL1_REG 0x0180
57#define AB4500_CTRL2_REG 0x0181
58
59/*
60 * System control 2 register offsets.
61 * bank = 0x02
62 */
63#define AB4500_CTRL3_REG 0x0200
64#define AB4500_MAIN_WDOG_CTRL_REG 0x0201
65#define AB4500_MAIN_WDOG_TIMER_REG 0x0202
66#define AB4500_LOW_BAT_REG 0x0203
67#define AB4500_BATT_OK_REG 0x0204
68#define AB4500_SYSCLK_TIMER_REG 0x0205
69#define AB4500_SMPSCLK_CTRL_REG 0x0206
70#define AB4500_SMPSCLK_SEL1_REG 0x0207
71#define AB4500_SMPSCLK_SEL2_REG 0x0208
72#define AB4500_SMPSCLK_SEL3_REG 0x0209
73#define AB4500_SYSULPCLK_CONF_REG 0x020A
74#define AB4500_SYSULPCLK_CTRL1_REG 0x020B
75#define AB4500_SYSCLK_CTRL_REG 0x020C
76#define AB4500_SYSCLK_REQ1_VALID_REG 0x020D
77#define AB4500_SYSCLK_REQ_VALID_REG 0x020E
78#define AB4500_SYSCTRL_SPARE_REG 0x020F
79#define AB4500_PAD_CONF_REG 0x0210
80
81/*
82 * Regu control1 register offsets
83 * Bank = 0x03
84 */
85#define AB4500_REGU_SERIAL_CTRL1_REG 0x0300
86#define AB4500_REGU_SERIAL_CTRL2_REG 0x0301
87#define AB4500_REGU_SERIAL_CTRL3_REG 0x0302
88#define AB4500_REGU_REQ_CTRL1_REG 0x0303
89#define AB4500_REGU_REQ_CTRL2_REG 0x0304
90#define AB4500_REGU_REQ_CTRL3_REG 0x0305
91#define AB4500_REGU_REQ_CTRL4_REG 0x0306
92#define AB4500_REGU_MISC1_REG 0x0380
93#define AB4500_REGU_OTGSUPPLY_CTRL_REG 0x0381
94#define AB4500_REGU_VUSB_CTRL_REG 0x0382
95#define AB4500_REGU_VAUDIO_SUPPLY_REG 0x0383
96#define AB4500_REGU_CTRL1_SPARE_REG 0x0384
97
98/*
99 * Regu control2 Vmod register offsets
100 */
101#define AB4500_REGU_VMOD_REGU_REG 0x0440
102#define AB4500_REGU_VMOD_SEL1_REG 0x0441
103#define AB4500_REGU_VMOD_SEL2_REG 0x0442
104#define AB4500_REGU_CTRL_DISCH_REG 0x0443
105#define AB4500_REGU_CTRL_DISCH2_REG 0x0444
106
107/*
108 * USB/ULPI register offsets
109 * Bank : 0x5
110 */
111#define AB4500_USB_LINE_STAT_REG 0x0580
112#define AB4500_USB_LINE_CTRL1_REG 0x0581
113#define AB4500_USB_LINE_CTRL2_REG 0x0582
114#define AB4500_USB_LINE_CTRL3_REG 0x0583
115#define AB4500_USB_LINE_CTRL4_REG 0x0584
116#define AB4500_USB_LINE_CTRL5_REG 0x0585
117#define AB4500_USB_OTG_CTRL_REG 0x0587
118#define AB4500_USB_OTG_STAT_REG 0x0588
119#define AB4500_USB_OTG_STAT_REG 0x0588
120#define AB4500_USB_CTRL_SPARE_REG 0x0589
121#define AB4500_USB_PHY_CTRL_REG 0x058A
122
123/*
124 * TVOUT / CTRL register offsets
125 * Bank : 0x06
126 */
127#define AB4500_TVOUT_CTRL_REG 0x0680
128
129/*
130 * DBI register offsets
131 * Bank : 0x07
132 */
133#define AB4500_DBI_REG1_REG 0x0700
134#define AB4500_DBI_REG2_REG 0x0701
135
136/*
137 * ECI regsiter offsets
138 * Bank : 0x08
139 */
140#define AB4500_ECI_CTRL_REG 0x0800
141#define AB4500_ECI_HOOKLEVEL_REG 0x0801
142#define AB4500_ECI_DATAOUT_REG 0x0802
143#define AB4500_ECI_DATAIN_REG 0x0803
144
145/*
146 * AV Connector register offsets
147 * Bank : 0x08
148 */
149#define AB4500_AV_CONN_REG 0x0840
150
151/*
152 * Accessory detection register offsets
153 * Bank : 0x08
154 */
155#define AB4500_ACC_DET_DB1_REG 0x0880
156#define AB4500_ACC_DET_DB2_REG 0x0881
157
158/*
159 * GPADC register offsets
160 * Bank : 0x0A
161 */
162#define AB4500_GPADC_CTRL1_REG 0x0A00
163#define AB4500_GPADC_CTRL2_REG 0x0A01
164#define AB4500_GPADC_CTRL3_REG 0x0A02
165#define AB4500_GPADC_AUTO_TIMER_REG 0x0A03
166#define AB4500_GPADC_STAT_REG 0x0A04
167#define AB4500_GPADC_MANDATAL_REG 0x0A05
168#define AB4500_GPADC_MANDATAH_REG 0x0A06
169#define AB4500_GPADC_AUTODATAL_REG 0x0A07
170#define AB4500_GPADC_AUTODATAH_REG 0x0A08
171#define AB4500_GPADC_MUX_CTRL_REG 0x0A09
172
173/*
174 * Charger / status register offfsets
175 * Bank : 0x0B
176 */
177#define AB4500_CH_STATUS1_REG 0x0B00
178#define AB4500_CH_STATUS2_REG 0x0B01
179#define AB4500_CH_USBCH_STAT1_REG 0x0B02
180#define AB4500_CH_USBCH_STAT2_REG 0x0B03
181#define AB4500_CH_FSM_STAT_REG 0x0B04
182#define AB4500_CH_STAT_REG 0x0B05
183
184/*
185 * Charger / control register offfsets
186 * Bank : 0x0B
187 */
188#define AB4500_CH_VOLT_LVL_REG 0x0B40
189
190/*
191 * Charger / main control register offfsets
192 * Bank : 0x0B
193 */
194#define AB4500_MCH_CTRL1 0x0B80
195#define AB4500_MCH_CTRL2 0x0B81
196#define AB4500_MCH_IPT_CURLVL_REG 0x0B82
197#define AB4500_CH_WD_REG 0x0B83
198
199/*
200 * Charger / USB control register offsets
201 * Bank : 0x0B
202 */
203#define AB4500_USBCH_CTRL1_REG 0x0BC0
204#define AB4500_USBCH_CTRL2_REG 0x0BC1
205#define AB4500_USBCH_IPT_CRNTLVL_REG 0x0BC2
206
207/*
208 * RTC bank register offsets
209 * Bank : 0xF
210 */
211#define AB4500_RTC_SOFF_STAT_REG 0x0F00
212#define AB4500_RTC_CC_CONF_REG 0x0F01
213#define AB4500_RTC_READ_REQ_REG 0x0F02
214#define AB4500_RTC_WATCH_TSECMID_REG 0x0F03
215#define AB4500_RTC_WATCH_TSECHI_REG 0x0F04
216#define AB4500_RTC_WATCH_TMIN_LOW_REG 0x0F05
217#define AB4500_RTC_WATCH_TMIN_MID_REG 0x0F06
218#define AB4500_RTC_WATCH_TMIN_HI_REG 0x0F07
219#define AB4500_RTC_ALRM_MIN_LOW_REG 0x0F08
220#define AB4500_RTC_ALRM_MIN_MID_REG 0x0F09
221#define AB4500_RTC_ALRM_MIN_HI_REG 0x0F0A
222#define AB4500_RTC_STAT_REG 0x0F0B
223#define AB4500_RTC_BKUP_CHG_REG 0x0F0C
224#define AB4500_RTC_FORCE_BKUP_REG 0x0F0D
225#define AB4500_RTC_CALIB_REG 0x0F0E
226#define AB4500_RTC_SWITCH_STAT_REG 0x0F0F
227
228/*
229 * PWM Out generators
230 * Bank: 0x10
231 */
232#define AB4500_PWM_OUT_CTRL1_REG 0x1060
233#define AB4500_PWM_OUT_CTRL2_REG 0x1061
234#define AB4500_PWM_OUT_CTRL3_REG 0x1062
235#define AB4500_PWM_OUT_CTRL4_REG 0x1063
236#define AB4500_PWM_OUT_CTRL5_REG 0x1064
237#define AB4500_PWM_OUT_CTRL6_REG 0x1065
238#define AB4500_PWM_OUT_CTRL7_REG 0x1066
239
240#define AB4500_I2C_PAD_CTRL_REG 0x1067
241#define AB4500_REV_REG 0x1080
242
243/**
244 * struct ab4500
245 * @spi: spi device structure
246 * @tx_buf: transmit buffer
247 * @rx_buf: receive buffer
248 * @lock: sync primitive
249 */
250struct ab4500 {
251 struct spi_device *spi;
252 unsigned long tx_buf[4];
253 unsigned long rx_buf[4];
254 struct mutex lock;
255};
256
257int ab4500_write(struct ab4500 *ab4500, unsigned char block,
258 unsigned long addr, unsigned char data);
259int ab4500_read(struct ab4500 *ab4500, unsigned char block,
260 unsigned long addr);
261
262#endif /* MFD_AB4500_H */
diff --git a/include/linux/mfd/ab8500.h b/include/linux/mfd/ab8500.h
new file mode 100644
index 000000000000..f5cec4500f38
--- /dev/null
+++ b/include/linux/mfd/ab8500.h
@@ -0,0 +1,134 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License v2
5 * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
6 */
7#ifndef MFD_AB8500_H
8#define MFD_AB8500_H
9
10#include <linux/device.h>
11
12/*
13 * Interrupts
14 */
15
16#define AB8500_INT_MAIN_EXT_CH_NOT_OK 0
17#define AB8500_INT_UN_PLUG_TV_DET 1
18#define AB8500_INT_PLUG_TV_DET 2
19#define AB8500_INT_TEMP_WARM 3
20#define AB8500_INT_PON_KEY2DB_F 4
21#define AB8500_INT_PON_KEY2DB_R 5
22#define AB8500_INT_PON_KEY1DB_F 6
23#define AB8500_INT_PON_KEY1DB_R 7
24#define AB8500_INT_BATT_OVV 8
25#define AB8500_INT_MAIN_CH_UNPLUG_DET 10
26#define AB8500_INT_MAIN_CH_PLUG_DET 11
27#define AB8500_INT_USB_ID_DET_F 12
28#define AB8500_INT_USB_ID_DET_R 13
29#define AB8500_INT_VBUS_DET_F 14
30#define AB8500_INT_VBUS_DET_R 15
31#define AB8500_INT_VBUS_CH_DROP_END 16
32#define AB8500_INT_RTC_60S 17
33#define AB8500_INT_RTC_ALARM 18
34#define AB8500_INT_BAT_CTRL_INDB 20
35#define AB8500_INT_CH_WD_EXP 21
36#define AB8500_INT_VBUS_OVV 22
37#define AB8500_INT_MAIN_CH_DROP_END 23
38#define AB8500_INT_CCN_CONV_ACC 24
39#define AB8500_INT_INT_AUD 25
40#define AB8500_INT_CCEOC 26
41#define AB8500_INT_CC_INT_CALIB 27
42#define AB8500_INT_LOW_BAT_F 28
43#define AB8500_INT_LOW_BAT_R 29
44#define AB8500_INT_BUP_CHG_NOT_OK 30
45#define AB8500_INT_BUP_CHG_OK 31
46#define AB8500_INT_GP_HW_ADC_CONV_END 32
47#define AB8500_INT_ACC_DETECT_1DB_F 33
48#define AB8500_INT_ACC_DETECT_1DB_R 34
49#define AB8500_INT_ACC_DETECT_22DB_F 35
50#define AB8500_INT_ACC_DETECT_22DB_R 36
51#define AB8500_INT_ACC_DETECT_21DB_F 37
52#define AB8500_INT_ACC_DETECT_21DB_R 38
53#define AB8500_INT_GP_SW_ADC_CONV_END 39
54#define AB8500_INT_BTEMP_LOW 72
55#define AB8500_INT_BTEMP_LOW_MEDIUM 73
56#define AB8500_INT_BTEMP_MEDIUM_HIGH 74
57#define AB8500_INT_BTEMP_HIGH 75
58#define AB8500_INT_USB_CHARGER_NOT_OK 81
59#define AB8500_INT_ID_WAKEUP_R 82
60#define AB8500_INT_ID_DET_R1R 84
61#define AB8500_INT_ID_DET_R2R 85
62#define AB8500_INT_ID_DET_R3R 86
63#define AB8500_INT_ID_DET_R4R 87
64#define AB8500_INT_ID_WAKEUP_F 88
65#define AB8500_INT_ID_DET_R1F 90
66#define AB8500_INT_ID_DET_R2F 91
67#define AB8500_INT_ID_DET_R3F 92
68#define AB8500_INT_ID_DET_R4F 93
69#define AB8500_INT_USB_CHG_DET_DONE 94
70#define AB8500_INT_USB_CH_TH_PROT_F 96
71#define AB8500_INT_USB_CH_TH_PROP_R 97
72#define AB8500_INT_MAIN_CH_TH_PROP_F 98
73#define AB8500_INT_MAIN_CH_TH_PROT_R 99
74#define AB8500_INT_USB_CHARGER_NOT_OKF 103
75
76#define AB8500_NR_IRQS 104
77#define AB8500_NUM_IRQ_REGS 13
78
79#define AB8500_NUM_REGULATORS 15
80
81/**
82 * struct ab8500 - ab8500 internal structure
83 * @dev: parent device
84 * @lock: read/write operations lock
85 * @irq_lock: genirq bus lock
86 * @revision: chip revision
87 * @irq: irq line
88 * @write: register write
89 * @read: register read
90 * @rx_buf: rx buf for SPI
91 * @tx_buf: tx buf for SPI
92 * @mask: cache of IRQ regs for bus lock
93 * @oldmask: cache of previous IRQ regs for bus lock
94 */
95struct ab8500 {
96 struct device *dev;
97 struct mutex lock;
98 struct mutex irq_lock;
99 int revision;
100 int irq_base;
101 int irq;
102
103 int (*write) (struct ab8500 *a8500, u16 addr, u8 data);
104 int (*read) (struct ab8500 *a8500, u16 addr);
105
106 unsigned long tx_buf[4];
107 unsigned long rx_buf[4];
108
109 u8 mask[AB8500_NUM_IRQ_REGS];
110 u8 oldmask[AB8500_NUM_IRQ_REGS];
111};
112
113struct regulator_init_data;
114
115/**
116 * struct ab8500_platform_data - AB8500 platform data
117 * @irq_base: start of AB8500 IRQs, AB8500_NR_IRQS will be used
118 * @init: board-specific initialization after detection of ab8500
119 * @regulator: machine-specific constraints for regulators
120 */
121struct ab8500_platform_data {
122 int irq_base;
123 void (*init) (struct ab8500 *);
124 struct regulator_init_data *regulator[AB8500_NUM_REGULATORS];
125};
126
127extern int ab8500_write(struct ab8500 *a8500, u16 addr, u8 data);
128extern int ab8500_read(struct ab8500 *a8500, u16 addr);
129extern int ab8500_set_bits(struct ab8500 *a8500, u16 addr, u8 mask, u8 data);
130
131extern int __devinit ab8500_init(struct ab8500 *ab8500);
132extern int __devexit ab8500_exit(struct ab8500 *ab8500);
133
134#endif /* MFD_AB8500_H */
diff --git a/include/linux/mfd/ab3100.h b/include/linux/mfd/abx500.h
index 9a881c305a50..390726fcbcb1 100644
--- a/include/linux/mfd/ab3100.h
+++ b/include/linux/mfd/abx500.h
@@ -3,17 +3,37 @@
3 * License terms: GNU General Public License (GPL) version 2 3 * License terms: GNU General Public License (GPL) version 2
4 * AB3100 core access functions 4 * AB3100 core access functions
5 * Author: Linus Walleij <linus.walleij@stericsson.com> 5 * Author: Linus Walleij <linus.walleij@stericsson.com>
6 *
7 * ABX500 core access functions.
8 * The abx500 interface is used for the Analog Baseband chip
9 * ab3100, ab3550, ab5500 and possibly comming. It is not used for
10 * ab4500 and ab8500 since they are another family of chip.
11 *
12 * Author: Mattias Wallin <mattias.wallin@stericsson.com>
13 * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
14 * Author: Bengt Jonsson <bengt.g.jonsson@stericsson.com>
15 * Author: Rickard Andersson <rickard.andersson@stericsson.com>
6 */ 16 */
7 17
8#include <linux/device.h> 18#include <linux/device.h>
9#include <linux/regulator/machine.h> 19#include <linux/regulator/machine.h>
10 20
11#ifndef MFD_AB3100_H 21#ifndef MFD_ABX500_H
12#define MFD_AB3100_H 22#define MFD_ABX500_H
13 23
14#define ABUNKNOWN 0 24#define AB3100_P1A 0xc0
15#define AB3000 1 25#define AB3100_P1B 0xc1
16#define AB3100 2 26#define AB3100_P1C 0xc2
27#define AB3100_P1D 0xc3
28#define AB3100_P1E 0xc4
29#define AB3100_P1F 0xc5
30#define AB3100_P1G 0xc6
31#define AB3100_R2A 0xc7
32#define AB3100_R2B 0xc8
33#define AB3550_P1A 0x10
34#define AB5500_1_0 0x20
35#define AB5500_2_0 0x21
36#define AB5500_2_1 0x22
17 37
18/* 38/*
19 * AB3100, EVENTA1, A2 and A3 event register flags 39 * AB3100, EVENTA1, A2 and A3 event register flags
@@ -89,7 +109,7 @@ struct ab3100 {
89 char chip_name[32]; 109 char chip_name[32];
90 u8 chip_id; 110 u8 chip_id;
91 struct blocking_notifier_head event_subscribers; 111 struct blocking_notifier_head event_subscribers;
92 u32 startup_events; 112 u8 startup_events[3];
93 bool startup_events_read; 113 bool startup_events_read;
94}; 114};
95 115
@@ -112,18 +132,102 @@ struct ab3100_platform_data {
112 int external_voltage; 132 int external_voltage;
113}; 133};
114 134
115int ab3100_set_register_interruptible(struct ab3100 *ab3100, u8 reg, u8 regval);
116int ab3100_get_register_interruptible(struct ab3100 *ab3100, u8 reg, u8 *regval);
117int ab3100_get_register_page_interruptible(struct ab3100 *ab3100,
118 u8 first_reg, u8 *regvals, u8 numregs);
119int ab3100_mask_and_set_register_interruptible(struct ab3100 *ab3100,
120 u8 reg, u8 andmask, u8 ormask);
121u8 ab3100_get_chip_type(struct ab3100 *ab3100);
122int ab3100_event_register(struct ab3100 *ab3100, 135int ab3100_event_register(struct ab3100 *ab3100,
123 struct notifier_block *nb); 136 struct notifier_block *nb);
124int ab3100_event_unregister(struct ab3100 *ab3100, 137int ab3100_event_unregister(struct ab3100 *ab3100,
125 struct notifier_block *nb); 138 struct notifier_block *nb);
126int ab3100_event_registers_startup_state_get(struct ab3100 *ab3100,
127 u32 *fatevent);
128 139
140/* AB3550, STR register flags */
141#define AB3550_STR_ONSWA (0x01)
142#define AB3550_STR_ONSWB (0x02)
143#define AB3550_STR_ONSWC (0x04)
144#define AB3550_STR_DCIO (0x08)
145#define AB3550_STR_BOOT_MODE (0x10)
146#define AB3550_STR_SIM_OFF (0x20)
147#define AB3550_STR_BATT_REMOVAL (0x40)
148#define AB3550_STR_VBUS (0x80)
149
150/* Interrupt mask registers */
151#define AB3550_IMR1 0x29
152#define AB3550_IMR2 0x2a
153#define AB3550_IMR3 0x2b
154#define AB3550_IMR4 0x2c
155#define AB3550_IMR5 0x2d
156
157enum ab3550_devid {
158 AB3550_DEVID_ADC,
159 AB3550_DEVID_DAC,
160 AB3550_DEVID_LEDS,
161 AB3550_DEVID_POWER,
162 AB3550_DEVID_REGULATORS,
163 AB3550_DEVID_SIM,
164 AB3550_DEVID_UART,
165 AB3550_DEVID_RTC,
166 AB3550_DEVID_CHARGER,
167 AB3550_DEVID_FUELGAUGE,
168 AB3550_DEVID_VIBRATOR,
169 AB3550_DEVID_CODEC,
170 AB3550_NUM_DEVICES,
171};
172
173/**
174 * struct abx500_init_setting
175 * Initial value of the registers for driver to use during setup.
176 */
177struct abx500_init_settings {
178 u8 bank;
179 u8 reg;
180 u8 setting;
181};
182
183/**
184 * struct ab3550_platform_data
185 * Data supplied to initialize board connections to the AB3550
186 */
187struct ab3550_platform_data {
188 struct {unsigned int base; unsigned int count; } irq;
189 void *dev_data[AB3550_NUM_DEVICES];
190 size_t dev_data_sz[AB3550_NUM_DEVICES];
191 struct abx500_init_settings *init_settings;
192 unsigned int init_settings_sz;
193};
194
195int abx500_set_register_interruptible(struct device *dev, u8 bank, u8 reg,
196 u8 value);
197int abx500_get_register_interruptible(struct device *dev, u8 bank, u8 reg,
198 u8 *value);
199int abx500_get_register_page_interruptible(struct device *dev, u8 bank,
200 u8 first_reg, u8 *regvals, u8 numregs);
201int abx500_set_register_page_interruptible(struct device *dev, u8 bank,
202 u8 first_reg, u8 *regvals, u8 numregs);
203/**
204 * abx500_mask_and_set_register_inerruptible() - Modifies selected bits of a
205 * target register
206 *
207 * @dev: The AB sub device.
208 * @bank: The i2c bank number.
209 * @bitmask: The bit mask to use.
210 * @bitvalues: The new bit values.
211 *
212 * Updates the value of an AB register:
213 * value -> ((value & ~bitmask) | (bitvalues & bitmask))
214 */
215int abx500_mask_and_set_register_interruptible(struct device *dev, u8 bank,
216 u8 reg, u8 bitmask, u8 bitvalues);
217int abx500_get_chip_id(struct device *dev);
218int abx500_event_registers_startup_state_get(struct device *dev, u8 *event);
219int abx500_startup_irq_enabled(struct device *dev, unsigned int irq);
220
221struct abx500_ops {
222 int (*get_chip_id) (struct device *);
223 int (*get_register) (struct device *, u8, u8, u8 *);
224 int (*set_register) (struct device *, u8, u8, u8);
225 int (*get_register_page) (struct device *, u8, u8, u8 *, u8);
226 int (*set_register_page) (struct device *, u8, u8, u8 *, u8);
227 int (*mask_and_set_register) (struct device *, u8, u8, u8, u8);
228 int (*event_registers_startup_state_get) (struct device *, u8 *);
229 int (*startup_irq_enabled) (struct device *, unsigned int);
230};
231
232int abx500_register_ops(struct device *core_dev, struct abx500_ops *ops);
129#endif 233#endif
diff --git a/include/linux/mfd/davinci_voicecodec.h b/include/linux/mfd/davinci_voicecodec.h
new file mode 100644
index 000000000000..0ab61320ffa8
--- /dev/null
+++ b/include/linux/mfd/davinci_voicecodec.h
@@ -0,0 +1,126 @@
1/*
2 * DaVinci Voice Codec Core Interface for TI platforms
3 *
4 * Copyright (C) 2010 Texas Instruments, Inc
5 *
6 * Author: Miguel Aguilar <miguel.aguilar@ridgerun.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#ifndef __LINUX_MFD_DAVINCI_VOICECODEC_H_
24#define __LINUX_MFD_DAVINIC_VOICECODEC_H_
25
26#include <linux/kernel.h>
27#include <linux/platform_device.h>
28#include <linux/mfd/core.h>
29
30#include <mach/edma.h>
31
32/*
33 * Register values.
34 */
35#define DAVINCI_VC_PID 0x00
36#define DAVINCI_VC_CTRL 0x04
37#define DAVINCI_VC_INTEN 0x08
38#define DAVINCI_VC_INTSTATUS 0x0c
39#define DAVINCI_VC_INTCLR 0x10
40#define DAVINCI_VC_EMUL_CTRL 0x14
41#define DAVINCI_VC_RFIFO 0x20
42#define DAVINCI_VC_WFIFO 0x24
43#define DAVINCI_VC_FIFOSTAT 0x28
44#define DAVINCI_VC_TST_CTRL 0x2C
45#define DAVINCI_VC_REG05 0x94
46#define DAVINCI_VC_REG09 0xA4
47#define DAVINCI_VC_REG12 0xB0
48
49/* DAVINCI_VC_CTRL bit fields */
50#define DAVINCI_VC_CTRL_MASK 0x5500
51#define DAVINCI_VC_CTRL_RSTADC BIT(0)
52#define DAVINCI_VC_CTRL_RSTDAC BIT(1)
53#define DAVINCI_VC_CTRL_RD_BITS_8 BIT(4)
54#define DAVINCI_VC_CTRL_RD_UNSIGNED BIT(5)
55#define DAVINCI_VC_CTRL_WD_BITS_8 BIT(6)
56#define DAVINCI_VC_CTRL_WD_UNSIGNED BIT(7)
57#define DAVINCI_VC_CTRL_RFIFOEN BIT(8)
58#define DAVINCI_VC_CTRL_RFIFOCL BIT(9)
59#define DAVINCI_VC_CTRL_RFIFOMD_WORD_1 BIT(10)
60#define DAVINCI_VC_CTRL_WFIFOEN BIT(12)
61#define DAVINCI_VC_CTRL_WFIFOCL BIT(13)
62#define DAVINCI_VC_CTRL_WFIFOMD_WORD_1 BIT(14)
63
64/* DAVINCI_VC_INT bit fields */
65#define DAVINCI_VC_INT_MASK 0x3F
66#define DAVINCI_VC_INT_RDRDY_MASK BIT(0)
67#define DAVINCI_VC_INT_RERROVF_MASK BIT(1)
68#define DAVINCI_VC_INT_RERRUDR_MASK BIT(2)
69#define DAVINCI_VC_INT_WDREQ_MASK BIT(3)
70#define DAVINCI_VC_INT_WERROVF_MASKBIT BIT(4)
71#define DAVINCI_VC_INT_WERRUDR_MASK BIT(5)
72
73/* DAVINCI_VC_REG05 bit fields */
74#define DAVINCI_VC_REG05_PGA_GAIN 0x07
75
76/* DAVINCI_VC_REG09 bit fields */
77#define DAVINCI_VC_REG09_MUTE 0x40
78#define DAVINCI_VC_REG09_DIG_ATTEN 0x3F
79
80/* DAVINCI_VC_REG12 bit fields */
81#define DAVINCI_VC_REG12_POWER_ALL_ON 0xFD
82#define DAVINCI_VC_REG12_POWER_ALL_OFF 0x00
83
84#define DAVINCI_VC_CELLS 2
85
86enum davinci_vc_cells {
87 DAVINCI_VC_VCIF_CELL,
88 DAVINCI_VC_CQ93VC_CELL,
89};
90
91struct davinci_vcif {
92 struct platform_device *pdev;
93 u32 dma_tx_channel;
94 u32 dma_rx_channel;
95 dma_addr_t dma_tx_addr;
96 dma_addr_t dma_rx_addr;
97};
98
99struct cq93vc {
100 struct platform_device *pdev;
101 struct snd_soc_codec *codec;
102 u32 sysclk;
103};
104
105struct davinci_vc;
106
107struct davinci_vc {
108 /* Device data */
109 struct device *dev;
110 struct platform_device *pdev;
111 struct clk *clk;
112
113 /* Memory resources */
114 void __iomem *base;
115 resource_size_t pbase;
116 size_t base_size;
117
118 /* MFD cells */
119 struct mfd_cell cells[DAVINCI_VC_CELLS];
120
121 /* Client devices */
122 struct davinci_vcif davinci_vcif;
123 struct cq93vc cq93vc;
124};
125
126#endif
diff --git a/include/linux/mfd/janz.h b/include/linux/mfd/janz.h
new file mode 100644
index 000000000000..e9994c469803
--- /dev/null
+++ b/include/linux/mfd/janz.h
@@ -0,0 +1,54 @@
1/*
2 * Common Definitions for Janz MODULbus devices
3 *
4 * Copyright (c) 2010 Ira W. Snyder <iws@ovro.caltech.edu>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12#ifndef JANZ_H
13#define JANZ_H
14
15struct janz_platform_data {
16 /* MODULbus Module Number */
17 unsigned int modno;
18};
19
20/* PLX bridge chip onboard registers */
21struct janz_cmodio_onboard_regs {
22 u8 unused1;
23
24 /*
25 * Read access: interrupt status
26 * Write access: interrupt disable
27 */
28 u8 int_disable;
29 u8 unused2;
30
31 /*
32 * Read access: MODULbus number (hex switch)
33 * Write access: interrupt enable
34 */
35 u8 int_enable;
36 u8 unused3;
37
38 /* write-only */
39 u8 reset_assert;
40 u8 unused4;
41
42 /* write-only */
43 u8 reset_deassert;
44 u8 unused5;
45
46 /* read-write access to serial EEPROM */
47 u8 eep;
48 u8 unused6;
49
50 /* write-only access to EEPROM chip select */
51 u8 enid;
52};
53
54#endif /* JANZ_H */
diff --git a/include/linux/mfd/max8998-private.h b/include/linux/mfd/max8998-private.h
new file mode 100644
index 000000000000..6dc75b3e2d33
--- /dev/null
+++ b/include/linux/mfd/max8998-private.h
@@ -0,0 +1,112 @@
1/*
2 * max8698.h - Voltage regulator driver for the Maxim 8998
3 *
4 * Copyright (C) 2009-2010 Samsung Electrnoics
5 * Kyungmin Park <kyungmin.park@samsung.com>
6 * Marek Szyprowski <m.szyprowski@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#ifndef __LINUX_MFD_MAX8998_PRIV_H
24#define __LINUX_MFD_MAX8998_PRIV_H
25
26/* MAX 8998 registers */
27enum {
28 MAX8998_REG_IRQ1,
29 MAX8998_REG_IRQ2,
30 MAX8998_REG_IRQ3,
31 MAX8998_REG_IRQ4,
32 MAX8998_REG_IRQM1,
33 MAX8998_REG_IRQM2,
34 MAX8998_REG_IRQM3,
35 MAX8998_REG_IRQM4,
36 MAX8998_REG_STATUS1,
37 MAX8998_REG_STATUS2,
38 MAX8998_REG_STATUSM1,
39 MAX8998_REG_STATUSM2,
40 MAX8998_REG_CHGR1,
41 MAX8998_REG_CHGR2,
42 MAX8998_REG_LDO_ACTIVE_DISCHARGE1,
43 MAX8998_REG_LDO_ACTIVE_DISCHARGE2,
44 MAX8998_REG_BUCK_ACTIVE_DISCHARGE3,
45 MAX8998_REG_ONOFF1,
46 MAX8998_REG_ONOFF2,
47 MAX8998_REG_ONOFF3,
48 MAX8998_REG_ONOFF4,
49 MAX8998_REG_BUCK1_DVSARM1,
50 MAX8998_REG_BUCK1_DVSARM2,
51 MAX8998_REG_BUCK1_DVSARM3,
52 MAX8998_REG_BUCK1_DVSARM4,
53 MAX8998_REG_BUCK2_DVSINT1,
54 MAX8998_REG_BUCK2_DVSINT2,
55 MAX8998_REG_BUCK3,
56 MAX8998_REG_BUCK4,
57 MAX8998_REG_LDO2_LDO3,
58 MAX8998_REG_LDO4,
59 MAX8998_REG_LDO5,
60 MAX8998_REG_LDO6,
61 MAX8998_REG_LDO7,
62 MAX8998_REG_LDO8_LDO9,
63 MAX8998_REG_LDO10_LDO11,
64 MAX8998_REG_LDO12,
65 MAX8998_REG_LDO13,
66 MAX8998_REG_LDO14,
67 MAX8998_REG_LDO15,
68 MAX8998_REG_LDO16,
69 MAX8998_REG_LDO17,
70 MAX8998_REG_BKCHR,
71 MAX8998_REG_LBCNFG1,
72 MAX8998_REG_LBCNFG2,
73};
74
75/**
76 * struct max8998_dev - max8998 master device for sub-drivers
77 * @dev: master device of the chip (can be used to access platform data)
78 * @i2c_client: i2c client private data
79 * @dev_read(): chip register read function
80 * @dev_write(): chip register write function
81 * @dev_update(): chip register update function
82 * @iolock: mutex for serializing io access
83 */
84
85struct max8998_dev {
86 struct device *dev;
87 struct i2c_client *i2c_client;
88 int (*dev_read)(struct max8998_dev *max8998, u8 reg, u8 *dest);
89 int (*dev_write)(struct max8998_dev *max8998, u8 reg, u8 val);
90 int (*dev_update)(struct max8998_dev *max8998, u8 reg, u8 val, u8 mask);
91 struct mutex iolock;
92};
93
94static inline int max8998_read_reg(struct max8998_dev *max8998, u8 reg,
95 u8 *value)
96{
97 return max8998->dev_read(max8998, reg, value);
98}
99
100static inline int max8998_write_reg(struct max8998_dev *max8998, u8 reg,
101 u8 value)
102{
103 return max8998->dev_write(max8998, reg, value);
104}
105
106static inline int max8998_update_reg(struct max8998_dev *max8998, u8 reg,
107 u8 value, u8 mask)
108{
109 return max8998->dev_update(max8998, reg, value, mask);
110}
111
112#endif /* __LINUX_MFD_MAX8998_PRIV_H */
diff --git a/include/linux/mfd/max8998.h b/include/linux/mfd/max8998.h
new file mode 100644
index 000000000000..1d3601a2d853
--- /dev/null
+++ b/include/linux/mfd/max8998.h
@@ -0,0 +1,78 @@
1/*
2 * max8698.h - Voltage regulator driver for the Maxim 8998
3 *
4 * Copyright (C) 2009-2010 Samsung Electrnoics
5 * Kyungmin Park <kyungmin.park@samsung.com>
6 * Marek Szyprowski <m.szyprowski@samsung.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#ifndef __LINUX_MFD_MAX8998_H
24#define __LINUX_MFD_MAX8998_H
25
26#include <linux/regulator/machine.h>
27
28/* MAX 8998 regulator ids */
29enum {
30 MAX8998_LDO2 = 2,
31 MAX8998_LDO3,
32 MAX8998_LDO4,
33 MAX8998_LDO5,
34 MAX8998_LDO6,
35 MAX8998_LDO7,
36 MAX8998_LDO8,
37 MAX8998_LDO9,
38 MAX8998_LDO10,
39 MAX8998_LDO11,
40 MAX8998_LDO12,
41 MAX8998_LDO13,
42 MAX8998_LDO14,
43 MAX8998_LDO15,
44 MAX8998_LDO16,
45 MAX8998_LDO17,
46 MAX8998_BUCK1,
47 MAX8998_BUCK2,
48 MAX8998_BUCK3,
49 MAX8998_BUCK4,
50 MAX8998_EN32KHZ_AP,
51 MAX8998_EN32KHZ_CP,
52 MAX8998_ENVICHG,
53 MAX8998_ESAFEOUT1,
54 MAX8998_ESAFEOUT2,
55};
56
57/**
58 * max8998_regulator_data - regulator data
59 * @id: regulator id
60 * @initdata: regulator init data (contraints, supplies, ...)
61 */
62struct max8998_regulator_data {
63 int id;
64 struct regulator_init_data *initdata;
65};
66
67/**
68 * struct max8998_board - packages regulator init data
69 * @num_regulators: number of regultors used
70 * @regulators: array of defined regulators
71 */
72
73struct max8998_platform_data {
74 int num_regulators;
75 struct max8998_regulator_data *regulators;
76};
77
78#endif /* __LINUX_MFD_MAX8998_H */
diff --git a/include/linux/mfd/mc13783-private.h b/include/linux/mfd/mc13783-private.h
deleted file mode 100644
index 95cf9360553f..000000000000
--- a/include/linux/mfd/mc13783-private.h
+++ /dev/null
@@ -1,220 +0,0 @@
1/*
2 * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
3 *
4 * Initial development of this code was funded by
5 * Phytec Messtechnik GmbH, http://www.phytec.de
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */
21
22#ifndef __LINUX_MFD_MC13783_PRIV_H
23#define __LINUX_MFD_MC13783_PRIV_H
24
25#include <linux/platform_device.h>
26#include <linux/mfd/mc13783.h>
27#include <linux/mutex.h>
28#include <linux/interrupt.h>
29
30struct mc13783 {
31 struct spi_device *spidev;
32 struct mutex lock;
33 int irq;
34 int flags;
35
36 irq_handler_t irqhandler[MC13783_NUM_IRQ];
37 void *irqdata[MC13783_NUM_IRQ];
38
39 /* XXX these should go as platformdata to the regulator subdevice */
40 struct mc13783_regulator_init_data *regulators;
41 int num_regulators;
42};
43
44#define MC13783_REG_INTERRUPT_STATUS_0 0
45#define MC13783_REG_INTERRUPT_MASK_0 1
46#define MC13783_REG_INTERRUPT_SENSE_0 2
47#define MC13783_REG_INTERRUPT_STATUS_1 3
48#define MC13783_REG_INTERRUPT_MASK_1 4
49#define MC13783_REG_INTERRUPT_SENSE_1 5
50#define MC13783_REG_POWER_UP_MODE_SENSE 6
51#define MC13783_REG_REVISION 7
52#define MC13783_REG_SEMAPHORE 8
53#define MC13783_REG_ARBITRATION_PERIPHERAL_AUDIO 9
54#define MC13783_REG_ARBITRATION_SWITCHERS 10
55#define MC13783_REG_ARBITRATION_REGULATORS_0 11
56#define MC13783_REG_ARBITRATION_REGULATORS_1 12
57#define MC13783_REG_POWER_CONTROL_0 13
58#define MC13783_REG_POWER_CONTROL_1 14
59#define MC13783_REG_POWER_CONTROL_2 15
60#define MC13783_REG_REGEN_ASSIGNMENT 16
61#define MC13783_REG_CONTROL_SPARE 17
62#define MC13783_REG_MEMORY_A 18
63#define MC13783_REG_MEMORY_B 19
64#define MC13783_REG_RTC_TIME 20
65#define MC13783_REG_RTC_ALARM 21
66#define MC13783_REG_RTC_DAY 22
67#define MC13783_REG_RTC_DAY_ALARM 23
68#define MC13783_REG_SWITCHERS_0 24
69#define MC13783_REG_SWITCHERS_1 25
70#define MC13783_REG_SWITCHERS_2 26
71#define MC13783_REG_SWITCHERS_3 27
72#define MC13783_REG_SWITCHERS_4 28
73#define MC13783_REG_SWITCHERS_5 29
74#define MC13783_REG_REGULATOR_SETTING_0 30
75#define MC13783_REG_REGULATOR_SETTING_1 31
76#define MC13783_REG_REGULATOR_MODE_0 32
77#define MC13783_REG_REGULATOR_MODE_1 33
78#define MC13783_REG_POWER_MISCELLANEOUS 34
79#define MC13783_REG_POWER_SPARE 35
80#define MC13783_REG_AUDIO_RX_0 36
81#define MC13783_REG_AUDIO_RX_1 37
82#define MC13783_REG_AUDIO_TX 38
83#define MC13783_REG_AUDIO_SSI_NETWORK 39
84#define MC13783_REG_AUDIO_CODEC 40
85#define MC13783_REG_AUDIO_STEREO_DAC 41
86#define MC13783_REG_AUDIO_SPARE 42
87#define MC13783_REG_ADC_0 43
88#define MC13783_REG_ADC_1 44
89#define MC13783_REG_ADC_2 45
90#define MC13783_REG_ADC_3 46
91#define MC13783_REG_ADC_4 47
92#define MC13783_REG_CHARGER 48
93#define MC13783_REG_USB 49
94#define MC13783_REG_CHARGE_USB_SPARE 50
95#define MC13783_REG_LED_CONTROL_0 51
96#define MC13783_REG_LED_CONTROL_1 52
97#define MC13783_REG_LED_CONTROL_2 53
98#define MC13783_REG_LED_CONTROL_3 54
99#define MC13783_REG_LED_CONTROL_4 55
100#define MC13783_REG_LED_CONTROL_5 56
101#define MC13783_REG_SPARE 57
102#define MC13783_REG_TRIM_0 58
103#define MC13783_REG_TRIM_1 59
104#define MC13783_REG_TEST_0 60
105#define MC13783_REG_TEST_1 61
106#define MC13783_REG_TEST_2 62
107#define MC13783_REG_TEST_3 63
108#define MC13783_REG_NB 64
109
110/*
111 * Reg Regulator Mode 0
112 */
113#define MC13783_REGCTRL_VAUDIO_EN (1 << 0)
114#define MC13783_REGCTRL_VAUDIO_STBY (1 << 1)
115#define MC13783_REGCTRL_VAUDIO_MODE (1 << 2)
116#define MC13783_REGCTRL_VIOHI_EN (1 << 3)
117#define MC13783_REGCTRL_VIOHI_STBY (1 << 4)
118#define MC13783_REGCTRL_VIOHI_MODE (1 << 5)
119#define MC13783_REGCTRL_VIOLO_EN (1 << 6)
120#define MC13783_REGCTRL_VIOLO_STBY (1 << 7)
121#define MC13783_REGCTRL_VIOLO_MODE (1 << 8)
122#define MC13783_REGCTRL_VDIG_EN (1 << 9)
123#define MC13783_REGCTRL_VDIG_STBY (1 << 10)
124#define MC13783_REGCTRL_VDIG_MODE (1 << 11)
125#define MC13783_REGCTRL_VGEN_EN (1 << 12)
126#define MC13783_REGCTRL_VGEN_STBY (1 << 13)
127#define MC13783_REGCTRL_VGEN_MODE (1 << 14)
128#define MC13783_REGCTRL_VRFDIG_EN (1 << 15)
129#define MC13783_REGCTRL_VRFDIG_STBY (1 << 16)
130#define MC13783_REGCTRL_VRFDIG_MODE (1 << 17)
131#define MC13783_REGCTRL_VRFREF_EN (1 << 18)
132#define MC13783_REGCTRL_VRFREF_STBY (1 << 19)
133#define MC13783_REGCTRL_VRFREF_MODE (1 << 20)
134#define MC13783_REGCTRL_VRFCP_EN (1 << 21)
135#define MC13783_REGCTRL_VRFCP_STBY (1 << 22)
136#define MC13783_REGCTRL_VRFCP_MODE (1 << 23)
137
138/*
139 * Reg Regulator Mode 1
140 */
141#define MC13783_REGCTRL_VSIM_EN (1 << 0)
142#define MC13783_REGCTRL_VSIM_STBY (1 << 1)
143#define MC13783_REGCTRL_VSIM_MODE (1 << 2)
144#define MC13783_REGCTRL_VESIM_EN (1 << 3)
145#define MC13783_REGCTRL_VESIM_STBY (1 << 4)
146#define MC13783_REGCTRL_VESIM_MODE (1 << 5)
147#define MC13783_REGCTRL_VCAM_EN (1 << 6)
148#define MC13783_REGCTRL_VCAM_STBY (1 << 7)
149#define MC13783_REGCTRL_VCAM_MODE (1 << 8)
150#define MC13783_REGCTRL_VRFBG_EN (1 << 9)
151#define MC13783_REGCTRL_VRFBG_STBY (1 << 10)
152#define MC13783_REGCTRL_VVIB_EN (1 << 11)
153#define MC13783_REGCTRL_VRF1_EN (1 << 12)
154#define MC13783_REGCTRL_VRF1_STBY (1 << 13)
155#define MC13783_REGCTRL_VRF1_MODE (1 << 14)
156#define MC13783_REGCTRL_VRF2_EN (1 << 15)
157#define MC13783_REGCTRL_VRF2_STBY (1 << 16)
158#define MC13783_REGCTRL_VRF2_MODE (1 << 17)
159#define MC13783_REGCTRL_VMMC1_EN (1 << 18)
160#define MC13783_REGCTRL_VMMC1_STBY (1 << 19)
161#define MC13783_REGCTRL_VMMC1_MODE (1 << 20)
162#define MC13783_REGCTRL_VMMC2_EN (1 << 21)
163#define MC13783_REGCTRL_VMMC2_STBY (1 << 22)
164#define MC13783_REGCTRL_VMMC2_MODE (1 << 23)
165
166/*
167 * Reg Regulator Misc.
168 */
169#define MC13783_REGCTRL_GPO1_EN (1 << 6)
170#define MC13783_REGCTRL_GPO2_EN (1 << 8)
171#define MC13783_REGCTRL_GPO3_EN (1 << 10)
172#define MC13783_REGCTRL_GPO4_EN (1 << 12)
173#define MC13783_REGCTRL_VIBPINCTRL (1 << 14)
174
175/*
176 * Reg Switcher 4
177 */
178#define MC13783_SWCTRL_SW1A_MODE (1 << 0)
179#define MC13783_SWCTRL_SW1A_STBY_MODE (1 << 2)
180#define MC13783_SWCTRL_SW1A_DVS_SPEED (1 << 6)
181#define MC13783_SWCTRL_SW1A_PANIC_MODE (1 << 8)
182#define MC13783_SWCTRL_SW1A_SOFTSTART (1 << 9)
183#define MC13783_SWCTRL_SW1B_MODE (1 << 10)
184#define MC13783_SWCTRL_SW1B_STBY_MODE (1 << 12)
185#define MC13783_SWCTRL_SW1B_DVS_SPEED (1 << 14)
186#define MC13783_SWCTRL_SW1B_PANIC_MODE (1 << 16)
187#define MC13783_SWCTRL_SW1B_SOFTSTART (1 << 17)
188#define MC13783_SWCTRL_PLL_EN (1 << 18)
189#define MC13783_SWCTRL_PLL_FACTOR (1 << 19)
190
191/*
192 * Reg Switcher 5
193 */
194#define MC13783_SWCTRL_SW2A_MODE (1 << 0)
195#define MC13783_SWCTRL_SW2A_STBY_MODE (1 << 2)
196#define MC13783_SWCTRL_SW2A_DVS_SPEED (1 << 6)
197#define MC13783_SWCTRL_SW2A_PANIC_MODE (1 << 8)
198#define MC13783_SWCTRL_SW2A_SOFTSTART (1 << 9)
199#define MC13783_SWCTRL_SW2B_MODE (1 << 10)
200#define MC13783_SWCTRL_SW2B_STBY_MODE (1 << 12)
201#define MC13783_SWCTRL_SW2B_DVS_SPEED (1 << 14)
202#define MC13783_SWCTRL_SW2B_PANIC_MODE (1 << 16)
203#define MC13783_SWCTRL_SW2B_SOFTSTART (1 << 17)
204#define MC13783_SWSET_SW3 (1 << 18)
205#define MC13783_SWCTRL_SW3_EN (1 << 20)
206#define MC13783_SWCTRL_SW3_STBY (1 << 21)
207#define MC13783_SWCTRL_SW3_MODE (1 << 22)
208
209static inline int mc13783_set_bits(struct mc13783 *mc13783, unsigned int offset,
210 u32 mask, u32 val)
211{
212 int ret;
213 mc13783_lock(mc13783);
214 ret = mc13783_reg_rmw(mc13783, offset, mask, val);
215 mc13783_unlock(mc13783);
216
217 return ret;
218}
219
220#endif /* __LINUX_MFD_MC13783_PRIV_H */
diff --git a/include/linux/mfd/mc13783.h b/include/linux/mfd/mc13783.h
index 8895d9d8879c..0fa44fb8dd26 100644
--- a/include/linux/mfd/mc13783.h
+++ b/include/linux/mfd/mc13783.h
@@ -21,6 +21,8 @@ int mc13783_reg_write(struct mc13783 *mc13783, unsigned int offset, u32 val);
21int mc13783_reg_rmw(struct mc13783 *mc13783, unsigned int offset, 21int mc13783_reg_rmw(struct mc13783 *mc13783, unsigned int offset,
22 u32 mask, u32 val); 22 u32 mask, u32 val);
23 23
24int mc13783_get_flags(struct mc13783 *mc13783);
25
24int mc13783_irq_request(struct mc13783 *mc13783, int irq, 26int mc13783_irq_request(struct mc13783 *mc13783, int irq,
25 irq_handler_t handler, const char *name, void *dev); 27 irq_handler_t handler, const char *name, void *dev);
26int mc13783_irq_request_nounmask(struct mc13783 *mc13783, int irq, 28int mc13783_irq_request_nounmask(struct mc13783 *mc13783, int irq,
@@ -64,6 +66,70 @@ static inline int mc13783_ackirq(struct mc13783 *mc13783, int irq)
64 MC13783_ADC0_TSMOD1 | \ 66 MC13783_ADC0_TSMOD1 | \
65 MC13783_ADC0_TSMOD2) 67 MC13783_ADC0_TSMOD2)
66 68
69struct mc13783_led_platform_data {
70#define MC13783_LED_MD 0
71#define MC13783_LED_AD 1
72#define MC13783_LED_KP 2
73#define MC13783_LED_R1 3
74#define MC13783_LED_G1 4
75#define MC13783_LED_B1 5
76#define MC13783_LED_R2 6
77#define MC13783_LED_G2 7
78#define MC13783_LED_B2 8
79#define MC13783_LED_R3 9
80#define MC13783_LED_G3 10
81#define MC13783_LED_B3 11
82#define MC13783_LED_MAX MC13783_LED_B3
83 int id;
84 const char *name;
85 const char *default_trigger;
86
87/* Three or two bits current selection depending on the led */
88 char max_current;
89};
90
91struct mc13783_leds_platform_data {
92 int num_leds;
93 struct mc13783_led_platform_data *led;
94
95#define MC13783_LED_TRIODE_MD (1 << 0)
96#define MC13783_LED_TRIODE_AD (1 << 1)
97#define MC13783_LED_TRIODE_KP (1 << 2)
98#define MC13783_LED_BOOST_EN (1 << 3)
99#define MC13783_LED_TC1HALF (1 << 4)
100#define MC13783_LED_SLEWLIMTC (1 << 5)
101#define MC13783_LED_SLEWLIMBL (1 << 6)
102#define MC13783_LED_TRIODE_TC1 (1 << 7)
103#define MC13783_LED_TRIODE_TC2 (1 << 8)
104#define MC13783_LED_TRIODE_TC3 (1 << 9)
105 int flags;
106
107#define MC13783_LED_AB_DISABLED 0
108#define MC13783_LED_AB_MD1 1
109#define MC13783_LED_AB_MD12 2
110#define MC13783_LED_AB_MD123 3
111#define MC13783_LED_AB_MD1234 4
112#define MC13783_LED_AB_MD1234_AD1 5
113#define MC13783_LED_AB_MD1234_AD12 6
114#define MC13783_LED_AB_MD1_AD 7
115 char abmode;
116
117#define MC13783_LED_ABREF_200MV 0
118#define MC13783_LED_ABREF_400MV 1
119#define MC13783_LED_ABREF_600MV 2
120#define MC13783_LED_ABREF_800MV 3
121 char abref;
122
123#define MC13783_LED_PERIOD_10MS 0
124#define MC13783_LED_PERIOD_100MS 1
125#define MC13783_LED_PERIOD_500MS 2
126#define MC13783_LED_PERIOD_2S 3
127 char bl_period;
128 char tc1_period;
129 char tc2_period;
130 char tc3_period;
131};
132
67/* to be cleaned up */ 133/* to be cleaned up */
68struct regulator_init_data; 134struct regulator_init_data;
69 135
@@ -80,12 +146,14 @@ struct mc13783_regulator_platform_data {
80struct mc13783_platform_data { 146struct mc13783_platform_data {
81 int num_regulators; 147 int num_regulators;
82 struct mc13783_regulator_init_data *regulators; 148 struct mc13783_regulator_init_data *regulators;
149 struct mc13783_leds_platform_data *leds;
83 150
84#define MC13783_USE_TOUCHSCREEN (1 << 0) 151#define MC13783_USE_TOUCHSCREEN (1 << 0)
85#define MC13783_USE_CODEC (1 << 1) 152#define MC13783_USE_CODEC (1 << 1)
86#define MC13783_USE_ADC (1 << 2) 153#define MC13783_USE_ADC (1 << 2)
87#define MC13783_USE_RTC (1 << 3) 154#define MC13783_USE_RTC (1 << 3)
88#define MC13783_USE_REGULATOR (1 << 4) 155#define MC13783_USE_REGULATOR (1 << 4)
156#define MC13783_USE_LED (1 << 5)
89 unsigned int flags; 157 unsigned int flags;
90}; 158};
91 159
diff --git a/include/linux/mfd/pcf50633/backlight.h b/include/linux/mfd/pcf50633/backlight.h
new file mode 100644
index 000000000000..83747e217b27
--- /dev/null
+++ b/include/linux/mfd/pcf50633/backlight.h
@@ -0,0 +1,51 @@
1/*
2 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
3 * PCF50633 backlight device driver
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#ifndef __LINUX_MFD_PCF50633_BACKLIGHT
17#define __LINUX_MFD_PCF50633_BACKLIGHT
18
19/*
20* @default_brightness: Backlight brightness is initialized to this value
21*
22* Brightness to be used after the driver has been probed.
23* Valid range 0-63.
24*
25* @default_brightness_limit: The actual brightness is limited by this value
26*
27* Brightness limit to be used after the driver has been probed. This is useful
28* when it is not known how much power is available for the backlight during
29* probe.
30* Valid range 0-63. Can be changed later with pcf50633_bl_set_brightness_limit.
31*
32* @ramp_time: Display ramp time when changing brightness
33*
34* When changing the backlights brightness the change is not instant, instead
35* it fades smooth from one state to another. This value specifies how long
36* the fade should take. The lower the value the higher the fade time.
37* Valid range 0-255
38*/
39struct pcf50633_bl_platform_data {
40 unsigned int default_brightness;
41 unsigned int default_brightness_limit;
42 uint8_t ramp_time;
43};
44
45
46struct pcf50633;
47
48int pcf50633_bl_set_brightness_limit(struct pcf50633 *pcf, unsigned int limit);
49
50#endif
51
diff --git a/include/linux/mfd/pcf50633/core.h b/include/linux/mfd/pcf50633/core.h
index 3398bd9aab11..ad411a78870c 100644
--- a/include/linux/mfd/pcf50633/core.h
+++ b/include/linux/mfd/pcf50633/core.h
@@ -18,6 +18,7 @@
18#include <linux/regulator/driver.h> 18#include <linux/regulator/driver.h>
19#include <linux/regulator/machine.h> 19#include <linux/regulator/machine.h>
20#include <linux/power_supply.h> 20#include <linux/power_supply.h>
21#include <linux/mfd/pcf50633/backlight.h>
21 22
22struct pcf50633; 23struct pcf50633;
23 24
@@ -43,6 +44,8 @@ struct pcf50633_platform_data {
43 void (*force_shutdown)(struct pcf50633 *); 44 void (*force_shutdown)(struct pcf50633 *);
44 45
45 u8 resumers[5]; 46 u8 resumers[5];
47
48 struct pcf50633_bl_platform_data *backlight_data;
46}; 49};
47 50
48struct pcf50633_irq { 51struct pcf50633_irq {
@@ -152,6 +155,7 @@ struct pcf50633 {
152 struct platform_device *mbc_pdev; 155 struct platform_device *mbc_pdev;
153 struct platform_device *adc_pdev; 156 struct platform_device *adc_pdev;
154 struct platform_device *input_pdev; 157 struct platform_device *input_pdev;
158 struct platform_device *bl_pdev;
155 struct platform_device *regulator_pdev[PCF50633_NUM_REGULATORS]; 159 struct platform_device *regulator_pdev[PCF50633_NUM_REGULATORS];
156}; 160};
157 161
diff --git a/include/linux/mfd/rdc321x.h b/include/linux/mfd/rdc321x.h
new file mode 100644
index 000000000000..4bdf19c8eedf
--- /dev/null
+++ b/include/linux/mfd/rdc321x.h
@@ -0,0 +1,26 @@
1#ifndef __RDC321X_MFD_H
2#define __RDC321X_MFD_H
3
4#include <linux/types.h>
5#include <linux/pci.h>
6
7/* Offsets to be accessed in the southbridge PCI
8 * device configuration register */
9#define RDC321X_WDT_CTRL 0x44
10#define RDC321X_GPIO_CTRL_REG1 0x48
11#define RDC321X_GPIO_DATA_REG1 0x4c
12#define RDC321X_GPIO_CTRL_REG2 0x84
13#define RDC321X_GPIO_DATA_REG2 0x88
14
15#define RDC321X_MAX_GPIO 58
16
17struct rdc321x_gpio_pdata {
18 struct pci_dev *sb_pdev;
19 unsigned max_gpios;
20};
21
22struct rdc321x_wdt_pdata {
23 struct pci_dev *sb_pdev;
24};
25
26#endif /* __RDC321X_MFD_H */
diff --git a/include/linux/mfd/sh_mobile_sdhi.h b/include/linux/mfd/sh_mobile_sdhi.h
index 3bcd7163485c..49067802a6d7 100644
--- a/include/linux/mfd/sh_mobile_sdhi.h
+++ b/include/linux/mfd/sh_mobile_sdhi.h
@@ -1,7 +1,13 @@
1#ifndef __SH_MOBILE_SDHI_H__ 1#ifndef __SH_MOBILE_SDHI_H__
2#define __SH_MOBILE_SDHI_H__ 2#define __SH_MOBILE_SDHI_H__
3 3
4#include <linux/types.h>
5
4struct sh_mobile_sdhi_info { 6struct sh_mobile_sdhi_info {
7 int dma_slave_tx;
8 int dma_slave_rx;
9 unsigned long tmio_flags;
10 u32 tmio_ocr_mask; /* available MMC voltages */
5 void (*set_pwr)(struct platform_device *pdev, int state); 11 void (*set_pwr)(struct platform_device *pdev, int state);
6}; 12};
7 13
diff --git a/include/linux/mfd/stmpe.h b/include/linux/mfd/stmpe.h
new file mode 100644
index 000000000000..39ca7588659b
--- /dev/null
+++ b/include/linux/mfd/stmpe.h
@@ -0,0 +1,201 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License, version 2
5 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
6 */
7
8#ifndef __LINUX_MFD_STMPE_H
9#define __LINUX_MFD_STMPE_H
10
11#include <linux/device.h>
12
13enum stmpe_block {
14 STMPE_BLOCK_GPIO = 1 << 0,
15 STMPE_BLOCK_KEYPAD = 1 << 1,
16 STMPE_BLOCK_TOUCHSCREEN = 1 << 2,
17 STMPE_BLOCK_ADC = 1 << 3,
18 STMPE_BLOCK_PWM = 1 << 4,
19 STMPE_BLOCK_ROTATOR = 1 << 5,
20};
21
22enum stmpe_partnum {
23 STMPE811,
24 STMPE1601,
25 STMPE2401,
26 STMPE2403,
27};
28
29/*
30 * For registers whose locations differ on variants, the correct address is
31 * obtained by indexing stmpe->regs with one of the following.
32 */
33enum {
34 STMPE_IDX_CHIP_ID,
35 STMPE_IDX_ICR_LSB,
36 STMPE_IDX_IER_LSB,
37 STMPE_IDX_ISR_MSB,
38 STMPE_IDX_GPMR_LSB,
39 STMPE_IDX_GPSR_LSB,
40 STMPE_IDX_GPCR_LSB,
41 STMPE_IDX_GPDR_LSB,
42 STMPE_IDX_GPEDR_MSB,
43 STMPE_IDX_GPRER_LSB,
44 STMPE_IDX_GPFER_LSB,
45 STMPE_IDX_GPAFR_U_MSB,
46 STMPE_IDX_IEGPIOR_LSB,
47 STMPE_IDX_ISGPIOR_MSB,
48 STMPE_IDX_MAX,
49};
50
51
52struct stmpe_variant_info;
53
54/**
55 * struct stmpe - STMPE MFD structure
56 * @lock: lock protecting I/O operations
57 * @irq_lock: IRQ bus lock
58 * @dev: device, mostly for dev_dbg()
59 * @i2c: i2c client
60 * @variant: the detected STMPE model number
61 * @regs: list of addresses of registers which are at different addresses on
62 * different variants. Indexed by one of STMPE_IDX_*.
63 * @irq_base: starting IRQ number for internal IRQs
64 * @num_gpios: number of gpios, differs for variants
65 * @ier: cache of IER registers for bus_lock
66 * @oldier: cache of IER registers for bus_lock
67 * @pdata: platform data
68 */
69struct stmpe {
70 struct mutex lock;
71 struct mutex irq_lock;
72 struct device *dev;
73 struct i2c_client *i2c;
74 enum stmpe_partnum partnum;
75 struct stmpe_variant_info *variant;
76 const u8 *regs;
77
78 int irq_base;
79 int num_gpios;
80 u8 ier[2];
81 u8 oldier[2];
82 struct stmpe_platform_data *pdata;
83};
84
85extern int stmpe_reg_write(struct stmpe *stmpe, u8 reg, u8 data);
86extern int stmpe_reg_read(struct stmpe *stmpe, u8 reg);
87extern int stmpe_block_read(struct stmpe *stmpe, u8 reg, u8 length,
88 u8 *values);
89extern int stmpe_block_write(struct stmpe *stmpe, u8 reg, u8 length,
90 const u8 *values);
91extern int stmpe_set_bits(struct stmpe *stmpe, u8 reg, u8 mask, u8 val);
92extern int stmpe_set_altfunc(struct stmpe *stmpe, u32 pins,
93 enum stmpe_block block);
94extern int stmpe_enable(struct stmpe *stmpe, unsigned int blocks);
95extern int stmpe_disable(struct stmpe *stmpe, unsigned int blocks);
96
97struct matrix_keymap_data;
98
99/**
100 * struct stmpe_keypad_platform_data - STMPE keypad platform data
101 * @keymap_data: key map table and size
102 * @debounce_ms: debounce interval, in ms. Maximum is
103 * %STMPE_KEYPAD_MAX_DEBOUNCE.
104 * @scan_count: number of key scanning cycles to confirm key data.
105 * Maximum is %STMPE_KEYPAD_MAX_SCAN_COUNT.
106 * @no_autorepeat: disable key autorepeat
107 */
108struct stmpe_keypad_platform_data {
109 struct matrix_keymap_data *keymap_data;
110 unsigned int debounce_ms;
111 unsigned int scan_count;
112 bool no_autorepeat;
113};
114
115/**
116 * struct stmpe_gpio_platform_data - STMPE GPIO platform data
117 * @gpio_base: first gpio number assigned. A maximum of
118 * %STMPE_NR_GPIOS GPIOs will be allocated.
119 */
120struct stmpe_gpio_platform_data {
121 int gpio_base;
122 void (*setup)(struct stmpe *stmpe, unsigned gpio_base);
123 void (*remove)(struct stmpe *stmpe, unsigned gpio_base);
124};
125
126/**
127 * struct stmpe_ts_platform_data - stmpe811 touch screen controller platform
128 * data
129 * @sample_time: ADC converstion time in number of clock.
130 * (0 -> 36 clocks, 1 -> 44 clocks, 2 -> 56 clocks, 3 -> 64 clocks,
131 * 4 -> 80 clocks, 5 -> 96 clocks, 6 -> 144 clocks),
132 * recommended is 4.
133 * @mod_12b: ADC Bit mode (0 -> 10bit ADC, 1 -> 12bit ADC)
134 * @ref_sel: ADC reference source
135 * (0 -> internal reference, 1 -> external reference)
136 * @adc_freq: ADC Clock speed
137 * (0 -> 1.625 MHz, 1 -> 3.25 MHz, 2 || 3 -> 6.5 MHz)
138 * @ave_ctrl: Sample average control
139 * (0 -> 1 sample, 1 -> 2 samples, 2 -> 4 samples, 3 -> 8 samples)
140 * @touch_det_delay: Touch detect interrupt delay
141 * (0 -> 10 us, 1 -> 50 us, 2 -> 100 us, 3 -> 500 us,
142 * 4-> 1 ms, 5 -> 5 ms, 6 -> 10 ms, 7 -> 50 ms)
143 * recommended is 3
144 * @settling: Panel driver settling time
145 * (0 -> 10 us, 1 -> 100 us, 2 -> 500 us, 3 -> 1 ms,
146 * 4 -> 5 ms, 5 -> 10 ms, 6 for 50 ms, 7 -> 100 ms)
147 * recommended is 2
148 * @fraction_z: Length of the fractional part in z
149 * (fraction_z ([0..7]) = Count of the fractional part)
150 * recommended is 7
151 * @i_drive: current limit value of the touchscreen drivers
152 * (0 -> 20 mA typical 35 mA max, 1 -> 50 mA typical 80 mA max)
153 *
154 * */
155struct stmpe_ts_platform_data {
156 u8 sample_time;
157 u8 mod_12b;
158 u8 ref_sel;
159 u8 adc_freq;
160 u8 ave_ctrl;
161 u8 touch_det_delay;
162 u8 settling;
163 u8 fraction_z;
164 u8 i_drive;
165};
166
167/**
168 * struct stmpe_platform_data - STMPE platform data
169 * @id: device id to distinguish between multiple STMPEs on the same board
170 * @blocks: bitmask of blocks to enable (use STMPE_BLOCK_*)
171 * @irq_trigger: IRQ trigger to use for the interrupt to the host
172 * @irq_invert_polarity: IRQ line is connected with reversed polarity
173 * @autosleep: bool to enable/disable stmpe autosleep
174 * @autosleep_timeout: inactivity timeout in milliseconds for autosleep
175 * @irq_base: base IRQ number. %STMPE_NR_IRQS irqs will be used, or
176 * %STMPE_NR_INTERNAL_IRQS if the GPIO driver is not used.
177 * @gpio: GPIO-specific platform data
178 * @keypad: keypad-specific platform data
179 * @ts: touchscreen-specific platform data
180 */
181struct stmpe_platform_data {
182 int id;
183 unsigned int blocks;
184 int irq_base;
185 unsigned int irq_trigger;
186 bool irq_invert_polarity;
187 bool autosleep;
188 int autosleep_timeout;
189
190 struct stmpe_gpio_platform_data *gpio;
191 struct stmpe_keypad_platform_data *keypad;
192 struct stmpe_ts_platform_data *ts;
193};
194
195#define STMPE_NR_INTERNAL_IRQS 9
196#define STMPE_INT_GPIO(x) (STMPE_NR_INTERNAL_IRQS + (x))
197
198#define STMPE_NR_GPIOS 24
199#define STMPE_NR_IRQS STMPE_INT_GPIO(STMPE_NR_GPIOS)
200
201#endif
diff --git a/include/linux/mfd/tc35892.h b/include/linux/mfd/tc35892.h
new file mode 100644
index 000000000000..e47f770d3068
--- /dev/null
+++ b/include/linux/mfd/tc35892.h
@@ -0,0 +1,132 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License, version 2
5 */
6
7#ifndef __LINUX_MFD_TC35892_H
8#define __LINUX_MFD_TC35892_H
9
10#include <linux/device.h>
11
12#define TC35892_RSTCTRL_IRQRST (1 << 4)
13#define TC35892_RSTCTRL_TIMRST (1 << 3)
14#define TC35892_RSTCTRL_ROTRST (1 << 2)
15#define TC35892_RSTCTRL_KBDRST (1 << 1)
16#define TC35892_RSTCTRL_GPIRST (1 << 0)
17
18#define TC35892_IRQST 0x91
19
20#define TC35892_MANFCODE_MAGIC 0x03
21#define TC35892_MANFCODE 0x80
22#define TC35892_VERSION 0x81
23#define TC35892_IOCFG 0xA7
24
25#define TC35892_CLKMODE 0x88
26#define TC35892_CLKCFG 0x89
27#define TC35892_CLKEN 0x8A
28
29#define TC35892_RSTCTRL 0x82
30#define TC35892_EXTRSTN 0x83
31#define TC35892_RSTINTCLR 0x84
32
33#define TC35892_GPIOIS0 0xC9
34#define TC35892_GPIOIS1 0xCA
35#define TC35892_GPIOIS2 0xCB
36#define TC35892_GPIOIBE0 0xCC
37#define TC35892_GPIOIBE1 0xCD
38#define TC35892_GPIOIBE2 0xCE
39#define TC35892_GPIOIEV0 0xCF
40#define TC35892_GPIOIEV1 0xD0
41#define TC35892_GPIOIEV2 0xD1
42#define TC35892_GPIOIE0 0xD2
43#define TC35892_GPIOIE1 0xD3
44#define TC35892_GPIOIE2 0xD4
45#define TC35892_GPIORIS0 0xD6
46#define TC35892_GPIORIS1 0xD7
47#define TC35892_GPIORIS2 0xD8
48#define TC35892_GPIOMIS0 0xD9
49#define TC35892_GPIOMIS1 0xDA
50#define TC35892_GPIOMIS2 0xDB
51#define TC35892_GPIOIC0 0xDC
52#define TC35892_GPIOIC1 0xDD
53#define TC35892_GPIOIC2 0xDE
54
55#define TC35892_GPIODATA0 0xC0
56#define TC35892_GPIOMASK0 0xc1
57#define TC35892_GPIODATA1 0xC2
58#define TC35892_GPIOMASK1 0xc3
59#define TC35892_GPIODATA2 0xC4
60#define TC35892_GPIOMASK2 0xC5
61
62#define TC35892_GPIODIR0 0xC6
63#define TC35892_GPIODIR1 0xC7
64#define TC35892_GPIODIR2 0xC8
65
66#define TC35892_GPIOSYNC0 0xE6
67#define TC35892_GPIOSYNC1 0xE7
68#define TC35892_GPIOSYNC2 0xE8
69
70#define TC35892_GPIOWAKE0 0xE9
71#define TC35892_GPIOWAKE1 0xEA
72#define TC35892_GPIOWAKE2 0xEB
73
74#define TC35892_GPIOODM0 0xE0
75#define TC35892_GPIOODE0 0xE1
76#define TC35892_GPIOODM1 0xE2
77#define TC35892_GPIOODE1 0xE3
78#define TC35892_GPIOODM2 0xE4
79#define TC35892_GPIOODE2 0xE5
80
81#define TC35892_INT_GPIIRQ 0
82#define TC35892_INT_TI0IRQ 1
83#define TC35892_INT_TI1IRQ 2
84#define TC35892_INT_TI2IRQ 3
85#define TC35892_INT_ROTIRQ 5
86#define TC35892_INT_KBDIRQ 6
87#define TC35892_INT_PORIRQ 7
88
89#define TC35892_NR_INTERNAL_IRQS 8
90#define TC35892_INT_GPIO(x) (TC35892_NR_INTERNAL_IRQS + (x))
91
92struct tc35892 {
93 struct mutex lock;
94 struct device *dev;
95 struct i2c_client *i2c;
96
97 int irq_base;
98 int num_gpio;
99 struct tc35892_platform_data *pdata;
100};
101
102extern int tc35892_reg_write(struct tc35892 *tc35892, u8 reg, u8 data);
103extern int tc35892_reg_read(struct tc35892 *tc35892, u8 reg);
104extern int tc35892_block_read(struct tc35892 *tc35892, u8 reg, u8 length,
105 u8 *values);
106extern int tc35892_block_write(struct tc35892 *tc35892, u8 reg, u8 length,
107 const u8 *values);
108extern int tc35892_set_bits(struct tc35892 *tc35892, u8 reg, u8 mask, u8 val);
109
110/**
111 * struct tc35892_gpio_platform_data - TC35892 GPIO platform data
112 * @gpio_base: first gpio number assigned to TC35892. A maximum of
113 * %TC35892_NR_GPIOS GPIOs will be allocated.
114 */
115struct tc35892_gpio_platform_data {
116 int gpio_base;
117};
118
119/**
120 * struct tc35892_platform_data - TC35892 platform data
121 * @irq_base: base IRQ number. %TC35892_NR_IRQS irqs will be used.
122 * @gpio: GPIO-specific platform data
123 */
124struct tc35892_platform_data {
125 int irq_base;
126 struct tc35892_gpio_platform_data *gpio;
127};
128
129#define TC35892_NR_GPIOS 24
130#define TC35892_NR_IRQS TC35892_INT_GPIO(TC35892_NR_GPIOS)
131
132#endif
diff --git a/include/linux/mfd/tmio.h b/include/linux/mfd/tmio.h
index c3f7dff8effc..f07425bc3dcd 100644
--- a/include/linux/mfd/tmio.h
+++ b/include/linux/mfd/tmio.h
@@ -50,17 +50,28 @@
50 tmio_iowrite16((val) >> 16, (base) + ((reg + 2) << (shift))); \ 50 tmio_iowrite16((val) >> 16, (base) + ((reg + 2) << (shift))); \
51 } while (0) 51 } while (0)
52 52
53/* tmio MMC platform flags */
54#define TMIO_MMC_WRPROTECT_DISABLE (1 << 0)
55
53int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base); 56int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base);
54int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base); 57int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base);
55void tmio_core_mmc_pwr(void __iomem *cnf, int shift, int state); 58void tmio_core_mmc_pwr(void __iomem *cnf, int shift, int state);
56void tmio_core_mmc_clk_div(void __iomem *cnf, int shift, int state); 59void tmio_core_mmc_clk_div(void __iomem *cnf, int shift, int state);
57 60
61struct tmio_mmc_dma {
62 void *chan_priv_tx;
63 void *chan_priv_rx;
64};
65
58/* 66/*
59 * data for the MMC controller 67 * data for the MMC controller
60 */ 68 */
61struct tmio_mmc_data { 69struct tmio_mmc_data {
62 unsigned int hclk; 70 unsigned int hclk;
63 unsigned long capabilities; 71 unsigned long capabilities;
72 unsigned long flags;
73 u32 ocr_mask; /* available voltages */
74 struct tmio_mmc_dma *dma;
64 void (*set_pwr)(struct platform_device *host, int state); 75 void (*set_pwr)(struct platform_device *host, int state);
65 void (*set_clk_div)(struct platform_device *host, int state); 76 void (*set_clk_div)(struct platform_device *host, int state);
66}; 77};
diff --git a/include/linux/mfd/tps6507x.h b/include/linux/mfd/tps6507x.h
new file mode 100644
index 000000000000..c923e4864f55
--- /dev/null
+++ b/include/linux/mfd/tps6507x.h
@@ -0,0 +1,169 @@
1/* linux/mfd/tps6507x.h
2 *
3 * Functions to access TPS65070 power management chip.
4 *
5 * Copyright (c) 2009 RidgeRun (todd.fischer@ridgerun.com)
6 *
7 *
8 * For licencing details see kernel-base/COPYING
9 */
10
11#ifndef __LINUX_MFD_TPS6507X_H
12#define __LINUX_MFD_TPS6507X_H
13
14/*
15 * ----------------------------------------------------------------------------
16 * Registers, all 8 bits
17 * ----------------------------------------------------------------------------
18 */
19
20
21/* Register definitions */
22#define TPS6507X_REG_PPATH1 0X01
23#define TPS6507X_CHG_USB BIT(7)
24#define TPS6507X_CHG_AC BIT(6)
25#define TPS6507X_CHG_USB_PW_ENABLE BIT(5)
26#define TPS6507X_CHG_AC_PW_ENABLE BIT(4)
27#define TPS6507X_CHG_AC_CURRENT BIT(2)
28#define TPS6507X_CHG_USB_CURRENT BIT(0)
29
30#define TPS6507X_REG_INT 0X02
31#define TPS6507X_REG_MASK_AC_USB BIT(7)
32#define TPS6507X_REG_MASK_TSC BIT(6)
33#define TPS6507X_REG_MASK_PB_IN BIT(5)
34#define TPS6507X_REG_TSC_INT BIT(3)
35#define TPS6507X_REG_PB_IN_INT BIT(2)
36#define TPS6507X_REG_AC_USB_APPLIED BIT(1)
37#define TPS6507X_REG_AC_USB_REMOVED BIT(0)
38
39#define TPS6507X_REG_CHGCONFIG0 0X03
40
41#define TPS6507X_REG_CHGCONFIG1 0X04
42#define TPS6507X_CON_CTRL1_DCDC1_ENABLE BIT(4)
43#define TPS6507X_CON_CTRL1_DCDC2_ENABLE BIT(3)
44#define TPS6507X_CON_CTRL1_DCDC3_ENABLE BIT(2)
45#define TPS6507X_CON_CTRL1_LDO1_ENABLE BIT(1)
46#define TPS6507X_CON_CTRL1_LDO2_ENABLE BIT(0)
47
48#define TPS6507X_REG_CHGCONFIG2 0X05
49
50#define TPS6507X_REG_CHGCONFIG3 0X06
51
52#define TPS6507X_REG_ADCONFIG 0X07
53#define TPS6507X_ADCONFIG_AD_ENABLE BIT(7)
54#define TPS6507X_ADCONFIG_START_CONVERSION BIT(6)
55#define TPS6507X_ADCONFIG_CONVERSION_DONE BIT(5)
56#define TPS6507X_ADCONFIG_VREF_ENABLE BIT(4)
57#define TPS6507X_ADCONFIG_INPUT_AD_IN1 0
58#define TPS6507X_ADCONFIG_INPUT_AD_IN2 1
59#define TPS6507X_ADCONFIG_INPUT_AD_IN3 2
60#define TPS6507X_ADCONFIG_INPUT_AD_IN4 3
61#define TPS6507X_ADCONFIG_INPUT_TS_PIN 4
62#define TPS6507X_ADCONFIG_INPUT_BAT_CURRENT 5
63#define TPS6507X_ADCONFIG_INPUT_AC_VOLTAGE 6
64#define TPS6507X_ADCONFIG_INPUT_SYS_VOLTAGE 7
65#define TPS6507X_ADCONFIG_INPUT_CHARGER_VOLTAGE 8
66#define TPS6507X_ADCONFIG_INPUT_BAT_VOLTAGE 9
67#define TPS6507X_ADCONFIG_INPUT_THRESHOLD_VOLTAGE 10
68#define TPS6507X_ADCONFIG_INPUT_ISET1_VOLTAGE 11
69#define TPS6507X_ADCONFIG_INPUT_ISET2_VOLTAGE 12
70#define TPS6507X_ADCONFIG_INPUT_REAL_TSC 14
71#define TPS6507X_ADCONFIG_INPUT_TSC 15
72
73#define TPS6507X_REG_TSCMODE 0X08
74#define TPS6507X_TSCMODE_X_POSITION 0
75#define TPS6507X_TSCMODE_Y_POSITION 1
76#define TPS6507X_TSCMODE_PRESSURE 2
77#define TPS6507X_TSCMODE_X_PLATE 3
78#define TPS6507X_TSCMODE_Y_PLATE 4
79#define TPS6507X_TSCMODE_STANDBY 5
80#define TPS6507X_TSCMODE_ADC_INPUT 6
81#define TPS6507X_TSCMODE_DISABLE 7
82
83#define TPS6507X_REG_ADRESULT_1 0X09
84
85#define TPS6507X_REG_ADRESULT_2 0X0A
86#define TPS6507X_REG_ADRESULT_2_MASK (BIT(1) | BIT(0))
87
88#define TPS6507X_REG_PGOOD 0X0B
89
90#define TPS6507X_REG_PGOODMASK 0X0C
91
92#define TPS6507X_REG_CON_CTRL1 0X0D
93#define TPS6507X_CON_CTRL1_DCDC1_ENABLE BIT(4)
94#define TPS6507X_CON_CTRL1_DCDC2_ENABLE BIT(3)
95#define TPS6507X_CON_CTRL1_DCDC3_ENABLE BIT(2)
96#define TPS6507X_CON_CTRL1_LDO1_ENABLE BIT(1)
97#define TPS6507X_CON_CTRL1_LDO2_ENABLE BIT(0)
98
99#define TPS6507X_REG_CON_CTRL2 0X0E
100
101#define TPS6507X_REG_CON_CTRL3 0X0F
102
103#define TPS6507X_REG_DEFDCDC1 0X10
104#define TPS6507X_DEFDCDC1_DCDC1_EXT_ADJ_EN BIT(7)
105#define TPS6507X_DEFDCDC1_DCDC1_MASK 0X3F
106
107#define TPS6507X_REG_DEFDCDC2_LOW 0X11
108#define TPS6507X_DEFDCDC2_LOW_DCDC2_MASK 0X3F
109
110#define TPS6507X_REG_DEFDCDC2_HIGH 0X12
111#define TPS6507X_DEFDCDC2_HIGH_DCDC2_MASK 0X3F
112
113#define TPS6507X_REG_DEFDCDC3_LOW 0X13
114#define TPS6507X_DEFDCDC3_LOW_DCDC3_MASK 0X3F
115
116#define TPS6507X_REG_DEFDCDC3_HIGH 0X14
117#define TPS6507X_DEFDCDC3_HIGH_DCDC3_MASK 0X3F
118
119#define TPS6507X_REG_DEFSLEW 0X15
120
121#define TPS6507X_REG_LDO_CTRL1 0X16
122#define TPS6507X_REG_LDO_CTRL1_LDO1_MASK 0X0F
123
124#define TPS6507X_REG_DEFLDO2 0X17
125#define TPS6507X_REG_DEFLDO2_LDO2_MASK 0X3F
126
127#define TPS6507X_REG_WLED_CTRL1 0X18
128
129#define TPS6507X_REG_WLED_CTRL2 0X19
130
131/* VDCDC MASK */
132#define TPS6507X_DEFDCDCX_DCDC_MASK 0X3F
133
134#define TPS6507X_MAX_REGISTER 0X19
135
136/**
137 * struct tps6507x_board - packages regulator and touchscreen init data
138 * @tps6507x_regulator_data: regulator initialization values
139 *
140 * Board data may be used to initialize regulator and touchscreen.
141 */
142
143struct tps6507x_board {
144 struct regulator_init_data *tps6507x_pmic_init_data;
145 struct touchscreen_init_data *tps6507x_ts_init_data;
146};
147
148/**
149 * struct tps6507x_dev - tps6507x sub-driver chip access routines
150 * @read_dev() - I2C register read function
151 * @write_dev() - I2C register write function
152 *
153 * Device data may be used to access the TPS6507x chip
154 */
155
156struct tps6507x_dev {
157 struct device *dev;
158 struct i2c_client *i2c_client;
159 int (*read_dev)(struct tps6507x_dev *tps6507x, char reg, int size,
160 void *dest);
161 int (*write_dev)(struct tps6507x_dev *tps6507x, char reg, int size,
162 void *src);
163
164 /* Client devices */
165 struct tps6507x_pmic *pmic;
166 struct tps6507x_ts *ts;
167};
168
169#endif /* __LINUX_MFD_TPS6507X_H */
diff --git a/include/linux/mfd/tps6586x.h b/include/linux/mfd/tps6586x.h
new file mode 100644
index 000000000000..772b3ae640af
--- /dev/null
+++ b/include/linux/mfd/tps6586x.h
@@ -0,0 +1,47 @@
1#ifndef __LINUX_MFD_TPS6586X_H
2#define __LINUX_MFD_TPS6586X_H
3
4enum {
5 TPS6586X_ID_SM_0,
6 TPS6586X_ID_SM_1,
7 TPS6586X_ID_SM_2,
8 TPS6586X_ID_LDO_0,
9 TPS6586X_ID_LDO_1,
10 TPS6586X_ID_LDO_2,
11 TPS6586X_ID_LDO_3,
12 TPS6586X_ID_LDO_4,
13 TPS6586X_ID_LDO_5,
14 TPS6586X_ID_LDO_6,
15 TPS6586X_ID_LDO_7,
16 TPS6586X_ID_LDO_8,
17 TPS6586X_ID_LDO_9,
18 TPS6586X_ID_LDO_RTC,
19};
20
21struct tps6586x_subdev_info {
22 int id;
23 const char *name;
24 void *platform_data;
25};
26
27struct tps6586x_platform_data {
28 int num_subdevs;
29 struct tps6586x_subdev_info *subdevs;
30
31 int gpio_base;
32};
33
34/*
35 * NOTE: the functions below are not intended for use outside
36 * of the TPS6586X sub-device drivers
37 */
38extern int tps6586x_write(struct device *dev, int reg, uint8_t val);
39extern int tps6586x_writes(struct device *dev, int reg, int len, uint8_t *val);
40extern int tps6586x_read(struct device *dev, int reg, uint8_t *val);
41extern int tps6586x_reads(struct device *dev, int reg, int len, uint8_t *val);
42extern int tps6586x_set_bits(struct device *dev, int reg, uint8_t bit_mask);
43extern int tps6586x_clr_bits(struct device *dev, int reg, uint8_t bit_mask);
44extern int tps6586x_update(struct device *dev, int reg, uint8_t val,
45 uint8_t mask);
46
47#endif /*__LINUX_MFD_TPS6586X_H */
diff --git a/include/linux/mfd/wm831x/core.h b/include/linux/mfd/wm831x/core.h
index 5915f6e3d9ab..eb5bd4e0e03c 100644
--- a/include/linux/mfd/wm831x/core.h
+++ b/include/linux/mfd/wm831x/core.h
@@ -256,8 +256,9 @@ struct wm831x {
256 int irq_masks_cache[WM831X_NUM_IRQ_REGS]; /* Cached hardware value */ 256 int irq_masks_cache[WM831X_NUM_IRQ_REGS]; /* Cached hardware value */
257 257
258 /* Chip revision based flags */ 258 /* Chip revision based flags */
259 unsigned has_gpio_ena:1; /* Has GPIO enable bit */ 259 unsigned has_gpio_ena:1; /* Has GPIO enable bit */
260 unsigned has_cs_sts:1; /* Has current sink status bit */ 260 unsigned has_cs_sts:1; /* Has current sink status bit */
261 unsigned charger_irq_wake:1; /* Are charger IRQs a wake source? */
261 262
262 int num_gpio; 263 int num_gpio;
263 264
diff --git a/include/linux/mfd/wm8350/audio.h b/include/linux/mfd/wm8350/audio.h
index d899dc0223ba..a95141eafce3 100644
--- a/include/linux/mfd/wm8350/audio.h
+++ b/include/linux/mfd/wm8350/audio.h
@@ -492,6 +492,8 @@
492 */ 492 */
493#define WM8350_JACK_L_LVL 0x0800 493#define WM8350_JACK_L_LVL 0x0800
494#define WM8350_JACK_R_LVL 0x0400 494#define WM8350_JACK_R_LVL 0x0400
495#define WM8350_JACK_MICSCD_LVL 0x0200
496#define WM8350_JACK_MICSD_LVL 0x0100
495 497
496/* 498/*
497 * WM8350 Platform setup 499 * WM8350 Platform setup
diff --git a/include/linux/mfd/wm8994/core.h b/include/linux/mfd/wm8994/core.h
index b06ff2846748..de79baee4925 100644
--- a/include/linux/mfd/wm8994/core.h
+++ b/include/linux/mfd/wm8994/core.h
@@ -15,14 +15,38 @@
15#ifndef __MFD_WM8994_CORE_H__ 15#ifndef __MFD_WM8994_CORE_H__
16#define __MFD_WM8994_CORE_H__ 16#define __MFD_WM8994_CORE_H__
17 17
18#include <linux/interrupt.h>
19
18struct regulator_dev; 20struct regulator_dev;
19struct regulator_bulk_data; 21struct regulator_bulk_data;
20 22
21#define WM8994_NUM_GPIO_REGS 11 23#define WM8994_NUM_GPIO_REGS 11
22#define WM8994_NUM_LDO_REGS 2 24#define WM8994_NUM_LDO_REGS 2
25#define WM8994_NUM_IRQ_REGS 2
26
27#define WM8994_IRQ_TEMP_SHUT 0
28#define WM8994_IRQ_MIC1_DET 1
29#define WM8994_IRQ_MIC1_SHRT 2
30#define WM8994_IRQ_MIC2_DET 3
31#define WM8994_IRQ_MIC2_SHRT 4
32#define WM8994_IRQ_FLL1_LOCK 5
33#define WM8994_IRQ_FLL2_LOCK 6
34#define WM8994_IRQ_SRC1_LOCK 7
35#define WM8994_IRQ_SRC2_LOCK 8
36#define WM8994_IRQ_AIF1DRC1_SIG_DET 9
37#define WM8994_IRQ_AIF1DRC2_SIG_DET 10
38#define WM8994_IRQ_AIF2DRC_SIG_DET 11
39#define WM8994_IRQ_FIFOS_ERR 12
40#define WM8994_IRQ_WSEQ_DONE 13
41#define WM8994_IRQ_DCS_DONE 14
42#define WM8994_IRQ_TEMP_WARN 15
43
44/* GPIOs in the chip are numbered from 1-11 */
45#define WM8994_IRQ_GPIO(x) (x + WM8994_IRQ_TEMP_WARN)
23 46
24struct wm8994 { 47struct wm8994 {
25 struct mutex io_lock; 48 struct mutex io_lock;
49 struct mutex irq_lock;
26 50
27 struct device *dev; 51 struct device *dev;
28 int (*read_dev)(struct wm8994 *wm8994, unsigned short reg, 52 int (*read_dev)(struct wm8994 *wm8994, unsigned short reg,
@@ -33,6 +57,11 @@ struct wm8994 {
33 void *control_data; 57 void *control_data;
34 58
35 int gpio_base; 59 int gpio_base;
60 int irq_base;
61
62 int irq;
63 u16 irq_masks_cur[WM8994_NUM_IRQ_REGS];
64 u16 irq_masks_cache[WM8994_NUM_IRQ_REGS];
36 65
37 /* Used over suspend/resume */ 66 /* Used over suspend/resume */
38 u16 ldo_regs[WM8994_NUM_LDO_REGS]; 67 u16 ldo_regs[WM8994_NUM_LDO_REGS];
@@ -51,4 +80,26 @@ int wm8994_set_bits(struct wm8994 *wm8994, unsigned short reg,
51int wm8994_bulk_read(struct wm8994 *wm8994, unsigned short reg, 80int wm8994_bulk_read(struct wm8994 *wm8994, unsigned short reg,
52 int count, u16 *buf); 81 int count, u16 *buf);
53 82
83
84/* Helper to save on boilerplate */
85static inline int wm8994_request_irq(struct wm8994 *wm8994, int irq,
86 irq_handler_t handler, const char *name,
87 void *data)
88{
89 if (!wm8994->irq_base)
90 return -EINVAL;
91 return request_threaded_irq(wm8994->irq_base + irq, NULL, handler,
92 IRQF_TRIGGER_RISING, name,
93 data);
94}
95static inline void wm8994_free_irq(struct wm8994 *wm8994, int irq, void *data)
96{
97 if (!wm8994->irq_base)
98 return;
99 free_irq(wm8994->irq_base + irq, data);
100}
101
102int wm8994_irq_init(struct wm8994 *wm8994);
103void wm8994_irq_exit(struct wm8994 *wm8994);
104
54#endif 105#endif
diff --git a/include/linux/mfd/wm8994/gpio.h b/include/linux/mfd/wm8994/gpio.h
index b4d4c22991e8..0c79b5ff4b5a 100644
--- a/include/linux/mfd/wm8994/gpio.h
+++ b/include/linux/mfd/wm8994/gpio.h
@@ -36,6 +36,10 @@
36#define WM8994_GP_FN_WSEQ_STATUS 16 36#define WM8994_GP_FN_WSEQ_STATUS 16
37#define WM8994_GP_FN_FIFO_ERROR 17 37#define WM8994_GP_FN_FIFO_ERROR 17
38#define WM8994_GP_FN_OPCLK 18 38#define WM8994_GP_FN_OPCLK 18
39#define WM8994_GP_FN_THW 19
40#define WM8994_GP_FN_DCS_DONE 20
41#define WM8994_GP_FN_FLL1_OUT 21
42#define WM8994_GP_FN_FLL2_OUT 22
39 43
40#define WM8994_GPN_DIR 0x8000 /* GPN_DIR */ 44#define WM8994_GPN_DIR 0x8000 /* GPN_DIR */
41#define WM8994_GPN_DIR_MASK 0x8000 /* GPN_DIR */ 45#define WM8994_GPN_DIR_MASK 0x8000 /* GPN_DIR */
diff --git a/include/linux/mfd/wm8994/pdata.h b/include/linux/mfd/wm8994/pdata.h
index 70d6a8687dc5..5c51f367c061 100644
--- a/include/linux/mfd/wm8994/pdata.h
+++ b/include/linux/mfd/wm8994/pdata.h
@@ -70,6 +70,7 @@ struct wm8994_pdata {
70 70
71 struct wm8994_ldo_pdata ldo[WM8994_NUM_LDO]; 71 struct wm8994_ldo_pdata ldo[WM8994_NUM_LDO];
72 72
73 int irq_base; /** Base IRQ number for WM8994, required for IRQs */
73 74
74 int num_drc_cfgs; 75 int num_drc_cfgs;
75 struct wm8994_drc_cfg *drc_cfgs; 76 struct wm8994_drc_cfg *drc_cfgs;
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-07 18:22:33 -0500