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-rw-r--r--include/linux/mfd/abx500.h27
-rw-r--r--include/linux/mfd/abx500/ab8500-bm.h61
-rw-r--r--include/linux/mfd/abx500/ab8500-gpadc.h74
-rw-r--r--include/linux/mfd/abx500/ab8500-sysctrl.h6
-rw-r--r--include/linux/mfd/abx500/ab8500.h14
-rw-r--r--include/linux/mfd/abx500/ux500_chargalg.h7
-rw-r--r--include/linux/mfd/arizona/core.h3
-rw-r--r--include/linux/mfd/arizona/pdata.h28
-rw-r--r--include/linux/mfd/arizona/registers.h46
-rw-r--r--include/linux/mfd/cros_ec.h170
-rw-r--r--include/linux/mfd/cros_ec_commands.h1369
-rw-r--r--include/linux/mfd/db8500-prcmu.h10
-rw-r--r--include/linux/mfd/dbx500-prcmu.h38
-rw-r--r--include/linux/mfd/palmas.h36
-rw-r--r--include/linux/mfd/retu.h8
-rw-r--r--include/linux/mfd/rtsx_pci.h36
-rw-r--r--include/linux/mfd/si476x-core.h533
-rw-r--r--include/linux/mfd/si476x-platform.h267
-rw-r--r--include/linux/mfd/si476x-reports.h163
-rw-r--r--include/linux/mfd/stmpe.h3
-rw-r--r--include/linux/mfd/syscon.h3
-rw-r--r--include/linux/mfd/tps65090.h6
-rw-r--r--include/linux/mfd/tps65217.h1
-rw-r--r--include/linux/mfd/wm8994/pdata.h8
24 files changed, 2825 insertions, 92 deletions
diff --git a/include/linux/mfd/abx500.h b/include/linux/mfd/abx500.h
index 9ead60bc66b7..3301b2031c8d 100644
--- a/include/linux/mfd/abx500.h
+++ b/include/linux/mfd/abx500.h
@@ -89,6 +89,11 @@ struct abx500_fg;
89 * points. 89 * points.
90 * @maint_thres This is the threshold where we stop reporting 90 * @maint_thres This is the threshold where we stop reporting
91 * battery full while in maintenance, in per cent 91 * battery full while in maintenance, in per cent
92 * @pcut_enable: Enable power cut feature in ab8505
93 * @pcut_max_time: Max time threshold
94 * @pcut_flag_time: Flagtime threshold
95 * @pcut_max_restart: Max number of restarts
96 * @pcut_debounce_time: Sets battery debounce time
92 */ 97 */
93struct abx500_fg_parameters { 98struct abx500_fg_parameters {
94 int recovery_sleep_timer; 99 int recovery_sleep_timer;
@@ -106,6 +111,11 @@ struct abx500_fg_parameters {
106 int battok_raising_th_sel1; 111 int battok_raising_th_sel1;
107 int user_cap_limit; 112 int user_cap_limit;
108 int maint_thres; 113 int maint_thres;
114 bool pcut_enable;
115 u8 pcut_max_time;
116 u8 pcut_flag_time;
117 u8 pcut_max_restart;
118 u8 pcut_debounce_time;
109}; 119};
110 120
111/** 121/**
@@ -173,11 +183,11 @@ struct abx500_battery_type {
173 int low_high_vol_lvl; 183 int low_high_vol_lvl;
174 int battery_resistance; 184 int battery_resistance;
175 int n_temp_tbl_elements; 185 int n_temp_tbl_elements;
176 struct abx500_res_to_temp *r_to_t_tbl; 186 const struct abx500_res_to_temp *r_to_t_tbl;
177 int n_v_cap_tbl_elements; 187 int n_v_cap_tbl_elements;
178 struct abx500_v_to_cap *v_to_cap_tbl; 188 const struct abx500_v_to_cap *v_to_cap_tbl;
179 int n_batres_tbl_elements; 189 int n_batres_tbl_elements;
180 struct batres_vs_temp *batres_tbl; 190 const struct batres_vs_temp *batres_tbl;
181}; 191};
182 192
183/** 193/**
@@ -236,7 +246,11 @@ struct abx500_bm_charger_parameters {
236 * @interval_not_charging charge alg cycle period time when not charging (sec) 246 * @interval_not_charging charge alg cycle period time when not charging (sec)
237 * @temp_hysteresis temperature hysteresis 247 * @temp_hysteresis temperature hysteresis
238 * @gnd_lift_resistance Battery ground to phone ground resistance (mOhm) 248 * @gnd_lift_resistance Battery ground to phone ground resistance (mOhm)
239 * @maxi: maximization parameters 249 * @n_chg_out_curr number of elements in array chg_output_curr
250 * @n_chg_in_curr number of elements in array chg_input_curr
251 * @chg_output_curr charger output current level map
252 * @chg_input_curr charger input current level map
253 * @maxi maximization parameters
240 * @cap_levels capacity in percent for the different capacity levels 254 * @cap_levels capacity in percent for the different capacity levels
241 * @bat_type table of supported battery types 255 * @bat_type table of supported battery types
242 * @chg_params charger parameters 256 * @chg_params charger parameters
@@ -257,6 +271,7 @@ struct abx500_bm_data {
257 bool autopower_cfg; 271 bool autopower_cfg;
258 bool ac_enabled; 272 bool ac_enabled;
259 bool usb_enabled; 273 bool usb_enabled;
274 bool usb_power_path;
260 bool no_maintenance; 275 bool no_maintenance;
261 bool capacity_scaling; 276 bool capacity_scaling;
262 bool chg_unknown_bat; 277 bool chg_unknown_bat;
@@ -270,6 +285,10 @@ struct abx500_bm_data {
270 int interval_not_charging; 285 int interval_not_charging;
271 int temp_hysteresis; 286 int temp_hysteresis;
272 int gnd_lift_resistance; 287 int gnd_lift_resistance;
288 int n_chg_out_curr;
289 int n_chg_in_curr;
290 int *chg_output_curr;
291 int *chg_input_curr;
273 const struct abx500_maxim_parameters *maxi; 292 const struct abx500_maxim_parameters *maxi;
274 const struct abx500_bm_capacity_levels *cap_levels; 293 const struct abx500_bm_capacity_levels *cap_levels;
275 struct abx500_battery_type *bat_type; 294 struct abx500_battery_type *bat_type;
diff --git a/include/linux/mfd/abx500/ab8500-bm.h b/include/linux/mfd/abx500/ab8500-bm.h
index 8d35bfe164c8..cc892a8d8d6e 100644
--- a/include/linux/mfd/abx500/ab8500-bm.h
+++ b/include/linux/mfd/abx500/ab8500-bm.h
@@ -23,6 +23,7 @@
23 * Bank : 0x5 23 * Bank : 0x5
24 */ 24 */
25#define AB8500_USB_LINE_STAT_REG 0x80 25#define AB8500_USB_LINE_STAT_REG 0x80
26#define AB8500_USB_LINE_CTRL2_REG 0x82
26#define AB8500_USB_LINK1_STAT_REG 0x94 27#define AB8500_USB_LINK1_STAT_REG 0x94
27 28
28/* 29/*
@@ -33,7 +34,7 @@
33#define AB8500_CH_STATUS2_REG 0x01 34#define AB8500_CH_STATUS2_REG 0x01
34#define AB8500_CH_USBCH_STAT1_REG 0x02 35#define AB8500_CH_USBCH_STAT1_REG 0x02
35#define AB8500_CH_USBCH_STAT2_REG 0x03 36#define AB8500_CH_USBCH_STAT2_REG 0x03
36#define AB8500_CH_FSM_STAT_REG 0x04 37#define AB8540_CH_USBCH_STAT3_REG 0x04
37#define AB8500_CH_STAT_REG 0x05 38#define AB8500_CH_STAT_REG 0x05
38 39
39/* 40/*
@@ -69,6 +70,8 @@
69#define AB8500_USBCH_CTRL1_REG 0xC0 70#define AB8500_USBCH_CTRL1_REG 0xC0
70#define AB8500_USBCH_CTRL2_REG 0xC1 71#define AB8500_USBCH_CTRL2_REG 0xC1
71#define AB8500_USBCH_IPT_CRNTLVL_REG 0xC2 72#define AB8500_USBCH_IPT_CRNTLVL_REG 0xC2
73#define AB8540_USB_PP_MODE_REG 0xC5
74#define AB8540_USB_PP_CHR_REG 0xC6
72 75
73/* 76/*
74 * Gas Gauge register offsets 77 * Gas Gauge register offsets
@@ -105,6 +108,7 @@
105#define AB8500_RTC_BACKUP_CHG_REG 0x0C 108#define AB8500_RTC_BACKUP_CHG_REG 0x0C
106#define AB8500_RTC_CC_CONF_REG 0x01 109#define AB8500_RTC_CC_CONF_REG 0x01
107#define AB8500_RTC_CTRL_REG 0x0B 110#define AB8500_RTC_CTRL_REG 0x0B
111#define AB8500_RTC_CTRL1_REG 0x11
108 112
109/* 113/*
110 * OTP register offsets 114 * OTP register offsets
@@ -154,6 +158,7 @@
154#define CH_OP_CUR_LVL_1P4 0x0D 158#define CH_OP_CUR_LVL_1P4 0x0D
155#define CH_OP_CUR_LVL_1P5 0x0E 159#define CH_OP_CUR_LVL_1P5 0x0E
156#define CH_OP_CUR_LVL_1P6 0x0F 160#define CH_OP_CUR_LVL_1P6 0x0F
161#define CH_OP_CUR_LVL_2P 0x3F
157 162
158/* BTEMP High thermal limits */ 163/* BTEMP High thermal limits */
159#define BTEMP_HIGH_TH_57_0 0x00 164#define BTEMP_HIGH_TH_57_0 0x00
@@ -179,10 +184,25 @@
179#define BUP_ICH_SEL_300UA 0x08 184#define BUP_ICH_SEL_300UA 0x08
180#define BUP_ICH_SEL_700UA 0x0C 185#define BUP_ICH_SEL_700UA 0x0C
181 186
182#define BUP_VCH_SEL_2P5V 0x00 187enum bup_vch_sel {
183#define BUP_VCH_SEL_2P6V 0x01 188 BUP_VCH_SEL_2P5V,
184#define BUP_VCH_SEL_2P8V 0x02 189 BUP_VCH_SEL_2P6V,
185#define BUP_VCH_SEL_3P1V 0x03 190 BUP_VCH_SEL_2P8V,
191 BUP_VCH_SEL_3P1V,
192 /*
193 * Note that the following 5 values 2.7v, 2.9v, 3.0v, 3.2v, 3.3v
194 * are only available on ab8540. You can't choose these 5
195 * voltage on ab8500/ab8505/ab9540.
196 */
197 BUP_VCH_SEL_2P7V,
198 BUP_VCH_SEL_2P9V,
199 BUP_VCH_SEL_3P0V,
200 BUP_VCH_SEL_3P2V,
201 BUP_VCH_SEL_3P3V,
202};
203
204#define BUP_VCH_RANGE 0x02
205#define VBUP33_VRTCN 0x01
186 206
187/* Battery OVV constants */ 207/* Battery OVV constants */
188#define BATT_OVV_ENA 0x02 208#define BATT_OVV_ENA 0x02
@@ -228,6 +248,8 @@
228#define BAT_CTRL_20U_ENA 0x02 248#define BAT_CTRL_20U_ENA 0x02
229#define BAT_CTRL_18U_ENA 0x01 249#define BAT_CTRL_18U_ENA 0x01
230#define BAT_CTRL_16U_ENA 0x02 250#define BAT_CTRL_16U_ENA 0x02
251#define BAT_CTRL_60U_ENA 0x01
252#define BAT_CTRL_120U_ENA 0x02
231#define BAT_CTRL_CMP_ENA 0x04 253#define BAT_CTRL_CMP_ENA 0x04
232#define FORCE_BAT_CTRL_CMP_HIGH 0x08 254#define FORCE_BAT_CTRL_CMP_HIGH 0x08
233#define BAT_CTRL_PULL_UP_ENA 0x10 255#define BAT_CTRL_PULL_UP_ENA 0x10
@@ -235,6 +257,24 @@
235/* Battery type */ 257/* Battery type */
236#define BATTERY_UNKNOWN 00 258#define BATTERY_UNKNOWN 00
237 259
260/* Registers for pcut feature in ab8505 and ab9540 */
261#define AB8505_RTC_PCUT_CTL_STATUS_REG 0x12
262#define AB8505_RTC_PCUT_TIME_REG 0x13
263#define AB8505_RTC_PCUT_MAX_TIME_REG 0x14
264#define AB8505_RTC_PCUT_FLAG_TIME_REG 0x15
265#define AB8505_RTC_PCUT_RESTART_REG 0x16
266#define AB8505_RTC_PCUT_DEBOUNCE_REG 0x17
267
268/* USB Power Path constants for ab8540 */
269#define BUS_VSYS_VOL_SELECT_MASK 0x06
270#define BUS_VSYS_VOL_SELECT_3P6V 0x00
271#define BUS_VSYS_VOL_SELECT_3P325V 0x02
272#define BUS_VSYS_VOL_SELECT_3P9V 0x04
273#define BUS_VSYS_VOL_SELECT_4P3V 0x06
274#define BUS_POWER_PATH_MODE_ENA 0x01
275#define BUS_PP_PRECHG_CURRENT_MASK 0x0E
276#define BUS_POWER_PATH_PRECHG_ENA 0x01
277
238/** 278/**
239 * struct res_to_temp - defines one point in a temp to res curve. To 279 * struct res_to_temp - defines one point in a temp to res curve. To
240 * be used in battery packs that combines the identification resistor with a 280 * be used in battery packs that combines the identification resistor with a
@@ -283,6 +323,11 @@ struct ab8500_fg;
283 * points. 323 * points.
284 * @maint_thres This is the threshold where we stop reporting 324 * @maint_thres This is the threshold where we stop reporting
285 * battery full while in maintenance, in per cent 325 * battery full while in maintenance, in per cent
326 * @pcut_enable: Enable power cut feature in ab8505
327 * @pcut_max_time: Max time threshold
328 * @pcut_flag_time: Flagtime threshold
329 * @pcut_max_restart: Max number of restarts
330 * @pcut_debunce_time: Sets battery debounce time
286 */ 331 */
287struct ab8500_fg_parameters { 332struct ab8500_fg_parameters {
288 int recovery_sleep_timer; 333 int recovery_sleep_timer;
@@ -299,6 +344,11 @@ struct ab8500_fg_parameters {
299 int battok_raising_th_sel1; 344 int battok_raising_th_sel1;
300 int user_cap_limit; 345 int user_cap_limit;
301 int maint_thres; 346 int maint_thres;
347 bool pcut_enable;
348 u8 pcut_max_time;
349 u8 pcut_flag_time;
350 u8 pcut_max_restart;
351 u8 pcut_debunce_time;
302}; 352};
303 353
304/** 354/**
@@ -415,6 +465,7 @@ void ab8500_fg_reinit(void);
415void ab8500_charger_usb_state_changed(u8 bm_usb_state, u16 mA); 465void ab8500_charger_usb_state_changed(u8 bm_usb_state, u16 mA);
416struct ab8500_btemp *ab8500_btemp_get(void); 466struct ab8500_btemp *ab8500_btemp_get(void);
417int ab8500_btemp_get_batctrl_temp(struct ab8500_btemp *btemp); 467int ab8500_btemp_get_batctrl_temp(struct ab8500_btemp *btemp);
468int ab8500_btemp_get_temp(struct ab8500_btemp *btemp);
418struct ab8500_fg *ab8500_fg_get(void); 469struct ab8500_fg *ab8500_fg_get(void);
419int ab8500_fg_inst_curr_blocking(struct ab8500_fg *dev); 470int ab8500_fg_inst_curr_blocking(struct ab8500_fg *dev);
420int ab8500_fg_inst_curr_start(struct ab8500_fg *di); 471int ab8500_fg_inst_curr_start(struct ab8500_fg *di);
diff --git a/include/linux/mfd/abx500/ab8500-gpadc.h b/include/linux/mfd/abx500/ab8500-gpadc.h
index 252966769d93..49ded001049b 100644
--- a/include/linux/mfd/abx500/ab8500-gpadc.h
+++ b/include/linux/mfd/abx500/ab8500-gpadc.h
@@ -4,32 +4,72 @@
4 * 4 *
5 * Author: Arun R Murthy <arun.murthy@stericsson.com> 5 * Author: Arun R Murthy <arun.murthy@stericsson.com>
6 * Author: Daniel Willerud <daniel.willerud@stericsson.com> 6 * Author: Daniel Willerud <daniel.willerud@stericsson.com>
7 * Author: M'boumba Cedric Madianga <cedric.madianga@stericsson.com>
7 */ 8 */
8 9
9#ifndef _AB8500_GPADC_H 10#ifndef _AB8500_GPADC_H
10#define _AB8500_GPADC_H 11#define _AB8500_GPADC_H
11 12
12/* GPADC source: From datasheet(ADCSwSel[4:0] in GPADCCtrl2) */ 13/* GPADC source: From datasheet(ADCSwSel[4:0] in GPADCCtrl2
13#define BAT_CTRL 0x01 14 * and ADCHwSel[4:0] in GPADCCtrl3 ) */
14#define BTEMP_BALL 0x02 15#define BAT_CTRL 0x01
15#define MAIN_CHARGER_V 0x03 16#define BTEMP_BALL 0x02
16#define ACC_DETECT1 0x04 17#define MAIN_CHARGER_V 0x03
17#define ACC_DETECT2 0x05 18#define ACC_DETECT1 0x04
18#define ADC_AUX1 0x06 19#define ACC_DETECT2 0x05
19#define ADC_AUX2 0x07 20#define ADC_AUX1 0x06
20#define MAIN_BAT_V 0x08 21#define ADC_AUX2 0x07
21#define VBUS_V 0x09 22#define MAIN_BAT_V 0x08
22#define MAIN_CHARGER_C 0x0A 23#define VBUS_V 0x09
23#define USB_CHARGER_C 0x0B 24#define MAIN_CHARGER_C 0x0A
24#define BK_BAT_V 0x0C 25#define USB_CHARGER_C 0x0B
25#define DIE_TEMP 0x0D 26#define BK_BAT_V 0x0C
27#define DIE_TEMP 0x0D
28#define USB_ID 0x0E
29#define XTAL_TEMP 0x12
30#define VBAT_TRUE_MEAS 0x13
31#define BAT_CTRL_AND_IBAT 0x1C
32#define VBAT_MEAS_AND_IBAT 0x1D
33#define VBAT_TRUE_MEAS_AND_IBAT 0x1E
34#define BAT_TEMP_AND_IBAT 0x1F
35
36/* Virtual channel used only for ibat convertion to ampere
37 * Battery current conversion (ibat) cannot be requested as a single conversion
38 * but it is always in combination with other input requests
39 */
40#define IBAT_VIRTUAL_CHANNEL 0xFF
41
42#define SAMPLE_1 1
43#define SAMPLE_4 4
44#define SAMPLE_8 8
45#define SAMPLE_16 16
46#define RISING_EDGE 0
47#define FALLING_EDGE 1
48
49/* Arbitrary ADC conversion type constants */
50#define ADC_SW 0
51#define ADC_HW 1
26 52
27struct ab8500_gpadc; 53struct ab8500_gpadc;
28 54
29struct ab8500_gpadc *ab8500_gpadc_get(char *name); 55struct ab8500_gpadc *ab8500_gpadc_get(char *name);
30int ab8500_gpadc_convert(struct ab8500_gpadc *gpadc, u8 channel); 56int ab8500_gpadc_sw_hw_convert(struct ab8500_gpadc *gpadc, u8 channel,
31int ab8500_gpadc_read_raw(struct ab8500_gpadc *gpadc, u8 channel); 57 u8 avg_sample, u8 trig_edge, u8 trig_timer, u8 conv_type);
58static inline int ab8500_gpadc_convert(struct ab8500_gpadc *gpadc, u8 channel)
59{
60 return ab8500_gpadc_sw_hw_convert(gpadc, channel,
61 SAMPLE_16, 0, 0, ADC_SW);
62}
63
64int ab8500_gpadc_read_raw(struct ab8500_gpadc *gpadc, u8 channel,
65 u8 avg_sample, u8 trig_edge, u8 trig_timer, u8 conv_type);
66int ab8500_gpadc_double_read_raw(struct ab8500_gpadc *gpadc, u8 channel,
67 u8 avg_sample, u8 trig_edge, u8 trig_timer, u8 conv_type,
68 int *ibat);
32int ab8500_gpadc_ad_to_voltage(struct ab8500_gpadc *gpadc, 69int ab8500_gpadc_ad_to_voltage(struct ab8500_gpadc *gpadc,
33 u8 channel, int ad_value); 70 u8 channel, int ad_value);
71void ab8540_gpadc_get_otp(struct ab8500_gpadc *gpadc,
72 u16 *vmain_l, u16 *vmain_h, u16 *btemp_l, u16 *btemp_h,
73 u16 *vbat_l, u16 *vbat_h, u16 *ibat_l, u16 *ibat_h);
34 74
35#endif /* _AB8500_GPADC_H */ 75#endif /* _AB8500_GPADC_H */
diff --git a/include/linux/mfd/abx500/ab8500-sysctrl.h b/include/linux/mfd/abx500/ab8500-sysctrl.h
index ebf12e793db9..990bc93f46e1 100644
--- a/include/linux/mfd/abx500/ab8500-sysctrl.h
+++ b/include/linux/mfd/abx500/ab8500-sysctrl.h
@@ -12,6 +12,7 @@
12 12
13int ab8500_sysctrl_read(u16 reg, u8 *value); 13int ab8500_sysctrl_read(u16 reg, u8 *value);
14int ab8500_sysctrl_write(u16 reg, u8 mask, u8 value); 14int ab8500_sysctrl_write(u16 reg, u8 mask, u8 value);
15void ab8500_restart(char mode, const char *cmd);
15 16
16#else 17#else
17 18
@@ -40,6 +41,7 @@ static inline int ab8500_sysctrl_clear(u16 reg, u8 bits)
40/* Configuration data for SysClkReq1RfClkBuf - SysClkReq8RfClkBuf */ 41/* Configuration data for SysClkReq1RfClkBuf - SysClkReq8RfClkBuf */
41struct ab8500_sysctrl_platform_data { 42struct ab8500_sysctrl_platform_data {
42 u8 initial_req_buf_config[8]; 43 u8 initial_req_buf_config[8];
44 u16 (*reboot_reason_code)(const char *cmd);
43}; 45};
44 46
45/* Registers */ 47/* Registers */
@@ -299,4 +301,8 @@ struct ab8500_sysctrl_platform_data {
299#define AB9540_SYSCLK12BUF4VALID_SYSCLK12BUF4VALID_MASK 0xFF 301#define AB9540_SYSCLK12BUF4VALID_SYSCLK12BUF4VALID_MASK 0xFF
300#define AB9540_SYSCLK12BUF4VALID_SYSCLK12BUF4VALID_SHIFT 0 302#define AB9540_SYSCLK12BUF4VALID_SYSCLK12BUF4VALID_SHIFT 0
301 303
304#define AB8500_ENABLE_WD 0x1
305#define AB8500_KICK_WD 0x2
306#define AB8500_WD_RESTART_ON_EXPIRE 0x10
307
302#endif /* __AB8500_SYSCTRL_H */ 308#endif /* __AB8500_SYSCTRL_H */
diff --git a/include/linux/mfd/abx500/ab8500.h b/include/linux/mfd/abx500/ab8500.h
index 9db0bda446a0..fb1bf7d6a410 100644
--- a/include/linux/mfd/abx500/ab8500.h
+++ b/include/linux/mfd/abx500/ab8500.h
@@ -362,10 +362,10 @@ struct ab8500 {
362 u8 *oldmask; 362 u8 *oldmask;
363 int mask_size; 363 int mask_size;
364 const int *irq_reg_offset; 364 const int *irq_reg_offset;
365 int it_latchhier_num;
365}; 366};
366 367
367struct regulator_reg_init; 368struct ab8500_regulator_platform_data;
368struct regulator_init_data;
369struct ab8500_gpio_platform_data; 369struct ab8500_gpio_platform_data;
370struct ab8500_codec_platform_data; 370struct ab8500_codec_platform_data;
371struct ab8500_sysctrl_platform_data; 371struct ab8500_sysctrl_platform_data;
@@ -375,19 +375,13 @@ struct ab8500_sysctrl_platform_data;
375 * @irq_base: start of AB8500 IRQs, AB8500_NR_IRQS will be used 375 * @irq_base: start of AB8500 IRQs, AB8500_NR_IRQS will be used
376 * @pm_power_off: Should machine pm power off hook be registered or not 376 * @pm_power_off: Should machine pm power off hook be registered or not
377 * @init: board-specific initialization after detection of ab8500 377 * @init: board-specific initialization after detection of ab8500
378 * @num_regulator_reg_init: number of regulator init registers
379 * @regulator_reg_init: regulator init registers
380 * @num_regulator: number of regulators
381 * @regulator: machine-specific constraints for regulators 378 * @regulator: machine-specific constraints for regulators
382 */ 379 */
383struct ab8500_platform_data { 380struct ab8500_platform_data {
384 int irq_base; 381 int irq_base;
385 bool pm_power_off; 382 bool pm_power_off;
386 void (*init) (struct ab8500 *); 383 void (*init) (struct ab8500 *);
387 int num_regulator_reg_init; 384 struct ab8500_regulator_platform_data *regulator;
388 struct ab8500_regulator_reg_init *regulator_reg_init;
389 int num_regulator;
390 struct regulator_init_data *regulator;
391 struct abx500_gpio_platform_data *gpio; 385 struct abx500_gpio_platform_data *gpio;
392 struct ab8500_codec_platform_data *codec; 386 struct ab8500_codec_platform_data *codec;
393 struct ab8500_sysctrl_platform_data *sysctrl; 387 struct ab8500_sysctrl_platform_data *sysctrl;
@@ -512,6 +506,8 @@ static inline int is_ab9540_2p0_or_earlier(struct ab8500 *ab)
512 return (is_ab9540(ab) && (ab->chip_id < AB8500_CUT2P0)); 506 return (is_ab9540(ab) && (ab->chip_id < AB8500_CUT2P0));
513} 507}
514 508
509void ab8500_override_turn_on_stat(u8 mask, u8 set);
510
515#ifdef CONFIG_AB8500_DEBUG 511#ifdef CONFIG_AB8500_DEBUG
516void ab8500_dump_all_banks(struct device *dev); 512void ab8500_dump_all_banks(struct device *dev);
517void ab8500_debug_register_interrupt(int line); 513void ab8500_debug_register_interrupt(int line);
diff --git a/include/linux/mfd/abx500/ux500_chargalg.h b/include/linux/mfd/abx500/ux500_chargalg.h
index d43ac0f35526..234c99143bf7 100644
--- a/include/linux/mfd/abx500/ux500_chargalg.h
+++ b/include/linux/mfd/abx500/ux500_chargalg.h
@@ -17,8 +17,11 @@ struct ux500_charger;
17 17
18struct ux500_charger_ops { 18struct ux500_charger_ops {
19 int (*enable) (struct ux500_charger *, int, int, int); 19 int (*enable) (struct ux500_charger *, int, int, int);
20 int (*check_enable) (struct ux500_charger *, int, int);
20 int (*kick_wd) (struct ux500_charger *); 21 int (*kick_wd) (struct ux500_charger *);
21 int (*update_curr) (struct ux500_charger *, int); 22 int (*update_curr) (struct ux500_charger *, int);
23 int (*pp_enable) (struct ux500_charger *, bool);
24 int (*pre_chg_enable) (struct ux500_charger *, bool);
22}; 25};
23 26
24/** 27/**
@@ -29,6 +32,7 @@ struct ux500_charger_ops {
29 * @max_out_curr maximum output charger current in mA 32 * @max_out_curr maximum output charger current in mA
30 * @enabled indicates if this charger is used or not 33 * @enabled indicates if this charger is used or not
31 * @external external charger unit (pm2xxx) 34 * @external external charger unit (pm2xxx)
35 * @power_path USB power path support
32 */ 36 */
33struct ux500_charger { 37struct ux500_charger {
34 struct power_supply psy; 38 struct power_supply psy;
@@ -38,6 +42,9 @@ struct ux500_charger {
38 int wdt_refresh; 42 int wdt_refresh;
39 bool enabled; 43 bool enabled;
40 bool external; 44 bool external;
45 bool power_path;
41}; 46};
42 47
48extern struct blocking_notifier_head charger_notifier_list;
49
43#endif 50#endif
diff --git a/include/linux/mfd/arizona/core.h b/include/linux/mfd/arizona/core.h
index a710255528d7..cc281368dc55 100644
--- a/include/linux/mfd/arizona/core.h
+++ b/include/linux/mfd/arizona/core.h
@@ -100,6 +100,9 @@ struct arizona {
100 struct regmap_irq_chip_data *aod_irq_chip; 100 struct regmap_irq_chip_data *aod_irq_chip;
101 struct regmap_irq_chip_data *irq_chip; 101 struct regmap_irq_chip_data *irq_chip;
102 102
103 bool hpdet_magic;
104 unsigned int hp_ena;
105
103 struct mutex clk_lock; 106 struct mutex clk_lock;
104 int clk32k_ref; 107 int clk32k_ref;
105 108
diff --git a/include/linux/mfd/arizona/pdata.h b/include/linux/mfd/arizona/pdata.h
index 455c51d22d6b..80dead1f7100 100644
--- a/include/linux/mfd/arizona/pdata.h
+++ b/include/linux/mfd/arizona/pdata.h
@@ -78,6 +78,7 @@ struct arizona_micbias {
78 unsigned int ext_cap:1; /** External capacitor fitted */ 78 unsigned int ext_cap:1; /** External capacitor fitted */
79 unsigned int discharge:1; /** Actively discharge */ 79 unsigned int discharge:1; /** Actively discharge */
80 unsigned int fast_start:1; /** Enable aggressive startup ramp rate */ 80 unsigned int fast_start:1; /** Enable aggressive startup ramp rate */
81 unsigned int bypass:1; /** Use bypass mode */
81}; 82};
82 83
83struct arizona_micd_config { 84struct arizona_micd_config {
@@ -86,6 +87,11 @@ struct arizona_micd_config {
86 bool gpio; 87 bool gpio;
87}; 88};
88 89
90struct arizona_micd_range {
91 int max; /** Ohms */
92 int key; /** Key to report to input layer */
93};
94
89struct arizona_pdata { 95struct arizona_pdata {
90 int reset; /** GPIO controlling /RESET, if any */ 96 int reset; /** GPIO controlling /RESET, if any */
91 int ldoena; /** GPIO controlling LODENA, if any */ 97 int ldoena; /** GPIO controlling LODENA, if any */
@@ -99,7 +105,8 @@ struct arizona_pdata {
99 /** If a direct 32kHz clock is provided on an MCLK specify it here */ 105 /** If a direct 32kHz clock is provided on an MCLK specify it here */
100 int clk32k_src; 106 int clk32k_src;
101 107
102 bool irq_active_high; /** IRQ polarity */ 108 /** Mode for primary IRQ (defaults to active low) */
109 unsigned int irq_flags;
103 110
104 /* Base GPIO */ 111 /* Base GPIO */
105 int gpio_base; 112 int gpio_base;
@@ -117,12 +124,21 @@ struct arizona_pdata {
117 /** GPIO5 is used for jack detection */ 124 /** GPIO5 is used for jack detection */
118 bool jd_gpio5; 125 bool jd_gpio5;
119 126
127 /** Internal pull on GPIO5 is disabled when used for jack detection */
128 bool jd_gpio5_nopull;
129
120 /** Use the headphone detect circuit to identify the accessory */ 130 /** Use the headphone detect circuit to identify the accessory */
121 bool hpdet_acc_id; 131 bool hpdet_acc_id;
122 132
133 /** Check for line output with HPDET method */
134 bool hpdet_acc_id_line;
135
123 /** GPIO used for mic isolation with HPDET */ 136 /** GPIO used for mic isolation with HPDET */
124 int hpdet_id_gpio; 137 int hpdet_id_gpio;
125 138
139 /** Extra debounce timeout used during initial mic detection (ms) */
140 int micd_detect_debounce;
141
126 /** GPIO for mic detection polarity */ 142 /** GPIO for mic detection polarity */
127 int micd_pol_gpio; 143 int micd_pol_gpio;
128 144
@@ -135,9 +151,16 @@ struct arizona_pdata {
135 /** Mic detect debounce level */ 151 /** Mic detect debounce level */
136 int micd_dbtime; 152 int micd_dbtime;
137 153
154 /** Mic detect timeout (ms) */
155 int micd_timeout;
156
138 /** Force MICBIAS on for mic detect */ 157 /** Force MICBIAS on for mic detect */
139 bool micd_force_micbias; 158 bool micd_force_micbias;
140 159
160 /** Mic detect level parameters */
161 const struct arizona_micd_range *micd_ranges;
162 int num_micd_ranges;
163
141 /** Headset polarity configurations */ 164 /** Headset polarity configurations */
142 struct arizona_micd_config *micd_configs; 165 struct arizona_micd_config *micd_configs;
143 int num_micd_configs; 166 int num_micd_configs;
@@ -162,6 +185,9 @@ struct arizona_pdata {
162 185
163 /** Haptic actuator type */ 186 /** Haptic actuator type */
164 unsigned int hap_act; 187 unsigned int hap_act;
188
189 /** GPIO for primary IRQ (used for edge triggered emulation) */
190 int irq_gpio;
165}; 191};
166 192
167#endif 193#endif
diff --git a/include/linux/mfd/arizona/registers.h b/include/linux/mfd/arizona/registers.h
index 340355136069..715b6ba3d52a 100644
--- a/include/linux/mfd/arizona/registers.h
+++ b/include/linux/mfd/arizona/registers.h
@@ -85,12 +85,14 @@
85#define ARIZONA_FLL1_CONTROL_6 0x176 85#define ARIZONA_FLL1_CONTROL_6 0x176
86#define ARIZONA_FLL1_LOOP_FILTER_TEST_1 0x177 86#define ARIZONA_FLL1_LOOP_FILTER_TEST_1 0x177
87#define ARIZONA_FLL1_NCO_TEST_0 0x178 87#define ARIZONA_FLL1_NCO_TEST_0 0x178
88#define ARIZONA_FLL1_CONTROL_7 0x179
88#define ARIZONA_FLL1_SYNCHRONISER_1 0x181 89#define ARIZONA_FLL1_SYNCHRONISER_1 0x181
89#define ARIZONA_FLL1_SYNCHRONISER_2 0x182 90#define ARIZONA_FLL1_SYNCHRONISER_2 0x182
90#define ARIZONA_FLL1_SYNCHRONISER_3 0x183 91#define ARIZONA_FLL1_SYNCHRONISER_3 0x183
91#define ARIZONA_FLL1_SYNCHRONISER_4 0x184 92#define ARIZONA_FLL1_SYNCHRONISER_4 0x184
92#define ARIZONA_FLL1_SYNCHRONISER_5 0x185 93#define ARIZONA_FLL1_SYNCHRONISER_5 0x185
93#define ARIZONA_FLL1_SYNCHRONISER_6 0x186 94#define ARIZONA_FLL1_SYNCHRONISER_6 0x186
95#define ARIZONA_FLL1_SYNCHRONISER_7 0x187
94#define ARIZONA_FLL1_SPREAD_SPECTRUM 0x189 96#define ARIZONA_FLL1_SPREAD_SPECTRUM 0x189
95#define ARIZONA_FLL1_GPIO_CLOCK 0x18A 97#define ARIZONA_FLL1_GPIO_CLOCK 0x18A
96#define ARIZONA_FLL2_CONTROL_1 0x191 98#define ARIZONA_FLL2_CONTROL_1 0x191
@@ -101,12 +103,14 @@
101#define ARIZONA_FLL2_CONTROL_6 0x196 103#define ARIZONA_FLL2_CONTROL_6 0x196
102#define ARIZONA_FLL2_LOOP_FILTER_TEST_1 0x197 104#define ARIZONA_FLL2_LOOP_FILTER_TEST_1 0x197
103#define ARIZONA_FLL2_NCO_TEST_0 0x198 105#define ARIZONA_FLL2_NCO_TEST_0 0x198
106#define ARIZONA_FLL2_CONTROL_7 0x199
104#define ARIZONA_FLL2_SYNCHRONISER_1 0x1A1 107#define ARIZONA_FLL2_SYNCHRONISER_1 0x1A1
105#define ARIZONA_FLL2_SYNCHRONISER_2 0x1A2 108#define ARIZONA_FLL2_SYNCHRONISER_2 0x1A2
106#define ARIZONA_FLL2_SYNCHRONISER_3 0x1A3 109#define ARIZONA_FLL2_SYNCHRONISER_3 0x1A3
107#define ARIZONA_FLL2_SYNCHRONISER_4 0x1A4 110#define ARIZONA_FLL2_SYNCHRONISER_4 0x1A4
108#define ARIZONA_FLL2_SYNCHRONISER_5 0x1A5 111#define ARIZONA_FLL2_SYNCHRONISER_5 0x1A5
109#define ARIZONA_FLL2_SYNCHRONISER_6 0x1A6 112#define ARIZONA_FLL2_SYNCHRONISER_6 0x1A6
113#define ARIZONA_FLL2_SYNCHRONISER_7 0x1A7
110#define ARIZONA_FLL2_SPREAD_SPECTRUM 0x1A9 114#define ARIZONA_FLL2_SPREAD_SPECTRUM 0x1A9
111#define ARIZONA_FLL2_GPIO_CLOCK 0x1AA 115#define ARIZONA_FLL2_GPIO_CLOCK 0x1AA
112#define ARIZONA_MIC_CHARGE_PUMP_1 0x200 116#define ARIZONA_MIC_CHARGE_PUMP_1 0x200
@@ -124,6 +128,10 @@
124#define ARIZONA_MIC_DETECT_1 0x2A3 128#define ARIZONA_MIC_DETECT_1 0x2A3
125#define ARIZONA_MIC_DETECT_2 0x2A4 129#define ARIZONA_MIC_DETECT_2 0x2A4
126#define ARIZONA_MIC_DETECT_3 0x2A5 130#define ARIZONA_MIC_DETECT_3 0x2A5
131#define ARIZONA_MIC_DETECT_LEVEL_1 0x2A6
132#define ARIZONA_MIC_DETECT_LEVEL_2 0x2A7
133#define ARIZONA_MIC_DETECT_LEVEL_3 0x2A8
134#define ARIZONA_MIC_DETECT_LEVEL_4 0x2A9
127#define ARIZONA_MIC_NOISE_MIX_CONTROL_1 0x2C3 135#define ARIZONA_MIC_NOISE_MIX_CONTROL_1 0x2C3
128#define ARIZONA_ISOLATION_CONTROL 0x2CB 136#define ARIZONA_ISOLATION_CONTROL 0x2CB
129#define ARIZONA_JACK_DETECT_ANALOGUE 0x2D3 137#define ARIZONA_JACK_DETECT_ANALOGUE 0x2D3
@@ -213,6 +221,8 @@
213#define ARIZONA_PDM_SPK1_CTRL_2 0x491 221#define ARIZONA_PDM_SPK1_CTRL_2 0x491
214#define ARIZONA_PDM_SPK2_CTRL_1 0x492 222#define ARIZONA_PDM_SPK2_CTRL_1 0x492
215#define ARIZONA_PDM_SPK2_CTRL_2 0x493 223#define ARIZONA_PDM_SPK2_CTRL_2 0x493
224#define ARIZONA_SPK_CTRL_2 0x4B5
225#define ARIZONA_SPK_CTRL_3 0x4B6
216#define ARIZONA_DAC_COMP_1 0x4DC 226#define ARIZONA_DAC_COMP_1 0x4DC
217#define ARIZONA_DAC_COMP_2 0x4DD 227#define ARIZONA_DAC_COMP_2 0x4DD
218#define ARIZONA_DAC_COMP_3 0x4DE 228#define ARIZONA_DAC_COMP_3 0x4DE
@@ -1678,6 +1688,13 @@
1678#define ARIZONA_FLL1_FRC_INTEG_VAL_WIDTH 12 /* FLL1_FRC_INTEG_VAL - [11:0] */ 1688#define ARIZONA_FLL1_FRC_INTEG_VAL_WIDTH 12 /* FLL1_FRC_INTEG_VAL - [11:0] */
1679 1689
1680/* 1690/*
1691 * R377 (0x179) - FLL1 Control 7
1692 */
1693#define ARIZONA_FLL1_GAIN_MASK 0x003c /* FLL1_GAIN */
1694#define ARIZONA_FLL1_GAIN_SHIFT 2 /* FLL1_GAIN */
1695#define ARIZONA_FLL1_GAIN_WIDTH 4 /* FLL1_GAIN */
1696
1697/*
1681 * R385 (0x181) - FLL1 Synchroniser 1 1698 * R385 (0x181) - FLL1 Synchroniser 1
1682 */ 1699 */
1683#define ARIZONA_FLL1_SYNC_ENA 0x0001 /* FLL1_SYNC_ENA */ 1700#define ARIZONA_FLL1_SYNC_ENA 0x0001 /* FLL1_SYNC_ENA */
@@ -1724,6 +1741,17 @@
1724#define ARIZONA_FLL1_CLK_SYNC_SRC_WIDTH 4 /* FLL1_CLK_SYNC_SRC - [3:0] */ 1741#define ARIZONA_FLL1_CLK_SYNC_SRC_WIDTH 4 /* FLL1_CLK_SYNC_SRC - [3:0] */
1725 1742
1726/* 1743/*
1744 * R391 (0x187) - FLL1 Synchroniser 7
1745 */
1746#define ARIZONA_FLL1_SYNC_GAIN_MASK 0x003c /* FLL1_SYNC_GAIN */
1747#define ARIZONA_FLL1_SYNC_GAIN_SHIFT 2 /* FLL1_SYNC_GAIN */
1748#define ARIZONA_FLL1_SYNC_GAIN_WIDTH 4 /* FLL1_SYNC_GAIN */
1749#define ARIZONA_FLL1_SYNC_BW 0x0001 /* FLL1_SYNC_BW */
1750#define ARIZONA_FLL1_SYNC_BW_MASK 0x0001 /* FLL1_SYNC_BW */
1751#define ARIZONA_FLL1_SYNC_BW_SHIFT 0 /* FLL1_SYNC_BW */
1752#define ARIZONA_FLL1_SYNC_BW_WIDTH 1 /* FLL1_SYNC_BW */
1753
1754/*
1727 * R393 (0x189) - FLL1 Spread Spectrum 1755 * R393 (0x189) - FLL1 Spread Spectrum
1728 */ 1756 */
1729#define ARIZONA_FLL1_SS_AMPL_MASK 0x0030 /* FLL1_SS_AMPL - [5:4] */ 1757#define ARIZONA_FLL1_SS_AMPL_MASK 0x0030 /* FLL1_SS_AMPL - [5:4] */
@@ -1816,6 +1844,13 @@
1816#define ARIZONA_FLL2_FRC_INTEG_VAL_WIDTH 12 /* FLL2_FRC_INTEG_VAL - [11:0] */ 1844#define ARIZONA_FLL2_FRC_INTEG_VAL_WIDTH 12 /* FLL2_FRC_INTEG_VAL - [11:0] */
1817 1845
1818/* 1846/*
1847 * R409 (0x199) - FLL2 Control 7
1848 */
1849#define ARIZONA_FLL2_GAIN_MASK 0x003c /* FLL2_GAIN */
1850#define ARIZONA_FLL2_GAIN_SHIFT 2 /* FLL2_GAIN */
1851#define ARIZONA_FLL2_GAIN_WIDTH 4 /* FLL2_GAIN */
1852
1853/*
1819 * R417 (0x1A1) - FLL2 Synchroniser 1 1854 * R417 (0x1A1) - FLL2 Synchroniser 1
1820 */ 1855 */
1821#define ARIZONA_FLL2_SYNC_ENA 0x0001 /* FLL2_SYNC_ENA */ 1856#define ARIZONA_FLL2_SYNC_ENA 0x0001 /* FLL2_SYNC_ENA */
@@ -1862,6 +1897,17 @@
1862#define ARIZONA_FLL2_CLK_SYNC_SRC_WIDTH 4 /* FLL2_CLK_SYNC_SRC - [3:0] */ 1897#define ARIZONA_FLL2_CLK_SYNC_SRC_WIDTH 4 /* FLL2_CLK_SYNC_SRC - [3:0] */
1863 1898
1864/* 1899/*
1900 * R423 (0x1A7) - FLL2 Synchroniser 7
1901 */
1902#define ARIZONA_FLL2_SYNC_GAIN_MASK 0x003c /* FLL2_SYNC_GAIN */
1903#define ARIZONA_FLL2_SYNC_GAIN_SHIFT 2 /* FLL2_SYNC_GAIN */
1904#define ARIZONA_FLL2_SYNC_GAIN_WIDTH 4 /* FLL2_SYNC_GAIN */
1905#define ARIZONA_FLL2_SYNC_BW_MASK 0x0001 /* FLL2_SYNC_BW */
1906#define ARIZONA_FLL2_SYNC_BW_MASK 0x0001 /* FLL2_SYNC_BW */
1907#define ARIZONA_FLL2_SYNC_BW_SHIFT 0 /* FLL2_SYNC_BW */
1908#define ARIZONA_FLL2_SYNC_BW_WIDTH 1 /* FLL2_SYNC_BW */
1909
1910/*
1865 * R425 (0x1A9) - FLL2 Spread Spectrum 1911 * R425 (0x1A9) - FLL2 Spread Spectrum
1866 */ 1912 */
1867#define ARIZONA_FLL2_SS_AMPL_MASK 0x0030 /* FLL2_SS_AMPL - [5:4] */ 1913#define ARIZONA_FLL2_SS_AMPL_MASK 0x0030 /* FLL2_SS_AMPL - [5:4] */
diff --git a/include/linux/mfd/cros_ec.h b/include/linux/mfd/cros_ec.h
new file mode 100644
index 000000000000..032af7fc5b2e
--- /dev/null
+++ b/include/linux/mfd/cros_ec.h
@@ -0,0 +1,170 @@
1/*
2 * ChromeOS EC multi-function device
3 *
4 * Copyright (C) 2012 Google, Inc
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#ifndef __LINUX_MFD_CROS_EC_H
17#define __LINUX_MFD_CROS_EC_H
18
19#include <linux/mfd/cros_ec_commands.h>
20
21/*
22 * Command interface between EC and AP, for LPC, I2C and SPI interfaces.
23 */
24enum {
25 EC_MSG_TX_HEADER_BYTES = 3,
26 EC_MSG_TX_TRAILER_BYTES = 1,
27 EC_MSG_TX_PROTO_BYTES = EC_MSG_TX_HEADER_BYTES +
28 EC_MSG_TX_TRAILER_BYTES,
29 EC_MSG_RX_PROTO_BYTES = 3,
30
31 /* Max length of messages */
32 EC_MSG_BYTES = EC_HOST_PARAM_SIZE + EC_MSG_TX_PROTO_BYTES,
33
34};
35
36/**
37 * struct cros_ec_msg - A message sent to the EC, and its reply
38 *
39 * @version: Command version number (often 0)
40 * @cmd: Command to send (EC_CMD_...)
41 * @out_buf: Outgoing payload (to EC)
42 * @outlen: Outgoing length
43 * @in_buf: Incoming payload (from EC)
44 * @in_len: Incoming length
45 */
46struct cros_ec_msg {
47 u8 version;
48 u8 cmd;
49 uint8_t *out_buf;
50 int out_len;
51 uint8_t *in_buf;
52 int in_len;
53};
54
55/**
56 * struct cros_ec_device - Information about a ChromeOS EC device
57 *
58 * @name: Name of this EC interface
59 * @priv: Private data
60 * @irq: Interrupt to use
61 * @din: input buffer (from EC)
62 * @dout: output buffer (to EC)
63 * \note
64 * These two buffers will always be dword-aligned and include enough
65 * space for up to 7 word-alignment bytes also, so we can ensure that
66 * the body of the message is always dword-aligned (64-bit).
67 *
68 * We use this alignment to keep ARM and x86 happy. Probably word
69 * alignment would be OK, there might be a small performance advantage
70 * to using dword.
71 * @din_size: size of din buffer
72 * @dout_size: size of dout buffer
73 * @command_send: send a command
74 * @command_recv: receive a command
75 * @ec_name: name of EC device (e.g. 'chromeos-ec')
76 * @phys_name: name of physical comms layer (e.g. 'i2c-4')
77 * @parent: pointer to parent device (e.g. i2c or spi device)
78 * @dev: Device pointer
79 * dev_lock: Lock to prevent concurrent access
80 * @wake_enabled: true if this device can wake the system from sleep
81 * @was_wake_device: true if this device was set to wake the system from
82 * sleep at the last suspend
83 * @event_notifier: interrupt event notifier for transport devices
84 */
85struct cros_ec_device {
86 const char *name;
87 void *priv;
88 int irq;
89 uint8_t *din;
90 uint8_t *dout;
91 int din_size;
92 int dout_size;
93 int (*command_send)(struct cros_ec_device *ec,
94 uint16_t cmd, void *out_buf, int out_len);
95 int (*command_recv)(struct cros_ec_device *ec,
96 uint16_t cmd, void *in_buf, int in_len);
97 int (*command_sendrecv)(struct cros_ec_device *ec,
98 uint16_t cmd, void *out_buf, int out_len,
99 void *in_buf, int in_len);
100 int (*command_xfer)(struct cros_ec_device *ec,
101 struct cros_ec_msg *msg);
102
103 const char *ec_name;
104 const char *phys_name;
105 struct device *parent;
106
107 /* These are --private-- fields - do not assign */
108 struct device *dev;
109 struct mutex dev_lock;
110 bool wake_enabled;
111 bool was_wake_device;
112 struct blocking_notifier_head event_notifier;
113};
114
115/**
116 * cros_ec_suspend - Handle a suspend operation for the ChromeOS EC device
117 *
118 * This can be called by drivers to handle a suspend event.
119 *
120 * ec_dev: Device to suspend
121 * @return 0 if ok, -ve on error
122 */
123int cros_ec_suspend(struct cros_ec_device *ec_dev);
124
125/**
126 * cros_ec_resume - Handle a resume operation for the ChromeOS EC device
127 *
128 * This can be called by drivers to handle a resume event.
129 *
130 * @ec_dev: Device to resume
131 * @return 0 if ok, -ve on error
132 */
133int cros_ec_resume(struct cros_ec_device *ec_dev);
134
135/**
136 * cros_ec_prepare_tx - Prepare an outgoing message in the output buffer
137 *
138 * This is intended to be used by all ChromeOS EC drivers, but at present
139 * only SPI uses it. Once LPC uses the same protocol it can start using it.
140 * I2C could use it now, with a refactor of the existing code.
141 *
142 * @ec_dev: Device to register
143 * @msg: Message to write
144 */
145int cros_ec_prepare_tx(struct cros_ec_device *ec_dev,
146 struct cros_ec_msg *msg);
147
148/**
149 * cros_ec_remove - Remove a ChromeOS EC
150 *
151 * Call this to deregister a ChromeOS EC. After this you should call
152 * cros_ec_free().
153 *
154 * @ec_dev: Device to register
155 * @return 0 if ok, -ve on error
156 */
157int cros_ec_remove(struct cros_ec_device *ec_dev);
158
159/**
160 * cros_ec_register - Register a new ChromeOS EC, using the provided info
161 *
162 * Before calling this, allocate a pointer to a new device and then fill
163 * in all the fields up to the --private-- marker.
164 *
165 * @ec_dev: Device to register
166 * @return 0 if ok, -ve on error
167 */
168int cros_ec_register(struct cros_ec_device *ec_dev);
169
170#endif /* __LINUX_MFD_CROS_EC_H */
diff --git a/include/linux/mfd/cros_ec_commands.h b/include/linux/mfd/cros_ec_commands.h
new file mode 100644
index 000000000000..86fd06953bcd
--- /dev/null
+++ b/include/linux/mfd/cros_ec_commands.h
@@ -0,0 +1,1369 @@
1/*
2 * Host communication command constants for ChromeOS EC
3 *
4 * Copyright (C) 2012 Google, Inc
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * The ChromeOS EC multi function device is used to mux all the requests
16 * to the EC device for its multiple features: keyboard controller,
17 * battery charging and regulator control, firmware update.
18 *
19 * NOTE: This file is copied verbatim from the ChromeOS EC Open Source
20 * project in an attempt to make future updates easy to make.
21 */
22
23#ifndef __CROS_EC_COMMANDS_H
24#define __CROS_EC_COMMANDS_H
25
26/*
27 * Protocol overview
28 *
29 * request: CMD [ P0 P1 P2 ... Pn S ]
30 * response: ERR [ P0 P1 P2 ... Pn S ]
31 *
32 * where the bytes are defined as follow :
33 * - CMD is the command code. (defined by EC_CMD_ constants)
34 * - ERR is the error code. (defined by EC_RES_ constants)
35 * - Px is the optional payload.
36 * it is not sent if the error code is not success.
37 * (defined by ec_params_ and ec_response_ structures)
38 * - S is the checksum which is the sum of all payload bytes.
39 *
40 * On LPC, CMD and ERR are sent/received at EC_LPC_ADDR_KERNEL|USER_CMD
41 * and the payloads are sent/received at EC_LPC_ADDR_KERNEL|USER_PARAM.
42 * On I2C, all bytes are sent serially in the same message.
43 */
44
45/* Current version of this protocol */
46#define EC_PROTO_VERSION 0x00000002
47
48/* Command version mask */
49#define EC_VER_MASK(version) (1UL << (version))
50
51/* I/O addresses for ACPI commands */
52#define EC_LPC_ADDR_ACPI_DATA 0x62
53#define EC_LPC_ADDR_ACPI_CMD 0x66
54
55/* I/O addresses for host command */
56#define EC_LPC_ADDR_HOST_DATA 0x200
57#define EC_LPC_ADDR_HOST_CMD 0x204
58
59/* I/O addresses for host command args and params */
60#define EC_LPC_ADDR_HOST_ARGS 0x800
61#define EC_LPC_ADDR_HOST_PARAM 0x804
62#define EC_HOST_PARAM_SIZE 0x0fc /* Size of param area in bytes */
63
64/* I/O addresses for host command params, old interface */
65#define EC_LPC_ADDR_OLD_PARAM 0x880
66#define EC_OLD_PARAM_SIZE 0x080 /* Size of param area in bytes */
67
68/* EC command register bit functions */
69#define EC_LPC_CMDR_DATA (1 << 0) /* Data ready for host to read */
70#define EC_LPC_CMDR_PENDING (1 << 1) /* Write pending to EC */
71#define EC_LPC_CMDR_BUSY (1 << 2) /* EC is busy processing a command */
72#define EC_LPC_CMDR_CMD (1 << 3) /* Last host write was a command */
73#define EC_LPC_CMDR_ACPI_BRST (1 << 4) /* Burst mode (not used) */
74#define EC_LPC_CMDR_SCI (1 << 5) /* SCI event is pending */
75#define EC_LPC_CMDR_SMI (1 << 6) /* SMI event is pending */
76
77#define EC_LPC_ADDR_MEMMAP 0x900
78#define EC_MEMMAP_SIZE 255 /* ACPI IO buffer max is 255 bytes */
79#define EC_MEMMAP_TEXT_MAX 8 /* Size of a string in the memory map */
80
81/* The offset address of each type of data in mapped memory. */
82#define EC_MEMMAP_TEMP_SENSOR 0x00 /* Temp sensors */
83#define EC_MEMMAP_FAN 0x10 /* Fan speeds */
84#define EC_MEMMAP_TEMP_SENSOR_B 0x18 /* Temp sensors (second set) */
85#define EC_MEMMAP_ID 0x20 /* 'E' 'C' */
86#define EC_MEMMAP_ID_VERSION 0x22 /* Version of data in 0x20 - 0x2f */
87#define EC_MEMMAP_THERMAL_VERSION 0x23 /* Version of data in 0x00 - 0x1f */
88#define EC_MEMMAP_BATTERY_VERSION 0x24 /* Version of data in 0x40 - 0x7f */
89#define EC_MEMMAP_SWITCHES_VERSION 0x25 /* Version of data in 0x30 - 0x33 */
90#define EC_MEMMAP_EVENTS_VERSION 0x26 /* Version of data in 0x34 - 0x3f */
91#define EC_MEMMAP_HOST_CMD_FLAGS 0x27 /* Host command interface flags */
92#define EC_MEMMAP_SWITCHES 0x30
93#define EC_MEMMAP_HOST_EVENTS 0x34
94#define EC_MEMMAP_BATT_VOLT 0x40 /* Battery Present Voltage */
95#define EC_MEMMAP_BATT_RATE 0x44 /* Battery Present Rate */
96#define EC_MEMMAP_BATT_CAP 0x48 /* Battery Remaining Capacity */
97#define EC_MEMMAP_BATT_FLAG 0x4c /* Battery State, defined below */
98#define EC_MEMMAP_BATT_DCAP 0x50 /* Battery Design Capacity */
99#define EC_MEMMAP_BATT_DVLT 0x54 /* Battery Design Voltage */
100#define EC_MEMMAP_BATT_LFCC 0x58 /* Battery Last Full Charge Capacity */
101#define EC_MEMMAP_BATT_CCNT 0x5c /* Battery Cycle Count */
102#define EC_MEMMAP_BATT_MFGR 0x60 /* Battery Manufacturer String */
103#define EC_MEMMAP_BATT_MODEL 0x68 /* Battery Model Number String */
104#define EC_MEMMAP_BATT_SERIAL 0x70 /* Battery Serial Number String */
105#define EC_MEMMAP_BATT_TYPE 0x78 /* Battery Type String */
106
107/* Number of temp sensors at EC_MEMMAP_TEMP_SENSOR */
108#define EC_TEMP_SENSOR_ENTRIES 16
109/*
110 * Number of temp sensors at EC_MEMMAP_TEMP_SENSOR_B.
111 *
112 * Valid only if EC_MEMMAP_THERMAL_VERSION returns >= 2.
113 */
114#define EC_TEMP_SENSOR_B_ENTRIES 8
115#define EC_TEMP_SENSOR_NOT_PRESENT 0xff
116#define EC_TEMP_SENSOR_ERROR 0xfe
117#define EC_TEMP_SENSOR_NOT_POWERED 0xfd
118#define EC_TEMP_SENSOR_NOT_CALIBRATED 0xfc
119/*
120 * The offset of temperature value stored in mapped memory. This allows
121 * reporting a temperature range of 200K to 454K = -73C to 181C.
122 */
123#define EC_TEMP_SENSOR_OFFSET 200
124
125#define EC_FAN_SPEED_ENTRIES 4 /* Number of fans at EC_MEMMAP_FAN */
126#define EC_FAN_SPEED_NOT_PRESENT 0xffff /* Entry not present */
127#define EC_FAN_SPEED_STALLED 0xfffe /* Fan stalled */
128
129/* Battery bit flags at EC_MEMMAP_BATT_FLAG. */
130#define EC_BATT_FLAG_AC_PRESENT 0x01
131#define EC_BATT_FLAG_BATT_PRESENT 0x02
132#define EC_BATT_FLAG_DISCHARGING 0x04
133#define EC_BATT_FLAG_CHARGING 0x08
134#define EC_BATT_FLAG_LEVEL_CRITICAL 0x10
135
136/* Switch flags at EC_MEMMAP_SWITCHES */
137#define EC_SWITCH_LID_OPEN 0x01
138#define EC_SWITCH_POWER_BUTTON_PRESSED 0x02
139#define EC_SWITCH_WRITE_PROTECT_DISABLED 0x04
140/* Recovery requested via keyboard */
141#define EC_SWITCH_KEYBOARD_RECOVERY 0x08
142/* Recovery requested via dedicated signal (from servo board) */
143#define EC_SWITCH_DEDICATED_RECOVERY 0x10
144/* Was fake developer mode switch; now unused. Remove in next refactor. */
145#define EC_SWITCH_IGNORE0 0x20
146
147/* Host command interface flags */
148/* Host command interface supports LPC args (LPC interface only) */
149#define EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED 0x01
150
151/* Wireless switch flags */
152#define EC_WIRELESS_SWITCH_WLAN 0x01
153#define EC_WIRELESS_SWITCH_BLUETOOTH 0x02
154
155/*
156 * This header file is used in coreboot both in C and ACPI code. The ACPI code
157 * is pre-processed to handle constants but the ASL compiler is unable to
158 * handle actual C code so keep it separate.
159 */
160#ifndef __ACPI__
161
162/* LPC command status byte masks */
163/* EC has written a byte in the data register and host hasn't read it yet */
164#define EC_LPC_STATUS_TO_HOST 0x01
165/* Host has written a command/data byte and the EC hasn't read it yet */
166#define EC_LPC_STATUS_FROM_HOST 0x02
167/* EC is processing a command */
168#define EC_LPC_STATUS_PROCESSING 0x04
169/* Last write to EC was a command, not data */
170#define EC_LPC_STATUS_LAST_CMD 0x08
171/* EC is in burst mode. Unsupported by Chrome EC, so this bit is never set */
172#define EC_LPC_STATUS_BURST_MODE 0x10
173/* SCI event is pending (requesting SCI query) */
174#define EC_LPC_STATUS_SCI_PENDING 0x20
175/* SMI event is pending (requesting SMI query) */
176#define EC_LPC_STATUS_SMI_PENDING 0x40
177/* (reserved) */
178#define EC_LPC_STATUS_RESERVED 0x80
179
180/*
181 * EC is busy. This covers both the EC processing a command, and the host has
182 * written a new command but the EC hasn't picked it up yet.
183 */
184#define EC_LPC_STATUS_BUSY_MASK \
185 (EC_LPC_STATUS_FROM_HOST | EC_LPC_STATUS_PROCESSING)
186
187/* Host command response codes */
188enum ec_status {
189 EC_RES_SUCCESS = 0,
190 EC_RES_INVALID_COMMAND = 1,
191 EC_RES_ERROR = 2,
192 EC_RES_INVALID_PARAM = 3,
193 EC_RES_ACCESS_DENIED = 4,
194 EC_RES_INVALID_RESPONSE = 5,
195 EC_RES_INVALID_VERSION = 6,
196 EC_RES_INVALID_CHECKSUM = 7,
197 EC_RES_IN_PROGRESS = 8, /* Accepted, command in progress */
198 EC_RES_UNAVAILABLE = 9, /* No response available */
199 EC_RES_TIMEOUT = 10, /* We got a timeout */
200 EC_RES_OVERFLOW = 11, /* Table / data overflow */
201};
202
203/*
204 * Host event codes. Note these are 1-based, not 0-based, because ACPI query
205 * EC command uses code 0 to mean "no event pending". We explicitly specify
206 * each value in the enum listing so they won't change if we delete/insert an
207 * item or rearrange the list (it needs to be stable across platforms, not
208 * just within a single compiled instance).
209 */
210enum host_event_code {
211 EC_HOST_EVENT_LID_CLOSED = 1,
212 EC_HOST_EVENT_LID_OPEN = 2,
213 EC_HOST_EVENT_POWER_BUTTON = 3,
214 EC_HOST_EVENT_AC_CONNECTED = 4,
215 EC_HOST_EVENT_AC_DISCONNECTED = 5,
216 EC_HOST_EVENT_BATTERY_LOW = 6,
217 EC_HOST_EVENT_BATTERY_CRITICAL = 7,
218 EC_HOST_EVENT_BATTERY = 8,
219 EC_HOST_EVENT_THERMAL_THRESHOLD = 9,
220 EC_HOST_EVENT_THERMAL_OVERLOAD = 10,
221 EC_HOST_EVENT_THERMAL = 11,
222 EC_HOST_EVENT_USB_CHARGER = 12,
223 EC_HOST_EVENT_KEY_PRESSED = 13,
224 /*
225 * EC has finished initializing the host interface. The host can check
226 * for this event following sending a EC_CMD_REBOOT_EC command to
227 * determine when the EC is ready to accept subsequent commands.
228 */
229 EC_HOST_EVENT_INTERFACE_READY = 14,
230 /* Keyboard recovery combo has been pressed */
231 EC_HOST_EVENT_KEYBOARD_RECOVERY = 15,
232
233 /* Shutdown due to thermal overload */
234 EC_HOST_EVENT_THERMAL_SHUTDOWN = 16,
235 /* Shutdown due to battery level too low */
236 EC_HOST_EVENT_BATTERY_SHUTDOWN = 17,
237
238 /*
239 * The high bit of the event mask is not used as a host event code. If
240 * it reads back as set, then the entire event mask should be
241 * considered invalid by the host. This can happen when reading the
242 * raw event status via EC_MEMMAP_HOST_EVENTS but the LPC interface is
243 * not initialized on the EC, or improperly configured on the host.
244 */
245 EC_HOST_EVENT_INVALID = 32
246};
247/* Host event mask */
248#define EC_HOST_EVENT_MASK(event_code) (1UL << ((event_code) - 1))
249
250/* Arguments at EC_LPC_ADDR_HOST_ARGS */
251struct ec_lpc_host_args {
252 uint8_t flags;
253 uint8_t command_version;
254 uint8_t data_size;
255 /*
256 * Checksum; sum of command + flags + command_version + data_size +
257 * all params/response data bytes.
258 */
259 uint8_t checksum;
260} __packed;
261
262/* Flags for ec_lpc_host_args.flags */
263/*
264 * Args are from host. Data area at EC_LPC_ADDR_HOST_PARAM contains command
265 * params.
266 *
267 * If EC gets a command and this flag is not set, this is an old-style command.
268 * Command version is 0 and params from host are at EC_LPC_ADDR_OLD_PARAM with
269 * unknown length. EC must respond with an old-style response (that is,
270 * withouth setting EC_HOST_ARGS_FLAG_TO_HOST).
271 */
272#define EC_HOST_ARGS_FLAG_FROM_HOST 0x01
273/*
274 * Args are from EC. Data area at EC_LPC_ADDR_HOST_PARAM contains response.
275 *
276 * If EC responds to a command and this flag is not set, this is an old-style
277 * response. Command version is 0 and response data from EC is at
278 * EC_LPC_ADDR_OLD_PARAM with unknown length.
279 */
280#define EC_HOST_ARGS_FLAG_TO_HOST 0x02
281
282/*
283 * Notes on commands:
284 *
285 * Each command is an 8-byte command value. Commands which take params or
286 * return response data specify structs for that data. If no struct is
287 * specified, the command does not input or output data, respectively.
288 * Parameter/response length is implicit in the structs. Some underlying
289 * communication protocols (I2C, SPI) may add length or checksum headers, but
290 * those are implementation-dependent and not defined here.
291 */
292
293/*****************************************************************************/
294/* General / test commands */
295
296/*
297 * Get protocol version, used to deal with non-backward compatible protocol
298 * changes.
299 */
300#define EC_CMD_PROTO_VERSION 0x00
301
302struct ec_response_proto_version {
303 uint32_t version;
304} __packed;
305
306/*
307 * Hello. This is a simple command to test the EC is responsive to
308 * commands.
309 */
310#define EC_CMD_HELLO 0x01
311
312struct ec_params_hello {
313 uint32_t in_data; /* Pass anything here */
314} __packed;
315
316struct ec_response_hello {
317 uint32_t out_data; /* Output will be in_data + 0x01020304 */
318} __packed;
319
320/* Get version number */
321#define EC_CMD_GET_VERSION 0x02
322
323enum ec_current_image {
324 EC_IMAGE_UNKNOWN = 0,
325 EC_IMAGE_RO,
326 EC_IMAGE_RW
327};
328
329struct ec_response_get_version {
330 /* Null-terminated version strings for RO, RW */
331 char version_string_ro[32];
332 char version_string_rw[32];
333 char reserved[32]; /* Was previously RW-B string */
334 uint32_t current_image; /* One of ec_current_image */
335} __packed;
336
337/* Read test */
338#define EC_CMD_READ_TEST 0x03
339
340struct ec_params_read_test {
341 uint32_t offset; /* Starting value for read buffer */
342 uint32_t size; /* Size to read in bytes */
343} __packed;
344
345struct ec_response_read_test {
346 uint32_t data[32];
347} __packed;
348
349/*
350 * Get build information
351 *
352 * Response is null-terminated string.
353 */
354#define EC_CMD_GET_BUILD_INFO 0x04
355
356/* Get chip info */
357#define EC_CMD_GET_CHIP_INFO 0x05
358
359struct ec_response_get_chip_info {
360 /* Null-terminated strings */
361 char vendor[32];
362 char name[32];
363 char revision[32]; /* Mask version */
364} __packed;
365
366/* Get board HW version */
367#define EC_CMD_GET_BOARD_VERSION 0x06
368
369struct ec_response_board_version {
370 uint16_t board_version; /* A monotonously incrementing number. */
371} __packed;
372
373/*
374 * Read memory-mapped data.
375 *
376 * This is an alternate interface to memory-mapped data for bus protocols
377 * which don't support direct-mapped memory - I2C, SPI, etc.
378 *
379 * Response is params.size bytes of data.
380 */
381#define EC_CMD_READ_MEMMAP 0x07
382
383struct ec_params_read_memmap {
384 uint8_t offset; /* Offset in memmap (EC_MEMMAP_*) */
385 uint8_t size; /* Size to read in bytes */
386} __packed;
387
388/* Read versions supported for a command */
389#define EC_CMD_GET_CMD_VERSIONS 0x08
390
391struct ec_params_get_cmd_versions {
392 uint8_t cmd; /* Command to check */
393} __packed;
394
395struct ec_response_get_cmd_versions {
396 /*
397 * Mask of supported versions; use EC_VER_MASK() to compare with a
398 * desired version.
399 */
400 uint32_t version_mask;
401} __packed;
402
403/*
404 * Check EC communcations status (busy). This is needed on i2c/spi but not
405 * on lpc since it has its own out-of-band busy indicator.
406 *
407 * lpc must read the status from the command register. Attempting this on
408 * lpc will overwrite the args/parameter space and corrupt its data.
409 */
410#define EC_CMD_GET_COMMS_STATUS 0x09
411
412/* Avoid using ec_status which is for return values */
413enum ec_comms_status {
414 EC_COMMS_STATUS_PROCESSING = 1 << 0, /* Processing cmd */
415};
416
417struct ec_response_get_comms_status {
418 uint32_t flags; /* Mask of enum ec_comms_status */
419} __packed;
420
421
422/*****************************************************************************/
423/* Flash commands */
424
425/* Get flash info */
426#define EC_CMD_FLASH_INFO 0x10
427
428struct ec_response_flash_info {
429 /* Usable flash size, in bytes */
430 uint32_t flash_size;
431 /*
432 * Write block size. Write offset and size must be a multiple
433 * of this.
434 */
435 uint32_t write_block_size;
436 /*
437 * Erase block size. Erase offset and size must be a multiple
438 * of this.
439 */
440 uint32_t erase_block_size;
441 /*
442 * Protection block size. Protection offset and size must be a
443 * multiple of this.
444 */
445 uint32_t protect_block_size;
446} __packed;
447
448/*
449 * Read flash
450 *
451 * Response is params.size bytes of data.
452 */
453#define EC_CMD_FLASH_READ 0x11
454
455struct ec_params_flash_read {
456 uint32_t offset; /* Byte offset to read */
457 uint32_t size; /* Size to read in bytes */
458} __packed;
459
460/* Write flash */
461#define EC_CMD_FLASH_WRITE 0x12
462
463struct ec_params_flash_write {
464 uint32_t offset; /* Byte offset to write */
465 uint32_t size; /* Size to write in bytes */
466 /*
467 * Data to write. Could really use EC_PARAM_SIZE - 8, but tidiest to
468 * use a power of 2 so writes stay aligned.
469 */
470 uint8_t data[64];
471} __packed;
472
473/* Erase flash */
474#define EC_CMD_FLASH_ERASE 0x13
475
476struct ec_params_flash_erase {
477 uint32_t offset; /* Byte offset to erase */
478 uint32_t size; /* Size to erase in bytes */
479} __packed;
480
481/*
482 * Get/set flash protection.
483 *
484 * If mask!=0, sets/clear the requested bits of flags. Depending on the
485 * firmware write protect GPIO, not all flags will take effect immediately;
486 * some flags require a subsequent hard reset to take effect. Check the
487 * returned flags bits to see what actually happened.
488 *
489 * If mask=0, simply returns the current flags state.
490 */
491#define EC_CMD_FLASH_PROTECT 0x15
492#define EC_VER_FLASH_PROTECT 1 /* Command version 1 */
493
494/* Flags for flash protection */
495/* RO flash code protected when the EC boots */
496#define EC_FLASH_PROTECT_RO_AT_BOOT (1 << 0)
497/*
498 * RO flash code protected now. If this bit is set, at-boot status cannot
499 * be changed.
500 */
501#define EC_FLASH_PROTECT_RO_NOW (1 << 1)
502/* Entire flash code protected now, until reboot. */
503#define EC_FLASH_PROTECT_ALL_NOW (1 << 2)
504/* Flash write protect GPIO is asserted now */
505#define EC_FLASH_PROTECT_GPIO_ASSERTED (1 << 3)
506/* Error - at least one bank of flash is stuck locked, and cannot be unlocked */
507#define EC_FLASH_PROTECT_ERROR_STUCK (1 << 4)
508/*
509 * Error - flash protection is in inconsistent state. At least one bank of
510 * flash which should be protected is not protected. Usually fixed by
511 * re-requesting the desired flags, or by a hard reset if that fails.
512 */
513#define EC_FLASH_PROTECT_ERROR_INCONSISTENT (1 << 5)
514/* Entile flash code protected when the EC boots */
515#define EC_FLASH_PROTECT_ALL_AT_BOOT (1 << 6)
516
517struct ec_params_flash_protect {
518 uint32_t mask; /* Bits in flags to apply */
519 uint32_t flags; /* New flags to apply */
520} __packed;
521
522struct ec_response_flash_protect {
523 /* Current value of flash protect flags */
524 uint32_t flags;
525 /*
526 * Flags which are valid on this platform. This allows the caller
527 * to distinguish between flags which aren't set vs. flags which can't
528 * be set on this platform.
529 */
530 uint32_t valid_flags;
531 /* Flags which can be changed given the current protection state */
532 uint32_t writable_flags;
533} __packed;
534
535/*
536 * Note: commands 0x14 - 0x19 version 0 were old commands to get/set flash
537 * write protect. These commands may be reused with version > 0.
538 */
539
540/* Get the region offset/size */
541#define EC_CMD_FLASH_REGION_INFO 0x16
542#define EC_VER_FLASH_REGION_INFO 1
543
544enum ec_flash_region {
545 /* Region which holds read-only EC image */
546 EC_FLASH_REGION_RO,
547 /* Region which holds rewritable EC image */
548 EC_FLASH_REGION_RW,
549 /*
550 * Region which should be write-protected in the factory (a superset of
551 * EC_FLASH_REGION_RO)
552 */
553 EC_FLASH_REGION_WP_RO,
554};
555
556struct ec_params_flash_region_info {
557 uint32_t region; /* enum ec_flash_region */
558} __packed;
559
560struct ec_response_flash_region_info {
561 uint32_t offset;
562 uint32_t size;
563} __packed;
564
565/* Read/write VbNvContext */
566#define EC_CMD_VBNV_CONTEXT 0x17
567#define EC_VER_VBNV_CONTEXT 1
568#define EC_VBNV_BLOCK_SIZE 16
569
570enum ec_vbnvcontext_op {
571 EC_VBNV_CONTEXT_OP_READ,
572 EC_VBNV_CONTEXT_OP_WRITE,
573};
574
575struct ec_params_vbnvcontext {
576 uint32_t op;
577 uint8_t block[EC_VBNV_BLOCK_SIZE];
578} __packed;
579
580struct ec_response_vbnvcontext {
581 uint8_t block[EC_VBNV_BLOCK_SIZE];
582} __packed;
583
584/*****************************************************************************/
585/* PWM commands */
586
587/* Get fan target RPM */
588#define EC_CMD_PWM_GET_FAN_TARGET_RPM 0x20
589
590struct ec_response_pwm_get_fan_rpm {
591 uint32_t rpm;
592} __packed;
593
594/* Set target fan RPM */
595#define EC_CMD_PWM_SET_FAN_TARGET_RPM 0x21
596
597struct ec_params_pwm_set_fan_target_rpm {
598 uint32_t rpm;
599} __packed;
600
601/* Get keyboard backlight */
602#define EC_CMD_PWM_GET_KEYBOARD_BACKLIGHT 0x22
603
604struct ec_response_pwm_get_keyboard_backlight {
605 uint8_t percent;
606 uint8_t enabled;
607} __packed;
608
609/* Set keyboard backlight */
610#define EC_CMD_PWM_SET_KEYBOARD_BACKLIGHT 0x23
611
612struct ec_params_pwm_set_keyboard_backlight {
613 uint8_t percent;
614} __packed;
615
616/* Set target fan PWM duty cycle */
617#define EC_CMD_PWM_SET_FAN_DUTY 0x24
618
619struct ec_params_pwm_set_fan_duty {
620 uint32_t percent;
621} __packed;
622
623/*****************************************************************************/
624/*
625 * Lightbar commands. This looks worse than it is. Since we only use one HOST
626 * command to say "talk to the lightbar", we put the "and tell it to do X" part
627 * into a subcommand. We'll make separate structs for subcommands with
628 * different input args, so that we know how much to expect.
629 */
630#define EC_CMD_LIGHTBAR_CMD 0x28
631
632struct rgb_s {
633 uint8_t r, g, b;
634};
635
636#define LB_BATTERY_LEVELS 4
637/* List of tweakable parameters. NOTE: It's __packed so it can be sent in a
638 * host command, but the alignment is the same regardless. Keep it that way.
639 */
640struct lightbar_params {
641 /* Timing */
642 int google_ramp_up;
643 int google_ramp_down;
644 int s3s0_ramp_up;
645 int s0_tick_delay[2]; /* AC=0/1 */
646 int s0a_tick_delay[2]; /* AC=0/1 */
647 int s0s3_ramp_down;
648 int s3_sleep_for;
649 int s3_ramp_up;
650 int s3_ramp_down;
651
652 /* Oscillation */
653 uint8_t new_s0;
654 uint8_t osc_min[2]; /* AC=0/1 */
655 uint8_t osc_max[2]; /* AC=0/1 */
656 uint8_t w_ofs[2]; /* AC=0/1 */
657
658 /* Brightness limits based on the backlight and AC. */
659 uint8_t bright_bl_off_fixed[2]; /* AC=0/1 */
660 uint8_t bright_bl_on_min[2]; /* AC=0/1 */
661 uint8_t bright_bl_on_max[2]; /* AC=0/1 */
662
663 /* Battery level thresholds */
664 uint8_t battery_threshold[LB_BATTERY_LEVELS - 1];
665
666 /* Map [AC][battery_level] to color index */
667 uint8_t s0_idx[2][LB_BATTERY_LEVELS]; /* AP is running */
668 uint8_t s3_idx[2][LB_BATTERY_LEVELS]; /* AP is sleeping */
669
670 /* Color palette */
671 struct rgb_s color[8]; /* 0-3 are Google colors */
672} __packed;
673
674struct ec_params_lightbar {
675 uint8_t cmd; /* Command (see enum lightbar_command) */
676 union {
677 struct {
678 /* no args */
679 } dump, off, on, init, get_seq, get_params;
680
681 struct num {
682 uint8_t num;
683 } brightness, seq, demo;
684
685 struct reg {
686 uint8_t ctrl, reg, value;
687 } reg;
688
689 struct rgb {
690 uint8_t led, red, green, blue;
691 } rgb;
692
693 struct lightbar_params set_params;
694 };
695} __packed;
696
697struct ec_response_lightbar {
698 union {
699 struct dump {
700 struct {
701 uint8_t reg;
702 uint8_t ic0;
703 uint8_t ic1;
704 } vals[23];
705 } dump;
706
707 struct get_seq {
708 uint8_t num;
709 } get_seq;
710
711 struct lightbar_params get_params;
712
713 struct {
714 /* no return params */
715 } off, on, init, brightness, seq, reg, rgb, demo, set_params;
716 };
717} __packed;
718
719/* Lightbar commands */
720enum lightbar_command {
721 LIGHTBAR_CMD_DUMP = 0,
722 LIGHTBAR_CMD_OFF = 1,
723 LIGHTBAR_CMD_ON = 2,
724 LIGHTBAR_CMD_INIT = 3,
725 LIGHTBAR_CMD_BRIGHTNESS = 4,
726 LIGHTBAR_CMD_SEQ = 5,
727 LIGHTBAR_CMD_REG = 6,
728 LIGHTBAR_CMD_RGB = 7,
729 LIGHTBAR_CMD_GET_SEQ = 8,
730 LIGHTBAR_CMD_DEMO = 9,
731 LIGHTBAR_CMD_GET_PARAMS = 10,
732 LIGHTBAR_CMD_SET_PARAMS = 11,
733 LIGHTBAR_NUM_CMDS
734};
735
736/*****************************************************************************/
737/* Verified boot commands */
738
739/*
740 * Note: command code 0x29 version 0 was VBOOT_CMD in Link EVT; it may be
741 * reused for other purposes with version > 0.
742 */
743
744/* Verified boot hash command */
745#define EC_CMD_VBOOT_HASH 0x2A
746
747struct ec_params_vboot_hash {
748 uint8_t cmd; /* enum ec_vboot_hash_cmd */
749 uint8_t hash_type; /* enum ec_vboot_hash_type */
750 uint8_t nonce_size; /* Nonce size; may be 0 */
751 uint8_t reserved0; /* Reserved; set 0 */
752 uint32_t offset; /* Offset in flash to hash */
753 uint32_t size; /* Number of bytes to hash */
754 uint8_t nonce_data[64]; /* Nonce data; ignored if nonce_size=0 */
755} __packed;
756
757struct ec_response_vboot_hash {
758 uint8_t status; /* enum ec_vboot_hash_status */
759 uint8_t hash_type; /* enum ec_vboot_hash_type */
760 uint8_t digest_size; /* Size of hash digest in bytes */
761 uint8_t reserved0; /* Ignore; will be 0 */
762 uint32_t offset; /* Offset in flash which was hashed */
763 uint32_t size; /* Number of bytes hashed */
764 uint8_t hash_digest[64]; /* Hash digest data */
765} __packed;
766
767enum ec_vboot_hash_cmd {
768 EC_VBOOT_HASH_GET = 0, /* Get current hash status */
769 EC_VBOOT_HASH_ABORT = 1, /* Abort calculating current hash */
770 EC_VBOOT_HASH_START = 2, /* Start computing a new hash */
771 EC_VBOOT_HASH_RECALC = 3, /* Synchronously compute a new hash */
772};
773
774enum ec_vboot_hash_type {
775 EC_VBOOT_HASH_TYPE_SHA256 = 0, /* SHA-256 */
776};
777
778enum ec_vboot_hash_status {
779 EC_VBOOT_HASH_STATUS_NONE = 0, /* No hash (not started, or aborted) */
780 EC_VBOOT_HASH_STATUS_DONE = 1, /* Finished computing a hash */
781 EC_VBOOT_HASH_STATUS_BUSY = 2, /* Busy computing a hash */
782};
783
784/*
785 * Special values for offset for EC_VBOOT_HASH_START and EC_VBOOT_HASH_RECALC.
786 * If one of these is specified, the EC will automatically update offset and
787 * size to the correct values for the specified image (RO or RW).
788 */
789#define EC_VBOOT_HASH_OFFSET_RO 0xfffffffe
790#define EC_VBOOT_HASH_OFFSET_RW 0xfffffffd
791
792/*****************************************************************************/
793/* USB charging control commands */
794
795/* Set USB port charging mode */
796#define EC_CMD_USB_CHARGE_SET_MODE 0x30
797
798struct ec_params_usb_charge_set_mode {
799 uint8_t usb_port_id;
800 uint8_t mode;
801} __packed;
802
803/*****************************************************************************/
804/* Persistent storage for host */
805
806/* Maximum bytes that can be read/written in a single command */
807#define EC_PSTORE_SIZE_MAX 64
808
809/* Get persistent storage info */
810#define EC_CMD_PSTORE_INFO 0x40
811
812struct ec_response_pstore_info {
813 /* Persistent storage size, in bytes */
814 uint32_t pstore_size;
815 /* Access size; read/write offset and size must be a multiple of this */
816 uint32_t access_size;
817} __packed;
818
819/*
820 * Read persistent storage
821 *
822 * Response is params.size bytes of data.
823 */
824#define EC_CMD_PSTORE_READ 0x41
825
826struct ec_params_pstore_read {
827 uint32_t offset; /* Byte offset to read */
828 uint32_t size; /* Size to read in bytes */
829} __packed;
830
831/* Write persistent storage */
832#define EC_CMD_PSTORE_WRITE 0x42
833
834struct ec_params_pstore_write {
835 uint32_t offset; /* Byte offset to write */
836 uint32_t size; /* Size to write in bytes */
837 uint8_t data[EC_PSTORE_SIZE_MAX];
838} __packed;
839
840/*****************************************************************************/
841/* Real-time clock */
842
843/* RTC params and response structures */
844struct ec_params_rtc {
845 uint32_t time;
846} __packed;
847
848struct ec_response_rtc {
849 uint32_t time;
850} __packed;
851
852/* These use ec_response_rtc */
853#define EC_CMD_RTC_GET_VALUE 0x44
854#define EC_CMD_RTC_GET_ALARM 0x45
855
856/* These all use ec_params_rtc */
857#define EC_CMD_RTC_SET_VALUE 0x46
858#define EC_CMD_RTC_SET_ALARM 0x47
859
860/*****************************************************************************/
861/* Port80 log access */
862
863/* Get last port80 code from previous boot */
864#define EC_CMD_PORT80_LAST_BOOT 0x48
865
866struct ec_response_port80_last_boot {
867 uint16_t code;
868} __packed;
869
870/*****************************************************************************/
871/* Thermal engine commands */
872
873/* Set thershold value */
874#define EC_CMD_THERMAL_SET_THRESHOLD 0x50
875
876struct ec_params_thermal_set_threshold {
877 uint8_t sensor_type;
878 uint8_t threshold_id;
879 uint16_t value;
880} __packed;
881
882/* Get threshold value */
883#define EC_CMD_THERMAL_GET_THRESHOLD 0x51
884
885struct ec_params_thermal_get_threshold {
886 uint8_t sensor_type;
887 uint8_t threshold_id;
888} __packed;
889
890struct ec_response_thermal_get_threshold {
891 uint16_t value;
892} __packed;
893
894/* Toggle automatic fan control */
895#define EC_CMD_THERMAL_AUTO_FAN_CTRL 0x52
896
897/* Get TMP006 calibration data */
898#define EC_CMD_TMP006_GET_CALIBRATION 0x53
899
900struct ec_params_tmp006_get_calibration {
901 uint8_t index;
902} __packed;
903
904struct ec_response_tmp006_get_calibration {
905 float s0;
906 float b0;
907 float b1;
908 float b2;
909} __packed;
910
911/* Set TMP006 calibration data */
912#define EC_CMD_TMP006_SET_CALIBRATION 0x54
913
914struct ec_params_tmp006_set_calibration {
915 uint8_t index;
916 uint8_t reserved[3]; /* Reserved; set 0 */
917 float s0;
918 float b0;
919 float b1;
920 float b2;
921} __packed;
922
923/*****************************************************************************/
924/* MKBP - Matrix KeyBoard Protocol */
925
926/*
927 * Read key state
928 *
929 * Returns raw data for keyboard cols; see ec_response_mkbp_info.cols for
930 * expected response size.
931 */
932#define EC_CMD_MKBP_STATE 0x60
933
934/* Provide information about the matrix : number of rows and columns */
935#define EC_CMD_MKBP_INFO 0x61
936
937struct ec_response_mkbp_info {
938 uint32_t rows;
939 uint32_t cols;
940 uint8_t switches;
941} __packed;
942
943/* Simulate key press */
944#define EC_CMD_MKBP_SIMULATE_KEY 0x62
945
946struct ec_params_mkbp_simulate_key {
947 uint8_t col;
948 uint8_t row;
949 uint8_t pressed;
950} __packed;
951
952/* Configure keyboard scanning */
953#define EC_CMD_MKBP_SET_CONFIG 0x64
954#define EC_CMD_MKBP_GET_CONFIG 0x65
955
956/* flags */
957enum mkbp_config_flags {
958 EC_MKBP_FLAGS_ENABLE = 1, /* Enable keyboard scanning */
959};
960
961enum mkbp_config_valid {
962 EC_MKBP_VALID_SCAN_PERIOD = 1 << 0,
963 EC_MKBP_VALID_POLL_TIMEOUT = 1 << 1,
964 EC_MKBP_VALID_MIN_POST_SCAN_DELAY = 1 << 3,
965 EC_MKBP_VALID_OUTPUT_SETTLE = 1 << 4,
966 EC_MKBP_VALID_DEBOUNCE_DOWN = 1 << 5,
967 EC_MKBP_VALID_DEBOUNCE_UP = 1 << 6,
968 EC_MKBP_VALID_FIFO_MAX_DEPTH = 1 << 7,
969};
970
971/* Configuration for our key scanning algorithm */
972struct ec_mkbp_config {
973 uint32_t valid_mask; /* valid fields */
974 uint8_t flags; /* some flags (enum mkbp_config_flags) */
975 uint8_t valid_flags; /* which flags are valid */
976 uint16_t scan_period_us; /* period between start of scans */
977 /* revert to interrupt mode after no activity for this long */
978 uint32_t poll_timeout_us;
979 /*
980 * minimum post-scan relax time. Once we finish a scan we check
981 * the time until we are due to start the next one. If this time is
982 * shorter this field, we use this instead.
983 */
984 uint16_t min_post_scan_delay_us;
985 /* delay between setting up output and waiting for it to settle */
986 uint16_t output_settle_us;
987 uint16_t debounce_down_us; /* time for debounce on key down */
988 uint16_t debounce_up_us; /* time for debounce on key up */
989 /* maximum depth to allow for fifo (0 = no keyscan output) */
990 uint8_t fifo_max_depth;
991} __packed;
992
993struct ec_params_mkbp_set_config {
994 struct ec_mkbp_config config;
995} __packed;
996
997struct ec_response_mkbp_get_config {
998 struct ec_mkbp_config config;
999} __packed;
1000
1001/* Run the key scan emulation */
1002#define EC_CMD_KEYSCAN_SEQ_CTRL 0x66
1003
1004enum ec_keyscan_seq_cmd {
1005 EC_KEYSCAN_SEQ_STATUS = 0, /* Get status information */
1006 EC_KEYSCAN_SEQ_CLEAR = 1, /* Clear sequence */
1007 EC_KEYSCAN_SEQ_ADD = 2, /* Add item to sequence */
1008 EC_KEYSCAN_SEQ_START = 3, /* Start running sequence */
1009 EC_KEYSCAN_SEQ_COLLECT = 4, /* Collect sequence summary data */
1010};
1011
1012enum ec_collect_flags {
1013 /*
1014 * Indicates this scan was processed by the EC. Due to timing, some
1015 * scans may be skipped.
1016 */
1017 EC_KEYSCAN_SEQ_FLAG_DONE = 1 << 0,
1018};
1019
1020struct ec_collect_item {
1021 uint8_t flags; /* some flags (enum ec_collect_flags) */
1022};
1023
1024struct ec_params_keyscan_seq_ctrl {
1025 uint8_t cmd; /* Command to send (enum ec_keyscan_seq_cmd) */
1026 union {
1027 struct {
1028 uint8_t active; /* still active */
1029 uint8_t num_items; /* number of items */
1030 /* Current item being presented */
1031 uint8_t cur_item;
1032 } status;
1033 struct {
1034 /*
1035 * Absolute time for this scan, measured from the
1036 * start of the sequence.
1037 */
1038 uint32_t time_us;
1039 uint8_t scan[0]; /* keyscan data */
1040 } add;
1041 struct {
1042 uint8_t start_item; /* First item to return */
1043 uint8_t num_items; /* Number of items to return */
1044 } collect;
1045 };
1046} __packed;
1047
1048struct ec_result_keyscan_seq_ctrl {
1049 union {
1050 struct {
1051 uint8_t num_items; /* Number of items */
1052 /* Data for each item */
1053 struct ec_collect_item item[0];
1054 } collect;
1055 };
1056} __packed;
1057
1058/*****************************************************************************/
1059/* Temperature sensor commands */
1060
1061/* Read temperature sensor info */
1062#define EC_CMD_TEMP_SENSOR_GET_INFO 0x70
1063
1064struct ec_params_temp_sensor_get_info {
1065 uint8_t id;
1066} __packed;
1067
1068struct ec_response_temp_sensor_get_info {
1069 char sensor_name[32];
1070 uint8_t sensor_type;
1071} __packed;
1072
1073/*****************************************************************************/
1074
1075/*
1076 * Note: host commands 0x80 - 0x87 are reserved to avoid conflict with ACPI
1077 * commands accidentally sent to the wrong interface. See the ACPI section
1078 * below.
1079 */
1080
1081/*****************************************************************************/
1082/* Host event commands */
1083
1084/*
1085 * Host event mask params and response structures, shared by all of the host
1086 * event commands below.
1087 */
1088struct ec_params_host_event_mask {
1089 uint32_t mask;
1090} __packed;
1091
1092struct ec_response_host_event_mask {
1093 uint32_t mask;
1094} __packed;
1095
1096/* These all use ec_response_host_event_mask */
1097#define EC_CMD_HOST_EVENT_GET_B 0x87
1098#define EC_CMD_HOST_EVENT_GET_SMI_MASK 0x88
1099#define EC_CMD_HOST_EVENT_GET_SCI_MASK 0x89
1100#define EC_CMD_HOST_EVENT_GET_WAKE_MASK 0x8d
1101
1102/* These all use ec_params_host_event_mask */
1103#define EC_CMD_HOST_EVENT_SET_SMI_MASK 0x8a
1104#define EC_CMD_HOST_EVENT_SET_SCI_MASK 0x8b
1105#define EC_CMD_HOST_EVENT_CLEAR 0x8c
1106#define EC_CMD_HOST_EVENT_SET_WAKE_MASK 0x8e
1107#define EC_CMD_HOST_EVENT_CLEAR_B 0x8f
1108
1109/*****************************************************************************/
1110/* Switch commands */
1111
1112/* Enable/disable LCD backlight */
1113#define EC_CMD_SWITCH_ENABLE_BKLIGHT 0x90
1114
1115struct ec_params_switch_enable_backlight {
1116 uint8_t enabled;
1117} __packed;
1118
1119/* Enable/disable WLAN/Bluetooth */
1120#define EC_CMD_SWITCH_ENABLE_WIRELESS 0x91
1121
1122struct ec_params_switch_enable_wireless {
1123 uint8_t enabled;
1124} __packed;
1125
1126/*****************************************************************************/
1127/* GPIO commands. Only available on EC if write protect has been disabled. */
1128
1129/* Set GPIO output value */
1130#define EC_CMD_GPIO_SET 0x92
1131
1132struct ec_params_gpio_set {
1133 char name[32];
1134 uint8_t val;
1135} __packed;
1136
1137/* Get GPIO value */
1138#define EC_CMD_GPIO_GET 0x93
1139
1140struct ec_params_gpio_get {
1141 char name[32];
1142} __packed;
1143struct ec_response_gpio_get {
1144 uint8_t val;
1145} __packed;
1146
1147/*****************************************************************************/
1148/* I2C commands. Only available when flash write protect is unlocked. */
1149
1150/* Read I2C bus */
1151#define EC_CMD_I2C_READ 0x94
1152
1153struct ec_params_i2c_read {
1154 uint16_t addr;
1155 uint8_t read_size; /* Either 8 or 16. */
1156 uint8_t port;
1157 uint8_t offset;
1158} __packed;
1159struct ec_response_i2c_read {
1160 uint16_t data;
1161} __packed;
1162
1163/* Write I2C bus */
1164#define EC_CMD_I2C_WRITE 0x95
1165
1166struct ec_params_i2c_write {
1167 uint16_t data;
1168 uint16_t addr;
1169 uint8_t write_size; /* Either 8 or 16. */
1170 uint8_t port;
1171 uint8_t offset;
1172} __packed;
1173
1174/*****************************************************************************/
1175/* Charge state commands. Only available when flash write protect unlocked. */
1176
1177/* Force charge state machine to stop in idle mode */
1178#define EC_CMD_CHARGE_FORCE_IDLE 0x96
1179
1180struct ec_params_force_idle {
1181 uint8_t enabled;
1182} __packed;
1183
1184/*****************************************************************************/
1185/* Console commands. Only available when flash write protect is unlocked. */
1186
1187/* Snapshot console output buffer for use by EC_CMD_CONSOLE_READ. */
1188#define EC_CMD_CONSOLE_SNAPSHOT 0x97
1189
1190/*
1191 * Read next chunk of data from saved snapshot.
1192 *
1193 * Response is null-terminated string. Empty string, if there is no more
1194 * remaining output.
1195 */
1196#define EC_CMD_CONSOLE_READ 0x98
1197
1198/*****************************************************************************/
1199
1200/*
1201 * Cut off battery power output if the battery supports.
1202 *
1203 * For unsupported battery, just don't implement this command and lets EC
1204 * return EC_RES_INVALID_COMMAND.
1205 */
1206#define EC_CMD_BATTERY_CUT_OFF 0x99
1207
1208/*****************************************************************************/
1209/* Temporary debug commands. TODO: remove this crosbug.com/p/13849 */
1210
1211/*
1212 * Dump charge state machine context.
1213 *
1214 * Response is a binary dump of charge state machine context.
1215 */
1216#define EC_CMD_CHARGE_DUMP 0xa0
1217
1218/*
1219 * Set maximum battery charging current.
1220 */
1221#define EC_CMD_CHARGE_CURRENT_LIMIT 0xa1
1222
1223struct ec_params_current_limit {
1224 uint32_t limit;
1225} __packed;
1226
1227/*****************************************************************************/
1228/* System commands */
1229
1230/*
1231 * TODO: this is a confusing name, since it doesn't necessarily reboot the EC.
1232 * Rename to "set image" or something similar.
1233 */
1234#define EC_CMD_REBOOT_EC 0xd2
1235
1236/* Command */
1237enum ec_reboot_cmd {
1238 EC_REBOOT_CANCEL = 0, /* Cancel a pending reboot */
1239 EC_REBOOT_JUMP_RO = 1, /* Jump to RO without rebooting */
1240 EC_REBOOT_JUMP_RW = 2, /* Jump to RW without rebooting */
1241 /* (command 3 was jump to RW-B) */
1242 EC_REBOOT_COLD = 4, /* Cold-reboot */
1243 EC_REBOOT_DISABLE_JUMP = 5, /* Disable jump until next reboot */
1244 EC_REBOOT_HIBERNATE = 6 /* Hibernate EC */
1245};
1246
1247/* Flags for ec_params_reboot_ec.reboot_flags */
1248#define EC_REBOOT_FLAG_RESERVED0 (1 << 0) /* Was recovery request */
1249#define EC_REBOOT_FLAG_ON_AP_SHUTDOWN (1 << 1) /* Reboot after AP shutdown */
1250
1251struct ec_params_reboot_ec {
1252 uint8_t cmd; /* enum ec_reboot_cmd */
1253 uint8_t flags; /* See EC_REBOOT_FLAG_* */
1254} __packed;
1255
1256/*
1257 * Get information on last EC panic.
1258 *
1259 * Returns variable-length platform-dependent panic information. See panic.h
1260 * for details.
1261 */
1262#define EC_CMD_GET_PANIC_INFO 0xd3
1263
1264/*****************************************************************************/
1265/*
1266 * ACPI commands
1267 *
1268 * These are valid ONLY on the ACPI command/data port.
1269 */
1270
1271/*
1272 * ACPI Read Embedded Controller
1273 *
1274 * This reads from ACPI memory space on the EC (EC_ACPI_MEM_*).
1275 *
1276 * Use the following sequence:
1277 *
1278 * - Write EC_CMD_ACPI_READ to EC_LPC_ADDR_ACPI_CMD
1279 * - Wait for EC_LPC_CMDR_PENDING bit to clear
1280 * - Write address to EC_LPC_ADDR_ACPI_DATA
1281 * - Wait for EC_LPC_CMDR_DATA bit to set
1282 * - Read value from EC_LPC_ADDR_ACPI_DATA
1283 */
1284#define EC_CMD_ACPI_READ 0x80
1285
1286/*
1287 * ACPI Write Embedded Controller
1288 *
1289 * This reads from ACPI memory space on the EC (EC_ACPI_MEM_*).
1290 *
1291 * Use the following sequence:
1292 *
1293 * - Write EC_CMD_ACPI_WRITE to EC_LPC_ADDR_ACPI_CMD
1294 * - Wait for EC_LPC_CMDR_PENDING bit to clear
1295 * - Write address to EC_LPC_ADDR_ACPI_DATA
1296 * - Wait for EC_LPC_CMDR_PENDING bit to clear
1297 * - Write value to EC_LPC_ADDR_ACPI_DATA
1298 */
1299#define EC_CMD_ACPI_WRITE 0x81
1300
1301/*
1302 * ACPI Query Embedded Controller
1303 *
1304 * This clears the lowest-order bit in the currently pending host events, and
1305 * sets the result code to the 1-based index of the bit (event 0x00000001 = 1,
1306 * event 0x80000000 = 32), or 0 if no event was pending.
1307 */
1308#define EC_CMD_ACPI_QUERY_EVENT 0x84
1309
1310/* Valid addresses in ACPI memory space, for read/write commands */
1311/* Memory space version; set to EC_ACPI_MEM_VERSION_CURRENT */
1312#define EC_ACPI_MEM_VERSION 0x00
1313/*
1314 * Test location; writing value here updates test compliment byte to (0xff -
1315 * value).
1316 */
1317#define EC_ACPI_MEM_TEST 0x01
1318/* Test compliment; writes here are ignored. */
1319#define EC_ACPI_MEM_TEST_COMPLIMENT 0x02
1320/* Keyboard backlight brightness percent (0 - 100) */
1321#define EC_ACPI_MEM_KEYBOARD_BACKLIGHT 0x03
1322
1323/* Current version of ACPI memory address space */
1324#define EC_ACPI_MEM_VERSION_CURRENT 1
1325
1326
1327/*****************************************************************************/
1328/*
1329 * Special commands
1330 *
1331 * These do not follow the normal rules for commands. See each command for
1332 * details.
1333 */
1334
1335/*
1336 * Reboot NOW
1337 *
1338 * This command will work even when the EC LPC interface is busy, because the
1339 * reboot command is processed at interrupt level. Note that when the EC
1340 * reboots, the host will reboot too, so there is no response to this command.
1341 *
1342 * Use EC_CMD_REBOOT_EC to reboot the EC more politely.
1343 */
1344#define EC_CMD_REBOOT 0xd1 /* Think "die" */
1345
1346/*
1347 * Resend last response (not supported on LPC).
1348 *
1349 * Returns EC_RES_UNAVAILABLE if there is no response available - for example,
1350 * there was no previous command, or the previous command's response was too
1351 * big to save.
1352 */
1353#define EC_CMD_RESEND_RESPONSE 0xdb
1354
1355/*
1356 * This header byte on a command indicate version 0. Any header byte less
1357 * than this means that we are talking to an old EC which doesn't support
1358 * versioning. In that case, we assume version 0.
1359 *
1360 * Header bytes greater than this indicate a later version. For example,
1361 * EC_CMD_VERSION0 + 1 means we are using version 1.
1362 *
1363 * The old EC interface must not use commands 0dc or higher.
1364 */
1365#define EC_CMD_VERSION0 0xdc
1366
1367#endif /* !__ACPI__ */
1368
1369#endif /* __CROS_EC_COMMANDS_H */
diff --git a/include/linux/mfd/db8500-prcmu.h b/include/linux/mfd/db8500-prcmu.h
index 77a46ae2fc17..0bd69446bb05 100644
--- a/include/linux/mfd/db8500-prcmu.h
+++ b/include/linux/mfd/db8500-prcmu.h
@@ -489,7 +489,7 @@ struct prcmu_auto_pm_config {
489 489
490#ifdef CONFIG_MFD_DB8500_PRCMU 490#ifdef CONFIG_MFD_DB8500_PRCMU
491 491
492void db8500_prcmu_early_init(void); 492void db8500_prcmu_early_init(u32 phy_base, u32 size);
493int prcmu_set_rc_a2p(enum romcode_write); 493int prcmu_set_rc_a2p(enum romcode_write);
494enum romcode_read prcmu_get_rc_p2a(void); 494enum romcode_read prcmu_get_rc_p2a(void);
495enum ap_pwrst prcmu_get_xp70_current_state(void); 495enum ap_pwrst prcmu_get_xp70_current_state(void);
@@ -522,12 +522,6 @@ int db8500_prcmu_load_a9wdog(u8 id, u32 val);
522void db8500_prcmu_system_reset(u16 reset_code); 522void db8500_prcmu_system_reset(u16 reset_code);
523int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll); 523int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll);
524u8 db8500_prcmu_get_power_state_result(void); 524u8 db8500_prcmu_get_power_state_result(void);
525int db8500_prcmu_gic_decouple(void);
526int db8500_prcmu_gic_recouple(void);
527int db8500_prcmu_copy_gic_settings(void);
528bool db8500_prcmu_gic_pending_irq(void);
529bool db8500_prcmu_pending_irq(void);
530bool db8500_prcmu_is_cpu_in_wfi(int cpu);
531void db8500_prcmu_enable_wakeups(u32 wakeups); 525void db8500_prcmu_enable_wakeups(u32 wakeups);
532int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state); 526int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state);
533int db8500_prcmu_request_clock(u8 clock, bool enable); 527int db8500_prcmu_request_clock(u8 clock, bool enable);
@@ -553,7 +547,7 @@ void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value);
553 547
554#else /* !CONFIG_MFD_DB8500_PRCMU */ 548#else /* !CONFIG_MFD_DB8500_PRCMU */
555 549
556static inline void db8500_prcmu_early_init(void) {} 550static inline void db8500_prcmu_early_init(u32 phy_base, u32 size) {}
557 551
558static inline int prcmu_set_rc_a2p(enum romcode_write code) 552static inline int prcmu_set_rc_a2p(enum romcode_write code)
559{ 553{
diff --git a/include/linux/mfd/dbx500-prcmu.h b/include/linux/mfd/dbx500-prcmu.h
index 3abcca91eecd..689e6a0d9c99 100644
--- a/include/linux/mfd/dbx500-prcmu.h
+++ b/include/linux/mfd/dbx500-prcmu.h
@@ -237,6 +237,8 @@ struct prcmu_pdata
237 bool enable_set_ddr_opp; 237 bool enable_set_ddr_opp;
238 bool enable_ape_opp_100_voltage; 238 bool enable_ape_opp_100_voltage;
239 struct ab8500_platform_data *ab_platdata; 239 struct ab8500_platform_data *ab_platdata;
240 int ab_irq;
241 int irq_base;
240 u32 version_offset; 242 u32 version_offset;
241 u32 legacy_offset; 243 u32 legacy_offset;
242 u32 adt_offset; 244 u32 adt_offset;
@@ -276,9 +278,9 @@ struct prcmu_fw_version {
276 278
277#if defined(CONFIG_UX500_SOC_DB8500) 279#if defined(CONFIG_UX500_SOC_DB8500)
278 280
279static inline void __init prcmu_early_init(void) 281static inline void prcmu_early_init(u32 phy_base, u32 size)
280{ 282{
281 return db8500_prcmu_early_init(); 283 return db8500_prcmu_early_init(phy_base, size);
282} 284}
283 285
284static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk, 286static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
@@ -293,36 +295,6 @@ static inline u8 prcmu_get_power_state_result(void)
293 return db8500_prcmu_get_power_state_result(); 295 return db8500_prcmu_get_power_state_result();
294} 296}
295 297
296static inline int prcmu_gic_decouple(void)
297{
298 return db8500_prcmu_gic_decouple();
299}
300
301static inline int prcmu_gic_recouple(void)
302{
303 return db8500_prcmu_gic_recouple();
304}
305
306static inline bool prcmu_gic_pending_irq(void)
307{
308 return db8500_prcmu_gic_pending_irq();
309}
310
311static inline bool prcmu_is_cpu_in_wfi(int cpu)
312{
313 return db8500_prcmu_is_cpu_in_wfi(cpu);
314}
315
316static inline int prcmu_copy_gic_settings(void)
317{
318 return db8500_prcmu_copy_gic_settings();
319}
320
321static inline bool prcmu_pending_irq(void)
322{
323 return db8500_prcmu_pending_irq();
324}
325
326static inline int prcmu_set_epod(u16 epod_id, u8 epod_state) 298static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
327{ 299{
328 return db8500_prcmu_set_epod(epod_id, epod_state); 300 return db8500_prcmu_set_epod(epod_id, epod_state);
@@ -500,7 +472,7 @@ static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
500} 472}
501#else 473#else
502 474
503static inline void __init prcmu_early_init(void) {} 475static inline void prcmu_early_init(u32 phy_base, u32 size) {}
504 476
505static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk, 477static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
506 bool keep_ap_pll) 478 bool keep_ap_pll)
diff --git a/include/linux/mfd/palmas.h b/include/linux/mfd/palmas.h
index 3bbda22721ea..8f21daf62fb5 100644
--- a/include/linux/mfd/palmas.h
+++ b/include/linux/mfd/palmas.h
@@ -1,9 +1,10 @@
1/* 1/*
2 * TI Palmas 2 * TI Palmas
3 * 3 *
4 * Copyright 2011 Texas Instruments Inc. 4 * Copyright 2011-2013 Texas Instruments Inc.
5 * 5 *
6 * Author: Graeme Gregory <gg@slimlogic.co.uk> 6 * Author: Graeme Gregory <gg@slimlogic.co.uk>
7 * Author: Ian Lartey <ian@slimlogic.co.uk>
7 * 8 *
8 * This program is free software; you can redistribute it and/or modify it 9 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the 10 * under the terms of the GNU General Public License as published by the
@@ -22,6 +23,15 @@
22 23
23#define PALMAS_NUM_CLIENTS 3 24#define PALMAS_NUM_CLIENTS 3
24 25
26/* The ID_REVISION NUMBERS */
27#define PALMAS_CHIP_OLD_ID 0x0000
28#define PALMAS_CHIP_ID 0xC035
29#define PALMAS_CHIP_CHARGER_ID 0xC036
30
31#define is_palmas(a) (((a) == PALMAS_CHIP_OLD_ID) || \
32 ((a) == PALMAS_CHIP_ID))
33#define is_palmas_charger(a) ((a) == PALMAS_CHIP_CHARGER_ID)
34
25struct palmas_pmic; 35struct palmas_pmic;
26struct palmas_gpadc; 36struct palmas_gpadc;
27struct palmas_resource; 37struct palmas_resource;
@@ -109,19 +119,6 @@ struct palmas_reg_init {
109 */ 119 */
110 int mode_sleep; 120 int mode_sleep;
111 121
112 /* tstep is the timestep loaded to the TSTEP register
113 *
114 * For SMPS
115 *
116 * 0: Jump (no slope control)
117 * 1: 10mV/us
118 * 2: 5mV/us
119 * 3: 2.5mV/us
120 *
121 * For LDO unused
122 */
123 int tstep;
124
125 /* voltage_sel is the bitfield loaded onto the SMPSX_VOLTAGE 122 /* voltage_sel is the bitfield loaded onto the SMPSX_VOLTAGE
126 * register. Set this is the default voltage set in OTP needs 123 * register. Set this is the default voltage set in OTP needs
127 * to be overridden. 124 * to be overridden.
@@ -154,6 +151,12 @@ enum palmas_regulators {
154 PALMAS_REG_LDO9, 151 PALMAS_REG_LDO9,
155 PALMAS_REG_LDOLN, 152 PALMAS_REG_LDOLN,
156 PALMAS_REG_LDOUSB, 153 PALMAS_REG_LDOUSB,
154 /* External regulators */
155 PALMAS_REG_REGEN1,
156 PALMAS_REG_REGEN2,
157 PALMAS_REG_REGEN3,
158 PALMAS_REG_SYSEN1,
159 PALMAS_REG_SYSEN2,
157 /* Total number of regulators */ 160 /* Total number of regulators */
158 PALMAS_NUM_REGS, 161 PALMAS_NUM_REGS,
159}; 162};
@@ -171,6 +174,9 @@ struct palmas_pmic_platform_data {
171 174
172 /* use LDO6 for vibrator control */ 175 /* use LDO6 for vibrator control */
173 int ldo6_vibrator; 176 int ldo6_vibrator;
177
178 /* Enable tracking mode of LDO8 */
179 bool enable_ldo8_tracking;
174}; 180};
175 181
176struct palmas_usb_platform_data { 182struct palmas_usb_platform_data {
@@ -331,6 +337,8 @@ struct palmas_pmic {
331 int smps457; 337 int smps457;
332 338
333 int range[PALMAS_REG_SMPS10]; 339 int range[PALMAS_REG_SMPS10];
340 unsigned int ramp_delay[PALMAS_REG_SMPS10];
341 unsigned int current_reg_mode[PALMAS_REG_SMPS10];
334}; 342};
335 343
336struct palmas_resource { 344struct palmas_resource {
diff --git a/include/linux/mfd/retu.h b/include/linux/mfd/retu.h
index 1e2715d5b836..65471c4a3926 100644
--- a/include/linux/mfd/retu.h
+++ b/include/linux/mfd/retu.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Retu MFD driver interface 2 * Retu/Tahvo MFD driver interface
3 * 3 *
4 * This file is subject to the terms and conditions of the GNU General 4 * This file is subject to the terms and conditions of the GNU General
5 * Public License. See the file "COPYING" in the main directory of this 5 * Public License. See the file "COPYING" in the main directory of this
@@ -19,4 +19,10 @@ int retu_write(struct retu_dev *, u8, u16);
19#define RETU_REG_CC1 0x0d /* Common control register 1 */ 19#define RETU_REG_CC1 0x0d /* Common control register 1 */
20#define RETU_REG_STATUS 0x16 /* Status register */ 20#define RETU_REG_STATUS 0x16 /* Status register */
21 21
22/* Interrupt sources */
23#define TAHVO_INT_VBUS 0 /* VBUS state */
24
25/* Interrupt status */
26#define TAHVO_STAT_VBUS (1 << TAHVO_INT_VBUS)
27
22#endif /* __LINUX_MFD_RETU_H */ 28#endif /* __LINUX_MFD_RETU_H */
diff --git a/include/linux/mfd/rtsx_pci.h b/include/linux/mfd/rtsx_pci.h
index 26ea7f1b7caf..86bc635f8385 100644
--- a/include/linux/mfd/rtsx_pci.h
+++ b/include/linux/mfd/rtsx_pci.h
@@ -500,6 +500,8 @@
500#define BPP_POWER_15_PERCENT_ON 0x08 500#define BPP_POWER_15_PERCENT_ON 0x08
501#define BPP_POWER_ON 0x00 501#define BPP_POWER_ON 0x00
502#define BPP_POWER_MASK 0x0F 502#define BPP_POWER_MASK 0x0F
503#define SD_VCC_PARTIAL_POWER_ON 0x02
504#define SD_VCC_POWER_ON 0x00
503 505
504/* PWR_GATE_CTRL */ 506/* PWR_GATE_CTRL */
505#define PWR_GATE_EN 0x01 507#define PWR_GATE_EN 0x01
@@ -689,6 +691,40 @@
689#define IMAGE_FLAG_ADDR0 0xCE80 691#define IMAGE_FLAG_ADDR0 0xCE80
690#define IMAGE_FLAG_ADDR1 0xCE81 692#define IMAGE_FLAG_ADDR1 0xCE81
691 693
694/* Phy register */
695#define PHY_PCR 0x00
696#define PHY_RCR0 0x01
697#define PHY_RCR1 0x02
698#define PHY_RCR2 0x03
699#define PHY_RTCR 0x04
700#define PHY_RDR 0x05
701#define PHY_TCR0 0x06
702#define PHY_TCR1 0x07
703#define PHY_TUNE 0x08
704#define PHY_IMR 0x09
705#define PHY_BPCR 0x0A
706#define PHY_BIST 0x0B
707#define PHY_RAW_L 0x0C
708#define PHY_RAW_H 0x0D
709#define PHY_RAW_DATA 0x0E
710#define PHY_HOST_CLK_CTRL 0x0F
711#define PHY_DMR 0x10
712#define PHY_BACR 0x11
713#define PHY_IER 0x12
714#define PHY_BCSR 0x13
715#define PHY_BPR 0x14
716#define PHY_BPNR2 0x15
717#define PHY_BPNR 0x16
718#define PHY_BRNR2 0x17
719#define PHY_BENR 0x18
720#define PHY_REG_REV 0x19
721#define PHY_FLD0 0x1A
722#define PHY_FLD1 0x1B
723#define PHY_FLD2 0x1C
724#define PHY_FLD3 0x1D
725#define PHY_FLD4 0x1E
726#define PHY_DUM_REG 0x1F
727
692#define rtsx_pci_init_cmd(pcr) ((pcr)->ci = 0) 728#define rtsx_pci_init_cmd(pcr) ((pcr)->ci = 0)
693 729
694struct rtsx_pcr; 730struct rtsx_pcr;
diff --git a/include/linux/mfd/si476x-core.h b/include/linux/mfd/si476x-core.h
new file mode 100644
index 000000000000..ba89b94e4a56
--- /dev/null
+++ b/include/linux/mfd/si476x-core.h
@@ -0,0 +1,533 @@
1/*
2 * include/media/si476x-core.h -- Common definitions for si476x core
3 * device
4 *
5 * Copyright (C) 2012 Innovative Converged Devices(ICD)
6 * Copyright (C) 2013 Andrey Smirnov
7 *
8 * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
18 *
19 */
20
21#ifndef SI476X_CORE_H
22#define SI476X_CORE_H
23
24#include <linux/kfifo.h>
25#include <linux/atomic.h>
26#include <linux/i2c.h>
27#include <linux/regmap.h>
28#include <linux/mutex.h>
29#include <linux/mfd/core.h>
30#include <linux/videodev2.h>
31#include <linux/regulator/consumer.h>
32
33#include <linux/mfd/si476x-platform.h>
34#include <linux/mfd/si476x-reports.h>
35
36/* Command Timeouts */
37#define SI476X_DEFAULT_TIMEOUT 100000
38#define SI476X_TIMEOUT_TUNE 700000
39#define SI476X_TIMEOUT_POWER_UP 330000
40#define SI476X_STATUS_POLL_US 0
41
42/* -------------------- si476x-i2c.c ----------------------- */
43
44enum si476x_freq_supported_chips {
45 SI476X_CHIP_SI4761 = 1,
46 SI476X_CHIP_SI4764,
47 SI476X_CHIP_SI4768,
48};
49
50enum si476x_part_revisions {
51 SI476X_REVISION_A10 = 0,
52 SI476X_REVISION_A20 = 1,
53 SI476X_REVISION_A30 = 2,
54};
55
56enum si476x_mfd_cells {
57 SI476X_RADIO_CELL = 0,
58 SI476X_CODEC_CELL,
59 SI476X_MFD_CELLS,
60};
61
62/**
63 * enum si476x_power_state - possible power state of the si476x
64 * device.
65 *
66 * @SI476X_POWER_DOWN: In this state all regulators are turned off
67 * and the reset line is pulled low. The device is completely
68 * inactive.
69 * @SI476X_POWER_UP_FULL: In this state all the power regualtors are
70 * turned on, reset line pulled high, IRQ line is enabled(polling is
71 * active for polling use scenario) and device is turned on with
72 * POWER_UP command. The device is ready to be used.
73 * @SI476X_POWER_INCONSISTENT: This state indicates that previous
74 * power down was inconsistent, meaning some of the regulators were
75 * not turned down and thus use of the device, without power-cycling
76 * is impossible.
77 */
78enum si476x_power_state {
79 SI476X_POWER_DOWN = 0,
80 SI476X_POWER_UP_FULL = 1,
81 SI476X_POWER_INCONSISTENT = 2,
82};
83
84/**
85 * struct si476x_core - internal data structure representing the
86 * underlying "core" device which all the MFD cell-devices use.
87 *
88 * @client: Actual I2C client used to transfer commands to the chip.
89 * @chip_id: Last digit of the chip model(E.g. "1" for SI4761)
90 * @cells: MFD cell devices created by this driver.
91 * @cmd_lock: Mutex used to serialize all the requests to the core
92 * device. This filed should not be used directly. Instead
93 * si476x_core_lock()/si476x_core_unlock() should be used to get
94 * exclusive access to the "core" device.
95 * @users: Active users counter(Used by the radio cell)
96 * @rds_read_queue: Wait queue used to wait for RDS data.
97 * @rds_fifo: FIFO in which all the RDS data received from the chip is
98 * placed.
99 * @rds_fifo_drainer: Worker that drains on-chip RDS FIFO.
100 * @rds_drainer_is_working: Flag used for launching only one instance
101 * of the @rds_fifo_drainer.
102 * @rds_drainer_status_lock: Lock used to guard access to the
103 * @rds_drainer_is_working variable.
104 * @command: Wait queue for wainting on the command comapletion.
105 * @cts: Clear To Send flag set upon receiving first status with CTS
106 * set.
107 * @tuning: Wait queue used for wainting for tune/seek comand
108 * completion.
109 * @stc: Similar to @cts, but for the STC bit of the status value.
110 * @power_up_parameters: Parameters used as argument for POWER_UP
111 * command when the device is started.
112 * @state: Current power state of the device.
113 * @supplues: Structure containing handles to all power supplies used
114 * by the device (NULL ones are ignored).
115 * @gpio_reset: GPIO pin connectet to the RSTB pin of the chip.
116 * @pinmux: Chip's configurable pins configuration.
117 * @diversity_mode: Chips role when functioning in diversity mode.
118 * @status_monitor: Polling worker used in polling use case scenarion
119 * (when IRQ is not avalible).
120 * @revision: Chip's running firmware revision number(Used for correct
121 * command set support).
122 */
123
124struct si476x_core {
125 struct i2c_client *client;
126 struct regmap *regmap;
127 int chip_id;
128 struct mfd_cell cells[SI476X_MFD_CELLS];
129
130 struct mutex cmd_lock; /* for serializing fm radio operations */
131 atomic_t users;
132
133 wait_queue_head_t rds_read_queue;
134 struct kfifo rds_fifo;
135 struct work_struct rds_fifo_drainer;
136 bool rds_drainer_is_working;
137 struct mutex rds_drainer_status_lock;
138
139 wait_queue_head_t command;
140 atomic_t cts;
141
142 wait_queue_head_t tuning;
143 atomic_t stc;
144
145 struct si476x_power_up_args power_up_parameters;
146
147 enum si476x_power_state power_state;
148
149 struct regulator_bulk_data supplies[4];
150
151 int gpio_reset;
152
153 struct si476x_pinmux pinmux;
154 enum si476x_phase_diversity_mode diversity_mode;
155
156 atomic_t is_alive;
157
158 struct delayed_work status_monitor;
159#define SI476X_WORK_TO_CORE(w) container_of(to_delayed_work(w), \
160 struct si476x_core, \
161 status_monitor)
162
163 int revision;
164
165 int rds_fifo_depth;
166};
167
168static inline struct si476x_core *i2c_mfd_cell_to_core(struct device *dev)
169{
170 struct i2c_client *client = to_i2c_client(dev->parent);
171 return i2c_get_clientdata(client);
172}
173
174
175/**
176 * si476x_core_lock() - lock the core device to get an exclusive access
177 * to it.
178 */
179static inline void si476x_core_lock(struct si476x_core *core)
180{
181 mutex_lock(&core->cmd_lock);
182}
183
184/**
185 * si476x_core_unlock() - unlock the core device to relinquish an
186 * exclusive access to it.
187 */
188static inline void si476x_core_unlock(struct si476x_core *core)
189{
190 mutex_unlock(&core->cmd_lock);
191}
192
193/* *_TUNE_FREQ family of commands accept frequency in multiples of
194 10kHz */
195static inline u16 hz_to_si476x(struct si476x_core *core, int freq)
196{
197 u16 result;
198
199 switch (core->power_up_parameters.func) {
200 default:
201 case SI476X_FUNC_FM_RECEIVER:
202 result = freq / 10000;
203 break;
204 case SI476X_FUNC_AM_RECEIVER:
205 result = freq / 1000;
206 break;
207 }
208
209 return result;
210}
211
212static inline int si476x_to_hz(struct si476x_core *core, u16 freq)
213{
214 int result;
215
216 switch (core->power_up_parameters.func) {
217 default:
218 case SI476X_FUNC_FM_RECEIVER:
219 result = freq * 10000;
220 break;
221 case SI476X_FUNC_AM_RECEIVER:
222 result = freq * 1000;
223 break;
224 }
225
226 return result;
227}
228
229/* Since the V4L2_TUNER_CAP_LOW flag is supplied, V4L2 subsystem
230 * mesures frequency in 62.5 Hz units */
231
232static inline int hz_to_v4l2(int freq)
233{
234 return (freq * 10) / 625;
235}
236
237static inline int v4l2_to_hz(int freq)
238{
239 return (freq * 625) / 10;
240}
241
242static inline u16 v4l2_to_si476x(struct si476x_core *core, int freq)
243{
244 return hz_to_si476x(core, v4l2_to_hz(freq));
245}
246
247static inline int si476x_to_v4l2(struct si476x_core *core, u16 freq)
248{
249 return hz_to_v4l2(si476x_to_hz(core, freq));
250}
251
252
253
254/**
255 * struct si476x_func_info - structure containing result of the
256 * FUNC_INFO command.
257 *
258 * @firmware.major: Firmware major number.
259 * @firmware.minor[...]: Firmware minor numbers.
260 * @patch_id:
261 * @func: Mode tuner is working in.
262 */
263struct si476x_func_info {
264 struct {
265 u8 major, minor[2];
266 } firmware;
267 u16 patch_id;
268 enum si476x_func func;
269};
270
271/**
272 * struct si476x_power_down_args - structure used to pass parameters
273 * to POWER_DOWN command
274 *
275 * @xosc: true - Power down, but leav oscillator running.
276 * false - Full power down.
277 */
278struct si476x_power_down_args {
279 bool xosc;
280};
281
282/**
283 * enum si476x_tunemode - enum representing possible tune modes for
284 * the chip.
285 * @SI476X_TM_VALIDATED_NORMAL_TUNE: Unconditionally stay on the new
286 * channel after tune, tune status is valid.
287 * @SI476X_TM_INVALIDATED_FAST_TUNE: Unconditionally stay in the new
288 * channel after tune, tune status invalid.
289 * @SI476X_TM_VALIDATED_AF_TUNE: Jump back to previous channel if
290 * metric thresholds are not met.
291 * @SI476X_TM_VALIDATED_AF_CHECK: Unconditionally jump back to the
292 * previous channel.
293 */
294enum si476x_tunemode {
295 SI476X_TM_VALIDATED_NORMAL_TUNE = 0,
296 SI476X_TM_INVALIDATED_FAST_TUNE = 1,
297 SI476X_TM_VALIDATED_AF_TUNE = 2,
298 SI476X_TM_VALIDATED_AF_CHECK = 3,
299};
300
301/**
302 * enum si476x_smoothmetrics - enum containing the possible setting fo
303 * audio transitioning of the chip
304 * @SI476X_SM_INITIALIZE_AUDIO: Initialize audio state to match this
305 * new channel
306 * @SI476X_SM_TRANSITION_AUDIO: Transition audio state from previous
307 * channel values to the new values
308 */
309enum si476x_smoothmetrics {
310 SI476X_SM_INITIALIZE_AUDIO = 0,
311 SI476X_SM_TRANSITION_AUDIO = 1,
312};
313
314/**
315 * struct si476x_rds_status_report - the structure representing the
316 * response to 'FM_RD_STATUS' command
317 * @rdstpptyint: Traffic program flag(TP) and/or program type(PTY)
318 * code has changed.
319 * @rdspiint: Program indentifiaction(PI) code has changed.
320 * @rdssyncint: RDS synchronization has changed.
321 * @rdsfifoint: RDS was received and the RDS FIFO has at least
322 * 'FM_RDS_INTERRUPT_FIFO_COUNT' elements in it.
323 * @tpptyvalid: TP flag and PTY code are valid falg.
324 * @pivalid: PI code is valid flag.
325 * @rdssync: RDS is currently synchronized.
326 * @rdsfifolost: On or more RDS groups have been lost/discarded flag.
327 * @tp: Current channel's TP flag.
328 * @pty: Current channel's PTY code.
329 * @pi: Current channel's PI code.
330 * @rdsfifoused: Number of blocks remaining in the RDS FIFO (0 if
331 * empty).
332 */
333struct si476x_rds_status_report {
334 bool rdstpptyint, rdspiint, rdssyncint, rdsfifoint;
335 bool tpptyvalid, pivalid, rdssync, rdsfifolost;
336 bool tp;
337
338 u8 pty;
339 u16 pi;
340
341 u8 rdsfifoused;
342 u8 ble[4];
343
344 struct v4l2_rds_data rds[4];
345};
346
347struct si476x_rsq_status_args {
348 bool primary;
349 bool rsqack;
350 bool attune;
351 bool cancel;
352 bool stcack;
353};
354
355enum si476x_injside {
356 SI476X_INJSIDE_AUTO = 0,
357 SI476X_INJSIDE_LOW = 1,
358 SI476X_INJSIDE_HIGH = 2,
359};
360
361struct si476x_tune_freq_args {
362 bool zifsr;
363 bool hd;
364 enum si476x_injside injside;
365 int freq;
366 enum si476x_tunemode tunemode;
367 enum si476x_smoothmetrics smoothmetrics;
368 int antcap;
369};
370
371int si476x_core_stop(struct si476x_core *, bool);
372int si476x_core_start(struct si476x_core *, bool);
373int si476x_core_set_power_state(struct si476x_core *, enum si476x_power_state);
374bool si476x_core_has_am(struct si476x_core *);
375bool si476x_core_has_diversity(struct si476x_core *);
376bool si476x_core_is_a_secondary_tuner(struct si476x_core *);
377bool si476x_core_is_a_primary_tuner(struct si476x_core *);
378bool si476x_core_is_in_am_receiver_mode(struct si476x_core *core);
379bool si476x_core_is_powered_up(struct si476x_core *core);
380
381enum si476x_i2c_type {
382 SI476X_I2C_SEND,
383 SI476X_I2C_RECV
384};
385
386int si476x_core_i2c_xfer(struct si476x_core *,
387 enum si476x_i2c_type,
388 char *, int);
389
390
391/* -------------------- si476x-cmd.c ----------------------- */
392
393int si476x_core_cmd_func_info(struct si476x_core *, struct si476x_func_info *);
394int si476x_core_cmd_set_property(struct si476x_core *, u16, u16);
395int si476x_core_cmd_get_property(struct si476x_core *, u16);
396int si476x_core_cmd_dig_audio_pin_cfg(struct si476x_core *,
397 enum si476x_dclk_config,
398 enum si476x_dfs_config,
399 enum si476x_dout_config,
400 enum si476x_xout_config);
401int si476x_core_cmd_zif_pin_cfg(struct si476x_core *,
402 enum si476x_iqclk_config,
403 enum si476x_iqfs_config,
404 enum si476x_iout_config,
405 enum si476x_qout_config);
406int si476x_core_cmd_ic_link_gpo_ctl_pin_cfg(struct si476x_core *,
407 enum si476x_icin_config,
408 enum si476x_icip_config,
409 enum si476x_icon_config,
410 enum si476x_icop_config);
411int si476x_core_cmd_ana_audio_pin_cfg(struct si476x_core *,
412 enum si476x_lrout_config);
413int si476x_core_cmd_intb_pin_cfg(struct si476x_core *, enum si476x_intb_config,
414 enum si476x_a1_config);
415int si476x_core_cmd_fm_seek_start(struct si476x_core *, bool, bool);
416int si476x_core_cmd_am_seek_start(struct si476x_core *, bool, bool);
417int si476x_core_cmd_fm_rds_status(struct si476x_core *, bool, bool, bool,
418 struct si476x_rds_status_report *);
419int si476x_core_cmd_fm_rds_blockcount(struct si476x_core *, bool,
420 struct si476x_rds_blockcount_report *);
421int si476x_core_cmd_fm_tune_freq(struct si476x_core *,
422 struct si476x_tune_freq_args *);
423int si476x_core_cmd_am_tune_freq(struct si476x_core *,
424 struct si476x_tune_freq_args *);
425int si476x_core_cmd_am_rsq_status(struct si476x_core *,
426 struct si476x_rsq_status_args *,
427 struct si476x_rsq_status_report *);
428int si476x_core_cmd_fm_rsq_status(struct si476x_core *,
429 struct si476x_rsq_status_args *,
430 struct si476x_rsq_status_report *);
431int si476x_core_cmd_power_up(struct si476x_core *,
432 struct si476x_power_up_args *);
433int si476x_core_cmd_power_down(struct si476x_core *,
434 struct si476x_power_down_args *);
435int si476x_core_cmd_fm_phase_div_status(struct si476x_core *);
436int si476x_core_cmd_fm_phase_diversity(struct si476x_core *,
437 enum si476x_phase_diversity_mode);
438
439int si476x_core_cmd_fm_acf_status(struct si476x_core *,
440 struct si476x_acf_status_report *);
441int si476x_core_cmd_am_acf_status(struct si476x_core *,
442 struct si476x_acf_status_report *);
443int si476x_core_cmd_agc_status(struct si476x_core *,
444 struct si476x_agc_status_report *);
445
446enum si476x_power_grid_type {
447 SI476X_POWER_GRID_50HZ = 0,
448 SI476X_POWER_GRID_60HZ,
449};
450
451/* Properties */
452
453enum si476x_interrupt_flags {
454 SI476X_STCIEN = (1 << 0),
455 SI476X_ACFIEN = (1 << 1),
456 SI476X_RDSIEN = (1 << 2),
457 SI476X_RSQIEN = (1 << 3),
458
459 SI476X_ERRIEN = (1 << 6),
460 SI476X_CTSIEN = (1 << 7),
461
462 SI476X_STCREP = (1 << 8),
463 SI476X_ACFREP = (1 << 9),
464 SI476X_RDSREP = (1 << 10),
465 SI476X_RSQREP = (1 << 11),
466};
467
468enum si476x_rdsint_sources {
469 SI476X_RDSTPPTY = (1 << 4),
470 SI476X_RDSPI = (1 << 3),
471 SI476X_RDSSYNC = (1 << 1),
472 SI476X_RDSRECV = (1 << 0),
473};
474
475enum si476x_status_response_bits {
476 SI476X_CTS = (1 << 7),
477 SI476X_ERR = (1 << 6),
478 /* Status response for WB receiver */
479 SI476X_WB_ASQ_INT = (1 << 4),
480 SI476X_RSQ_INT = (1 << 3),
481 /* Status response for FM receiver */
482 SI476X_FM_RDS_INT = (1 << 2),
483 SI476X_ACF_INT = (1 << 1),
484 SI476X_STC_INT = (1 << 0),
485};
486
487/* -------------------- si476x-prop.c ----------------------- */
488
489enum si476x_common_receiver_properties {
490 SI476X_PROP_INT_CTL_ENABLE = 0x0000,
491 SI476X_PROP_DIGITAL_IO_INPUT_SAMPLE_RATE = 0x0200,
492 SI476X_PROP_DIGITAL_IO_INPUT_FORMAT = 0x0201,
493 SI476X_PROP_DIGITAL_IO_OUTPUT_SAMPLE_RATE = 0x0202,
494 SI476X_PROP_DIGITAL_IO_OUTPUT_FORMAT = 0x0203,
495
496 SI476X_PROP_SEEK_BAND_BOTTOM = 0x1100,
497 SI476X_PROP_SEEK_BAND_TOP = 0x1101,
498 SI476X_PROP_SEEK_FREQUENCY_SPACING = 0x1102,
499
500 SI476X_PROP_VALID_MAX_TUNE_ERROR = 0x2000,
501 SI476X_PROP_VALID_SNR_THRESHOLD = 0x2003,
502 SI476X_PROP_VALID_RSSI_THRESHOLD = 0x2004,
503};
504
505enum si476x_am_receiver_properties {
506 SI476X_PROP_AUDIO_PWR_LINE_FILTER = 0x0303,
507};
508
509enum si476x_fm_receiver_properties {
510 SI476X_PROP_AUDIO_DEEMPHASIS = 0x0302,
511
512 SI476X_PROP_FM_RDS_INTERRUPT_SOURCE = 0x4000,
513 SI476X_PROP_FM_RDS_INTERRUPT_FIFO_COUNT = 0x4001,
514 SI476X_PROP_FM_RDS_CONFIG = 0x4002,
515};
516
517enum si476x_prop_audio_pwr_line_filter_bits {
518 SI476X_PROP_PWR_HARMONICS_MASK = 0x001f,
519 SI476X_PROP_PWR_GRID_MASK = 0x0100,
520 SI476X_PROP_PWR_ENABLE_MASK = 0x0200,
521 SI476X_PROP_PWR_GRID_50HZ = 0x0000,
522 SI476X_PROP_PWR_GRID_60HZ = 0x0100,
523};
524
525enum si476x_prop_fm_rds_config_bits {
526 SI476X_PROP_RDSEN_MASK = 0x1,
527 SI476X_PROP_RDSEN = 0x1,
528};
529
530
531struct regmap *devm_regmap_init_si476x(struct si476x_core *);
532
533#endif /* SI476X_CORE_H */
diff --git a/include/linux/mfd/si476x-platform.h b/include/linux/mfd/si476x-platform.h
new file mode 100644
index 000000000000..88bb93b7a9d5
--- /dev/null
+++ b/include/linux/mfd/si476x-platform.h
@@ -0,0 +1,267 @@
1/*
2 * include/media/si476x-platform.h -- Platform data specific definitions
3 *
4 * Copyright (C) 2013 Andrey Smirnov
5 *
6 * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 */
18
19#ifndef __SI476X_PLATFORM_H__
20#define __SI476X_PLATFORM_H__
21
22/* It is possible to select one of the four adresses using pins A0
23 * and A1 on SI476x */
24#define SI476X_I2C_ADDR_1 0x60
25#define SI476X_I2C_ADDR_2 0x61
26#define SI476X_I2C_ADDR_3 0x62
27#define SI476X_I2C_ADDR_4 0x63
28
29enum si476x_iqclk_config {
30 SI476X_IQCLK_NOOP = 0,
31 SI476X_IQCLK_TRISTATE = 1,
32 SI476X_IQCLK_IQ = 21,
33};
34enum si476x_iqfs_config {
35 SI476X_IQFS_NOOP = 0,
36 SI476X_IQFS_TRISTATE = 1,
37 SI476X_IQFS_IQ = 21,
38};
39enum si476x_iout_config {
40 SI476X_IOUT_NOOP = 0,
41 SI476X_IOUT_TRISTATE = 1,
42 SI476X_IOUT_OUTPUT = 22,
43};
44enum si476x_qout_config {
45 SI476X_QOUT_NOOP = 0,
46 SI476X_QOUT_TRISTATE = 1,
47 SI476X_QOUT_OUTPUT = 22,
48};
49
50enum si476x_dclk_config {
51 SI476X_DCLK_NOOP = 0,
52 SI476X_DCLK_TRISTATE = 1,
53 SI476X_DCLK_DAUDIO = 10,
54};
55
56enum si476x_dfs_config {
57 SI476X_DFS_NOOP = 0,
58 SI476X_DFS_TRISTATE = 1,
59 SI476X_DFS_DAUDIO = 10,
60};
61
62enum si476x_dout_config {
63 SI476X_DOUT_NOOP = 0,
64 SI476X_DOUT_TRISTATE = 1,
65 SI476X_DOUT_I2S_OUTPUT = 12,
66 SI476X_DOUT_I2S_INPUT = 13,
67};
68
69enum si476x_xout_config {
70 SI476X_XOUT_NOOP = 0,
71 SI476X_XOUT_TRISTATE = 1,
72 SI476X_XOUT_I2S_INPUT = 13,
73 SI476X_XOUT_MODE_SELECT = 23,
74};
75
76enum si476x_icin_config {
77 SI476X_ICIN_NOOP = 0,
78 SI476X_ICIN_TRISTATE = 1,
79 SI476X_ICIN_GPO1_HIGH = 2,
80 SI476X_ICIN_GPO1_LOW = 3,
81 SI476X_ICIN_IC_LINK = 30,
82};
83
84enum si476x_icip_config {
85 SI476X_ICIP_NOOP = 0,
86 SI476X_ICIP_TRISTATE = 1,
87 SI476X_ICIP_GPO2_HIGH = 2,
88 SI476X_ICIP_GPO2_LOW = 3,
89 SI476X_ICIP_IC_LINK = 30,
90};
91
92enum si476x_icon_config {
93 SI476X_ICON_NOOP = 0,
94 SI476X_ICON_TRISTATE = 1,
95 SI476X_ICON_I2S = 10,
96 SI476X_ICON_IC_LINK = 30,
97};
98
99enum si476x_icop_config {
100 SI476X_ICOP_NOOP = 0,
101 SI476X_ICOP_TRISTATE = 1,
102 SI476X_ICOP_I2S = 10,
103 SI476X_ICOP_IC_LINK = 30,
104};
105
106
107enum si476x_lrout_config {
108 SI476X_LROUT_NOOP = 0,
109 SI476X_LROUT_TRISTATE = 1,
110 SI476X_LROUT_AUDIO = 2,
111 SI476X_LROUT_MPX = 3,
112};
113
114
115enum si476x_intb_config {
116 SI476X_INTB_NOOP = 0,
117 SI476X_INTB_TRISTATE = 1,
118 SI476X_INTB_DAUDIO = 10,
119 SI476X_INTB_IRQ = 40,
120};
121
122enum si476x_a1_config {
123 SI476X_A1_NOOP = 0,
124 SI476X_A1_TRISTATE = 1,
125 SI476X_A1_IRQ = 40,
126};
127
128
129struct si476x_pinmux {
130 enum si476x_dclk_config dclk;
131 enum si476x_dfs_config dfs;
132 enum si476x_dout_config dout;
133 enum si476x_xout_config xout;
134
135 enum si476x_iqclk_config iqclk;
136 enum si476x_iqfs_config iqfs;
137 enum si476x_iout_config iout;
138 enum si476x_qout_config qout;
139
140 enum si476x_icin_config icin;
141 enum si476x_icip_config icip;
142 enum si476x_icon_config icon;
143 enum si476x_icop_config icop;
144
145 enum si476x_lrout_config lrout;
146
147 enum si476x_intb_config intb;
148 enum si476x_a1_config a1;
149};
150
151enum si476x_ibias6x {
152 SI476X_IBIAS6X_OTHER = 0,
153 SI476X_IBIAS6X_RCVR1_NON_4MHZ_CLK = 1,
154};
155
156enum si476x_xstart {
157 SI476X_XSTART_MULTIPLE_TUNER = 0x11,
158 SI476X_XSTART_NORMAL = 0x77,
159};
160
161enum si476x_freq {
162 SI476X_FREQ_4_MHZ = 0,
163 SI476X_FREQ_37P209375_MHZ = 1,
164 SI476X_FREQ_36P4_MHZ = 2,
165 SI476X_FREQ_37P8_MHZ = 3,
166};
167
168enum si476x_xmode {
169 SI476X_XMODE_CRYSTAL_RCVR1 = 1,
170 SI476X_XMODE_EXT_CLOCK = 2,
171 SI476X_XMODE_CRYSTAL_RCVR2_3 = 3,
172};
173
174enum si476x_xbiashc {
175 SI476X_XBIASHC_SINGLE_RECEIVER = 0,
176 SI476X_XBIASHC_MULTIPLE_RECEIVER = 1,
177};
178
179enum si476x_xbias {
180 SI476X_XBIAS_RCVR2_3 = 0,
181 SI476X_XBIAS_4MHZ_RCVR1 = 3,
182 SI476X_XBIAS_RCVR1 = 7,
183};
184
185enum si476x_func {
186 SI476X_FUNC_BOOTLOADER = 0,
187 SI476X_FUNC_FM_RECEIVER = 1,
188 SI476X_FUNC_AM_RECEIVER = 2,
189 SI476X_FUNC_WB_RECEIVER = 3,
190};
191
192
193/**
194 * @xcload: Selects the amount of additional on-chip capacitance to
195 * be connected between XTAL1 and gnd and between XTAL2 and
196 * GND. One half of the capacitance value shown here is the
197 * additional load capacitance presented to the xtal. The
198 * minimum step size is 0.277 pF. Recommended value is 0x28
199 * but it will be layout dependent. Range is 0–0x3F i.e.
200 * (0–16.33 pF)
201 * @ctsien: enable CTSINT(interrupt request when CTS condition
202 * arises) when set
203 * @intsel: when set A1 pin becomes the interrupt pin; otherwise,
204 * INTB is the interrupt pin
205 * @func: selects the boot function of the device. I.e.
206 * SI476X_BOOTLOADER - Boot loader
207 * SI476X_FM_RECEIVER - FM receiver
208 * SI476X_AM_RECEIVER - AM receiver
209 * SI476X_WB_RECEIVER - Weatherband receiver
210 * @freq: oscillator's crystal frequency:
211 * SI476X_XTAL_37P209375_MHZ - 37.209375 Mhz
212 * SI476X_XTAL_36P4_MHZ - 36.4 Mhz
213 * SI476X_XTAL_37P8_MHZ - 37.8 Mhz
214 */
215struct si476x_power_up_args {
216 enum si476x_ibias6x ibias6x;
217 enum si476x_xstart xstart;
218 u8 xcload;
219 bool fastboot;
220 enum si476x_xbiashc xbiashc;
221 enum si476x_xbias xbias;
222 enum si476x_func func;
223 enum si476x_freq freq;
224 enum si476x_xmode xmode;
225};
226
227
228/**
229 * enum si476x_phase_diversity_mode - possbile phase diversity modes
230 * for SI4764/5/6/7 chips.
231 *
232 * @SI476X_PHDIV_DISABLED: Phase diversity feature is
233 * disabled.
234 * @SI476X_PHDIV_PRIMARY_COMBINING: Tuner works as a primary tuner
235 * in combination with a
236 * secondary one.
237 * @SI476X_PHDIV_PRIMARY_ANTENNA: Tuner works as a primary tuner
238 * using only its own antenna.
239 * @SI476X_PHDIV_SECONDARY_ANTENNA: Tuner works as a primary tuner
240 * usning seconary tuner's antenna.
241 * @SI476X_PHDIV_SECONDARY_COMBINING: Tuner works as a secondary
242 * tuner in combination with the
243 * primary one.
244 */
245enum si476x_phase_diversity_mode {
246 SI476X_PHDIV_DISABLED = 0,
247 SI476X_PHDIV_PRIMARY_COMBINING = 1,
248 SI476X_PHDIV_PRIMARY_ANTENNA = 2,
249 SI476X_PHDIV_SECONDARY_ANTENNA = 3,
250 SI476X_PHDIV_SECONDARY_COMBINING = 5,
251};
252
253
254/*
255 * Platform dependent definition
256 */
257struct si476x_platform_data {
258 int gpio_reset; /* < 0 if not used */
259
260 struct si476x_power_up_args power_up_parameters;
261 enum si476x_phase_diversity_mode diversity_mode;
262
263 struct si476x_pinmux pinmux;
264};
265
266
267#endif /* __SI476X_PLATFORM_H__ */
diff --git a/include/linux/mfd/si476x-reports.h b/include/linux/mfd/si476x-reports.h
new file mode 100644
index 000000000000..e0b9455a79c0
--- /dev/null
+++ b/include/linux/mfd/si476x-reports.h
@@ -0,0 +1,163 @@
1/*
2 * include/media/si476x-platform.h -- Definitions of the data formats
3 * returned by debugfs hooks
4 *
5 * Copyright (C) 2013 Andrey Smirnov
6 *
7 * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 */
19
20#ifndef __SI476X_REPORTS_H__
21#define __SI476X_REPORTS_H__
22
23/**
24 * struct si476x_rsq_status - structure containing received signal
25 * quality
26 * @multhint: Multipath Detect High.
27 * true - Indicatedes that the value is below
28 * FM_RSQ_MULTIPATH_HIGH_THRESHOLD
29 * false - Indicatedes that the value is above
30 * FM_RSQ_MULTIPATH_HIGH_THRESHOLD
31 * @multlint: Multipath Detect Low.
32 * true - Indicatedes that the value is below
33 * FM_RSQ_MULTIPATH_LOW_THRESHOLD
34 * false - Indicatedes that the value is above
35 * FM_RSQ_MULTIPATH_LOW_THRESHOLD
36 * @snrhint: SNR Detect High.
37 * true - Indicatedes that the value is below
38 * FM_RSQ_SNR_HIGH_THRESHOLD
39 * false - Indicatedes that the value is above
40 * FM_RSQ_SNR_HIGH_THRESHOLD
41 * @snrlint: SNR Detect Low.
42 * true - Indicatedes that the value is below
43 * FM_RSQ_SNR_LOW_THRESHOLD
44 * false - Indicatedes that the value is above
45 * FM_RSQ_SNR_LOW_THRESHOLD
46 * @rssihint: RSSI Detect High.
47 * true - Indicatedes that the value is below
48 * FM_RSQ_RSSI_HIGH_THRESHOLD
49 * false - Indicatedes that the value is above
50 * FM_RSQ_RSSI_HIGH_THRESHOLD
51 * @rssilint: RSSI Detect Low.
52 * true - Indicatedes that the value is below
53 * FM_RSQ_RSSI_LOW_THRESHOLD
54 * false - Indicatedes that the value is above
55 * FM_RSQ_RSSI_LOW_THRESHOLD
56 * @bltf: Band Limit.
57 * Set if seek command hits the band limit or wrapped to
58 * the original frequency.
59 * @snr_ready: SNR measurement in progress.
60 * @rssiready: RSSI measurement in progress.
61 * @afcrl: Set if FREQOFF >= MAX_TUNE_ERROR
62 * @valid: Set if the channel is valid
63 * rssi < FM_VALID_RSSI_THRESHOLD
64 * snr < FM_VALID_SNR_THRESHOLD
65 * tune_error < FM_VALID_MAX_TUNE_ERROR
66 * @readfreq: Current tuned frequency.
67 * @freqoff: Signed frequency offset.
68 * @rssi: Received Signal Strength Indicator(dBuV).
69 * @snr: RF SNR Indicator(dB).
70 * @lassi:
71 * @hassi: Low/High side Adjacent(100 kHz) Channel Strength Indicator
72 * @mult: Multipath indicator
73 * @dev: Who knows? But values may vary.
74 * @readantcap: Antenna tuning capacity value.
75 * @assi: Adjacent Channel(+/- 200kHz) Strength Indicator
76 * @usn: Ultrasonic Noise Inticator in -DBFS
77 */
78struct si476x_rsq_status_report {
79 __u8 multhint, multlint;
80 __u8 snrhint, snrlint;
81 __u8 rssihint, rssilint;
82 __u8 bltf;
83 __u8 snr_ready;
84 __u8 rssiready;
85 __u8 injside;
86 __u8 afcrl;
87 __u8 valid;
88
89 __u16 readfreq;
90 __s8 freqoff;
91 __s8 rssi;
92 __s8 snr;
93 __s8 issi;
94 __s8 lassi, hassi;
95 __s8 mult;
96 __u8 dev;
97 __u16 readantcap;
98 __s8 assi;
99 __s8 usn;
100
101 __u8 pilotdev;
102 __u8 rdsdev;
103 __u8 assidev;
104 __u8 strongdev;
105 __u16 rdspi;
106} __packed;
107
108/**
109 * si476x_acf_status_report - ACF report results
110 *
111 * @blend_int: If set, indicates that stereo separation has crossed
112 * below the blend threshold as set by FM_ACF_BLEND_THRESHOLD
113 * @hblend_int: If set, indicates that HiBlend cutoff frequency is
114 * lower than threshold as set by FM_ACF_HBLEND_THRESHOLD
115 * @hicut_int: If set, indicates that HiCut cutoff frequency is lower
116 * than the threshold set by ACF_
117
118 */
119struct si476x_acf_status_report {
120 __u8 blend_int;
121 __u8 hblend_int;
122 __u8 hicut_int;
123 __u8 chbw_int;
124 __u8 softmute_int;
125 __u8 smute;
126 __u8 smattn;
127 __u8 chbw;
128 __u8 hicut;
129 __u8 hiblend;
130 __u8 pilot;
131 __u8 stblend;
132} __packed;
133
134enum si476x_fmagc {
135 SI476X_FMAGC_10K_OHM = 0,
136 SI476X_FMAGC_800_OHM = 1,
137 SI476X_FMAGC_400_OHM = 2,
138 SI476X_FMAGC_200_OHM = 4,
139 SI476X_FMAGC_100_OHM = 8,
140 SI476X_FMAGC_50_OHM = 16,
141 SI476X_FMAGC_25_OHM = 32,
142 SI476X_FMAGC_12P5_OHM = 64,
143 SI476X_FMAGC_6P25_OHM = 128,
144};
145
146struct si476x_agc_status_report {
147 __u8 mxhi;
148 __u8 mxlo;
149 __u8 lnahi;
150 __u8 lnalo;
151 __u8 fmagc1;
152 __u8 fmagc2;
153 __u8 pgagain;
154 __u8 fmwblang;
155} __packed;
156
157struct si476x_rds_blockcount_report {
158 __u16 expected;
159 __u16 received;
160 __u16 uncorrectable;
161} __packed;
162
163#endif /* __SI476X_REPORTS_H__ */
diff --git a/include/linux/mfd/stmpe.h b/include/linux/mfd/stmpe.h
index 383ac1512a39..48395a69a7e9 100644
--- a/include/linux/mfd/stmpe.h
+++ b/include/linux/mfd/stmpe.h
@@ -26,6 +26,7 @@ enum stmpe_partnum {
26 STMPE801, 26 STMPE801,
27 STMPE811, 27 STMPE811,
28 STMPE1601, 28 STMPE1601,
29 STMPE1801,
29 STMPE2401, 30 STMPE2401,
30 STMPE2403, 31 STMPE2403,
31 STMPE_NBR_PARTS 32 STMPE_NBR_PARTS
@@ -39,6 +40,7 @@ enum {
39 STMPE_IDX_CHIP_ID, 40 STMPE_IDX_CHIP_ID,
40 STMPE_IDX_ICR_LSB, 41 STMPE_IDX_ICR_LSB,
41 STMPE_IDX_IER_LSB, 42 STMPE_IDX_IER_LSB,
43 STMPE_IDX_ISR_LSB,
42 STMPE_IDX_ISR_MSB, 44 STMPE_IDX_ISR_MSB,
43 STMPE_IDX_GPMR_LSB, 45 STMPE_IDX_GPMR_LSB,
44 STMPE_IDX_GPSR_LSB, 46 STMPE_IDX_GPSR_LSB,
@@ -49,6 +51,7 @@ enum {
49 STMPE_IDX_GPFER_LSB, 51 STMPE_IDX_GPFER_LSB,
50 STMPE_IDX_GPAFR_U_MSB, 52 STMPE_IDX_GPAFR_U_MSB,
51 STMPE_IDX_IEGPIOR_LSB, 53 STMPE_IDX_IEGPIOR_LSB,
54 STMPE_IDX_ISGPIOR_LSB,
52 STMPE_IDX_ISGPIOR_MSB, 55 STMPE_IDX_ISGPIOR_MSB,
53 STMPE_IDX_MAX, 56 STMPE_IDX_MAX,
54}; 57};
diff --git a/include/linux/mfd/syscon.h b/include/linux/mfd/syscon.h
index 6aeb6b8da64d..b473577f36db 100644
--- a/include/linux/mfd/syscon.h
+++ b/include/linux/mfd/syscon.h
@@ -15,8 +15,11 @@
15#ifndef __LINUX_MFD_SYSCON_H__ 15#ifndef __LINUX_MFD_SYSCON_H__
16#define __LINUX_MFD_SYSCON_H__ 16#define __LINUX_MFD_SYSCON_H__
17 17
18struct device_node;
19
18extern struct regmap *syscon_node_to_regmap(struct device_node *np); 20extern struct regmap *syscon_node_to_regmap(struct device_node *np);
19extern struct regmap *syscon_regmap_lookup_by_compatible(const char *s); 21extern struct regmap *syscon_regmap_lookup_by_compatible(const char *s);
22extern struct regmap *syscon_regmap_lookup_by_pdevname(const char *s);
20extern struct regmap *syscon_regmap_lookup_by_phandle( 23extern struct regmap *syscon_regmap_lookup_by_phandle(
21 struct device_node *np, 24 struct device_node *np,
22 const char *property); 25 const char *property);
diff --git a/include/linux/mfd/tps65090.h b/include/linux/mfd/tps65090.h
index 6694cf43e8b8..3f43069413e7 100644
--- a/include/linux/mfd/tps65090.h
+++ b/include/linux/mfd/tps65090.h
@@ -27,6 +27,7 @@
27 27
28/* TPS65090 IRQs */ 28/* TPS65090 IRQs */
29enum { 29enum {
30 TPS65090_IRQ_INTERRUPT,
30 TPS65090_IRQ_VAC_STATUS_CHANGE, 31 TPS65090_IRQ_VAC_STATUS_CHANGE,
31 TPS65090_IRQ_VSYS_STATUS_CHANGE, 32 TPS65090_IRQ_VSYS_STATUS_CHANGE,
32 TPS65090_IRQ_BAT_STATUS_CHANGE, 33 TPS65090_IRQ_BAT_STATUS_CHANGE,
@@ -86,6 +87,11 @@ struct tps65090_regulator_plat_data {
86 87
87struct tps65090_platform_data { 88struct tps65090_platform_data {
88 int irq_base; 89 int irq_base;
90
91 char **supplied_to;
92 size_t num_supplicants;
93 int enable_low_current_chrg;
94
89 struct tps65090_regulator_plat_data *reg_pdata[TPS65090_REGULATOR_MAX]; 95 struct tps65090_regulator_plat_data *reg_pdata[TPS65090_REGULATOR_MAX];
90}; 96};
91 97
diff --git a/include/linux/mfd/tps65217.h b/include/linux/mfd/tps65217.h
index 290762f93930..29eab2bd3dfa 100644
--- a/include/linux/mfd/tps65217.h
+++ b/include/linux/mfd/tps65217.h
@@ -228,6 +228,7 @@ enum tps65217_bl_fdim {
228struct tps65217_bl_pdata { 228struct tps65217_bl_pdata {
229 enum tps65217_bl_isel isel; 229 enum tps65217_bl_isel isel;
230 enum tps65217_bl_fdim fdim; 230 enum tps65217_bl_fdim fdim;
231 int dft_brightness;
231}; 232};
232 233
233/** 234/**
diff --git a/include/linux/mfd/wm8994/pdata.h b/include/linux/mfd/wm8994/pdata.h
index 8e21a094836d..68e776594889 100644
--- a/include/linux/mfd/wm8994/pdata.h
+++ b/include/linux/mfd/wm8994/pdata.h
@@ -17,6 +17,7 @@
17 17
18#define WM8994_NUM_LDO 2 18#define WM8994_NUM_LDO 2
19#define WM8994_NUM_GPIO 11 19#define WM8994_NUM_GPIO 11
20#define WM8994_NUM_AIF 3
20 21
21struct wm8994_ldo_pdata { 22struct wm8994_ldo_pdata {
22 /** GPIOs to enable regulator, 0 or less if not available */ 23 /** GPIOs to enable regulator, 0 or less if not available */
@@ -215,6 +216,13 @@ struct wm8994_pdata {
215 * system. 216 * system.
216 */ 217 */
217 bool spkmode_pu; 218 bool spkmode_pu;
219
220 /**
221 * Maximum number of channels clocks will be generated for,
222 * useful for systems where and I2S bus with multiple data
223 * lines is mastered.
224 */
225 int max_channels_clocked[WM8994_NUM_AIF];
218}; 226};
219 227
220#endif 228#endif
generated by cgit v1.2.2 (git 2.25.0) at 2026-03-24 08:13:23 -0400