diff options
Diffstat (limited to 'include/linux/mfd/palmas.h')
-rw-r--r-- | include/linux/mfd/palmas.h | 837 |
1 files changed, 837 insertions, 0 deletions
diff --git a/include/linux/mfd/palmas.h b/include/linux/mfd/palmas.h index 3420e09e2e20..fb0390a1a498 100644 --- a/include/linux/mfd/palmas.h +++ b/include/linux/mfd/palmas.h | |||
@@ -30,6 +30,8 @@ | |||
30 | #define PALMAS_CHIP_ID 0xC035 | 30 | #define PALMAS_CHIP_ID 0xC035 |
31 | #define PALMAS_CHIP_CHARGER_ID 0xC036 | 31 | #define PALMAS_CHIP_CHARGER_ID 0xC036 |
32 | 32 | ||
33 | #define TPS65917_RESERVED -1 | ||
34 | |||
33 | #define is_palmas(a) (((a) == PALMAS_CHIP_OLD_ID) || \ | 35 | #define is_palmas(a) (((a) == PALMAS_CHIP_OLD_ID) || \ |
34 | ((a) == PALMAS_CHIP_ID)) | 36 | ((a) == PALMAS_CHIP_ID)) |
35 | #define is_palmas_charger(a) ((a) == PALMAS_CHIP_CHARGER_ID) | 37 | #define is_palmas_charger(a) ((a) == PALMAS_CHIP_CHARGER_ID) |
@@ -51,6 +53,8 @@ struct palmas_pmic; | |||
51 | struct palmas_gpadc; | 53 | struct palmas_gpadc; |
52 | struct palmas_resource; | 54 | struct palmas_resource; |
53 | struct palmas_usb; | 55 | struct palmas_usb; |
56 | struct palmas_pmic_driver_data; | ||
57 | struct palmas_pmic_platform_data; | ||
54 | 58 | ||
55 | enum palmas_usb_state { | 59 | enum palmas_usb_state { |
56 | PALMAS_USB_STATE_DISCONNECT, | 60 | PALMAS_USB_STATE_DISCONNECT, |
@@ -74,6 +78,8 @@ struct palmas { | |||
74 | struct mutex irq_lock; | 78 | struct mutex irq_lock; |
75 | struct regmap_irq_chip_data *irq_data; | 79 | struct regmap_irq_chip_data *irq_data; |
76 | 80 | ||
81 | struct palmas_pmic_driver_data *pmic_ddata; | ||
82 | |||
77 | /* Child Devices */ | 83 | /* Child Devices */ |
78 | struct palmas_pmic *pmic; | 84 | struct palmas_pmic *pmic; |
79 | struct palmas_gpadc *gpadc; | 85 | struct palmas_gpadc *gpadc; |
@@ -86,6 +92,46 @@ struct palmas { | |||
86 | u8 pwm_muxed; | 92 | u8 pwm_muxed; |
87 | }; | 93 | }; |
88 | 94 | ||
95 | #define PALMAS_EXT_REQ (PALMAS_EXT_CONTROL_ENABLE1 | \ | ||
96 | PALMAS_EXT_CONTROL_ENABLE2 | \ | ||
97 | PALMAS_EXT_CONTROL_NSLEEP) | ||
98 | |||
99 | struct palmas_sleep_requestor_info { | ||
100 | int id; | ||
101 | int reg_offset; | ||
102 | int bit_pos; | ||
103 | }; | ||
104 | |||
105 | struct palmas_regs_info { | ||
106 | char *name; | ||
107 | char *sname; | ||
108 | u8 vsel_addr; | ||
109 | u8 ctrl_addr; | ||
110 | u8 tstep_addr; | ||
111 | int sleep_id; | ||
112 | }; | ||
113 | |||
114 | struct palmas_pmic_driver_data { | ||
115 | int smps_start; | ||
116 | int smps_end; | ||
117 | int ldo_begin; | ||
118 | int ldo_end; | ||
119 | int max_reg; | ||
120 | struct palmas_regs_info *palmas_regs_info; | ||
121 | struct of_regulator_match *palmas_matches; | ||
122 | struct palmas_sleep_requestor_info *sleep_req_info; | ||
123 | int (*smps_register)(struct palmas_pmic *pmic, | ||
124 | struct palmas_pmic_driver_data *ddata, | ||
125 | struct palmas_pmic_platform_data *pdata, | ||
126 | const char *pdev_name, | ||
127 | struct regulator_config config); | ||
128 | int (*ldo_register)(struct palmas_pmic *pmic, | ||
129 | struct palmas_pmic_driver_data *ddata, | ||
130 | struct palmas_pmic_platform_data *pdata, | ||
131 | const char *pdev_name, | ||
132 | struct regulator_config config); | ||
133 | }; | ||
134 | |||
89 | struct palmas_gpadc_platform_data { | 135 | struct palmas_gpadc_platform_data { |
90 | /* Channel 3 current source is only enabled during conversion */ | 136 | /* Channel 3 current source is only enabled during conversion */ |
91 | int ch3_current; | 137 | int ch3_current; |
@@ -184,6 +230,27 @@ enum palmas_regulators { | |||
184 | PALMAS_NUM_REGS, | 230 | PALMAS_NUM_REGS, |
185 | }; | 231 | }; |
186 | 232 | ||
233 | enum tps65917_regulators { | ||
234 | /* SMPS regulators */ | ||
235 | TPS65917_REG_SMPS1, | ||
236 | TPS65917_REG_SMPS2, | ||
237 | TPS65917_REG_SMPS3, | ||
238 | TPS65917_REG_SMPS4, | ||
239 | TPS65917_REG_SMPS5, | ||
240 | /* LDO regulators */ | ||
241 | TPS65917_REG_LDO1, | ||
242 | TPS65917_REG_LDO2, | ||
243 | TPS65917_REG_LDO3, | ||
244 | TPS65917_REG_LDO4, | ||
245 | TPS65917_REG_LDO5, | ||
246 | TPS65917_REG_REGEN1, | ||
247 | TPS65917_REG_REGEN2, | ||
248 | TPS65917_REG_REGEN3, | ||
249 | |||
250 | /* Total number of regulators */ | ||
251 | TPS65917_NUM_REGS, | ||
252 | }; | ||
253 | |||
187 | /* External controll signal name */ | 254 | /* External controll signal name */ |
188 | enum { | 255 | enum { |
189 | PALMAS_EXT_CONTROL_ENABLE1 = 0x1, | 256 | PALMAS_EXT_CONTROL_ENABLE1 = 0x1, |
@@ -228,6 +295,24 @@ enum palmas_external_requestor_id { | |||
228 | PALMAS_EXTERNAL_REQSTR_ID_MAX, | 295 | PALMAS_EXTERNAL_REQSTR_ID_MAX, |
229 | }; | 296 | }; |
230 | 297 | ||
298 | enum tps65917_external_requestor_id { | ||
299 | TPS65917_EXTERNAL_REQSTR_ID_REGEN1, | ||
300 | TPS65917_EXTERNAL_REQSTR_ID_REGEN2, | ||
301 | TPS65917_EXTERNAL_REQSTR_ID_REGEN3, | ||
302 | TPS65917_EXTERNAL_REQSTR_ID_SMPS1, | ||
303 | TPS65917_EXTERNAL_REQSTR_ID_SMPS2, | ||
304 | TPS65917_EXTERNAL_REQSTR_ID_SMPS3, | ||
305 | TPS65917_EXTERNAL_REQSTR_ID_SMPS4, | ||
306 | TPS65917_EXTERNAL_REQSTR_ID_SMPS5, | ||
307 | TPS65917_EXTERNAL_REQSTR_ID_LDO1, | ||
308 | TPS65917_EXTERNAL_REQSTR_ID_LDO2, | ||
309 | TPS65917_EXTERNAL_REQSTR_ID_LDO3, | ||
310 | TPS65917_EXTERNAL_REQSTR_ID_LDO4, | ||
311 | TPS65917_EXTERNAL_REQSTR_ID_LDO5, | ||
312 | /* Last entry */ | ||
313 | TPS65917_EXTERNAL_REQSTR_ID_MAX, | ||
314 | }; | ||
315 | |||
231 | struct palmas_pmic_platform_data { | 316 | struct palmas_pmic_platform_data { |
232 | /* An array of pointers to regulator init data indexed by regulator | 317 | /* An array of pointers to regulator init data indexed by regulator |
233 | * ID | 318 | * ID |
@@ -349,6 +434,48 @@ struct palmas_gpadc_result { | |||
349 | 434 | ||
350 | #define PALMAS_MAX_CHANNELS 16 | 435 | #define PALMAS_MAX_CHANNELS 16 |
351 | 436 | ||
437 | /* Define the tps65917 IRQ numbers */ | ||
438 | enum tps65917_irqs { | ||
439 | /* INT1 registers */ | ||
440 | TPS65917_RESERVED1, | ||
441 | TPS65917_PWRON_IRQ, | ||
442 | TPS65917_LONG_PRESS_KEY_IRQ, | ||
443 | TPS65917_RESERVED2, | ||
444 | TPS65917_PWRDOWN_IRQ, | ||
445 | TPS65917_HOTDIE_IRQ, | ||
446 | TPS65917_VSYS_MON_IRQ, | ||
447 | TPS65917_RESERVED3, | ||
448 | /* INT2 registers */ | ||
449 | TPS65917_RESERVED4, | ||
450 | TPS65917_OTP_ERROR_IRQ, | ||
451 | TPS65917_WDT_IRQ, | ||
452 | TPS65917_RESERVED5, | ||
453 | TPS65917_RESET_IN_IRQ, | ||
454 | TPS65917_FSD_IRQ, | ||
455 | TPS65917_SHORT_IRQ, | ||
456 | TPS65917_RESERVED6, | ||
457 | /* INT3 registers */ | ||
458 | TPS65917_GPADC_AUTO_0_IRQ, | ||
459 | TPS65917_GPADC_AUTO_1_IRQ, | ||
460 | TPS65917_GPADC_EOC_SW_IRQ, | ||
461 | TPS65917_RESREVED6, | ||
462 | TPS65917_RESERVED7, | ||
463 | TPS65917_RESERVED8, | ||
464 | TPS65917_RESERVED9, | ||
465 | TPS65917_VBUS_IRQ, | ||
466 | /* INT4 registers */ | ||
467 | TPS65917_GPIO_0_IRQ, | ||
468 | TPS65917_GPIO_1_IRQ, | ||
469 | TPS65917_GPIO_2_IRQ, | ||
470 | TPS65917_GPIO_3_IRQ, | ||
471 | TPS65917_GPIO_4_IRQ, | ||
472 | TPS65917_GPIO_5_IRQ, | ||
473 | TPS65917_GPIO_6_IRQ, | ||
474 | TPS65917_RESERVED10, | ||
475 | /* Total Number IRQs */ | ||
476 | TPS65917_NUM_IRQ, | ||
477 | }; | ||
478 | |||
352 | /* Define the palmas IRQ numbers */ | 479 | /* Define the palmas IRQ numbers */ |
353 | enum palmas_irqs { | 480 | enum palmas_irqs { |
354 | /* INT1 registers */ | 481 | /* INT1 registers */ |
@@ -400,6 +527,7 @@ struct palmas_pmic { | |||
400 | 527 | ||
401 | int smps123; | 528 | int smps123; |
402 | int smps457; | 529 | int smps457; |
530 | int smps12; | ||
403 | 531 | ||
404 | int range[PALMAS_REG_SMPS10_OUT1]; | 532 | int range[PALMAS_REG_SMPS10_OUT1]; |
405 | unsigned int ramp_delay[PALMAS_REG_SMPS10_OUT1]; | 533 | unsigned int ramp_delay[PALMAS_REG_SMPS10_OUT1]; |
@@ -2871,6 +2999,715 @@ enum usb_irq_events { | |||
2871 | #define PALMAS_GPADC_TRIM15 0x0E | 2999 | #define PALMAS_GPADC_TRIM15 0x0E |
2872 | #define PALMAS_GPADC_TRIM16 0x0F | 3000 | #define PALMAS_GPADC_TRIM16 0x0F |
2873 | 3001 | ||
3002 | /* TPS65917 Interrupt registers */ | ||
3003 | |||
3004 | /* Registers for function INTERRUPT */ | ||
3005 | #define TPS65917_INT1_STATUS 0x00 | ||
3006 | #define TPS65917_INT1_MASK 0x01 | ||
3007 | #define TPS65917_INT1_LINE_STATE 0x02 | ||
3008 | #define TPS65917_INT2_STATUS 0x05 | ||
3009 | #define TPS65917_INT2_MASK 0x06 | ||
3010 | #define TPS65917_INT2_LINE_STATE 0x07 | ||
3011 | #define TPS65917_INT3_STATUS 0x0A | ||
3012 | #define TPS65917_INT3_MASK 0x0B | ||
3013 | #define TPS65917_INT3_LINE_STATE 0x0C | ||
3014 | #define TPS65917_INT4_STATUS 0x0F | ||
3015 | #define TPS65917_INT4_MASK 0x10 | ||
3016 | #define TPS65917_INT4_LINE_STATE 0x11 | ||
3017 | #define TPS65917_INT4_EDGE_DETECT1 0x12 | ||
3018 | #define TPS65917_INT4_EDGE_DETECT2 0x13 | ||
3019 | #define TPS65917_INT_CTRL 0x14 | ||
3020 | |||
3021 | /* Bit definitions for INT1_STATUS */ | ||
3022 | #define TPS65917_INT1_STATUS_VSYS_MON 0x40 | ||
3023 | #define TPS65917_INT1_STATUS_VSYS_MON_SHIFT 0x06 | ||
3024 | #define TPS65917_INT1_STATUS_HOTDIE 0x20 | ||
3025 | #define TPS65917_INT1_STATUS_HOTDIE_SHIFT 0x05 | ||
3026 | #define TPS65917_INT1_STATUS_PWRDOWN 0x10 | ||
3027 | #define TPS65917_INT1_STATUS_PWRDOWN_SHIFT 0x04 | ||
3028 | #define TPS65917_INT1_STATUS_LONG_PRESS_KEY 0x04 | ||
3029 | #define TPS65917_INT1_STATUS_LONG_PRESS_KEY_SHIFT 0x02 | ||
3030 | #define TPS65917_INT1_STATUS_PWRON 0x02 | ||
3031 | #define TPS65917_INT1_STATUS_PWRON_SHIFT 0x01 | ||
3032 | |||
3033 | /* Bit definitions for INT1_MASK */ | ||
3034 | #define TPS65917_INT1_MASK_VSYS_MON 0x40 | ||
3035 | #define TPS65917_INT1_MASK_VSYS_MON_SHIFT 0x06 | ||
3036 | #define TPS65917_INT1_MASK_HOTDIE 0x20 | ||
3037 | #define TPS65917_INT1_MASK_HOTDIE_SHIFT 0x05 | ||
3038 | #define TPS65917_INT1_MASK_PWRDOWN 0x10 | ||
3039 | #define TPS65917_INT1_MASK_PWRDOWN_SHIFT 0x04 | ||
3040 | #define TPS65917_INT1_MASK_LONG_PRESS_KEY 0x04 | ||
3041 | #define TPS65917_INT1_MASK_LONG_PRESS_KEY_SHIFT 0x02 | ||
3042 | #define TPS65917_INT1_MASK_PWRON 0x02 | ||
3043 | #define TPS65917_INT1_MASK_PWRON_SHIFT 0x01 | ||
3044 | |||
3045 | /* Bit definitions for INT1_LINE_STATE */ | ||
3046 | #define TPS65917_INT1_LINE_STATE_VSYS_MON 0x40 | ||
3047 | #define TPS65917_INT1_LINE_STATE_VSYS_MON_SHIFT 0x06 | ||
3048 | #define TPS65917_INT1_LINE_STATE_HOTDIE 0x20 | ||
3049 | #define TPS65917_INT1_LINE_STATE_HOTDIE_SHIFT 0x05 | ||
3050 | #define TPS65917_INT1_LINE_STATE_PWRDOWN 0x10 | ||
3051 | #define TPS65917_INT1_LINE_STATE_PWRDOWN_SHIFT 0x04 | ||
3052 | #define TPS65917_INT1_LINE_STATE_LONG_PRESS_KEY 0x04 | ||
3053 | #define TPS65917_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 0x02 | ||
3054 | #define TPS65917_INT1_LINE_STATE_PWRON 0x02 | ||
3055 | #define TPS65917_INT1_LINE_STATE_PWRON_SHIFT 0x01 | ||
3056 | |||
3057 | /* Bit definitions for INT2_STATUS */ | ||
3058 | #define TPS65917_INT2_STATUS_SHORT 0x40 | ||
3059 | #define TPS65917_INT2_STATUS_SHORT_SHIFT 0x06 | ||
3060 | #define TPS65917_INT2_STATUS_FSD 0x20 | ||
3061 | #define TPS65917_INT2_STATUS_FSD_SHIFT 0x05 | ||
3062 | #define TPS65917_INT2_STATUS_RESET_IN 0x10 | ||
3063 | #define TPS65917_INT2_STATUS_RESET_IN_SHIFT 0x04 | ||
3064 | #define TPS65917_INT2_STATUS_WDT 0x04 | ||
3065 | #define TPS65917_INT2_STATUS_WDT_SHIFT 0x02 | ||
3066 | #define TPS65917_INT2_STATUS_OTP_ERROR 0x02 | ||
3067 | #define TPS65917_INT2_STATUS_OTP_ERROR_SHIFT 0x01 | ||
3068 | |||
3069 | /* Bit definitions for INT2_MASK */ | ||
3070 | #define TPS65917_INT2_MASK_SHORT 0x40 | ||
3071 | #define TPS65917_INT2_MASK_SHORT_SHIFT 0x06 | ||
3072 | #define TPS65917_INT2_MASK_FSD 0x20 | ||
3073 | #define TPS65917_INT2_MASK_FSD_SHIFT 0x05 | ||
3074 | #define TPS65917_INT2_MASK_RESET_IN 0x10 | ||
3075 | #define TPS65917_INT2_MASK_RESET_IN_SHIFT 0x04 | ||
3076 | #define TPS65917_INT2_MASK_WDT 0x04 | ||
3077 | #define TPS65917_INT2_MASK_WDT_SHIFT 0x02 | ||
3078 | #define TPS65917_INT2_MASK_OTP_ERROR_TIMER 0x02 | ||
3079 | #define TPS65917_INT2_MASK_OTP_ERROR_SHIFT 0x01 | ||
3080 | |||
3081 | /* Bit definitions for INT2_LINE_STATE */ | ||
3082 | #define TPS65917_INT2_LINE_STATE_SHORT 0x40 | ||
3083 | #define TPS65917_INT2_LINE_STATE_SHORT_SHIFT 0x06 | ||
3084 | #define TPS65917_INT2_LINE_STATE_FSD 0x20 | ||
3085 | #define TPS65917_INT2_LINE_STATE_FSD_SHIFT 0x05 | ||
3086 | #define TPS65917_INT2_LINE_STATE_RESET_IN 0x10 | ||
3087 | #define TPS65917_INT2_LINE_STATE_RESET_IN_SHIFT 0x04 | ||
3088 | #define TPS65917_INT2_LINE_STATE_WDT 0x04 | ||
3089 | #define TPS65917_INT2_LINE_STATE_WDT_SHIFT 0x02 | ||
3090 | #define TPS65917_INT2_LINE_STATE_OTP_ERROR 0x02 | ||
3091 | #define TPS65917_INT2_LINE_STATE_OTP_ERROR_SHIFT 0x01 | ||
3092 | |||
3093 | /* Bit definitions for INT3_STATUS */ | ||
3094 | #define TPS65917_INT3_STATUS_VBUS 0x80 | ||
3095 | #define TPS65917_INT3_STATUS_VBUS_SHIFT 0x07 | ||
3096 | #define TPS65917_INT3_STATUS_GPADC_EOC_SW 0x04 | ||
3097 | #define TPS65917_INT3_STATUS_GPADC_EOC_SW_SHIFT 0x02 | ||
3098 | #define TPS65917_INT3_STATUS_GPADC_AUTO_1 0x02 | ||
3099 | #define TPS65917_INT3_STATUS_GPADC_AUTO_1_SHIFT 0x01 | ||
3100 | #define TPS65917_INT3_STATUS_GPADC_AUTO_0 0x01 | ||
3101 | #define TPS65917_INT3_STATUS_GPADC_AUTO_0_SHIFT 0x00 | ||
3102 | |||
3103 | /* Bit definitions for INT3_MASK */ | ||
3104 | #define TPS65917_INT3_MASK_VBUS 0x80 | ||
3105 | #define TPS65917_INT3_MASK_VBUS_SHIFT 0x07 | ||
3106 | #define TPS65917_INT3_MASK_GPADC_EOC_SW 0x04 | ||
3107 | #define TPS65917_INT3_MASK_GPADC_EOC_SW_SHIFT 0x02 | ||
3108 | #define TPS65917_INT3_MASK_GPADC_AUTO_1 0x02 | ||
3109 | #define TPS65917_INT3_MASK_GPADC_AUTO_1_SHIFT 0x01 | ||
3110 | #define TPS65917_INT3_MASK_GPADC_AUTO_0 0x01 | ||
3111 | #define TPS65917_INT3_MASK_GPADC_AUTO_0_SHIFT 0x00 | ||
3112 | |||
3113 | /* Bit definitions for INT3_LINE_STATE */ | ||
3114 | #define TPS65917_INT3_LINE_STATE_VBUS 0x80 | ||
3115 | #define TPS65917_INT3_LINE_STATE_VBUS_SHIFT 0x07 | ||
3116 | #define TPS65917_INT3_LINE_STATE_GPADC_EOC_SW 0x04 | ||
3117 | #define TPS65917_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 0x02 | ||
3118 | #define TPS65917_INT3_LINE_STATE_GPADC_AUTO_1 0x02 | ||
3119 | #define TPS65917_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 0x01 | ||
3120 | #define TPS65917_INT3_LINE_STATE_GPADC_AUTO_0 0x01 | ||
3121 | #define TPS65917_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0x00 | ||
3122 | |||
3123 | /* Bit definitions for INT4_STATUS */ | ||
3124 | #define TPS65917_INT4_STATUS_GPIO_6 0x40 | ||
3125 | #define TPS65917_INT4_STATUS_GPIO_6_SHIFT 0x06 | ||
3126 | #define TPS65917_INT4_STATUS_GPIO_5 0x20 | ||
3127 | #define TPS65917_INT4_STATUS_GPIO_5_SHIFT 0x05 | ||
3128 | #define TPS65917_INT4_STATUS_GPIO_4 0x10 | ||
3129 | #define TPS65917_INT4_STATUS_GPIO_4_SHIFT 0x04 | ||
3130 | #define TPS65917_INT4_STATUS_GPIO_3 0x08 | ||
3131 | #define TPS65917_INT4_STATUS_GPIO_3_SHIFT 0x03 | ||
3132 | #define TPS65917_INT4_STATUS_GPIO_2 0x04 | ||
3133 | #define TPS65917_INT4_STATUS_GPIO_2_SHIFT 0x02 | ||
3134 | #define TPS65917_INT4_STATUS_GPIO_1 0x02 | ||
3135 | #define TPS65917_INT4_STATUS_GPIO_1_SHIFT 0x01 | ||
3136 | #define TPS65917_INT4_STATUS_GPIO_0 0x01 | ||
3137 | #define TPS65917_INT4_STATUS_GPIO_0_SHIFT 0x00 | ||
3138 | |||
3139 | /* Bit definitions for INT4_MASK */ | ||
3140 | #define TPS65917_INT4_MASK_GPIO_6 0x40 | ||
3141 | #define TPS65917_INT4_MASK_GPIO_6_SHIFT 0x06 | ||
3142 | #define TPS65917_INT4_MASK_GPIO_5 0x20 | ||
3143 | #define TPS65917_INT4_MASK_GPIO_5_SHIFT 0x05 | ||
3144 | #define TPS65917_INT4_MASK_GPIO_4 0x10 | ||
3145 | #define TPS65917_INT4_MASK_GPIO_4_SHIFT 0x04 | ||
3146 | #define TPS65917_INT4_MASK_GPIO_3 0x08 | ||
3147 | #define TPS65917_INT4_MASK_GPIO_3_SHIFT 0x03 | ||
3148 | #define TPS65917_INT4_MASK_GPIO_2 0x04 | ||
3149 | #define TPS65917_INT4_MASK_GPIO_2_SHIFT 0x02 | ||
3150 | #define TPS65917_INT4_MASK_GPIO_1 0x02 | ||
3151 | #define TPS65917_INT4_MASK_GPIO_1_SHIFT 0x01 | ||
3152 | #define TPS65917_INT4_MASK_GPIO_0 0x01 | ||
3153 | #define TPS65917_INT4_MASK_GPIO_0_SHIFT 0x00 | ||
3154 | |||
3155 | /* Bit definitions for INT4_LINE_STATE */ | ||
3156 | #define TPS65917_INT4_LINE_STATE_GPIO_6 0x40 | ||
3157 | #define TPS65917_INT4_LINE_STATE_GPIO_6_SHIFT 0x06 | ||
3158 | #define TPS65917_INT4_LINE_STATE_GPIO_5 0x20 | ||
3159 | #define TPS65917_INT4_LINE_STATE_GPIO_5_SHIFT 0x05 | ||
3160 | #define TPS65917_INT4_LINE_STATE_GPIO_4 0x10 | ||
3161 | #define TPS65917_INT4_LINE_STATE_GPIO_4_SHIFT 0x04 | ||
3162 | #define TPS65917_INT4_LINE_STATE_GPIO_3 0x08 | ||
3163 | #define TPS65917_INT4_LINE_STATE_GPIO_3_SHIFT 0x03 | ||
3164 | #define TPS65917_INT4_LINE_STATE_GPIO_2 0x04 | ||
3165 | #define TPS65917_INT4_LINE_STATE_GPIO_2_SHIFT 0x02 | ||
3166 | #define TPS65917_INT4_LINE_STATE_GPIO_1 0x02 | ||
3167 | #define TPS65917_INT4_LINE_STATE_GPIO_1_SHIFT 0x01 | ||
3168 | #define TPS65917_INT4_LINE_STATE_GPIO_0 0x01 | ||
3169 | #define TPS65917_INT4_LINE_STATE_GPIO_0_SHIFT 0x00 | ||
3170 | |||
3171 | /* Bit definitions for INT4_EDGE_DETECT1 */ | ||
3172 | #define TPS65917_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80 | ||
3173 | #define TPS65917_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 0x07 | ||
3174 | #define TPS65917_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40 | ||
3175 | #define TPS65917_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 0x06 | ||
3176 | #define TPS65917_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20 | ||
3177 | #define TPS65917_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 0x05 | ||
3178 | #define TPS65917_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10 | ||
3179 | #define TPS65917_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 0x04 | ||
3180 | #define TPS65917_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08 | ||
3181 | #define TPS65917_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 0x03 | ||
3182 | #define TPS65917_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04 | ||
3183 | #define TPS65917_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 0x02 | ||
3184 | #define TPS65917_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02 | ||
3185 | #define TPS65917_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 0x01 | ||
3186 | #define TPS65917_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01 | ||
3187 | #define TPS65917_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0x00 | ||
3188 | |||
3189 | /* Bit definitions for INT4_EDGE_DETECT2 */ | ||
3190 | #define TPS65917_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20 | ||
3191 | #define TPS65917_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 0x05 | ||
3192 | #define TPS65917_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10 | ||
3193 | #define TPS65917_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 0x04 | ||
3194 | #define TPS65917_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08 | ||
3195 | #define TPS65917_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 0x03 | ||
3196 | #define TPS65917_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04 | ||
3197 | #define TPS65917_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 0x02 | ||
3198 | #define TPS65917_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02 | ||
3199 | #define TPS65917_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 0x01 | ||
3200 | #define TPS65917_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01 | ||
3201 | #define TPS65917_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0x00 | ||
3202 | |||
3203 | /* Bit definitions for INT_CTRL */ | ||
3204 | #define TPS65917_INT_CTRL_INT_PENDING 0x04 | ||
3205 | #define TPS65917_INT_CTRL_INT_PENDING_SHIFT 0x02 | ||
3206 | #define TPS65917_INT_CTRL_INT_CLEAR 0x01 | ||
3207 | #define TPS65917_INT_CTRL_INT_CLEAR_SHIFT 0x00 | ||
3208 | |||
3209 | /* TPS65917 SMPS Registers */ | ||
3210 | |||
3211 | /* Registers for function SMPS */ | ||
3212 | #define TPS65917_SMPS1_CTRL 0x00 | ||
3213 | #define TPS65917_SMPS1_FORCE 0x02 | ||
3214 | #define TPS65917_SMPS1_VOLTAGE 0x03 | ||
3215 | #define TPS65917_SMPS2_CTRL 0x04 | ||
3216 | #define TPS65917_SMPS2_FORCE 0x06 | ||
3217 | #define TPS65917_SMPS2_VOLTAGE 0x07 | ||
3218 | #define TPS65917_SMPS3_CTRL 0x0C | ||
3219 | #define TPS65917_SMPS3_FORCE 0x0E | ||
3220 | #define TPS65917_SMPS3_VOLTAGE 0x0F | ||
3221 | #define TPS65917_SMPS4_CTRL 0x10 | ||
3222 | #define TPS65917_SMPS4_VOLTAGE 0x13 | ||
3223 | #define TPS65917_SMPS5_CTRL 0x18 | ||
3224 | #define TPS65917_SMPS5_VOLTAGE 0x1B | ||
3225 | #define TPS65917_SMPS_CTRL 0x24 | ||
3226 | #define TPS65917_SMPS_PD_CTRL 0x25 | ||
3227 | #define TPS65917_SMPS_THERMAL_EN 0x27 | ||
3228 | #define TPS65917_SMPS_THERMAL_STATUS 0x28 | ||
3229 | #define TPS65917_SMPS_SHORT_STATUS 0x29 | ||
3230 | #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN 0x2A | ||
3231 | #define TPS65917_SMPS_POWERGOOD_MASK1 0x2B | ||
3232 | #define TPS65917_SMPS_POWERGOOD_MASK2 0x2C | ||
3233 | |||
3234 | /* Bit definitions for SMPS1_CTRL */ | ||
3235 | #define TPS65917_SMPS1_CTRL_WR_S 0x80 | ||
3236 | #define TPS65917_SMPS1_CTRL_WR_S_SHIFT 0x07 | ||
3237 | #define TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN 0x40 | ||
3238 | #define TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 | ||
3239 | #define TPS65917_SMPS1_CTRL_STATUS_MASK 0x30 | ||
3240 | #define TPS65917_SMPS1_CTRL_STATUS_SHIFT 0x04 | ||
3241 | #define TPS65917_SMPS1_CTRL_MODE_SLEEP_MASK 0x0C | ||
3242 | #define TPS65917_SMPS1_CTRL_MODE_SLEEP_SHIFT 0x02 | ||
3243 | #define TPS65917_SMPS1_CTRL_MODE_ACTIVE_MASK 0x03 | ||
3244 | #define TPS65917_SMPS1_CTRL_MODE_ACTIVE_SHIFT 0x00 | ||
3245 | |||
3246 | /* Bit definitions for SMPS1_FORCE */ | ||
3247 | #define TPS65917_SMPS1_FORCE_CMD 0x80 | ||
3248 | #define TPS65917_SMPS1_FORCE_CMD_SHIFT 0x07 | ||
3249 | #define TPS65917_SMPS1_FORCE_VSEL_MASK 0x7F | ||
3250 | #define TPS65917_SMPS1_FORCE_VSEL_SHIFT 0x00 | ||
3251 | |||
3252 | /* Bit definitions for SMPS1_VOLTAGE */ | ||
3253 | #define TPS65917_SMPS1_VOLTAGE_RANGE 0x80 | ||
3254 | #define TPS65917_SMPS1_VOLTAGE_RANGE_SHIFT 0x07 | ||
3255 | #define TPS65917_SMPS1_VOLTAGE_VSEL_MASK 0x7F | ||
3256 | #define TPS65917_SMPS1_VOLTAGE_VSEL_SHIFT 0x00 | ||
3257 | |||
3258 | /* Bit definitions for SMPS2_CTRL */ | ||
3259 | #define TPS65917_SMPS2_CTRL_WR_S 0x80 | ||
3260 | #define TPS65917_SMPS2_CTRL_WR_S_SHIFT 0x07 | ||
3261 | #define TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN 0x40 | ||
3262 | #define TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 | ||
3263 | #define TPS65917_SMPS2_CTRL_STATUS_MASK 0x30 | ||
3264 | #define TPS65917_SMPS2_CTRL_STATUS_SHIFT 0x04 | ||
3265 | #define TPS65917_SMPS2_CTRL_MODE_SLEEP_MASK 0x0C | ||
3266 | #define TPS65917_SMPS2_CTRL_MODE_SLEEP_SHIFT 0x02 | ||
3267 | #define TPS65917_SMPS2_CTRL_MODE_ACTIVE_MASK 0x03 | ||
3268 | #define TPS65917_SMPS2_CTRL_MODE_ACTIVE_SHIFT 0x00 | ||
3269 | |||
3270 | /* Bit definitions for SMPS2_FORCE */ | ||
3271 | #define TPS65917_SMPS2_FORCE_CMD 0x80 | ||
3272 | #define TPS65917_SMPS2_FORCE_CMD_SHIFT 0x07 | ||
3273 | #define TPS65917_SMPS2_FORCE_VSEL_MASK 0x7F | ||
3274 | #define TPS65917_SMPS2_FORCE_VSEL_SHIFT 0x00 | ||
3275 | |||
3276 | /* Bit definitions for SMPS2_VOLTAGE */ | ||
3277 | #define TPS65917_SMPS2_VOLTAGE_RANGE 0x80 | ||
3278 | #define TPS65917_SMPS2_VOLTAGE_RANGE_SHIFT 0x07 | ||
3279 | #define TPS65917_SMPS2_VOLTAGE_VSEL_MASK 0x7F | ||
3280 | #define TPS65917_SMPS2_VOLTAGE_VSEL_SHIFT 0x00 | ||
3281 | |||
3282 | /* Bit definitions for SMPS3_CTRL */ | ||
3283 | #define TPS65917_SMPS3_CTRL_WR_S 0x80 | ||
3284 | #define TPS65917_SMPS3_CTRL_WR_S_SHIFT 0x07 | ||
3285 | #define TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN 0x40 | ||
3286 | #define TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 | ||
3287 | #define TPS65917_SMPS3_CTRL_STATUS_MASK 0x30 | ||
3288 | #define TPS65917_SMPS3_CTRL_STATUS_SHIFT 0x04 | ||
3289 | #define TPS65917_SMPS3_CTRL_MODE_SLEEP_MASK 0x0C | ||
3290 | #define TPS65917_SMPS3_CTRL_MODE_SLEEP_SHIFT 0x02 | ||
3291 | #define TPS65917_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03 | ||
3292 | #define TPS65917_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0x00 | ||
3293 | |||
3294 | /* Bit definitions for SMPS3_FORCE */ | ||
3295 | #define TPS65917_SMPS3_FORCE_CMD 0x80 | ||
3296 | #define TPS65917_SMPS3_FORCE_CMD_SHIFT 0x07 | ||
3297 | #define TPS65917_SMPS3_FORCE_VSEL_MASK 0x7F | ||
3298 | #define TPS65917_SMPS3_FORCE_VSEL_SHIFT 0x00 | ||
3299 | |||
3300 | /* Bit definitions for SMPS3_VOLTAGE */ | ||
3301 | #define TPS65917_SMPS3_VOLTAGE_RANGE 0x80 | ||
3302 | #define TPS65917_SMPS3_VOLTAGE_RANGE_SHIFT 0x07 | ||
3303 | #define TPS65917_SMPS3_VOLTAGE_VSEL_MASK 0x7F | ||
3304 | #define TPS65917_SMPS3_VOLTAGE_VSEL_SHIFT 0x00 | ||
3305 | |||
3306 | /* Bit definitions for SMPS4_CTRL */ | ||
3307 | #define TPS65917_SMPS4_CTRL_WR_S 0x80 | ||
3308 | #define TPS65917_SMPS4_CTRL_WR_S_SHIFT 0x07 | ||
3309 | #define TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN 0x40 | ||
3310 | #define TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 | ||
3311 | #define TPS65917_SMPS4_CTRL_STATUS_MASK 0x30 | ||
3312 | #define TPS65917_SMPS4_CTRL_STATUS_SHIFT 0x04 | ||
3313 | #define TPS65917_SMPS4_CTRL_MODE_SLEEP_MASK 0x0C | ||
3314 | #define TPS65917_SMPS4_CTRL_MODE_SLEEP_SHIFT 0x02 | ||
3315 | #define TPS65917_SMPS4_CTRL_MODE_ACTIVE_MASK 0x03 | ||
3316 | #define TPS65917_SMPS4_CTRL_MODE_ACTIVE_SHIFT 0x00 | ||
3317 | |||
3318 | /* Bit definitions for SMPS4_VOLTAGE */ | ||
3319 | #define TPS65917_SMPS4_VOLTAGE_RANGE 0x80 | ||
3320 | #define TPS65917_SMPS4_VOLTAGE_RANGE_SHIFT 0x07 | ||
3321 | #define TPS65917_SMPS4_VOLTAGE_VSEL_MASK 0x7F | ||
3322 | #define TPS65917_SMPS4_VOLTAGE_VSEL_SHIFT 0x00 | ||
3323 | |||
3324 | /* Bit definitions for SMPS5_CTRL */ | ||
3325 | #define TPS65917_SMPS5_CTRL_WR_S 0x80 | ||
3326 | #define TPS65917_SMPS5_CTRL_WR_S_SHIFT 0x07 | ||
3327 | #define TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN 0x40 | ||
3328 | #define TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN_SHIFT 0x06 | ||
3329 | #define TPS65917_SMPS5_CTRL_STATUS_MASK 0x30 | ||
3330 | #define TPS65917_SMPS5_CTRL_STATUS_SHIFT 0x04 | ||
3331 | #define TPS65917_SMPS5_CTRL_MODE_SLEEP_MASK 0x0C | ||
3332 | #define TPS65917_SMPS5_CTRL_MODE_SLEEP_SHIFT 0x02 | ||
3333 | #define TPS65917_SMPS5_CTRL_MODE_ACTIVE_MASK 0x03 | ||
3334 | #define TPS65917_SMPS5_CTRL_MODE_ACTIVE_SHIFT 0x00 | ||
3335 | |||
3336 | /* Bit definitions for SMPS5_VOLTAGE */ | ||
3337 | #define TPS65917_SMPS5_VOLTAGE_RANGE 0x80 | ||
3338 | #define TPS65917_SMPS5_VOLTAGE_RANGE_SHIFT 0x07 | ||
3339 | #define TPS65917_SMPS5_VOLTAGE_VSEL_MASK 0x7F | ||
3340 | #define TPS65917_SMPS5_VOLTAGE_VSEL_SHIFT 0x00 | ||
3341 | |||
3342 | /* Bit definitions for SMPS_CTRL */ | ||
3343 | #define TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN 0x10 | ||
3344 | #define TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN_SHIFT 0x04 | ||
3345 | #define TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL 0x03 | ||
3346 | #define TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL_SHIFT 0x00 | ||
3347 | |||
3348 | /* Bit definitions for SMPS_PD_CTRL */ | ||
3349 | #define TPS65917_SMPS_PD_CTRL_SMPS5 0x40 | ||
3350 | #define TPS65917_SMPS_PD_CTRL_SMPS5_SHIFT 0x06 | ||
3351 | #define TPS65917_SMPS_PD_CTRL_SMPS4 0x10 | ||
3352 | #define TPS65917_SMPS_PD_CTRL_SMPS4_SHIFT 0x04 | ||
3353 | #define TPS65917_SMPS_PD_CTRL_SMPS3 0x08 | ||
3354 | #define TPS65917_SMPS_PD_CTRL_SMPS3_SHIFT 0x03 | ||
3355 | #define TPS65917_SMPS_PD_CTRL_SMPS2 0x02 | ||
3356 | #define TPS65917_SMPS_PD_CTRL_SMPS2_SHIFT 0x01 | ||
3357 | #define TPS65917_SMPS_PD_CTRL_SMPS1 0x01 | ||
3358 | #define TPS65917_SMPS_PD_CTRL_SMPS1_SHIFT 0x00 | ||
3359 | |||
3360 | /* Bit definitions for SMPS_THERMAL_EN */ | ||
3361 | #define TPS65917_SMPS_THERMAL_EN_SMPS5 0x40 | ||
3362 | #define TPS65917_SMPS_THERMAL_EN_SMPS5_SHIFT 0x06 | ||
3363 | #define TPS65917_SMPS_THERMAL_EN_SMPS3 0x08 | ||
3364 | #define TPS65917_SMPS_THERMAL_EN_SMPS3_SHIFT 0x03 | ||
3365 | #define TPS65917_SMPS_THERMAL_EN_SMPS12 0x01 | ||
3366 | #define TPS65917_SMPS_THERMAL_EN_SMPS12_SHIFT 0x00 | ||
3367 | |||
3368 | /* Bit definitions for SMPS_THERMAL_STATUS */ | ||
3369 | #define TPS65917_SMPS_THERMAL_STATUS_SMPS5 0x40 | ||
3370 | #define TPS65917_SMPS_THERMAL_STATUS_SMPS5_SHIFT 0x06 | ||
3371 | #define TPS65917_SMPS_THERMAL_STATUS_SMPS3 0x08 | ||
3372 | #define TPS65917_SMPS_THERMAL_STATUS_SMPS3_SHIFT 0x03 | ||
3373 | #define TPS65917_SMPS_THERMAL_STATUS_SMPS12 0x01 | ||
3374 | #define TPS65917_SMPS_THERMAL_STATUS_SMPS12_SHIFT 0x00 | ||
3375 | |||
3376 | /* Bit definitions for SMPS_SHORT_STATUS */ | ||
3377 | #define TPS65917_SMPS_SHORT_STATUS_SMPS5 0x40 | ||
3378 | #define TPS65917_SMPS_SHORT_STATUS_SMPS5_SHIFT 0x06 | ||
3379 | #define TPS65917_SMPS_SHORT_STATUS_SMPS4 0x10 | ||
3380 | #define TPS65917_SMPS_SHORT_STATUS_SMPS4_SHIFT 0x04 | ||
3381 | #define TPS65917_SMPS_SHORT_STATUS_SMPS3 0x08 | ||
3382 | #define TPS65917_SMPS_SHORT_STATUS_SMPS3_SHIFT 0x03 | ||
3383 | #define TPS65917_SMPS_SHORT_STATUS_SMPS2 0x02 | ||
3384 | #define TPS65917_SMPS_SHORT_STATUS_SMPS2_SHIFT 0x01 | ||
3385 | #define TPS65917_SMPS_SHORT_STATUS_SMPS1 0x01 | ||
3386 | #define TPS65917_SMPS_SHORT_STATUS_SMPS1_SHIFT 0x00 | ||
3387 | |||
3388 | /* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */ | ||
3389 | #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS5 0x40 | ||
3390 | #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS5_SHIFT 0x06 | ||
3391 | #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS4 0x10 | ||
3392 | #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS4_SHIFT 0x04 | ||
3393 | #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x08 | ||
3394 | #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 0x03 | ||
3395 | #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS2 0x02 | ||
3396 | #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS2_SHIFT 0x01 | ||
3397 | #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS1 0x01 | ||
3398 | #define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS1_SHIFT 0x00 | ||
3399 | |||
3400 | /* Bit definitions for SMPS_POWERGOOD_MASK1 */ | ||
3401 | #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS5 0x40 | ||
3402 | #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS5_SHIFT 0x06 | ||
3403 | #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS4 0x10 | ||
3404 | #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS4_SHIFT 0x04 | ||
3405 | #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS3 0x08 | ||
3406 | #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 0x03 | ||
3407 | #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS2 0x02 | ||
3408 | #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS2_SHIFT 0x01 | ||
3409 | #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS1 0x01 | ||
3410 | #define TPS65917_SMPS_POWERGOOD_MASK1_SMPS1_SHIFT 0x00 | ||
3411 | |||
3412 | /* Bit definitions for SMPS_POWERGOOD_MASK2 */ | ||
3413 | #define TPS65917_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80 | ||
3414 | #define TPS65917_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 0x07 | ||
3415 | #define TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALARM_SHIFT 0x10 | ||
3416 | #define TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALARM 0x04 | ||
3417 | |||
3418 | /* Bit definitions for SMPS_PLL_CTRL */ | ||
3419 | |||
3420 | #define TPS65917_SMPS_PLL_CTRL_PLL_EN_PLL_BYPASS_SHIFT 0x08 | ||
3421 | #define TPS65917_SMPS_PLL_CTRL_PLL_PLL_EN_BYPASS 0x03 | ||
3422 | #define TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS_CLK_SHIFT 0x04 | ||
3423 | #define TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS_CLK 0x02 | ||
3424 | |||
3425 | /* Registers for function LDO */ | ||
3426 | #define TPS65917_LDO1_CTRL 0x00 | ||
3427 | #define TPS65917_LDO1_VOLTAGE 0x01 | ||
3428 | #define TPS65917_LDO2_CTRL 0x02 | ||
3429 | #define TPS65917_LDO2_VOLTAGE 0x03 | ||
3430 | #define TPS65917_LDO3_CTRL 0x04 | ||
3431 | #define TPS65917_LDO3_VOLTAGE 0x05 | ||
3432 | #define TPS65917_LDO4_CTRL 0x0E | ||
3433 | #define TPS65917_LDO4_VOLTAGE 0x0F | ||
3434 | #define TPS65917_LDO5_CTRL 0x12 | ||
3435 | #define TPS65917_LDO5_VOLTAGE 0x13 | ||
3436 | #define TPS65917_LDO_PD_CTRL1 0x1B | ||
3437 | #define TPS65917_LDO_PD_CTRL2 0x1C | ||
3438 | #define TPS65917_LDO_SHORT_STATUS1 0x1D | ||
3439 | #define TPS65917_LDO_SHORT_STATUS2 0x1E | ||
3440 | #define TPS65917_LDO_PD_CTRL3 0x2D | ||
3441 | #define TPS65917_LDO_SHORT_STATUS3 0x2E | ||
3442 | |||
3443 | /* Bit definitions for LDO1_CTRL */ | ||
3444 | #define TPS65917_LDO1_CTRL_WR_S 0x80 | ||
3445 | #define TPS65917_LDO1_CTRL_WR_S_SHIFT 0x07 | ||
3446 | #define TPS65917_LDO1_CTRL_BYPASS_EN 0x40 | ||
3447 | #define TPS65917_LDO1_CTRL_BYPASS_EN_SHIFT 0x06 | ||
3448 | #define TPS65917_LDO1_CTRL_STATUS 0x10 | ||
3449 | #define TPS65917_LDO1_CTRL_STATUS_SHIFT 0x04 | ||
3450 | #define TPS65917_LDO1_CTRL_MODE_SLEEP 0x04 | ||
3451 | #define TPS65917_LDO1_CTRL_MODE_SLEEP_SHIFT 0x02 | ||
3452 | #define TPS65917_LDO1_CTRL_MODE_ACTIVE 0x01 | ||
3453 | #define TPS65917_LDO1_CTRL_MODE_ACTIVE_SHIFT 0x00 | ||
3454 | |||
3455 | /* Bit definitions for LDO1_VOLTAGE */ | ||
3456 | #define TPS65917_LDO1_VOLTAGE_VSEL_MASK 0x2F | ||
3457 | #define TPS65917_LDO1_VOLTAGE_VSEL_SHIFT 0x00 | ||
3458 | |||
3459 | /* Bit definitions for LDO2_CTRL */ | ||
3460 | #define TPS65917_LDO2_CTRL_WR_S 0x80 | ||
3461 | #define TPS65917_LDO2_CTRL_WR_S_SHIFT 0x07 | ||
3462 | #define TPS65917_LDO2_CTRL_BYPASS_EN 0x40 | ||
3463 | #define TPS65917_LDO2_CTRL_BYPASS_EN_SHIFT 0x06 | ||
3464 | #define TPS65917_LDO2_CTRL_STATUS 0x10 | ||
3465 | #define TPS65917_LDO2_CTRL_STATUS_SHIFT 0x04 | ||
3466 | #define TPS65917_LDO2_CTRL_MODE_SLEEP 0x04 | ||
3467 | #define TPS65917_LDO2_CTRL_MODE_SLEEP_SHIFT 0x02 | ||
3468 | #define TPS65917_LDO2_CTRL_MODE_ACTIVE 0x01 | ||
3469 | #define TPS65917_LDO2_CTRL_MODE_ACTIVE_SHIFT 0x00 | ||
3470 | |||
3471 | /* Bit definitions for LDO2_VOLTAGE */ | ||
3472 | #define TPS65917_LDO2_VOLTAGE_VSEL_MASK 0x2F | ||
3473 | #define TPS65917_LDO2_VOLTAGE_VSEL_SHIFT 0x00 | ||
3474 | |||
3475 | /* Bit definitions for LDO3_CTRL */ | ||
3476 | #define TPS65917_LDO3_CTRL_WR_S 0x80 | ||
3477 | #define TPS65917_LDO3_CTRL_WR_S_SHIFT 0x07 | ||
3478 | #define TPS65917_LDO3_CTRL_STATUS 0x10 | ||
3479 | #define TPS65917_LDO3_CTRL_STATUS_SHIFT 0x04 | ||
3480 | #define TPS65917_LDO3_CTRL_MODE_SLEEP 0x04 | ||
3481 | #define TPS65917_LDO3_CTRL_MODE_SLEEP_SHIFT 0x02 | ||
3482 | #define TPS65917_LDO3_CTRL_MODE_ACTIVE 0x01 | ||
3483 | #define TPS65917_LDO3_CTRL_MODE_ACTIVE_SHIFT 0x00 | ||
3484 | |||
3485 | /* Bit definitions for LDO3_VOLTAGE */ | ||
3486 | #define TPS65917_LDO3_VOLTAGE_VSEL_MASK 0x2F | ||
3487 | #define TPS65917_LDO3_VOLTAGE_VSEL_SHIFT 0x00 | ||
3488 | |||
3489 | /* Bit definitions for LDO4_CTRL */ | ||
3490 | #define TPS65917_LDO4_CTRL_WR_S 0x80 | ||
3491 | #define TPS65917_LDO4_CTRL_WR_S_SHIFT 0x07 | ||
3492 | #define TPS65917_LDO4_CTRL_STATUS 0x10 | ||
3493 | #define TPS65917_LDO4_CTRL_STATUS_SHIFT 0x04 | ||
3494 | #define TPS65917_LDO4_CTRL_MODE_SLEEP 0x04 | ||
3495 | #define TPS65917_LDO4_CTRL_MODE_SLEEP_SHIFT 0x02 | ||
3496 | #define TPS65917_LDO4_CTRL_MODE_ACTIVE 0x01 | ||
3497 | #define TPS65917_LDO4_CTRL_MODE_ACTIVE_SHIFT 0x00 | ||
3498 | |||
3499 | /* Bit definitions for LDO4_VOLTAGE */ | ||
3500 | #define TPS65917_LDO4_VOLTAGE_VSEL_MASK 0x2F | ||
3501 | #define TPS65917_LDO4_VOLTAGE_VSEL_SHIFT 0x00 | ||
3502 | |||
3503 | /* Bit definitions for LDO5_CTRL */ | ||
3504 | #define TPS65917_LDO5_CTRL_WR_S 0x80 | ||
3505 | #define TPS65917_LDO5_CTRL_WR_S_SHIFT 0x07 | ||
3506 | #define TPS65917_LDO5_CTRL_STATUS 0x10 | ||
3507 | #define TPS65917_LDO5_CTRL_STATUS_SHIFT 0x04 | ||
3508 | #define TPS65917_LDO5_CTRL_MODE_SLEEP 0x04 | ||
3509 | #define TPS65917_LDO5_CTRL_MODE_SLEEP_SHIFT 0x02 | ||
3510 | #define TPS65917_LDO5_CTRL_MODE_ACTIVE 0x01 | ||
3511 | #define TPS65917_LDO5_CTRL_MODE_ACTIVE_SHIFT 0x00 | ||
3512 | |||
3513 | /* Bit definitions for LDO5_VOLTAGE */ | ||
3514 | #define TPS65917_LDO5_VOLTAGE_VSEL_MASK 0x2F | ||
3515 | #define TPS65917_LDO5_VOLTAGE_VSEL_SHIFT 0x00 | ||
3516 | |||
3517 | /* Bit definitions for LDO_PD_CTRL1 */ | ||
3518 | #define TPS65917_LDO_PD_CTRL1_LDO4 0x80 | ||
3519 | #define TPS65917_LDO_PD_CTRL1_LDO4_SHIFT 0x07 | ||
3520 | #define TPS65917_LDO_PD_CTRL1_LDO2 0x02 | ||
3521 | #define TPS65917_LDO_PD_CTRL1_LDO2_SHIFT 0x01 | ||
3522 | #define TPS65917_LDO_PD_CTRL1_LDO1 0x01 | ||
3523 | #define TPS65917_LDO_PD_CTRL1_LDO1_SHIFT 0x00 | ||
3524 | |||
3525 | /* Bit definitions for LDO_PD_CTRL2 */ | ||
3526 | #define TPS65917_LDO_PD_CTRL2_LDO3 0x04 | ||
3527 | #define TPS65917_LDO_PD_CTRL2_LDO3_SHIFT 0x02 | ||
3528 | #define TPS65917_LDO_PD_CTRL2_LDO5 0x02 | ||
3529 | #define TPS65917_LDO_PD_CTRL2_LDO5_SHIFT 0x01 | ||
3530 | |||
3531 | /* Bit definitions for LDO_PD_CTRL3 */ | ||
3532 | #define TPS65917_LDO_PD_CTRL2_LDOVANA 0x80 | ||
3533 | #define TPS65917_LDO_PD_CTRL2_LDOVANA_SHIFT 0x07 | ||
3534 | |||
3535 | /* Bit definitions for LDO_SHORT_STATUS1 */ | ||
3536 | #define TPS65917_LDO_SHORT_STATUS1_LDO4 0x80 | ||
3537 | #define TPS65917_LDO_SHORT_STATUS1_LDO4_SHIFT 0x07 | ||
3538 | #define TPS65917_LDO_SHORT_STATUS1_LDO2 0x02 | ||
3539 | #define TPS65917_LDO_SHORT_STATUS1_LDO2_SHIFT 0x01 | ||
3540 | #define TPS65917_LDO_SHORT_STATUS1_LDO1 0x01 | ||
3541 | #define TPS65917_LDO_SHORT_STATUS1_LDO1_SHIFT 0x00 | ||
3542 | |||
3543 | /* Bit definitions for LDO_SHORT_STATUS2 */ | ||
3544 | #define TPS65917_LDO_SHORT_STATUS2_LDO3 0x04 | ||
3545 | #define TPS65917_LDO_SHORT_STATUS2_LDO3_SHIFT 0x02 | ||
3546 | #define TPS65917_LDO_SHORT_STATUS2_LDO5 0x02 | ||
3547 | #define TPS65917_LDO_SHORT_STATUS2_LDO5_SHIFT 0x01 | ||
3548 | |||
3549 | /* Bit definitions for LDO_SHORT_STATUS2 */ | ||
3550 | #define TPS65917_LDO_SHORT_STATUS2_LDOVANA 0x80 | ||
3551 | #define TPS65917_LDO_SHORT_STATUS2_LDOVANA_SHIFT 0x07 | ||
3552 | |||
3553 | /* Bit definitions for REGEN1_CTRL */ | ||
3554 | #define TPS65917_REGEN1_CTRL_STATUS 0x10 | ||
3555 | #define TPS65917_REGEN1_CTRL_STATUS_SHIFT 0x04 | ||
3556 | #define TPS65917_REGEN1_CTRL_MODE_SLEEP 0x04 | ||
3557 | #define TPS65917_REGEN1_CTRL_MODE_SLEEP_SHIFT 0x02 | ||
3558 | #define TPS65917_REGEN1_CTRL_MODE_ACTIVE 0x01 | ||
3559 | #define TPS65917_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0x00 | ||
3560 | |||
3561 | /* Bit definitions for PLLEN_CTRL */ | ||
3562 | #define TPS65917_PLLEN_CTRL_STATUS 0x10 | ||
3563 | #define TPS65917_PLLEN_CTRL_STATUS_SHIFT 0x04 | ||
3564 | #define TPS65917_PLLEN_CTRL_MODE_SLEEP 0x04 | ||
3565 | #define TPS65917_PLLEN_CTRL_MODE_SLEEP_SHIFT 0x02 | ||
3566 | #define TPS65917_PLLEN_CTRL_MODE_ACTIVE 0x01 | ||
3567 | #define TPS65917_PLLEN_CTRL_MODE_ACTIVE_SHIFT 0x00 | ||
3568 | |||
3569 | /* Bit definitions for REGEN2_CTRL */ | ||
3570 | #define TPS65917_REGEN2_CTRL_STATUS 0x10 | ||
3571 | #define TPS65917_REGEN2_CTRL_STATUS_SHIFT 0x04 | ||
3572 | #define TPS65917_REGEN2_CTRL_MODE_SLEEP 0x04 | ||
3573 | #define TPS65917_REGEN2_CTRL_MODE_SLEEP_SHIFT 0x02 | ||
3574 | #define TPS65917_REGEN2_CTRL_MODE_ACTIVE 0x01 | ||
3575 | #define TPS65917_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0x00 | ||
3576 | |||
3577 | /* Bit definitions for NSLEEP_RES_ASSIGN */ | ||
3578 | #define TPS65917_NSLEEP_RES_ASSIGN_PLL_EN 0x08 | ||
3579 | #define TPS65917_NSLEEP_RES_ASSIGN_PLL_EN_SHIFT 0x03 | ||
3580 | #define TPS65917_NSLEEP_RES_ASSIGN_REGEN3 0x04 | ||
3581 | #define TPS65917_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 0x02 | ||
3582 | #define TPS65917_NSLEEP_RES_ASSIGN_REGEN2 0x02 | ||
3583 | #define TPS65917_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 0x01 | ||
3584 | #define TPS65917_NSLEEP_RES_ASSIGN_REGEN1 0x01 | ||
3585 | #define TPS65917_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0x00 | ||
3586 | |||
3587 | /* Bit definitions for NSLEEP_SMPS_ASSIGN */ | ||
3588 | #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5 0x40 | ||
3589 | #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5_SHIFT 0x06 | ||
3590 | #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4 0x10 | ||
3591 | #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4_SHIFT 0x04 | ||
3592 | #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3 0x08 | ||
3593 | #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 0x03 | ||
3594 | #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2 0x02 | ||
3595 | #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2_SHIFT 0x01 | ||
3596 | #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1 0x01 | ||
3597 | #define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1_SHIFT 0x00 | ||
3598 | |||
3599 | /* Bit definitions for NSLEEP_LDO_ASSIGN1 */ | ||
3600 | #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO4 0x80 | ||
3601 | #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 0x07 | ||
3602 | #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO2 0x02 | ||
3603 | #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 0x01 | ||
3604 | #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO1 0x01 | ||
3605 | #define TPS65917_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0x00 | ||
3606 | |||
3607 | /* Bit definitions for NSLEEP_LDO_ASSIGN2 */ | ||
3608 | #define TPS65917_NSLEEP_LDO_ASSIGN2_LDO3 0x04 | ||
3609 | #define TPS65917_NSLEEP_LDO_ASSIGN2_LDO3_SHIFT 0x02 | ||
3610 | #define TPS65917_NSLEEP_LDO_ASSIGN2_LDO5 0x02 | ||
3611 | #define TPS65917_NSLEEP_LDO_ASSIGN2_LDO5_SHIFT 0x01 | ||
3612 | |||
3613 | /* Bit definitions for ENABLE1_RES_ASSIGN */ | ||
3614 | #define TPS65917_ENABLE1_RES_ASSIGN_PLLEN 0x08 | ||
3615 | #define TPS65917_ENABLE1_RES_ASSIGN_PLLEN_SHIFT 0x03 | ||
3616 | #define TPS65917_ENABLE1_RES_ASSIGN_REGEN3 0x04 | ||
3617 | #define TPS65917_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 0x02 | ||
3618 | #define TPS65917_ENABLE1_RES_ASSIGN_REGEN2 0x02 | ||
3619 | #define TPS65917_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 0x01 | ||
3620 | #define TPS65917_ENABLE1_RES_ASSIGN_REGEN1 0x01 | ||
3621 | #define TPS65917_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0x00 | ||
3622 | |||
3623 | /* Bit definitions for ENABLE1_SMPS_ASSIGN */ | ||
3624 | #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5 0x40 | ||
3625 | #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5_SHIFT 0x06 | ||
3626 | #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4 0x10 | ||
3627 | #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4_SHIFT 0x04 | ||
3628 | #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3 0x08 | ||
3629 | #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 0x03 | ||
3630 | #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2 0x02 | ||
3631 | #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2_SHIFT 0x01 | ||
3632 | #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1 0x01 | ||
3633 | #define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1_SHIFT 0x00 | ||
3634 | |||
3635 | /* Bit definitions for ENABLE1_LDO_ASSIGN1 */ | ||
3636 | #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO4 0x80 | ||
3637 | #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 0x07 | ||
3638 | #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO2 0x02 | ||
3639 | #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 0x01 | ||
3640 | #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO1 0x01 | ||
3641 | #define TPS65917_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0x00 | ||
3642 | |||
3643 | /* Bit definitions for ENABLE1_LDO_ASSIGN2 */ | ||
3644 | #define TPS65917_ENABLE1_LDO_ASSIGN2_LDO3 0x04 | ||
3645 | #define TPS65917_ENABLE1_LDO_ASSIGN2_LDO3_SHIFT 0x02 | ||
3646 | #define TPS65917_ENABLE1_LDO_ASSIGN2_LDO5 0x02 | ||
3647 | #define TPS65917_ENABLE1_LDO_ASSIGN2_LDO5_SHIFT 0x01 | ||
3648 | |||
3649 | /* Bit definitions for ENABLE2_RES_ASSIGN */ | ||
3650 | #define TPS65917_ENABLE2_RES_ASSIGN_PLLEN 0x08 | ||
3651 | #define TPS65917_ENABLE2_RES_ASSIGN_PLLEN_SHIFT 0x03 | ||
3652 | #define TPS65917_ENABLE2_RES_ASSIGN_REGEN3 0x04 | ||
3653 | #define TPS65917_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 0x02 | ||
3654 | #define TPS65917_ENABLE2_RES_ASSIGN_REGEN2 0x02 | ||
3655 | #define TPS65917_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 0x01 | ||
3656 | #define TPS65917_ENABLE2_RES_ASSIGN_REGEN1 0x01 | ||
3657 | #define TPS65917_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0x00 | ||
3658 | |||
3659 | /* Bit definitions for ENABLE2_SMPS_ASSIGN */ | ||
3660 | #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5 0x40 | ||
3661 | #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5_SHIFT 0x06 | ||
3662 | #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4 0x10 | ||
3663 | #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4_SHIFT 0x04 | ||
3664 | #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3 0x08 | ||
3665 | #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 0x03 | ||
3666 | #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2 0x02 | ||
3667 | #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2_SHIFT 0x01 | ||
3668 | #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1 0x01 | ||
3669 | #define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1_SHIFT 0x00 | ||
3670 | |||
3671 | /* Bit definitions for ENABLE2_LDO_ASSIGN1 */ | ||
3672 | #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO4 0x80 | ||
3673 | #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 0x07 | ||
3674 | #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO2 0x02 | ||
3675 | #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 0x01 | ||
3676 | #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO1 0x01 | ||
3677 | #define TPS65917_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0x00 | ||
3678 | |||
3679 | /* Bit definitions for ENABLE2_LDO_ASSIGN2 */ | ||
3680 | #define TPS65917_ENABLE2_LDO_ASSIGN2_LDO3 0x04 | ||
3681 | #define TPS65917_ENABLE2_LDO_ASSIGN2_LDO3_SHIFT 0x02 | ||
3682 | #define TPS65917_ENABLE2_LDO_ASSIGN2_LDO5 0x02 | ||
3683 | #define TPS65917_ENABLE2_LDO_ASSIGN2_LDO5_SHIFT 0x01 | ||
3684 | |||
3685 | /* Bit definitions for REGEN3_CTRL */ | ||
3686 | #define TPS65917_REGEN3_CTRL_STATUS 0x10 | ||
3687 | #define TPS65917_REGEN3_CTRL_STATUS_SHIFT 0x04 | ||
3688 | #define TPS65917_REGEN3_CTRL_MODE_SLEEP 0x04 | ||
3689 | #define TPS65917_REGEN3_CTRL_MODE_SLEEP_SHIFT 0x02 | ||
3690 | #define TPS65917_REGEN3_CTRL_MODE_ACTIVE 0x01 | ||
3691 | #define TPS65917_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0x00 | ||
3692 | |||
3693 | /* Registers for function RESOURCE */ | ||
3694 | #define TPS65917_REGEN1_CTRL 0x2 | ||
3695 | #define TPS65917_PLLEN_CTRL 0x3 | ||
3696 | #define TPS65917_NSLEEP_RES_ASSIGN 0x6 | ||
3697 | #define TPS65917_NSLEEP_SMPS_ASSIGN 0x7 | ||
3698 | #define TPS65917_NSLEEP_LDO_ASSIGN1 0x8 | ||
3699 | #define TPS65917_NSLEEP_LDO_ASSIGN2 0x9 | ||
3700 | #define TPS65917_ENABLE1_RES_ASSIGN 0xA | ||
3701 | #define TPS65917_ENABLE1_SMPS_ASSIGN 0xB | ||
3702 | #define TPS65917_ENABLE1_LDO_ASSIGN1 0xC | ||
3703 | #define TPS65917_ENABLE1_LDO_ASSIGN2 0xD | ||
3704 | #define TPS65917_ENABLE2_RES_ASSIGN 0xE | ||
3705 | #define TPS65917_ENABLE2_SMPS_ASSIGN 0xF | ||
3706 | #define TPS65917_ENABLE2_LDO_ASSIGN1 0x10 | ||
3707 | #define TPS65917_ENABLE2_LDO_ASSIGN2 0x11 | ||
3708 | #define TPS65917_REGEN2_CTRL 0x12 | ||
3709 | #define TPS65917_REGEN3_CTRL 0x13 | ||
3710 | |||
2874 | static inline int palmas_read(struct palmas *palmas, unsigned int base, | 3711 | static inline int palmas_read(struct palmas *palmas, unsigned int base, |
2875 | unsigned int reg, unsigned int *val) | 3712 | unsigned int reg, unsigned int *val) |
2876 | { | 3713 | { |