diff options
Diffstat (limited to 'include/linux/mfd/abx500/ab8500-sysctrl.h')
-rw-r--r-- | include/linux/mfd/abx500/ab8500-sysctrl.h | 254 |
1 files changed, 254 insertions, 0 deletions
diff --git a/include/linux/mfd/abx500/ab8500-sysctrl.h b/include/linux/mfd/abx500/ab8500-sysctrl.h new file mode 100644 index 000000000000..10da0291f8f8 --- /dev/null +++ b/include/linux/mfd/abx500/ab8500-sysctrl.h | |||
@@ -0,0 +1,254 @@ | |||
1 | /* | ||
2 | * Copyright (C) ST-Ericsson SA 2010 | ||
3 | * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com> for ST Ericsson. | ||
4 | * License terms: GNU General Public License (GPL) version 2 | ||
5 | */ | ||
6 | #ifndef __AB8500_SYSCTRL_H | ||
7 | #define __AB8500_SYSCTRL_H | ||
8 | |||
9 | #include <linux/bitops.h> | ||
10 | |||
11 | #ifdef CONFIG_AB8500_CORE | ||
12 | |||
13 | int ab8500_sysctrl_read(u16 reg, u8 *value); | ||
14 | int ab8500_sysctrl_write(u16 reg, u8 mask, u8 value); | ||
15 | |||
16 | #else | ||
17 | |||
18 | static inline int ab8500_sysctrl_read(u16 reg, u8 *value) | ||
19 | { | ||
20 | return 0; | ||
21 | } | ||
22 | |||
23 | static inline int ab8500_sysctrl_write(u16 reg, u8 mask, u8 value) | ||
24 | { | ||
25 | return 0; | ||
26 | } | ||
27 | |||
28 | #endif /* CONFIG_AB8500_CORE */ | ||
29 | |||
30 | static inline int ab8500_sysctrl_set(u16 reg, u8 bits) | ||
31 | { | ||
32 | return ab8500_sysctrl_write(reg, bits, bits); | ||
33 | } | ||
34 | |||
35 | static inline int ab8500_sysctrl_clear(u16 reg, u8 bits) | ||
36 | { | ||
37 | return ab8500_sysctrl_write(reg, bits, 0); | ||
38 | } | ||
39 | |||
40 | /* Registers */ | ||
41 | #define AB8500_TURNONSTATUS 0x100 | ||
42 | #define AB8500_RESETSTATUS 0x101 | ||
43 | #define AB8500_PONKEY1PRESSSTATUS 0x102 | ||
44 | #define AB8500_SYSCLKREQSTATUS 0x142 | ||
45 | #define AB8500_STW4500CTRL1 0x180 | ||
46 | #define AB8500_STW4500CTRL2 0x181 | ||
47 | #define AB8500_STW4500CTRL3 0x200 | ||
48 | #define AB8500_MAINWDOGCTRL 0x201 | ||
49 | #define AB8500_MAINWDOGTIMER 0x202 | ||
50 | #define AB8500_LOWBAT 0x203 | ||
51 | #define AB8500_BATTOK 0x204 | ||
52 | #define AB8500_SYSCLKTIMER 0x205 | ||
53 | #define AB8500_SMPSCLKCTRL 0x206 | ||
54 | #define AB8500_SMPSCLKSEL1 0x207 | ||
55 | #define AB8500_SMPSCLKSEL2 0x208 | ||
56 | #define AB8500_SMPSCLKSEL3 0x209 | ||
57 | #define AB8500_SYSULPCLKCONF 0x20A | ||
58 | #define AB8500_SYSULPCLKCTRL1 0x20B | ||
59 | #define AB8500_SYSCLKCTRL 0x20C | ||
60 | #define AB8500_SYSCLKREQ1VALID 0x20D | ||
61 | #define AB8500_SYSTEMCTRLSUP 0x20F | ||
62 | #define AB8500_SYSCLKREQ1RFCLKBUF 0x210 | ||
63 | #define AB8500_SYSCLKREQ2RFCLKBUF 0x211 | ||
64 | #define AB8500_SYSCLKREQ3RFCLKBUF 0x212 | ||
65 | #define AB8500_SYSCLKREQ4RFCLKBUF 0x213 | ||
66 | #define AB8500_SYSCLKREQ5RFCLKBUF 0x214 | ||
67 | #define AB8500_SYSCLKREQ6RFCLKBUF 0x215 | ||
68 | #define AB8500_SYSCLKREQ7RFCLKBUF 0x216 | ||
69 | #define AB8500_SYSCLKREQ8RFCLKBUF 0x217 | ||
70 | #define AB8500_DITHERCLKCTRL 0x220 | ||
71 | #define AB8500_SWATCTRL 0x230 | ||
72 | #define AB8500_HIQCLKCTRL 0x232 | ||
73 | #define AB8500_VSIMSYSCLKCTRL 0x233 | ||
74 | |||
75 | /* Bits */ | ||
76 | #define AB8500_TURNONSTATUS_PORNVBAT BIT(0) | ||
77 | #define AB8500_TURNONSTATUS_PONKEY1DBF BIT(1) | ||
78 | #define AB8500_TURNONSTATUS_PONKEY2DBF BIT(2) | ||
79 | #define AB8500_TURNONSTATUS_RTCALARM BIT(3) | ||
80 | #define AB8500_TURNONSTATUS_MAINCHDET BIT(4) | ||
81 | #define AB8500_TURNONSTATUS_VBUSDET BIT(5) | ||
82 | #define AB8500_TURNONSTATUS_USBIDDETECT BIT(6) | ||
83 | |||
84 | #define AB8500_RESETSTATUS_RESETN4500NSTATUS BIT(0) | ||
85 | #define AB8500_RESETSTATUS_SWRESETN4500NSTATUS BIT(2) | ||
86 | |||
87 | #define AB8500_PONKEY1PRESSSTATUS_PONKEY1PRESSTIME_MASK 0x7F | ||
88 | #define AB8500_PONKEY1PRESSSTATUS_PONKEY1PRESSTIME_SHIFT 0 | ||
89 | |||
90 | #define AB8500_SYSCLKREQSTATUS_SYSCLKREQ1STATUS BIT(0) | ||
91 | #define AB8500_SYSCLKREQSTATUS_SYSCLKREQ2STATUS BIT(1) | ||
92 | #define AB8500_SYSCLKREQSTATUS_SYSCLKREQ3STATUS BIT(2) | ||
93 | #define AB8500_SYSCLKREQSTATUS_SYSCLKREQ4STATUS BIT(3) | ||
94 | #define AB8500_SYSCLKREQSTATUS_SYSCLKREQ5STATUS BIT(4) | ||
95 | #define AB8500_SYSCLKREQSTATUS_SYSCLKREQ6STATUS BIT(5) | ||
96 | #define AB8500_SYSCLKREQSTATUS_SYSCLKREQ7STATUS BIT(6) | ||
97 | #define AB8500_SYSCLKREQSTATUS_SYSCLKREQ8STATUS BIT(7) | ||
98 | |||
99 | #define AB8500_STW4500CTRL1_SWOFF BIT(0) | ||
100 | #define AB8500_STW4500CTRL1_SWRESET4500N BIT(1) | ||
101 | #define AB8500_STW4500CTRL1_THDB8500SWOFF BIT(2) | ||
102 | |||
103 | #define AB8500_STW4500CTRL2_RESETNVAUX1VALID BIT(0) | ||
104 | #define AB8500_STW4500CTRL2_RESETNVAUX2VALID BIT(1) | ||
105 | #define AB8500_STW4500CTRL2_RESETNVAUX3VALID BIT(2) | ||
106 | #define AB8500_STW4500CTRL2_RESETNVMODVALID BIT(3) | ||
107 | #define AB8500_STW4500CTRL2_RESETNVEXTSUPPLY1VALID BIT(4) | ||
108 | #define AB8500_STW4500CTRL2_RESETNVEXTSUPPLY2VALID BIT(5) | ||
109 | #define AB8500_STW4500CTRL2_RESETNVEXTSUPPLY3VALID BIT(6) | ||
110 | #define AB8500_STW4500CTRL2_RESETNVSMPS1VALID BIT(7) | ||
111 | |||
112 | #define AB8500_STW4500CTRL3_CLK32KOUT2DIS BIT(0) | ||
113 | #define AB8500_STW4500CTRL3_RESETAUDN BIT(1) | ||
114 | #define AB8500_STW4500CTRL3_RESETDENCN BIT(2) | ||
115 | #define AB8500_STW4500CTRL3_THSDENA BIT(3) | ||
116 | |||
117 | #define AB8500_MAINWDOGCTRL_MAINWDOGENA BIT(0) | ||
118 | #define AB8500_MAINWDOGCTRL_MAINWDOGKICK BIT(1) | ||
119 | #define AB8500_MAINWDOGCTRL_WDEXPTURNONVALID BIT(4) | ||
120 | |||
121 | #define AB8500_MAINWDOGTIMER_MAINWDOGTIMER_MASK 0x7F | ||
122 | #define AB8500_MAINWDOGTIMER_MAINWDOGTIMER_SHIFT 0 | ||
123 | |||
124 | #define AB8500_LOWBAT_LOWBATENA BIT(0) | ||
125 | #define AB8500_LOWBAT_LOWBAT_MASK 0x7E | ||
126 | #define AB8500_LOWBAT_LOWBAT_SHIFT 1 | ||
127 | |||
128 | #define AB8500_BATTOK_BATTOKSEL0THF_MASK 0x0F | ||
129 | #define AB8500_BATTOK_BATTOKSEL0THF_SHIFT 0 | ||
130 | #define AB8500_BATTOK_BATTOKSEL1THF_MASK 0xF0 | ||
131 | #define AB8500_BATTOK_BATTOKSEL1THF_SHIFT 4 | ||
132 | |||
133 | #define AB8500_SYSCLKTIMER_SYSCLKTIMER_MASK 0x0F | ||
134 | #define AB8500_SYSCLKTIMER_SYSCLKTIMER_SHIFT 0 | ||
135 | #define AB8500_SYSCLKTIMER_SYSCLKTIMERADJ_MASK 0xF0 | ||
136 | #define AB8500_SYSCLKTIMER_SYSCLKTIMERADJ_SHIFT 4 | ||
137 | |||
138 | #define AB8500_SMPSCLKCTRL_SMPSCLKINTSEL_MASK 0x03 | ||
139 | #define AB8500_SMPSCLKCTRL_SMPSCLKINTSEL_SHIFT 0 | ||
140 | #define AB8500_SMPSCLKCTRL_3M2CLKINTENA BIT(2) | ||
141 | |||
142 | #define AB8500_SMPSCLKSEL1_VARMCLKSEL_MASK 0x07 | ||
143 | #define AB8500_SMPSCLKSEL1_VARMCLKSEL_SHIFT 0 | ||
144 | #define AB8500_SMPSCLKSEL1_VAPECLKSEL_MASK 0x38 | ||
145 | #define AB8500_SMPSCLKSEL1_VAPECLKSEL_SHIFT 3 | ||
146 | |||
147 | #define AB8500_SMPSCLKSEL2_VMODCLKSEL_MASK 0x07 | ||
148 | #define AB8500_SMPSCLKSEL2_VMODCLKSEL_SHIFT 0 | ||
149 | #define AB8500_SMPSCLKSEL2_VSMPS1CLKSEL_MASK 0x38 | ||
150 | #define AB8500_SMPSCLKSEL2_VSMPS1CLKSEL_SHIFT 3 | ||
151 | |||
152 | #define AB8500_SMPSCLKSEL3_VSMPS2CLKSEL_MASK 0x07 | ||
153 | #define AB8500_SMPSCLKSEL3_VSMPS2CLKSEL_SHIFT 0 | ||
154 | #define AB8500_SMPSCLKSEL3_VSMPS3CLKSEL_MASK 0x38 | ||
155 | #define AB8500_SMPSCLKSEL3_VSMPS3CLKSEL_SHIFT 3 | ||
156 | |||
157 | #define AB8500_SYSULPCLKCONF_ULPCLKCONF_MASK 0x03 | ||
158 | #define AB8500_SYSULPCLKCONF_ULPCLKCONF_SHIFT 0 | ||
159 | #define AB8500_SYSULPCLKCONF_CLK27MHZSTRE BIT(2) | ||
160 | #define AB8500_SYSULPCLKCONF_TVOUTCLKDELN BIT(3) | ||
161 | #define AB8500_SYSULPCLKCONF_TVOUTCLKINV BIT(4) | ||
162 | #define AB8500_SYSULPCLKCONF_ULPCLKSTRE BIT(5) | ||
163 | #define AB8500_SYSULPCLKCONF_CLK27MHZBUFENA BIT(6) | ||
164 | #define AB8500_SYSULPCLKCONF_CLK27MHZPDENA BIT(7) | ||
165 | |||
166 | #define AB8500_SYSULPCLKCTRL1_SYSULPCLKINTSEL_MASK 0x03 | ||
167 | #define AB8500_SYSULPCLKCTRL1_SYSULPCLKINTSEL_SHIFT 0 | ||
168 | #define AB8500_SYSULPCLKCTRL1_ULPCLKREQ BIT(2) | ||
169 | #define AB8500_SYSULPCLKCTRL1_4500SYSCLKREQ BIT(3) | ||
170 | #define AB8500_SYSULPCLKCTRL1_AUDIOCLKENA BIT(4) | ||
171 | #define AB8500_SYSULPCLKCTRL1_SYSCLKBUF2REQ BIT(5) | ||
172 | #define AB8500_SYSULPCLKCTRL1_SYSCLKBUF3REQ BIT(6) | ||
173 | #define AB8500_SYSULPCLKCTRL1_SYSCLKBUF4REQ BIT(7) | ||
174 | |||
175 | #define AB8500_SYSCLKCTRL_TVOUTPLLENA BIT(0) | ||
176 | #define AB8500_SYSCLKCTRL_TVOUTCLKENA BIT(1) | ||
177 | #define AB8500_SYSCLKCTRL_USBCLKENA BIT(2) | ||
178 | |||
179 | #define AB8500_SYSCLKREQ1VALID_SYSCLKREQ1VALID BIT(0) | ||
180 | #define AB8500_SYSCLKREQ1VALID_ULPCLKREQ1VALID BIT(1) | ||
181 | #define AB8500_SYSCLKREQ1VALID_USBSYSCLKREQ1VALID BIT(2) | ||
182 | |||
183 | #define AB8500_SYSTEMCTRLSUP_EXTSUP12LPNCLKSEL_MASK 0x03 | ||
184 | #define AB8500_SYSTEMCTRLSUP_EXTSUP12LPNCLKSEL_SHIFT 0 | ||
185 | #define AB8500_SYSTEMCTRLSUP_EXTSUP3LPNCLKSEL_MASK 0x0C | ||
186 | #define AB8500_SYSTEMCTRLSUP_EXTSUP3LPNCLKSEL_SHIFT 2 | ||
187 | #define AB8500_SYSTEMCTRLSUP_INTDB8500NOD BIT(4) | ||
188 | |||
189 | #define AB8500_SYSCLKREQ1RFCLKBUF_SYSCLKREQ1RFCLKBUF2 BIT(2) | ||
190 | #define AB8500_SYSCLKREQ1RFCLKBUF_SYSCLKREQ1RFCLKBUF3 BIT(3) | ||
191 | #define AB8500_SYSCLKREQ1RFCLKBUF_SYSCLKREQ1RFCLKBUF4 BIT(4) | ||
192 | |||
193 | #define AB8500_SYSCLKREQ2RFCLKBUF_SYSCLKREQ2RFCLKBUF2 BIT(2) | ||
194 | #define AB8500_SYSCLKREQ2RFCLKBUF_SYSCLKREQ2RFCLKBUF3 BIT(3) | ||
195 | #define AB8500_SYSCLKREQ2RFCLKBUF_SYSCLKREQ2RFCLKBUF4 BIT(4) | ||
196 | |||
197 | #define AB8500_SYSCLKREQ3RFCLKBUF_SYSCLKREQ3RFCLKBUF2 BIT(2) | ||
198 | #define AB8500_SYSCLKREQ3RFCLKBUF_SYSCLKREQ3RFCLKBUF3 BIT(3) | ||
199 | #define AB8500_SYSCLKREQ3RFCLKBUF_SYSCLKREQ3RFCLKBUF4 BIT(4) | ||
200 | |||
201 | #define AB8500_SYSCLKREQ4RFCLKBUF_SYSCLKREQ4RFCLKBUF2 BIT(2) | ||
202 | #define AB8500_SYSCLKREQ4RFCLKBUF_SYSCLKREQ4RFCLKBUF3 BIT(3) | ||
203 | #define AB8500_SYSCLKREQ4RFCLKBUF_SYSCLKREQ4RFCLKBUF4 BIT(4) | ||
204 | |||
205 | #define AB8500_SYSCLKREQ5RFCLKBUF_SYSCLKREQ5RFCLKBUF2 BIT(2) | ||
206 | #define AB8500_SYSCLKREQ5RFCLKBUF_SYSCLKREQ5RFCLKBUF3 BIT(3) | ||
207 | #define AB8500_SYSCLKREQ5RFCLKBUF_SYSCLKREQ5RFCLKBUF4 BIT(4) | ||
208 | |||
209 | #define AB8500_SYSCLKREQ6RFCLKBUF_SYSCLKREQ6RFCLKBUF2 BIT(2) | ||
210 | #define AB8500_SYSCLKREQ6RFCLKBUF_SYSCLKREQ6RFCLKBUF3 BIT(3) | ||
211 | #define AB8500_SYSCLKREQ6RFCLKBUF_SYSCLKREQ6RFCLKBUF4 BIT(4) | ||
212 | |||
213 | #define AB8500_SYSCLKREQ7RFCLKBUF_SYSCLKREQ7RFCLKBUF2 BIT(2) | ||
214 | #define AB8500_SYSCLKREQ7RFCLKBUF_SYSCLKREQ7RFCLKBUF3 BIT(3) | ||
215 | #define AB8500_SYSCLKREQ7RFCLKBUF_SYSCLKREQ7RFCLKBUF4 BIT(4) | ||
216 | |||
217 | #define AB8500_SYSCLKREQ8RFCLKBUF_SYSCLKREQ8RFCLKBUF2 BIT(2) | ||
218 | #define AB8500_SYSCLKREQ8RFCLKBUF_SYSCLKREQ8RFCLKBUF3 BIT(3) | ||
219 | #define AB8500_SYSCLKREQ8RFCLKBUF_SYSCLKREQ8RFCLKBUF4 BIT(4) | ||
220 | |||
221 | #define AB8500_DITHERCLKCTRL_VARMDITHERENA BIT(0) | ||
222 | #define AB8500_DITHERCLKCTRL_VSMPS3DITHERENA BIT(1) | ||
223 | #define AB8500_DITHERCLKCTRL_VSMPS1DITHERENA BIT(2) | ||
224 | #define AB8500_DITHERCLKCTRL_VSMPS2DITHERENA BIT(3) | ||
225 | #define AB8500_DITHERCLKCTRL_VMODDITHERENA BIT(4) | ||
226 | #define AB8500_DITHERCLKCTRL_VAPEDITHERENA BIT(5) | ||
227 | #define AB8500_DITHERCLKCTRL_DITHERDEL_MASK 0xC0 | ||
228 | #define AB8500_DITHERCLKCTRL_DITHERDEL_SHIFT 6 | ||
229 | |||
230 | #define AB8500_SWATCTRL_UPDATERF BIT(0) | ||
231 | #define AB8500_SWATCTRL_SWATENABLE BIT(1) | ||
232 | #define AB8500_SWATCTRL_RFOFFTIMER_MASK 0x1C | ||
233 | #define AB8500_SWATCTRL_RFOFFTIMER_SHIFT 2 | ||
234 | #define AB8500_SWATCTRL_SWATBIT5 BIT(6) | ||
235 | |||
236 | #define AB8500_HIQCLKCTRL_SYSCLKREQ1HIQENAVALID BIT(0) | ||
237 | #define AB8500_HIQCLKCTRL_SYSCLKREQ2HIQENAVALID BIT(1) | ||
238 | #define AB8500_HIQCLKCTRL_SYSCLKREQ3HIQENAVALID BIT(2) | ||
239 | #define AB8500_HIQCLKCTRL_SYSCLKREQ4HIQENAVALID BIT(3) | ||
240 | #define AB8500_HIQCLKCTRL_SYSCLKREQ5HIQENAVALID BIT(4) | ||
241 | #define AB8500_HIQCLKCTRL_SYSCLKREQ6HIQENAVALID BIT(5) | ||
242 | #define AB8500_HIQCLKCTRL_SYSCLKREQ7HIQENAVALID BIT(6) | ||
243 | #define AB8500_HIQCLKCTRL_SYSCLKREQ8HIQENAVALID BIT(7) | ||
244 | |||
245 | #define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ1VALID BIT(0) | ||
246 | #define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ2VALID BIT(1) | ||
247 | #define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ3VALID BIT(2) | ||
248 | #define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ4VALID BIT(3) | ||
249 | #define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ5VALID BIT(4) | ||
250 | #define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ6VALID BIT(5) | ||
251 | #define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ7VALID BIT(6) | ||
252 | #define AB8500_VSIMSYSCLKCTRL_VSIMSYSCLKREQ8VALID BIT(7) | ||
253 | |||
254 | #endif /* __AB8500_SYSCTRL_H */ | ||