litmus-rt.git - The LITMUS^RT kernel.

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The LITMUS^RT kernel.

Bjoern Brandenburg

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ions <svcmobile_promotions@nvidia.com> 2017-08-24 12:34:43 -0400 gpu: nvgpu: Reorg gr HAL initialization' href='/cgit/cgit.cgi/nvgpu.git/commit/drivers/gpu/nvgpu/gp10b/gr_gp10b.h?h=gpu-paging&id=4b5b67d6d83430d8d670660b1dfc9cf024d60d88'>4b5b67d6

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/*
 * GP10B GPU GR
 *
 * Copyright (c) 2015-2018, NVIDIA CORPORATION.  All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */

#ifndef NVGPU_GR_GP10B_H
#define NVGPU_GR_GP10B_H

#include "gk20a/mm_gk20a.h"

struct gk20a;
struct gr_gk20a_isr_data;
struct nvgpu_gr_ctx;
struct zbc_entry;
struct nvgpu_preemption_modes_rec;
struct gk20a_debug_output;

enum {
	PASCAL_CHANNEL_GPFIFO_A  = 0xC06F,
	PASCAL_A                 = 0xC097,
	PASCAL_COMPUTE_A         = 0xC0C0,
	PASCAL_DMA_COPY_A        = 0xC0B5,
	PASCAL_DMA_COPY_B        = 0xC1B5,
};

#define NVC097_SET_GO_IDLE_TIMEOUT		0x022c
#define NVC097_SET_ALPHA_CIRCULAR_BUFFER_SIZE	0x02dc
#define NVC097_SET_COALESCE_BUFFER_SIZE		0x1028
#define NVC097_SET_RD_COALESCE			0x102c
#define NVC097_SET_CIRCULAR_BUFFER_SIZE		0x1280
#define NVC097_SET_SHADER_EXCEPTIONS		0x1528
#define NVC097_SET_BES_CROP_DEBUG3		0x10c4
#define NVC097_SET_BES_CROP_DEBUG4		0x10b0
#define NVC0C0_SET_SHADER_EXCEPTIONS		0x1528
#define NVC0C0_SET_RD_COALESCE			0x0228

#define NVC097_BES_CROP_DEBUG4_CLAMP_FP_BLEND_TO_INF	0x0
#define NVC097_BES_CROP_DEBUG4_CLAMP_FP_BLEND_TO_MAXVAL 0x1

int gr_gp10b_init_fs_state(struct gk20a *g);
int gr_gp10b_alloc_buffer(struct vm_gk20a *vm, size_t size,
			struct nvgpu_mem *mem);
void gr_gp10b_create_sysfs(struct gk20a *g);
void gr_gp10b_remove_sysfs(struct gk20a *g);
int gr_gp10b_handle_fecs_error(struct gk20a *g,
			struct channel_gk20a *__ch,
			struct gr_gk20a_isr_data *isr_data);
int gr_gp10b_set_cilp_preempt_pending(struct gk20a *g,
		struct channel_gk20a *fault_ch);

bool gr_gp10b_is_valid_class(struct gk20a *g, u32 class_num);
bool gr_gp10b_is_valid_gfx_class(struct gk20a *g, u32 class_num);
bool gr_gp10b_is_valid_compute_class(struct gk20a *g, u32 class_num);
int gr_gp10b_handle_sm_exception(struct gk20a *g,
			u32 gpc, u32 tpc, u32 sm,
			bool *post_event, struct channel_gk20a *fault_ch,
			u32 *hww_global_esr);
int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc,
		bool *post_event);
int gr_gp10b_commit_global_cb_manager(struct gk20a *g,
			struct channel_gk20a *c, bool patch);


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