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-rw-r--r--include/linux/dw_dmac.h40
1 files changed, 23 insertions, 17 deletions
diff --git a/include/linux/dw_dmac.h b/include/linux/dw_dmac.h
index e1c8c9e919ac..481ab2345d6b 100644
--- a/include/linux/dw_dmac.h
+++ b/include/linux/dw_dmac.h
@@ -15,14 +15,37 @@
15#include <linux/dmaengine.h> 15#include <linux/dmaengine.h>
16 16
17/** 17/**
18 * struct dw_dma_slave - Controller-specific information about a slave
19 *
20 * @dma_dev: required DMA master device. Depricated.
21 * @bus_id: name of this device channel, not just a device name since
22 * devices may have more than one channel e.g. "foo_tx"
23 * @cfg_hi: Platform-specific initializer for the CFG_HI register
24 * @cfg_lo: Platform-specific initializer for the CFG_LO register
25 * @src_master: src master for transfers on allocated channel.
26 * @dst_master: dest master for transfers on allocated channel.
27 */
28struct dw_dma_slave {
29 struct device *dma_dev;
30 u32 cfg_hi;
31 u32 cfg_lo;
32 u8 src_master;
33 u8 dst_master;
34};
35
36/**
18 * struct dw_dma_platform_data - Controller configuration parameters 37 * struct dw_dma_platform_data - Controller configuration parameters
19 * @nr_channels: Number of channels supported by hardware (max 8) 38 * @nr_channels: Number of channels supported by hardware (max 8)
20 * @is_private: The device channels should be marked as private and not for 39 * @is_private: The device channels should be marked as private and not for
21 * by the general purpose DMA channel allocator. 40 * by the general purpose DMA channel allocator.
41 * @chan_allocation_order: Allocate channels starting from 0 or 7
42 * @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0.
22 * @block_size: Maximum block size supported by the controller 43 * @block_size: Maximum block size supported by the controller
23 * @nr_masters: Number of AHB masters supported by the controller 44 * @nr_masters: Number of AHB masters supported by the controller
24 * @data_width: Maximum data width supported by hardware per AHB master 45 * @data_width: Maximum data width supported by hardware per AHB master
25 * (0 - 8bits, 1 - 16bits, ..., 5 - 256bits) 46 * (0 - 8bits, 1 - 16bits, ..., 5 - 256bits)
47 * @sd: slave specific data. Used for configuring channels
48 * @sd_count: count of slave data structures passed.
26 */ 49 */
27struct dw_dma_platform_data { 50struct dw_dma_platform_data {
28 unsigned int nr_channels; 51 unsigned int nr_channels;
@@ -50,23 +73,6 @@ enum dw_dma_msize {
50 DW_DMA_MSIZE_256, 73 DW_DMA_MSIZE_256,
51}; 74};
52 75
53/**
54 * struct dw_dma_slave - Controller-specific information about a slave
55 *
56 * @dma_dev: required DMA master device
57 * @cfg_hi: Platform-specific initializer for the CFG_HI register
58 * @cfg_lo: Platform-specific initializer for the CFG_LO register
59 * @src_master: src master for transfers on allocated channel.
60 * @dst_master: dest master for transfers on allocated channel.
61 */
62struct dw_dma_slave {
63 struct device *dma_dev;
64 u32 cfg_hi;
65 u32 cfg_lo;
66 u8 src_master;
67 u8 dst_master;
68};
69
70/* Platform-configurable bits in CFG_HI */ 76/* Platform-configurable bits in CFG_HI */
71#define DWC_CFGH_FCMODE (1 << 0) 77#define DWC_CFGH_FCMODE (1 << 0)
72#define DWC_CFGH_FIFO_MODE (1 << 1) 78#define DWC_CFGH_FIFO_MODE (1 << 1)