diff options
Diffstat (limited to 'include/linux/dmaengine.h')
| -rw-r--r-- | include/linux/dmaengine.h | 54 |
1 files changed, 51 insertions, 3 deletions
diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index cb286b1acdb6..0bc727534108 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h | |||
| @@ -38,7 +38,10 @@ typedef s32 dma_cookie_t; | |||
| 38 | #define DMA_MIN_COOKIE 1 | 38 | #define DMA_MIN_COOKIE 1 |
| 39 | #define DMA_MAX_COOKIE INT_MAX | 39 | #define DMA_MAX_COOKIE INT_MAX |
| 40 | 40 | ||
| 41 | #define dma_submit_error(cookie) ((cookie) < 0 ? 1 : 0) | 41 | static inline int dma_submit_error(dma_cookie_t cookie) |
| 42 | { | ||
| 43 | return cookie < 0 ? cookie : 0; | ||
| 44 | } | ||
| 42 | 45 | ||
| 43 | /** | 46 | /** |
| 44 | * enum dma_status - DMA transaction status | 47 | * enum dma_status - DMA transaction status |
| @@ -370,6 +373,25 @@ struct dma_slave_config { | |||
| 370 | unsigned int slave_id; | 373 | unsigned int slave_id; |
| 371 | }; | 374 | }; |
| 372 | 375 | ||
| 376 | /* struct dma_slave_caps - expose capabilities of a slave channel only | ||
| 377 | * | ||
| 378 | * @src_addr_widths: bit mask of src addr widths the channel supports | ||
| 379 | * @dstn_addr_widths: bit mask of dstn addr widths the channel supports | ||
| 380 | * @directions: bit mask of slave direction the channel supported | ||
| 381 | * since the enum dma_transfer_direction is not defined as bits for each | ||
| 382 | * type of direction, the dma controller should fill (1 << <TYPE>) and same | ||
| 383 | * should be checked by controller as well | ||
| 384 | * @cmd_pause: true, if pause and thereby resume is supported | ||
| 385 | * @cmd_terminate: true, if terminate cmd is supported | ||
| 386 | */ | ||
| 387 | struct dma_slave_caps { | ||
| 388 | u32 src_addr_widths; | ||
| 389 | u32 dstn_addr_widths; | ||
| 390 | u32 directions; | ||
| 391 | bool cmd_pause; | ||
| 392 | bool cmd_terminate; | ||
| 393 | }; | ||
| 394 | |||
| 373 | static inline const char *dma_chan_name(struct dma_chan *chan) | 395 | static inline const char *dma_chan_name(struct dma_chan *chan) |
| 374 | { | 396 | { |
| 375 | return dev_name(&chan->dev->device); | 397 | return dev_name(&chan->dev->device); |
| @@ -532,6 +554,7 @@ struct dma_tx_state { | |||
| 532 | * struct with auxiliary transfer status information, otherwise the call | 554 | * struct with auxiliary transfer status information, otherwise the call |
| 533 | * will just return a simple status code | 555 | * will just return a simple status code |
| 534 | * @device_issue_pending: push pending transactions to hardware | 556 | * @device_issue_pending: push pending transactions to hardware |
| 557 | * @device_slave_caps: return the slave channel capabilities | ||
| 535 | */ | 558 | */ |
| 536 | struct dma_device { | 559 | struct dma_device { |
| 537 | 560 | ||
| @@ -597,6 +620,7 @@ struct dma_device { | |||
| 597 | dma_cookie_t cookie, | 620 | dma_cookie_t cookie, |
| 598 | struct dma_tx_state *txstate); | 621 | struct dma_tx_state *txstate); |
| 599 | void (*device_issue_pending)(struct dma_chan *chan); | 622 | void (*device_issue_pending)(struct dma_chan *chan); |
| 623 | int (*device_slave_caps)(struct dma_chan *chan, struct dma_slave_caps *caps); | ||
| 600 | }; | 624 | }; |
| 601 | 625 | ||
| 602 | static inline int dmaengine_device_control(struct dma_chan *chan, | 626 | static inline int dmaengine_device_control(struct dma_chan *chan, |
| @@ -670,6 +694,21 @@ static inline struct dma_async_tx_descriptor *dmaengine_prep_interleaved_dma( | |||
| 670 | return chan->device->device_prep_interleaved_dma(chan, xt, flags); | 694 | return chan->device->device_prep_interleaved_dma(chan, xt, flags); |
| 671 | } | 695 | } |
| 672 | 696 | ||
| 697 | static inline int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps) | ||
| 698 | { | ||
| 699 | if (!chan || !caps) | ||
| 700 | return -EINVAL; | ||
| 701 | |||
| 702 | /* check if the channel supports slave transactions */ | ||
| 703 | if (!test_bit(DMA_SLAVE, chan->device->cap_mask.bits)) | ||
| 704 | return -ENXIO; | ||
| 705 | |||
| 706 | if (chan->device->device_slave_caps) | ||
| 707 | return chan->device->device_slave_caps(chan, caps); | ||
| 708 | |||
| 709 | return -ENXIO; | ||
| 710 | } | ||
| 711 | |||
| 673 | static inline int dmaengine_terminate_all(struct dma_chan *chan) | 712 | static inline int dmaengine_terminate_all(struct dma_chan *chan) |
| 674 | { | 713 | { |
| 675 | return dmaengine_device_control(chan, DMA_TERMINATE_ALL, 0); | 714 | return dmaengine_device_control(chan, DMA_TERMINATE_ALL, 0); |
| @@ -958,8 +997,9 @@ dma_set_tx_state(struct dma_tx_state *st, dma_cookie_t last, dma_cookie_t used, | |||
| 958 | } | 997 | } |
| 959 | } | 998 | } |
| 960 | 999 | ||
| 961 | enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie); | ||
| 962 | #ifdef CONFIG_DMA_ENGINE | 1000 | #ifdef CONFIG_DMA_ENGINE |
| 1001 | struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type); | ||
| 1002 | enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie); | ||
| 963 | enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx); | 1003 | enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx); |
| 964 | void dma_issue_pending_all(void); | 1004 | void dma_issue_pending_all(void); |
| 965 | struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask, | 1005 | struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask, |
| @@ -967,6 +1007,14 @@ struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask, | |||
| 967 | struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name); | 1007 | struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name); |
| 968 | void dma_release_channel(struct dma_chan *chan); | 1008 | void dma_release_channel(struct dma_chan *chan); |
| 969 | #else | 1009 | #else |
| 1010 | static inline struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type) | ||
| 1011 | { | ||
| 1012 | return NULL; | ||
| 1013 | } | ||
| 1014 | static inline enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie) | ||
| 1015 | { | ||
| 1016 | return DMA_SUCCESS; | ||
| 1017 | } | ||
| 970 | static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx) | 1018 | static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx) |
| 971 | { | 1019 | { |
| 972 | return DMA_SUCCESS; | 1020 | return DMA_SUCCESS; |
| @@ -994,7 +1042,7 @@ static inline void dma_release_channel(struct dma_chan *chan) | |||
| 994 | int dma_async_device_register(struct dma_device *device); | 1042 | int dma_async_device_register(struct dma_device *device); |
| 995 | void dma_async_device_unregister(struct dma_device *device); | 1043 | void dma_async_device_unregister(struct dma_device *device); |
| 996 | void dma_run_dependencies(struct dma_async_tx_descriptor *tx); | 1044 | void dma_run_dependencies(struct dma_async_tx_descriptor *tx); |
| 997 | struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type); | 1045 | struct dma_chan *dma_get_slave_channel(struct dma_chan *chan); |
| 998 | struct dma_chan *net_dma_find_channel(void); | 1046 | struct dma_chan *net_dma_find_channel(void); |
| 999 | #define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y) | 1047 | #define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y) |
| 1000 | #define dma_request_slave_channel_compat(mask, x, y, dev, name) \ | 1048 | #define dma_request_slave_channel_compat(mask, x, y, dev, name) \ |
