1 files changed, 37 insertions, 44 deletions

diff --git a/include/linux/acpi.h b/include/linux/acpi.h
index a5db4aeefa36..e2e52cf53224 100644
--- a/include/linux/acpi.h
+++ b/include/linux/acpi.h
@@ -294,58 +294,51 @@ void __init acpi_nvs_nosave_s3(void);
 #endif /* CONFIG_PM_SLEEP */
 
 struct acpi_osc_context {
-        char *uuid_str; /* uuid string */
+        char *uuid_str;                 /* UUID string */
         int rev;
-        struct acpi_buffer cap; /* arg2/arg3 */
-        struct acpi_buffer ret; /* free by caller if success */
+        struct acpi_buffer cap;         /* list of DWORD capabilities */
+        struct acpi_buffer ret;         /* free by caller if success */
 };
 
-#define OSC_QUERY_TYPE                  0
-#define OSC_SUPPORT_TYPE                1
-#define OSC_CONTROL_TYPE                2
-
-/* _OSC DW0 Definition */
-#define OSC_QUERY_ENABLE                1
-#define OSC_REQUEST_ERROR               2
-#define OSC_INVALID_UUID_ERROR          4
-#define OSC_INVALID_REVISION_ERROR      8
-#define OSC_CAPABILITIES_MASK_ERROR     16
-
 acpi_status acpi_run_osc(acpi_handle handle, struct acpi_osc_context *context);
 
-/* platform-wide _OSC bits */
-#define OSC_SB_PAD_SUPPORT              1
-#define OSC_SB_PPC_OST_SUPPORT          2
-#define OSC_SB_PR3_SUPPORT              4
-#define OSC_SB_HOTPLUG_OST_SUPPORT      8
-#define OSC_SB_APEI_SUPPORT             16
+/* Indexes into _OSC Capabilities Buffer (DWORDs 2 & 3 are device-specific) */
+#define OSC_QUERY_DWORD                         0       /* DWORD 1 */
+#define OSC_SUPPORT_DWORD                       1       /* DWORD 2 */
+#define OSC_CONTROL_DWORD                       2       /* DWORD 3 */
+
+/* _OSC Capabilities DWORD 1: Query/Control and Error Returns (generic) */
+#define OSC_QUERY_ENABLE                        0x00000001  /* input */
+#define OSC_REQUEST_ERROR                       0x00000002  /* return */
+#define OSC_INVALID_UUID_ERROR                  0x00000004  /* return */
+#define OSC_INVALID_REVISION_ERROR              0x00000008  /* return */
+#define OSC_CAPABILITIES_MASK_ERROR             0x00000010  /* return */
+
+/* Platform-Wide Capabilities _OSC: Capabilities DWORD 2: Support Field */
+#define OSC_SB_PAD_SUPPORT                      0x00000001
+#define OSC_SB_PPC_OST_SUPPORT                  0x00000002
+#define OSC_SB_PR3_SUPPORT                      0x00000004
+#define OSC_SB_HOTPLUG_OST_SUPPORT              0x00000008
+#define OSC_SB_APEI_SUPPORT                     0x00000010
+#define OSC_SB_CPC_SUPPORT                      0x00000020
 
 extern bool osc_sb_apei_support_acked;
 
-/* PCI defined _OSC bits */
-/* _OSC DW1 Definition (OS Support Fields) */
-#define OSC_EXT_PCI_CONFIG_SUPPORT              1
-#define OSC_ACTIVE_STATE_PWR_SUPPORT            2
-#define OSC_CLOCK_PWR_CAPABILITY_SUPPORT        4
-#define OSC_PCI_SEGMENT_GROUPS_SUPPORT          8
-#define OSC_MSI_SUPPORT                         16
-#define OSC_PCI_SUPPORT_MASKS                   0x1f
-
-/* _OSC DW1 Definition (OS Control Fields) */
-#define OSC_PCI_EXPRESS_NATIVE_HP_CONTROL       1
-#define OSC_SHPC_NATIVE_HP_CONTROL              2
-#define OSC_PCI_EXPRESS_PME_CONTROL             4
-#define OSC_PCI_EXPRESS_AER_CONTROL             8
-#define OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL   16
-
-#define OSC_PCI_CONTROL_MASKS   (OSC_PCI_EXPRESS_NATIVE_HP_CONTROL |    \
-                                OSC_SHPC_NATIVE_HP_CONTROL |            \
-                                OSC_PCI_EXPRESS_PME_CONTROL |           \
-                                OSC_PCI_EXPRESS_AER_CONTROL |           \
-                                OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL)
-
-#define OSC_PCI_NATIVE_HOTPLUG  (OSC_PCI_EXPRESS_NATIVE_HP_CONTROL |    \
-                                OSC_SHPC_NATIVE_HP_CONTROL)
+/* PCI Host Bridge _OSC: Capabilities DWORD 2: Support Field */
+#define OSC_PCI_EXT_CONFIG_SUPPORT              0x00000001
+#define OSC_PCI_ASPM_SUPPORT                    0x00000002
+#define OSC_PCI_CLOCK_PM_SUPPORT                0x00000004
+#define OSC_PCI_SEGMENT_GROUPS_SUPPORT          0x00000008
+#define OSC_PCI_MSI_SUPPORT                     0x00000010
+#define OSC_PCI_SUPPORT_MASKS                   0x0000001f
+
+/* PCI Host Bridge _OSC: Capabilities DWORD 3: Control Field */
+#define OSC_PCI_EXPRESS_NATIVE_HP_CONTROL       0x00000001
+#define OSC_PCI_SHPC_NATIVE_HP_CONTROL          0x00000002
+#define OSC_PCI_EXPRESS_PME_CONTROL             0x00000004
+#define OSC_PCI_EXPRESS_AER_CONTROL             0x00000008
+#define OSC_PCI_EXPRESS_CAPABILITY_CONTROL      0x00000010
+#define OSC_PCI_CONTROL_MASKS                   0x0000001f
 
 extern acpi_status acpi_pci_osc_control_set(acpi_handle handle,
                                              u32 *mask, u32 req);