diff options
Diffstat (limited to 'include/dt-bindings/clock/qcom,gcc-msm8960.h')
-rw-r--r-- | include/dt-bindings/clock/qcom,gcc-msm8960.h | 313 |
1 files changed, 313 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8960.h b/include/dt-bindings/clock/qcom,gcc-msm8960.h new file mode 100644 index 000000000000..03bbf49d43b7 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-msm8960.h | |||
@@ -0,0 +1,313 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2013, The Linux Foundation. All rights reserved. | ||
3 | * | ||
4 | * This software is licensed under the terms of the GNU General Public | ||
5 | * License version 2, as published by the Free Software Foundation, and | ||
6 | * may be copied, distributed, and modified under those terms. | ||
7 | * | ||
8 | * This program is distributed in the hope that it will be useful, | ||
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
11 | * GNU General Public License for more details. | ||
12 | */ | ||
13 | |||
14 | #ifndef _DT_BINDINGS_CLK_MSM_GCC_8960_H | ||
15 | #define _DT_BINDINGS_CLK_MSM_GCC_8960_H | ||
16 | |||
17 | #define AFAB_CLK_SRC 0 | ||
18 | #define AFAB_CORE_CLK 1 | ||
19 | #define SFAB_MSS_Q6_SW_A_CLK 2 | ||
20 | #define SFAB_MSS_Q6_FW_A_CLK 3 | ||
21 | #define QDSS_STM_CLK 4 | ||
22 | #define SCSS_A_CLK 5 | ||
23 | #define SCSS_H_CLK 6 | ||
24 | #define SCSS_XO_SRC_CLK 7 | ||
25 | #define AFAB_EBI1_CH0_A_CLK 8 | ||
26 | #define AFAB_EBI1_CH1_A_CLK 9 | ||
27 | #define AFAB_AXI_S0_FCLK 10 | ||
28 | #define AFAB_AXI_S1_FCLK 11 | ||
29 | #define AFAB_AXI_S2_FCLK 12 | ||
30 | #define AFAB_AXI_S3_FCLK 13 | ||
31 | #define AFAB_AXI_S4_FCLK 14 | ||
32 | #define SFAB_CORE_CLK 15 | ||
33 | #define SFAB_AXI_S0_FCLK 16 | ||
34 | #define SFAB_AXI_S1_FCLK 17 | ||
35 | #define SFAB_AXI_S2_FCLK 18 | ||
36 | #define SFAB_AXI_S3_FCLK 19 | ||
37 | #define SFAB_AXI_S4_FCLK 20 | ||
38 | #define SFAB_AHB_S0_FCLK 21 | ||
39 | #define SFAB_AHB_S1_FCLK 22 | ||
40 | #define SFAB_AHB_S2_FCLK 23 | ||
41 | #define SFAB_AHB_S3_FCLK 24 | ||
42 | #define SFAB_AHB_S4_FCLK 25 | ||
43 | #define SFAB_AHB_S5_FCLK 26 | ||
44 | #define SFAB_AHB_S6_FCLK 27 | ||
45 | #define SFAB_AHB_S7_FCLK 28 | ||
46 | #define QDSS_AT_CLK_SRC 29 | ||
47 | #define QDSS_AT_CLK 30 | ||
48 | #define QDSS_TRACECLKIN_CLK_SRC 31 | ||
49 | #define QDSS_TRACECLKIN_CLK 32 | ||
50 | #define QDSS_TSCTR_CLK_SRC 33 | ||
51 | #define QDSS_TSCTR_CLK 34 | ||
52 | #define SFAB_ADM0_M0_A_CLK 35 | ||
53 | #define SFAB_ADM0_M1_A_CLK 36 | ||
54 | #define SFAB_ADM0_M2_A_CLK 37 | ||
55 | #define ADM0_CLK 38 | ||
56 | #define ADM0_PBUS_CLK 39 | ||
57 | #define MSS_XPU_CLK 40 | ||
58 | #define IMEM0_A_CLK 41 | ||
59 | #define QDSS_H_CLK 42 | ||
60 | #define PCIE_A_CLK 43 | ||
61 | #define PCIE_AUX_CLK 44 | ||
62 | #define PCIE_PHY_REF_CLK 45 | ||
63 | #define PCIE_H_CLK 46 | ||
64 | #define SFAB_CLK_SRC 47 | ||
65 | #define MAHB0_CLK 48 | ||
66 | #define Q6SW_CLK_SRC 49 | ||
67 | #define Q6SW_CLK 50 | ||
68 | #define Q6FW_CLK_SRC 51 | ||
69 | #define Q6FW_CLK 52 | ||
70 | #define SFAB_MSS_M_A_CLK 53 | ||
71 | #define SFAB_USB3_M_A_CLK 54 | ||
72 | #define SFAB_LPASS_Q6_A_CLK 55 | ||
73 | #define SFAB_AFAB_M_A_CLK 56 | ||
74 | #define AFAB_SFAB_M0_A_CLK 57 | ||
75 | #define AFAB_SFAB_M1_A_CLK 58 | ||
76 | #define SFAB_SATA_S_H_CLK 59 | ||
77 | #define DFAB_CLK_SRC 60 | ||
78 | #define DFAB_CLK 61 | ||
79 | #define SFAB_DFAB_M_A_CLK 62 | ||
80 | #define DFAB_SFAB_M_A_CLK 63 | ||
81 | #define DFAB_SWAY0_H_CLK 64 | ||
82 | #define DFAB_SWAY1_H_CLK 65 | ||
83 | #define DFAB_ARB0_H_CLK 66 | ||
84 | #define DFAB_ARB1_H_CLK 67 | ||
85 | #define PPSS_H_CLK 68 | ||
86 | #define PPSS_PROC_CLK 69 | ||
87 | #define PPSS_TIMER0_CLK 70 | ||
88 | #define PPSS_TIMER1_CLK 71 | ||
89 | #define PMEM_A_CLK 72 | ||
90 | #define DMA_BAM_H_CLK 73 | ||
91 | #define SIC_H_CLK 74 | ||
92 | #define SPS_TIC_H_CLK 75 | ||
93 | #define SLIMBUS_H_CLK 76 | ||
94 | #define SLIMBUS_XO_SRC_CLK 77 | ||
95 | #define CFPB_2X_CLK_SRC 78 | ||
96 | #define CFPB_CLK 79 | ||
97 | #define CFPB0_H_CLK 80 | ||
98 | #define CFPB1_H_CLK 81 | ||
99 | #define CFPB2_H_CLK 82 | ||
100 | #define SFAB_CFPB_M_H_CLK 83 | ||
101 | #define CFPB_MASTER_H_CLK 84 | ||
102 | #define SFAB_CFPB_S_HCLK 85 | ||
103 | #define CFPB_SPLITTER_H_CLK 86 | ||
104 | #define TSIF_H_CLK 87 | ||
105 | #define TSIF_INACTIVITY_TIMERS_CLK 88 | ||
106 | #define TSIF_REF_SRC 89 | ||
107 | #define TSIF_REF_CLK 90 | ||
108 | #define CE1_H_CLK 91 | ||
109 | #define CE1_CORE_CLK 92 | ||
110 | #define CE1_SLEEP_CLK 93 | ||
111 | #define CE2_H_CLK 94 | ||
112 | #define CE2_CORE_CLK 95 | ||
113 | #define CE2_SLEEP_CLK 96 | ||
114 | #define SFPB_H_CLK_SRC 97 | ||
115 | #define SFPB_H_CLK 98 | ||
116 | #define SFAB_SFPB_M_H_CLK 99 | ||
117 | #define SFAB_SFPB_S_H_CLK 100 | ||
118 | #define RPM_PROC_CLK 101 | ||
119 | #define RPM_BUS_H_CLK 102 | ||
120 | #define RPM_SLEEP_CLK 103 | ||
121 | #define RPM_TIMER_CLK 104 | ||
122 | #define RPM_MSG_RAM_H_CLK 105 | ||
123 | #define PMIC_ARB0_H_CLK 106 | ||
124 | #define PMIC_ARB1_H_CLK 107 | ||
125 | #define PMIC_SSBI2_SRC 108 | ||
126 | #define PMIC_SSBI2_CLK 109 | ||
127 | #define SDC1_H_CLK 110 | ||
128 | #define SDC2_H_CLK 111 | ||
129 | #define SDC3_H_CLK 112 | ||
130 | #define SDC4_H_CLK 113 | ||
131 | #define SDC5_H_CLK 114 | ||
132 | #define SDC1_SRC 115 | ||
133 | #define SDC2_SRC 116 | ||
134 | #define SDC3_SRC 117 | ||
135 | #define SDC4_SRC 118 | ||
136 | #define SDC5_SRC 119 | ||
137 | #define SDC1_CLK 120 | ||
138 | #define SDC2_CLK 121 | ||
139 | #define SDC3_CLK 122 | ||
140 | #define SDC4_CLK 123 | ||
141 | #define SDC5_CLK 124 | ||
142 | #define DFAB_A2_H_CLK 125 | ||
143 | #define USB_HS1_H_CLK 126 | ||
144 | #define USB_HS1_XCVR_SRC 127 | ||
145 | #define USB_HS1_XCVR_CLK 128 | ||
146 | #define USB_HSIC_H_CLK 129 | ||
147 | #define USB_HSIC_XCVR_FS_SRC 130 | ||
148 | #define USB_HSIC_XCVR_FS_CLK 131 | ||
149 | #define USB_HSIC_SYSTEM_CLK_SRC 132 | ||
150 | #define USB_HSIC_SYSTEM_CLK 133 | ||
151 | #define CFPB0_C0_H_CLK 134 | ||
152 | #define CFPB0_C1_H_CLK 135 | ||
153 | #define CFPB0_D0_H_CLK 136 | ||
154 | #define CFPB0_D1_H_CLK 137 | ||
155 | #define USB_FS1_H_CLK 138 | ||
156 | #define USB_FS1_XCVR_FS_SRC 139 | ||
157 | #define USB_FS1_XCVR_FS_CLK 140 | ||
158 | #define USB_FS1_SYSTEM_CLK 141 | ||
159 | #define USB_FS2_H_CLK 142 | ||
160 | #define USB_FS2_XCVR_FS_SRC 143 | ||
161 | #define USB_FS2_XCVR_FS_CLK 144 | ||
162 | #define USB_FS2_SYSTEM_CLK 145 | ||
163 | #define GSBI_COMMON_SIM_SRC 146 | ||
164 | #define GSBI1_H_CLK 147 | ||
165 | #define GSBI2_H_CLK 148 | ||
166 | #define GSBI3_H_CLK 149 | ||
167 | #define GSBI4_H_CLK 150 | ||
168 | #define GSBI5_H_CLK 151 | ||
169 | #define GSBI6_H_CLK 152 | ||
170 | #define GSBI7_H_CLK 153 | ||
171 | #define GSBI8_H_CLK 154 | ||
172 | #define GSBI9_H_CLK 155 | ||
173 | #define GSBI10_H_CLK 156 | ||
174 | #define GSBI11_H_CLK 157 | ||
175 | #define GSBI12_H_CLK 158 | ||
176 | #define GSBI1_UART_SRC 159 | ||
177 | #define GSBI1_UART_CLK 160 | ||
178 | #define GSBI2_UART_SRC 161 | ||
179 | #define GSBI2_UART_CLK 162 | ||
180 | #define GSBI3_UART_SRC 163 | ||
181 | #define GSBI3_UART_CLK 164 | ||
182 | #define GSBI4_UART_SRC 165 | ||
183 | #define GSBI4_UART_CLK 166 | ||
184 | #define GSBI5_UART_SRC 167 | ||
185 | #define GSBI5_UART_CLK 168 | ||
186 | #define GSBI6_UART_SRC 169 | ||
187 | #define GSBI6_UART_CLK 170 | ||
188 | #define GSBI7_UART_SRC 171 | ||
189 | #define GSBI7_UART_CLK 172 | ||
190 | #define GSBI8_UART_SRC 173 | ||
191 | #define GSBI8_UART_CLK 174 | ||
192 | #define GSBI9_UART_SRC 175 | ||
193 | #define GSBI9_UART_CLK 176 | ||
194 | #define GSBI10_UART_SRC 177 | ||
195 | #define GSBI10_UART_CLK 178 | ||
196 | #define GSBI11_UART_SRC 179 | ||
197 | #define GSBI11_UART_CLK 180 | ||
198 | #define GSBI12_UART_SRC 181 | ||
199 | #define GSBI12_UART_CLK 182 | ||
200 | #define GSBI1_QUP_SRC 183 | ||
201 | #define GSBI1_QUP_CLK 184 | ||
202 | #define GSBI2_QUP_SRC 185 | ||
203 | #define GSBI2_QUP_CLK 186 | ||
204 | #define GSBI3_QUP_SRC 187 | ||
205 | #define GSBI3_QUP_CLK 188 | ||
206 | #define GSBI4_QUP_SRC 189 | ||
207 | #define GSBI4_QUP_CLK 190 | ||
208 | #define GSBI5_QUP_SRC 191 | ||
209 | #define GSBI5_QUP_CLK 192 | ||
210 | #define GSBI6_QUP_SRC 193 | ||
211 | #define GSBI6_QUP_CLK 194 | ||
212 | #define GSBI7_QUP_SRC 195 | ||
213 | #define GSBI7_QUP_CLK 196 | ||
214 | #define GSBI8_QUP_SRC 197 | ||
215 | #define GSBI8_QUP_CLK 198 | ||
216 | #define GSBI9_QUP_SRC 199 | ||
217 | #define GSBI9_QUP_CLK 200 | ||
218 | #define GSBI10_QUP_SRC 201 | ||
219 | #define GSBI10_QUP_CLK 202 | ||
220 | #define GSBI11_QUP_SRC 203 | ||
221 | #define GSBI11_QUP_CLK 204 | ||
222 | #define GSBI12_QUP_SRC 205 | ||
223 | #define GSBI12_QUP_CLK 206 | ||
224 | #define GSBI1_SIM_CLK 207 | ||
225 | #define GSBI2_SIM_CLK 208 | ||
226 | #define GSBI3_SIM_CLK 209 | ||
227 | #define GSBI4_SIM_CLK 210 | ||
228 | #define GSBI5_SIM_CLK 211 | ||
229 | #define GSBI6_SIM_CLK 212 | ||
230 | #define GSBI7_SIM_CLK 213 | ||
231 | #define GSBI8_SIM_CLK 214 | ||
232 | #define GSBI9_SIM_CLK 215 | ||
233 | #define GSBI10_SIM_CLK 216 | ||
234 | #define GSBI11_SIM_CLK 217 | ||
235 | #define GSBI12_SIM_CLK 218 | ||
236 | #define USB_HSIC_HSIC_CLK_SRC 219 | ||
237 | #define USB_HSIC_HSIC_CLK 220 | ||
238 | #define USB_HSIC_HSIO_CAL_CLK 221 | ||
239 | #define SPDM_CFG_H_CLK 222 | ||
240 | #define SPDM_MSTR_H_CLK 223 | ||
241 | #define SPDM_FF_CLK_SRC 224 | ||
242 | #define SPDM_FF_CLK 225 | ||
243 | #define SEC_CTRL_CLK 226 | ||
244 | #define SEC_CTRL_ACC_CLK_SRC 227 | ||
245 | #define SEC_CTRL_ACC_CLK 228 | ||
246 | #define TLMM_H_CLK 229 | ||
247 | #define TLMM_CLK 230 | ||
248 | #define SFAB_MSS_S_H_CLK 231 | ||
249 | #define MSS_SLP_CLK 232 | ||
250 | #define MSS_Q6SW_JTAG_CLK 233 | ||
251 | #define MSS_Q6FW_JTAG_CLK 234 | ||
252 | #define MSS_S_H_CLK 235 | ||
253 | #define MSS_CXO_SRC_CLK 236 | ||
254 | #define SATA_H_CLK 237 | ||
255 | #define SATA_SRC_CLK 238 | ||
256 | #define SATA_RXOOB_CLK 239 | ||
257 | #define SATA_PMALIVE_CLK 240 | ||
258 | #define SATA_PHY_REF_CLK 241 | ||
259 | #define TSSC_CLK_SRC 242 | ||
260 | #define TSSC_CLK 243 | ||
261 | #define PDM_SRC 244 | ||
262 | #define PDM_CLK 245 | ||
263 | #define GP0_SRC 246 | ||
264 | #define GP0_CLK 247 | ||
265 | #define GP1_SRC 248 | ||
266 | #define GP1_CLK 249 | ||
267 | #define GP2_SRC 250 | ||
268 | #define GP2_CLK 251 | ||
269 | #define MPM_CLK 252 | ||
270 | #define EBI1_CLK_SRC 253 | ||
271 | #define EBI1_CH0_CLK 254 | ||
272 | #define EBI1_CH1_CLK 255 | ||
273 | #define EBI1_2X_CLK 256 | ||
274 | #define EBI1_CH0_DQ_CLK 257 | ||
275 | #define EBI1_CH1_DQ_CLK 258 | ||
276 | #define EBI1_CH0_CA_CLK 259 | ||
277 | #define EBI1_CH1_CA_CLK 260 | ||
278 | #define EBI1_XO_CLK 261 | ||
279 | #define SFAB_SMPSS_S_H_CLK 262 | ||
280 | #define PRNG_SRC 263 | ||
281 | #define PRNG_CLK 264 | ||
282 | #define PXO_SRC 265 | ||
283 | #define LPASS_CXO_CLK 266 | ||
284 | #define LPASS_PXO_CLK 267 | ||
285 | #define SPDM_CY_PORT0_CLK 268 | ||
286 | #define SPDM_CY_PORT1_CLK 269 | ||
287 | #define SPDM_CY_PORT2_CLK 270 | ||
288 | #define SPDM_CY_PORT3_CLK 271 | ||
289 | #define SPDM_CY_PORT4_CLK 272 | ||
290 | #define SPDM_CY_PORT5_CLK 273 | ||
291 | #define SPDM_CY_PORT6_CLK 274 | ||
292 | #define SPDM_CY_PORT7_CLK 275 | ||
293 | #define PLL0 276 | ||
294 | #define PLL0_VOTE 277 | ||
295 | #define PLL3 278 | ||
296 | #define PLL3_VOTE 279 | ||
297 | #define PLL4_VOTE 280 | ||
298 | #define PLL5 281 | ||
299 | #define PLL5_VOTE 282 | ||
300 | #define PLL6 283 | ||
301 | #define PLL6_VOTE 284 | ||
302 | #define PLL7_VOTE 285 | ||
303 | #define PLL8 286 | ||
304 | #define PLL8_VOTE 287 | ||
305 | #define PLL9 288 | ||
306 | #define PLL10 289 | ||
307 | #define PLL11 290 | ||
308 | #define PLL12 291 | ||
309 | #define PLL13 292 | ||
310 | #define PLL14 293 | ||
311 | #define PLL14_VOTE 294 | ||
312 | |||
313 | #endif | ||