1 files changed, 220 insertions, 0 deletions
diff --git a/include/drm/nouveau_drm.h b/include/drm/nouveau_drm.h
new file mode 100644
index 000000000000..1e67c441ea82
--- /dev/null
+++ b/include/drm/nouveau_drm.h
@@ -0,0 +1,220 @@
+/*
+ * Copyright 2005 Stephane Marchesin.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef __NOUVEAU_DRM_H__
+#define __NOUVEAU_DRM_H__
+#define NOUVEAU_DRM_HEADER_PATCHLEVEL 15
+struct drm_nouveau_channel_alloc {
+        uint32_t     fb_ctxdma_handle;
+        uint32_t     tt_ctxdma_handle;
+        int          channel;
+        /* Notifier memory */
+        uint32_t     notifier_handle;
+        /* DRM-enforced subchannel assignments */
+        struct {
+                uint32_t handle;
+                uint32_t grclass;
+        } subchan[8];
+        uint32_t nr_subchan;
+};
+struct drm_nouveau_channel_free {
+        int channel;
+};
+struct drm_nouveau_grobj_alloc {
+        int      channel;
+        uint32_t handle;
+        int      class;
+};
+struct drm_nouveau_notifierobj_alloc {
+        uint32_t channel;
+        uint32_t handle;
+        uint32_t size;
+        uint32_t offset;
+};
+struct drm_nouveau_gpuobj_free {
+        int      channel;
+        uint32_t handle;
+};
+/* FIXME : maybe unify {GET,SET}PARAMs */
+#define NOUVEAU_GETPARAM_PCI_VENDOR      3
+#define NOUVEAU_GETPARAM_PCI_DEVICE      4
+#define NOUVEAU_GETPARAM_BUS_TYPE        5
+#define NOUVEAU_GETPARAM_FB_PHYSICAL     6
+#define NOUVEAU_GETPARAM_AGP_PHYSICAL    7
+#define NOUVEAU_GETPARAM_FB_SIZE         8
+#define NOUVEAU_GETPARAM_AGP_SIZE        9
+#define NOUVEAU_GETPARAM_PCI_PHYSICAL    10
+#define NOUVEAU_GETPARAM_CHIPSET_ID      11
+#define NOUVEAU_GETPARAM_VM_VRAM_BASE    12
+struct drm_nouveau_getparam {
+        uint64_t param;
+        uint64_t value;
+};
+struct drm_nouveau_setparam {
+        uint64_t param;
+        uint64_t value;
+};
+#define NOUVEAU_GEM_DOMAIN_CPU       (1 << 0)
+#define NOUVEAU_GEM_DOMAIN_VRAM      (1 << 1)
+#define NOUVEAU_GEM_DOMAIN_GART      (1 << 2)
+#define NOUVEAU_GEM_DOMAIN_MAPPABLE  (1 << 3)
+struct drm_nouveau_gem_info {
+        uint32_t handle;
+        uint32_t domain;
+        uint64_t size;
+        uint64_t offset;
+        uint64_t map_handle;
+        uint32_t tile_mode;
+        uint32_t tile_flags;
+};
+struct drm_nouveau_gem_new {
+        struct drm_nouveau_gem_info info;
+        uint32_t channel_hint;
+        uint32_t align;
+};
+struct drm_nouveau_gem_pushbuf_bo {
+        uint64_t user_priv;
+        uint32_t handle;
+        uint32_t read_domains;
+        uint32_t write_domains;
+        uint32_t valid_domains;
+        uint32_t presumed_ok;
+        uint32_t presumed_domain;
+        uint64_t presumed_offset;
+};
+#define NOUVEAU_GEM_RELOC_LOW  (1 << 0)
+#define NOUVEAU_GEM_RELOC_HIGH (1 << 1)
+#define NOUVEAU_GEM_RELOC_OR   (1 << 2)
+struct drm_nouveau_gem_pushbuf_reloc {
+        uint32_t bo_index;
+        uint32_t reloc_index;
+        uint32_t flags;
+        uint32_t data;
+        uint32_t vor;
+        uint32_t tor;
+};
+#define NOUVEAU_GEM_MAX_BUFFERS 1024
+#define NOUVEAU_GEM_MAX_RELOCS 1024
+struct drm_nouveau_gem_pushbuf {
+        uint32_t channel;
+        uint32_t nr_dwords;
+        uint32_t nr_buffers;
+        uint32_t nr_relocs;
+        uint64_t dwords;
+        uint64_t buffers;
+        uint64_t relocs;
+};
+struct drm_nouveau_gem_pushbuf_call {
+        uint32_t channel;
+        uint32_t handle;
+        uint32_t offset;
+        uint32_t nr_buffers;
+        uint32_t nr_relocs;
+        uint32_t nr_dwords;
+        uint64_t buffers;
+        uint64_t relocs;
+        uint32_t suffix0;
+        uint32_t suffix1;
+        /* below only accessed for CALL2 */
+        uint64_t vram_available;
+        uint64_t gart_available;
+};
+struct drm_nouveau_gem_pin {
+        uint32_t handle;
+        uint32_t domain;
+        uint64_t offset;
+};
+struct drm_nouveau_gem_unpin {
+        uint32_t handle;
+};
+#define NOUVEAU_GEM_CPU_PREP_NOWAIT                                  0x00000001
+#define NOUVEAU_GEM_CPU_PREP_NOBLOCK                                 0x00000002
+#define NOUVEAU_GEM_CPU_PREP_WRITE                                   0x00000004
+struct drm_nouveau_gem_cpu_prep {
+        uint32_t handle;
+        uint32_t flags;
+};
+struct drm_nouveau_gem_cpu_fini {
+        uint32_t handle;
+};
+struct drm_nouveau_gem_tile {
+        uint32_t handle;
+        uint32_t offset;
+        uint32_t size;
+        uint32_t tile_mode;
+        uint32_t tile_flags;
+};
+enum nouveau_bus_type {
+        NV_AGP     = 0,
+        NV_PCI     = 1,
+        NV_PCIE    = 2,
+};
+struct drm_nouveau_sarea {
+};
+#define DRM_NOUVEAU_CARD_INIT          0x00
+#define DRM_NOUVEAU_GETPARAM           0x01
+#define DRM_NOUVEAU_SETPARAM           0x02
+#define DRM_NOUVEAU_CHANNEL_ALLOC      0x03
+#define DRM_NOUVEAU_CHANNEL_FREE       0x04
+#define DRM_NOUVEAU_GROBJ_ALLOC        0x05
+#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC  0x06
+#define DRM_NOUVEAU_GPUOBJ_FREE        0x07
+#define DRM_NOUVEAU_GEM_NEW            0x40
+#define DRM_NOUVEAU_GEM_PUSHBUF        0x41
+#define DRM_NOUVEAU_GEM_PUSHBUF_CALL   0x42
+#define DRM_NOUVEAU_GEM_PIN            0x43 /* !KMS only */
+#define DRM_NOUVEAU_GEM_UNPIN          0x44 /* !KMS only */
+#define DRM_NOUVEAU_GEM_CPU_PREP       0x45
+#define DRM_NOUVEAU_GEM_CPU_FINI       0x46
+#define DRM_NOUVEAU_GEM_INFO           0x47
+#define DRM_NOUVEAU_GEM_PUSHBUF_CALL2  0x48
+#endif /* __NOUVEAU_DRM_H__ */

diff --git a/include/drm/nouveau_drm.h b/include/drm/nouveau_drm.h new file mode 100644 index 000000000000..1e67c441ea82 --- /dev/null +++ b/include/drm/nouveau_drm.h
@@ -0,0 +1,220 @@
	1	/*
	2	* Copyright 2005 Stephane Marchesin.
	3	* All Rights Reserved.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining a
	6	* copy of this software and associated documentation files (the "Software"),
	7	* to deal in the Software without restriction, including without limitation
	8	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	9	* and/or sell copies of the Software, and to permit persons to whom the
	10	* Software is furnished to do so, subject to the following conditions:
	11	*
	12	* The above copyright notice and this permission notice (including the next
	13	* paragraph) shall be included in all copies or substantial portions of the
	14	* Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
	20	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	21	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	22	* OTHER DEALINGS IN THE SOFTWARE.
	23	*/
	24
	25	#ifndef __NOUVEAU_DRM_H__
	26	#define __NOUVEAU_DRM_H__
	27
	28	#define NOUVEAU_DRM_HEADER_PATCHLEVEL 15
	29
	30	struct drm_nouveau_channel_alloc {
	31	uint32_t fb_ctxdma_handle;
	32	uint32_t tt_ctxdma_handle;
	33
	34	int channel;
	35
	36	/* Notifier memory */
	37	uint32_t notifier_handle;
	38
	39	/* DRM-enforced subchannel assignments */
	40	struct {
	41	uint32_t handle;
	42	uint32_t grclass;
	43	} subchan[8];
	44	uint32_t nr_subchan;
	45	};
	46
	47	struct drm_nouveau_channel_free {
	48	int channel;
	49	};
	50
	51	struct drm_nouveau_grobj_alloc {
	52	int channel;
	53	uint32_t handle;
	54	int class;
	55	};
	56
	57	struct drm_nouveau_notifierobj_alloc {
	58	uint32_t channel;
	59	uint32_t handle;
	60	uint32_t size;
	61	uint32_t offset;
	62	};
	63
	64	struct drm_nouveau_gpuobj_free {
	65	int channel;
	66	uint32_t handle;
	67	};
	68
	69	/* FIXME : maybe unify {GET,SET}PARAMs */
	70	#define NOUVEAU_GETPARAM_PCI_VENDOR 3
	71	#define NOUVEAU_GETPARAM_PCI_DEVICE 4
	72	#define NOUVEAU_GETPARAM_BUS_TYPE 5
	73	#define NOUVEAU_GETPARAM_FB_PHYSICAL 6
	74	#define NOUVEAU_GETPARAM_AGP_PHYSICAL 7
	75	#define NOUVEAU_GETPARAM_FB_SIZE 8
	76	#define NOUVEAU_GETPARAM_AGP_SIZE 9
	77	#define NOUVEAU_GETPARAM_PCI_PHYSICAL 10
	78	#define NOUVEAU_GETPARAM_CHIPSET_ID 11
	79	#define NOUVEAU_GETPARAM_VM_VRAM_BASE 12
	80	struct drm_nouveau_getparam {
	81	uint64_t param;
	82	uint64_t value;
	83	};
	84
	85	struct drm_nouveau_setparam {
	86	uint64_t param;
	87	uint64_t value;
	88	};
	89
	90	#define NOUVEAU_GEM_DOMAIN_CPU (1 << 0)
	91	#define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1)
	92	#define NOUVEAU_GEM_DOMAIN_GART (1 << 2)
	93	#define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3)
	94
	95	struct drm_nouveau_gem_info {
	96	uint32_t handle;
	97	uint32_t domain;
	98	uint64_t size;
	99	uint64_t offset;
	100	uint64_t map_handle;
	101	uint32_t tile_mode;
	102	uint32_t tile_flags;
	103	};
	104
	105	struct drm_nouveau_gem_new {
	106	struct drm_nouveau_gem_info info;
	107	uint32_t channel_hint;
	108	uint32_t align;
	109	};
	110
	111	struct drm_nouveau_gem_pushbuf_bo {
	112	uint64_t user_priv;
	113	uint32_t handle;
	114	uint32_t read_domains;
	115	uint32_t write_domains;
	116	uint32_t valid_domains;
	117	uint32_t presumed_ok;
	118	uint32_t presumed_domain;
	119	uint64_t presumed_offset;
	120	};
	121
	122	#define NOUVEAU_GEM_RELOC_LOW (1 << 0)
	123	#define NOUVEAU_GEM_RELOC_HIGH (1 << 1)
	124	#define NOUVEAU_GEM_RELOC_OR (1 << 2)
	125	struct drm_nouveau_gem_pushbuf_reloc {
	126	uint32_t bo_index;
	127	uint32_t reloc_index;
	128	uint32_t flags;
	129	uint32_t data;
	130	uint32_t vor;
	131	uint32_t tor;
	132	};
	133
	134	#define NOUVEAU_GEM_MAX_BUFFERS 1024
	135	#define NOUVEAU_GEM_MAX_RELOCS 1024
	136
	137	struct drm_nouveau_gem_pushbuf {
	138	uint32_t channel;
	139	uint32_t nr_dwords;
	140	uint32_t nr_buffers;
	141	uint32_t nr_relocs;
	142	uint64_t dwords;
	143	uint64_t buffers;
	144	uint64_t relocs;
	145	};
	146
	147	struct drm_nouveau_gem_pushbuf_call {
	148	uint32_t channel;
	149	uint32_t handle;
	150	uint32_t offset;
	151	uint32_t nr_buffers;
	152	uint32_t nr_relocs;
	153	uint32_t nr_dwords;
	154	uint64_t buffers;
	155	uint64_t relocs;
	156	uint32_t suffix0;
	157	uint32_t suffix1;
	158	/* below only accessed for CALL2 */
	159	uint64_t vram_available;
	160	uint64_t gart_available;
	161	};
	162
	163	struct drm_nouveau_gem_pin {
	164	uint32_t handle;
	165	uint32_t domain;
	166	uint64_t offset;
	167	};
	168
	169	struct drm_nouveau_gem_unpin {
	170	uint32_t handle;
	171	};
	172
	173	#define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001
	174	#define NOUVEAU_GEM_CPU_PREP_NOBLOCK 0x00000002
	175	#define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004
	176	struct drm_nouveau_gem_cpu_prep {
	177	uint32_t handle;
	178	uint32_t flags;
	179	};
	180
	181	struct drm_nouveau_gem_cpu_fini {
	182	uint32_t handle;
	183	};
	184
	185	struct drm_nouveau_gem_tile {
	186	uint32_t handle;
	187	uint32_t offset;
	188	uint32_t size;
	189	uint32_t tile_mode;
	190	uint32_t tile_flags;
	191	};
	192
	193	enum nouveau_bus_type {
	194	NV_AGP = 0,
	195	NV_PCI = 1,
	196	NV_PCIE = 2,
	197	};
	198
	199	struct drm_nouveau_sarea {
	200	};
	201
	202	#define DRM_NOUVEAU_CARD_INIT 0x00
	203	#define DRM_NOUVEAU_GETPARAM 0x01
	204	#define DRM_NOUVEAU_SETPARAM 0x02
	205	#define DRM_NOUVEAU_CHANNEL_ALLOC 0x03
	206	#define DRM_NOUVEAU_CHANNEL_FREE 0x04
	207	#define DRM_NOUVEAU_GROBJ_ALLOC 0x05
	208	#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x06
	209	#define DRM_NOUVEAU_GPUOBJ_FREE 0x07
	210	#define DRM_NOUVEAU_GEM_NEW 0x40
	211	#define DRM_NOUVEAU_GEM_PUSHBUF 0x41
	212	#define DRM_NOUVEAU_GEM_PUSHBUF_CALL 0x42
	213	#define DRM_NOUVEAU_GEM_PIN 0x43 /* !KMS only */
	214	#define DRM_NOUVEAU_GEM_UNPIN 0x44 /* !KMS only */
	215	#define DRM_NOUVEAU_GEM_CPU_PREP 0x45
	216	#define DRM_NOUVEAU_GEM_CPU_FINI 0x46
	217	#define DRM_NOUVEAU_GEM_INFO 0x47
	218	#define DRM_NOUVEAU_GEM_PUSHBUF_CALL2 0x48
	219
	220	#endif /* __NOUVEAU_DRM_H__ */