1 files changed, 129 insertions, 3 deletions

diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index 7e0cb1da92e6..b64a8d7cdf6d 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -27,11 +27,11 @@
 #ifndef _I915_DRM_H_
 #define _I915_DRM_H_
 
+#include "drm.h"
+
 /* Please note that modifications to all structs defined here are
  * subject to backwards-compatibility constraints.
  */
-#include <linux/types.h>
-#include "drm.h"
 
 /* Each region is a minimum of 16k, and there are at most 255 of them.
  */
@@ -186,6 +186,9 @@ typedef struct _drm_i915_sarea {
 #define DRM_I915_GEM_MMAP_GTT   0x24
 #define DRM_I915_GET_PIPE_FROM_CRTC_ID  0x25
 #define DRM_I915_GEM_MADVISE    0x26
+#define DRM_I915_OVERLAY_PUT_IMAGE      0x27
+#define DRM_I915_OVERLAY_ATTRS  0x28
+#define DRM_I915_GEM_EXECBUFFER2        0x29
 
 #define DRM_IOCTL_I915_INIT             DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
 #define DRM_IOCTL_I915_FLUSH            DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
@@ -205,6 +208,7 @@ typedef struct _drm_i915_sarea {
 #define DRM_IOCTL_I915_VBLANK_SWAP      DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
 #define DRM_IOCTL_I915_GEM_INIT         DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
 #define DRM_IOCTL_I915_GEM_EXECBUFFER   DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
+#define DRM_IOCTL_I915_GEM_EXECBUFFER2  DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
 #define DRM_IOCTL_I915_GEM_PIN          DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
 #define DRM_IOCTL_I915_GEM_UNPIN        DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
 #define DRM_IOCTL_I915_GEM_BUSY         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
@@ -221,8 +225,10 @@ typedef struct _drm_i915_sarea {
 #define DRM_IOCTL_I915_GEM_SET_TILING   DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
 #define DRM_IOCTL_I915_GEM_GET_TILING   DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
 #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR  (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
-#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_intel_get_pipe_from_crtc_id)
+#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
 #define DRM_IOCTL_I915_GEM_MADVISE      DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
+#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE        DRM_IOW(DRM_COMMAND_BASE + DRM_IOCTL_I915_OVERLAY_ATTRS, struct drm_intel_overlay_put_image)
+#define DRM_IOCTL_I915_OVERLAY_ATTRS    DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
 
 /* Allow drivers to submit batchbuffers directly to hardware, relying
  * on the security mechanisms provided by hardware.
@@ -266,6 +272,9 @@ typedef struct drm_i915_irq_wait {
 #define I915_PARAM_CHIPSET_ID            4
 #define I915_PARAM_HAS_GEM               5
 #define I915_PARAM_NUM_FENCES_AVAIL      6
+#define I915_PARAM_HAS_OVERLAY           7
+#define I915_PARAM_HAS_PAGEFLIPPING      8
+#define I915_PARAM_HAS_EXECBUF2          9
 
 typedef struct drm_i915_getparam {
         int param;
@@ -561,6 +570,57 @@ struct drm_i915_gem_execbuffer {
         __u64 cliprects_ptr;
 };
 
+struct drm_i915_gem_exec_object2 {
+        /**
+         * User's handle for a buffer to be bound into the GTT for this
+         * operation.
+         */
+        __u32 handle;
+
+        /** Number of relocations to be performed on this buffer */
+        __u32 relocation_count;
+        /**
+         * Pointer to array of struct drm_i915_gem_relocation_entry containing
+         * the relocations to be performed in this buffer.
+         */
+        __u64 relocs_ptr;
+
+        /** Required alignment in graphics aperture */
+        __u64 alignment;
+
+        /**
+         * Returned value of the updated offset of the object, for future
+         * presumed_offset writes.
+         */
+        __u64 offset;
+
+#define EXEC_OBJECT_NEEDS_FENCE (1<<0)
+        __u64 flags;
+        __u64 rsvd1;
+        __u64 rsvd2;
+};
+
+struct drm_i915_gem_execbuffer2 {
+        /**
+         * List of gem_exec_object2 structs
+         */
+        __u64 buffers_ptr;
+        __u32 buffer_count;
+
+        /** Offset in the batchbuffer to start execution from. */
+        __u32 batch_start_offset;
+        /** Bytes used in batchbuffer from batch_start_offset */
+        __u32 batch_len;
+        __u32 DR1;
+        __u32 DR4;
+        __u32 num_cliprects;
+        /** This is a struct drm_clip_rect *cliprects */
+        __u64 cliprects_ptr;
+        __u64 flags; /* currently unused */
+        __u64 rsvd1;
+        __u64 rsvd2;
+};
+
 struct drm_i915_gem_pin {
         /** Handle of the buffer to be pinned. */
         __u32 handle;
@@ -686,4 +746,70 @@ struct drm_i915_gem_madvise {
         __u32 retained;
 };
 
+/* flags */
+#define I915_OVERLAY_TYPE_MASK          0xff
+#define I915_OVERLAY_YUV_PLANAR         0x01
+#define I915_OVERLAY_YUV_PACKED         0x02
+#define I915_OVERLAY_RGB                0x03
+
+#define I915_OVERLAY_DEPTH_MASK         0xff00
+#define I915_OVERLAY_RGB24              0x1000
+#define I915_OVERLAY_RGB16              0x2000
+#define I915_OVERLAY_RGB15              0x3000
+#define I915_OVERLAY_YUV422             0x0100
+#define I915_OVERLAY_YUV411             0x0200
+#define I915_OVERLAY_YUV420             0x0300
+#define I915_OVERLAY_YUV410             0x0400
+
+#define I915_OVERLAY_SWAP_MASK          0xff0000
+#define I915_OVERLAY_NO_SWAP            0x000000
+#define I915_OVERLAY_UV_SWAP            0x010000
+#define I915_OVERLAY_Y_SWAP             0x020000
+#define I915_OVERLAY_Y_AND_UV_SWAP      0x030000
+
+#define I915_OVERLAY_FLAGS_MASK         0xff000000
+#define I915_OVERLAY_ENABLE             0x01000000
+
+struct drm_intel_overlay_put_image {
+        /* various flags and src format description */
+        __u32 flags;
+        /* source picture description */
+        __u32 bo_handle;
+        /* stride values and offsets are in bytes, buffer relative */
+        __u16 stride_Y; /* stride for packed formats */
+        __u16 stride_UV;
+        __u32 offset_Y; /* offset for packet formats */
+        __u32 offset_U;
+        __u32 offset_V;
+        /* in pixels */
+        __u16 src_width;
+        __u16 src_height;
+        /* to compensate the scaling factors for partially covered surfaces */
+        __u16 src_scan_width;
+        __u16 src_scan_height;
+        /* output crtc description */
+        __u32 crtc_id;
+        __u16 dst_x;
+        __u16 dst_y;
+        __u16 dst_width;
+        __u16 dst_height;
+};
+
+/* flags */
+#define I915_OVERLAY_UPDATE_ATTRS       (1<<0)
+#define I915_OVERLAY_UPDATE_GAMMA       (1<<1)
+struct drm_intel_overlay_attrs {
+        __u32 flags;
+        __u32 color_key;
+        __s32 brightness;
+        __u32 contrast;
+        __u32 saturation;
+        __u32 gamma0;
+        __u32 gamma1;
+        __u32 gamma2;
+        __u32 gamma3;
+        __u32 gamma4;
+        __u32 gamma5;
+};
+
 #endif                          /* _I915_DRM_H_ */