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-rw-r--r--include/asm-xtensa/pgtable.h32
1 files changed, 20 insertions, 12 deletions
diff --git a/include/asm-xtensa/pgtable.h b/include/asm-xtensa/pgtable.h
index 667a6c46b5a1..c0fcc1c9660c 100644
--- a/include/asm-xtensa/pgtable.h
+++ b/include/asm-xtensa/pgtable.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/include/asm-xtensa/pgtable.h 2 * include/asm-xtensa/pgtable.h
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as 5 * it under the terms of the GNU General Public License version 2 as
@@ -60,16 +60,20 @@
60#define FIRST_USER_ADDRESS 0 60#define FIRST_USER_ADDRESS 0
61#define FIRST_USER_PGD_NR (FIRST_USER_ADDRESS >> PGDIR_SHIFT) 61#define FIRST_USER_PGD_NR (FIRST_USER_ADDRESS >> PGDIR_SHIFT)
62 62
63/* virtual memory area. We keep a distance to other memory regions to be 63/*
64 * Virtual memory area. We keep a distance to other memory regions to be
64 * on the safe side. We also use this area for cache aliasing. 65 * on the safe side. We also use this area for cache aliasing.
65 */ 66 */
66 67
67// FIXME: virtual memory area must be configuration-dependent
68
69#define VMALLOC_START 0xC0000000 68#define VMALLOC_START 0xC0000000
70#define VMALLOC_END 0xC7FF0000 69#define VMALLOC_END 0xC6FEFFFF
70#define TLBTEMP_BASE_1 0xC6FF0000
71#define TLBTEMP_BASE_2 0xC6FF8000
72#define MODULE_START 0xC7000000
73#define MODULE_END 0xC7FFFFFF
71 74
72/* Xtensa Linux config PTE layout (when present): 75/*
76 * Xtensa Linux config PTE layout (when present):
73 * 31-12: PPN 77 * 31-12: PPN
74 * 11-6: Software 78 * 11-6: Software
75 * 5-4: RING 79 * 5-4: RING
@@ -126,12 +130,13 @@
126#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITABLE) 130#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITABLE)
127#define PAGE_SHARED_EXEC \ 131#define PAGE_SHARED_EXEC \
128 __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITABLE | _PAGE_HW_EXEC) 132 __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITABLE | _PAGE_HW_EXEC)
129#define PAGE_KERNEL __pgprot(_PAGE_PRESENT) 133#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_HW_WRITE)
134#define PAGE_KERNEL_EXEC __pgprot(_PAGE_PRESENT|_PAGE_HW_WRITE|_PAGE_HW_EXEC)
130 135
131#if (DCACHE_WAY_SIZE > PAGE_SIZE) 136#if (DCACHE_WAY_SIZE > PAGE_SIZE)
132# define _PAGE_DIRECTORY (_PAGE_VALID | _PAGE_ACCESSED | _PAGE_HW_WRITE) 137# define _PAGE_DIRECTORY (_PAGE_VALID | _PAGE_ACCESSED)
133#else 138#else
134# define _PAGE_DIRECTORY (_PAGE_VALID|_PAGE_ACCESSED|_PAGE_HW_WRITE|_PAGE_CA_WB) 139# define _PAGE_DIRECTORY (_PAGE_VALID | _PAGE_ACCESSED | _PAGE_CA_WB)
135#endif 140#endif
136 141
137#else /* no mmu */ 142#else /* no mmu */
@@ -244,6 +249,10 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
244static inline void update_pte(pte_t *ptep, pte_t pteval) 249static inline void update_pte(pte_t *ptep, pte_t pteval)
245{ 250{
246 *ptep = pteval; 251 *ptep = pteval;
252#if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
253 __asm__ __volatile__ ("dhwb %0, 0" :: "a" (ptep));
254#endif
255
247} 256}
248 257
249struct mm_struct; 258struct mm_struct;
@@ -383,13 +392,12 @@ extern void update_mmu_cache(struct vm_area_struct * vma,
383 * remap a physical page `pfn' of size `size' with page protection `prot' 392 * remap a physical page `pfn' of size `size' with page protection `prot'
384 * into virtual address `from' 393 * into virtual address `from'
385 */ 394 */
395
386#define io_remap_pfn_range(vma,from,pfn,size,prot) \ 396#define io_remap_pfn_range(vma,from,pfn,size,prot) \
387 remap_pfn_range(vma, from, pfn, size, prot) 397 remap_pfn_range(vma, from, pfn, size, prot)
388 398
389 399
390/* No page table caches to init */ 400extern void pgtable_cache_init(void);
391
392#define pgtable_cache_init() do { } while (0)
393 401
394typedef pte_t *pte_addr_t; 402typedef pte_t *pte_addr_t;
395 403