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-rw-r--r--include/asm-x86/tlbflush_32.h7
1 files changed, 0 insertions, 7 deletions
diff --git a/include/asm-x86/tlbflush_32.h b/include/asm-x86/tlbflush_32.h
index a50fa6741486..2bd5b95e2048 100644
--- a/include/asm-x86/tlbflush_32.h
+++ b/include/asm-x86/tlbflush_32.h
@@ -78,7 +78,6 @@
78 * - flush_tlb_page(vma, vmaddr) flushes one page 78 * - flush_tlb_page(vma, vmaddr) flushes one page
79 * - flush_tlb_range(vma, start, end) flushes a range of pages 79 * - flush_tlb_range(vma, start, end) flushes a range of pages
80 * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages 80 * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
81 * - flush_tlb_pgtables(mm, start, end) flushes a range of page tables
82 * - flush_tlb_others(cpumask, mm, va) flushes a TLBs on other cpus 81 * - flush_tlb_others(cpumask, mm, va) flushes a TLBs on other cpus
83 * 82 *
84 * ..but the i386 has somewhat limited tlb flushing capabilities, 83 * ..but the i386 has somewhat limited tlb flushing capabilities,
@@ -166,10 +165,4 @@ static inline void flush_tlb_kernel_range(unsigned long start,
166 flush_tlb_all(); 165 flush_tlb_all();
167} 166}
168 167
169static inline void flush_tlb_pgtables(struct mm_struct *mm,
170 unsigned long start, unsigned long end)
171{
172 /* i386 does not keep any page table caches in TLB */
173}
174
175#endif /* _I386_TLBFLUSH_H */ 168#endif /* _I386_TLBFLUSH_H */