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-rw-r--r--include/asm-x86/processor_32.h87
1 files changed, 0 insertions, 87 deletions
diff --git a/include/asm-x86/processor_32.h b/include/asm-x86/processor_32.h
index b586902acd85..e7fc023cd810 100644
--- a/include/asm-x86/processor_32.h
+++ b/include/asm-x86/processor_32.h
@@ -120,33 +120,6 @@ extern void detect_ht(struct cpuinfo_x86 *c);
120static inline void detect_ht(struct cpuinfo_x86 *c) {} 120static inline void detect_ht(struct cpuinfo_x86 *c) {}
121#endif 121#endif
122 122
123
124/*
125 * Save the cr4 feature set we're using (ie
126 * Pentium 4MB enable and PPro Global page
127 * enable), so that any CPU's that boot up
128 * after us can get the correct flags.
129 */
130extern unsigned long mmu_cr4_features;
131
132static inline void set_in_cr4 (unsigned long mask)
133{
134 unsigned cr4;
135 mmu_cr4_features |= mask;
136 cr4 = read_cr4();
137 cr4 |= mask;
138 write_cr4(cr4);
139}
140
141static inline void clear_in_cr4 (unsigned long mask)
142{
143 unsigned cr4;
144 mmu_cr4_features &= ~mask;
145 cr4 = read_cr4();
146 cr4 &= ~mask;
147 write_cr4(cr4);
148}
149
150/* Stop speculative execution */ 123/* Stop speculative execution */
151static inline void sync_core(void) 124static inline void sync_core(void)
152{ 125{
@@ -482,57 +455,6 @@ static inline void native_load_sp0(struct tss_struct *tss, struct thread_struct
482 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0); 455 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
483 } 456 }
484} 457}
485
486
487static inline unsigned long native_get_debugreg(int regno)
488{
489 unsigned long val = 0; /* Damn you, gcc! */
490
491 switch (regno) {
492 case 0:
493 asm("movl %%db0, %0" :"=r" (val)); break;
494 case 1:
495 asm("movl %%db1, %0" :"=r" (val)); break;
496 case 2:
497 asm("movl %%db2, %0" :"=r" (val)); break;
498 case 3:
499 asm("movl %%db3, %0" :"=r" (val)); break;
500 case 6:
501 asm("movl %%db6, %0" :"=r" (val)); break;
502 case 7:
503 asm("movl %%db7, %0" :"=r" (val)); break;
504 default:
505 BUG();
506 }
507 return val;
508}
509
510static inline void native_set_debugreg(int regno, unsigned long value)
511{
512 switch (regno) {
513 case 0:
514 asm("movl %0,%%db0" : /* no output */ :"r" (value));
515 break;
516 case 1:
517 asm("movl %0,%%db1" : /* no output */ :"r" (value));
518 break;
519 case 2:
520 asm("movl %0,%%db2" : /* no output */ :"r" (value));
521 break;
522 case 3:
523 asm("movl %0,%%db3" : /* no output */ :"r" (value));
524 break;
525 case 6:
526 asm("movl %0,%%db6" : /* no output */ :"r" (value));
527 break;
528 case 7:
529 asm("movl %0,%%db7" : /* no output */ :"r" (value));
530 break;
531 default:
532 BUG();
533 }
534}
535
536/* 458/*
537 * Set IOPL bits in EFLAGS from given mask 459 * Set IOPL bits in EFLAGS from given mask
538 */ 460 */
@@ -552,21 +474,12 @@ static inline void native_set_iopl_mask(unsigned mask)
552#ifdef CONFIG_PARAVIRT 474#ifdef CONFIG_PARAVIRT
553#include <asm/paravirt.h> 475#include <asm/paravirt.h>
554#else 476#else
555#define paravirt_enabled() 0
556 477
557static inline void load_sp0(struct tss_struct *tss, struct thread_struct *thread) 478static inline void load_sp0(struct tss_struct *tss, struct thread_struct *thread)
558{ 479{
559 native_load_sp0(tss, thread); 480 native_load_sp0(tss, thread);
560} 481}
561 482
562/*
563 * These special macros can be used to get or set a debugging register
564 */
565#define get_debugreg(var, register) \
566 (var) = native_get_debugreg(register)
567#define set_debugreg(value, register) \
568 native_set_debugreg(register, value)
569
570#define set_iopl_mask native_set_iopl_mask 483#define set_iopl_mask native_set_iopl_mask
571#endif /* CONFIG_PARAVIRT */ 484#endif /* CONFIG_PARAVIRT */
572 485