diff options
Diffstat (limited to 'include/asm-v850/rte_mb_a_pci.h')
| -rw-r--r-- | include/asm-v850/rte_mb_a_pci.h | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/include/asm-v850/rte_mb_a_pci.h b/include/asm-v850/rte_mb_a_pci.h new file mode 100644 index 000000000000..41ac185ca9cd --- /dev/null +++ b/include/asm-v850/rte_mb_a_pci.h | |||
| @@ -0,0 +1,56 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-v850/mb_a_pci.h -- PCI support for Midas lab RTE-MOTHER-A board | ||
| 3 | * | ||
| 4 | * Copyright (C) 2001 NEC Corporation | ||
| 5 | * Copyright (C) 2001 Miles Bader <miles@gnu.org> | ||
| 6 | * | ||
| 7 | * This file is subject to the terms and conditions of the GNU General | ||
| 8 | * Public License. See the file COPYING in the main directory of this | ||
| 9 | * archive for more details. | ||
| 10 | * | ||
| 11 | * Written by Miles Bader <miles@gnu.org> | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __V850_MB_A_PCI_H__ | ||
| 15 | #define __V850_MB_A_PCI_H__ | ||
| 16 | |||
| 17 | |||
| 18 | #define MB_A_PCI_MEM_ADDR GCS5_ADDR | ||
| 19 | #define MB_A_PCI_MEM_SIZE (GCS5_SIZE / 2) | ||
| 20 | #define MB_A_PCI_IO_ADDR (GCS5_ADDR + MB_A_PCI_MEM_SIZE) | ||
| 21 | #define MB_A_PCI_IO_SIZE (GCS5_SIZE / 2) | ||
| 22 | #define MB_A_PCI_REG_BASE_ADDR GCS6_ADDR | ||
| 23 | |||
| 24 | #define MB_A_PCI_PCICR_ADDR (MB_A_PCI_REG_BASE_ADDR + 0x4) | ||
| 25 | #define MB_A_PCI_PCICR (*(volatile u16 *)MB_A_PCI_PCICR_ADDR) | ||
| 26 | #define MB_A_PCI_PCISR_ADDR (MB_A_PCI_REG_BASE_ADDR + 0x6) | ||
| 27 | #define MB_A_PCI_PCISR (*(volatile u16 *)MB_A_PCI_PCISR_ADDR) | ||
| 28 | #define MB_A_PCI_PCILTR_ADDR (MB_A_PCI_REG_BASE_ADDR + 0xD) | ||
| 29 | #define MB_A_PCI_PCILTR (*(volatile u8 *)MB_A_PCI_PCILTR_ADDR) | ||
| 30 | #define MB_A_PCI_PCIBAR0_ADDR (MB_A_PCI_REG_BASE_ADDR + 0x10) | ||
| 31 | #define MB_A_PCI_PCIBAR0 (*(volatile u32 *)MB_A_PCI_PCIBAR0_ADDR) | ||
| 32 | #define MB_A_PCI_PCIBAR1_ADDR (MB_A_PCI_REG_BASE_ADDR + 0x14) | ||
| 33 | #define MB_A_PCI_PCIBAR1 (*(volatile u32 *)MB_A_PCI_PCIBAR1_ADDR) | ||
| 34 | #define MB_A_PCI_PCIBAR2_ADDR (MB_A_PCI_REG_BASE_ADDR + 0x18) | ||
| 35 | #define MB_A_PCI_PCIBAR2 (*(volatile u32 *)MB_A_PCI_PCIBAR2_ADDR) | ||
| 36 | #define MB_A_PCI_VENDOR_ID_ADDR (MB_A_PCI_REG_BASE_ADDR + 0x2C) | ||
| 37 | #define MB_A_PCI_VENDOR_ID (*(volatile u16 *)MB_A_PCI_VENDOR_ID_ADDR) | ||
| 38 | #define MB_A_PCI_DEVICE_ID_ADDR (MB_A_PCI_REG_BASE_ADDR + 0x2E) | ||
| 39 | #define MB_A_PCI_DEVICE_ID (*(volatile u16 *)MB_A_PCI_DEVICE_ID_ADDR) | ||
| 40 | #define MB_A_PCI_DMRR_ADDR (MB_A_PCI_REG_BASE_ADDR + 0x9C) | ||
| 41 | #define MB_A_PCI_DMRR (*(volatile u32 *)MB_A_PCI_DMRR_ADDR) | ||
| 42 | #define MB_A_PCI_DMLBAM_ADDR (MB_A_PCI_REG_BASE_ADDR + 0xA0) | ||
| 43 | #define MB_A_PCI_DMLBAM (*(volatile u32 *)MB_A_PCI_DMLBAM_ADDR) | ||
| 44 | #define MB_A_PCI_DMLBAI_ADDR (MB_A_PCI_REG_BASE_ADDR + 0xA4) | ||
| 45 | #define MB_A_PCI_DMLBAI (*(volatile u32 *)MB_A_PCI_DMLBAI_ADDR) | ||
| 46 | #define MB_A_PCI_PCIPBAM_ADDR (MB_A_PCI_REG_BASE_ADDR + 0xA8) | ||
| 47 | #define MB_A_PCI_PCIPBAM (*(volatile u32 *)MB_A_PCI_PCIPBAM_ADDR) | ||
| 48 | /* `PCI Configuration Address Register for Direct Master to PCI IO/CFG' */ | ||
| 49 | #define MB_A_PCI_DMCFGA_ADDR (MB_A_PCI_REG_BASE_ADDR + 0xAC) | ||
| 50 | #define MB_A_PCI_DMCFGA (*(volatile u32 *)MB_A_PCI_DMCFGA_ADDR) | ||
| 51 | /* `PCI Permanent Configuration ID Register' */ | ||
| 52 | #define MB_A_PCI_PCIHIDR_ADDR (MB_A_PCI_REG_BASE_ADDR + 0xF0) | ||
| 53 | #define MB_A_PCI_PCIHIDR (*(volatile u32 *)MB_A_PCI_PCIHIDR_ADDR) | ||
| 54 | |||
| 55 | |||
| 56 | #endif /* __V850_MB_A_PCI_H__ */ | ||