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-rw-r--r--include/asm-sparc64/hardirq.h2
-rw-r--r--include/asm-sparc64/hw_irq.h2
-rw-r--r--include/asm-sparc64/irq.h78
3 files changed, 6 insertions, 76 deletions
diff --git a/include/asm-sparc64/hardirq.h b/include/asm-sparc64/hardirq.h
index f0cf71376ec5..7c29fd1a87aa 100644
--- a/include/asm-sparc64/hardirq.h
+++ b/include/asm-sparc64/hardirq.h
@@ -12,6 +12,8 @@
12#define local_softirq_pending() \ 12#define local_softirq_pending() \
13 (local_cpu_data().__softirq_pending) 13 (local_cpu_data().__softirq_pending)
14 14
15void ack_bad_irq(unsigned int irq);
16
15#define HARDIRQ_BITS 8 17#define HARDIRQ_BITS 8
16 18
17#endif /* !(__SPARC64_HARDIRQ_H) */ 19#endif /* !(__SPARC64_HARDIRQ_H) */
diff --git a/include/asm-sparc64/hw_irq.h b/include/asm-sparc64/hw_irq.h
index 153cae2ddaee..599b3b073450 100644
--- a/include/asm-sparc64/hw_irq.h
+++ b/include/asm-sparc64/hw_irq.h
@@ -1,6 +1,6 @@
1#ifndef __ASM_SPARC64_HW_IRQ_H 1#ifndef __ASM_SPARC64_HW_IRQ_H
2#define __ASM_SPARC64_HW_IRQ_H 2#define __ASM_SPARC64_HW_IRQ_H
3 3
4/* Dummy include. */ 4extern void hw_resend_irq(struct hw_interrupt_type *handler, unsigned int virt_irq);
5 5
6#endif 6#endif
diff --git a/include/asm-sparc64/irq.h b/include/asm-sparc64/irq.h
index 9edcd90495f7..77a4f63cba7a 100644
--- a/include/asm-sparc64/irq.h
+++ b/include/asm-sparc64/irq.h
@@ -16,58 +16,6 @@
16#include <asm/pil.h> 16#include <asm/pil.h>
17#include <asm/ptrace.h> 17#include <asm/ptrace.h>
18 18
19struct ino_bucket;
20
21#define MAX_IRQ_DESC_ACTION 4
22
23struct irq_desc {
24 void (*pre_handler)(struct ino_bucket *, void *, void *);
25 void *pre_handler_arg1;
26 void *pre_handler_arg2;
27 u32 action_active_mask;
28 struct irqaction action[MAX_IRQ_DESC_ACTION];
29};
30
31/* You should not mess with this directly. That's the job of irq.c.
32 *
33 * If you make changes here, please update hand coded assembler of
34 * the vectored interrupt trap handler in entry.S -DaveM
35 *
36 * This is currently one DCACHE line, two buckets per L2 cache
37 * line. Keep this in mind please.
38 */
39struct ino_bucket {
40 /* Next handler in per-CPU IRQ worklist. We know that
41 * bucket pointers have the high 32-bits clear, so to
42 * save space we only store the bits we need.
43 */
44/*0x00*/unsigned int irq_chain;
45
46 /* Virtual interrupt number assigned to this INO. */
47/*0x04*/unsigned char virt_irq;
48
49 /* If an IVEC arrives while irq_info is NULL, we
50 * set this to notify request_irq() about the event.
51 */
52/*0x05*/unsigned char pending;
53
54 /* Miscellaneous flags. */
55/*0x06*/unsigned char flags;
56
57 /* Currently unused. */
58/*0x07*/unsigned char __pad;
59
60 /* Reference to IRQ descriptor for this bucket. */
61/*0x08*/struct irq_desc *irq_info;
62
63 /* Sun5 Interrupt Clear Register. */
64/*0x10*/unsigned long iclr;
65
66 /* Sun5 Interrupt Mapping Register. */
67/*0x18*/unsigned long imap;
68
69};
70
71/* IMAP/ICLR register defines */ 19/* IMAP/ICLR register defines */
72#define IMAP_VALID 0x80000000 /* IRQ Enabled */ 20#define IMAP_VALID 0x80000000 /* IRQ Enabled */
73#define IMAP_TID_UPA 0x7c000000 /* UPA TargetID */ 21#define IMAP_TID_UPA 0x7c000000 /* UPA TargetID */
@@ -85,19 +33,6 @@ struct ino_bucket {
85#define ICLR_TRANSMIT 0x00000001 /* Transmit state */ 33#define ICLR_TRANSMIT 0x00000001 /* Transmit state */
86#define ICLR_PENDING 0x00000003 /* Pending state */ 34#define ICLR_PENDING 0x00000003 /* Pending state */
87 35
88/* Only 8-bits are available, be careful. -DaveM */
89#define IBF_PCI 0x02 /* PSYCHO/SABRE/SCHIZO PCI interrupt. */
90#define IBF_ACTIVE 0x04 /* Interrupt is active and has a handler.*/
91#define IBF_INPROGRESS 0x10 /* IRQ is being serviced. */
92
93#define NUM_IVECS (IMAP_INR + 1)
94extern struct ino_bucket ivector_table[NUM_IVECS];
95
96#define __irq_ino(irq) \
97 (((struct ino_bucket *)(unsigned long)(irq)) - &ivector_table[0])
98#define __bucket(irq) ((struct ino_bucket *)(unsigned long)(irq))
99#define __irq(bucket) ((unsigned int)(unsigned long)(bucket))
100
101/* The largest number of unique interrupt sources we support. 36/* The largest number of unique interrupt sources we support.
102 * If this needs to ever be larger than 255, you need to change 37 * If this needs to ever be larger than 255, you need to change
103 * the type of ino_bucket->virt_irq as appropriate. 38 * the type of ino_bucket->virt_irq as appropriate.
@@ -107,14 +42,11 @@ extern struct ino_bucket ivector_table[NUM_IVECS];
107#define NR_IRQS 255 42#define NR_IRQS 255
108 43
109extern void irq_install_pre_handler(int virt_irq, 44extern void irq_install_pre_handler(int virt_irq,
110 void (*func)(struct ino_bucket *, void *, void *), 45 void (*func)(unsigned int, void *, void *),
111 void *arg1, void *arg2); 46 void *arg1, void *arg2);
112#define irq_canonicalize(irq) (irq) 47#define irq_canonicalize(irq) (irq)
113extern void disable_irq(unsigned int); 48extern unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap);
114#define disable_irq_nosync disable_irq 49extern unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino);
115extern void enable_irq(unsigned int);
116extern unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap, unsigned char flags);
117extern unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino, unsigned char flags);
118extern unsigned int sbus_build_irq(void *sbus, unsigned int ino); 50extern unsigned int sbus_build_irq(void *sbus, unsigned int ino);
119 51
120static __inline__ void set_softint(unsigned long bits) 52static __inline__ void set_softint(unsigned long bits)
@@ -140,8 +72,4 @@ static __inline__ unsigned long get_softint(void)
140 return retval; 72 return retval;
141} 73}
142 74
143struct irqaction;
144struct pt_regs;
145int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *);
146
147#endif 75#endif