[SPARC64]: Move over to GENERIC_HARDIRQS.

This is the long overdue conversion of sparc64 over to
the generic IRQ layer.

The kernel image is slightly larger, but the BSS is ~60K
smaller due to the reduced size of struct ino_bucket.

A lot of IRQ implementation details, including ino_bucket,
were moved out of asm-sparc64/irq.h and are now private to
arch/sparc64/kernel/irq.c, and most of the code in irq.c
totally disappeared.

One thing that's different at the moment is IRQ distribution,
we do it at enable_irq() time.  If the cpu mask is ALL then
we round-robin using a global rotating cpu counter, else
we pick the first cpu in the mask to support single cpu
targetting.  This is similar to what powerpc's XICS IRQ
support code does.

This works fine on my UP SB1000, and the SMP build goes
fine and runs on that machine, but lots of testing on
different setups is needed.

Signed-off-by: David S. Miller <davem@davemloft.net>

3 files changed, 6 insertions, 76 deletions

diff --git a/include/asm-sparc64/hardirq.h b/include/asm-sparc64/hardirq.h
index f0cf71376ec5..7c29fd1a87aa 100644
--- a/include/asm-sparc64/hardirq.h
+++ b/include/asm-sparc64/hardirq.h
@@ -12,6 +12,8 @@
 #define local_softirq_pending() \
         (local_cpu_data().__softirq_pending)
 
+void ack_bad_irq(unsigned int irq);
+
 #define HARDIRQ_BITS    8
 
 #endif /* !(__SPARC64_HARDIRQ_H) */
diff --git a/include/asm-sparc64/hw_irq.h b/include/asm-sparc64/hw_irq.h
index 153cae2ddaee..599b3b073450 100644
--- a/include/asm-sparc64/hw_irq.h
+++ b/include/asm-sparc64/hw_irq.h
@@ -1,6 +1,6 @@
 #ifndef __ASM_SPARC64_HW_IRQ_H
 #define __ASM_SPARC64_HW_IRQ_H
 
-/* Dummy include. */
+extern void hw_resend_irq(struct hw_interrupt_type *handler, unsigned int virt_irq);
 
 #endif
diff --git a/include/asm-sparc64/irq.h b/include/asm-sparc64/irq.h
index 9edcd90495f7..77a4f63cba7a 100644
--- a/include/asm-sparc64/irq.h
+++ b/include/asm-sparc64/irq.h
@@ -16,58 +16,6 @@
 #include <asm/pil.h>
 #include <asm/ptrace.h>
 
-struct ino_bucket;
-
-#define MAX_IRQ_DESC_ACTION     4
-
-struct irq_desc {
-        void                    (*pre_handler)(struct ino_bucket *, void *, void *);
-        void                    *pre_handler_arg1;
-        void                    *pre_handler_arg2;
-        u32                     action_active_mask;
-        struct irqaction        action[MAX_IRQ_DESC_ACTION];
-};
-
-/* You should not mess with this directly. That's the job of irq.c.
- *
- * If you make changes here, please update hand coded assembler of
- * the vectored interrupt trap handler in entry.S -DaveM
- *
- * This is currently one DCACHE line, two buckets per L2 cache
- * line.  Keep this in mind please.
- */
-struct ino_bucket {
-        /* Next handler in per-CPU IRQ worklist.  We know that
-         * bucket pointers have the high 32-bits clear, so to
-         * save space we only store the bits we need.
-         */
-/*0x00*/unsigned int irq_chain;
-
-        /* Virtual interrupt number assigned to this INO.  */
-/*0x04*/unsigned char virt_irq;
-
-        /* If an IVEC arrives while irq_info is NULL, we
-         * set this to notify request_irq() about the event.
-         */
-/*0x05*/unsigned char pending;
-
-        /* Miscellaneous flags. */
-/*0x06*/unsigned char flags;
-
-        /* Currently unused.  */
-/*0x07*/unsigned char __pad;
-
-        /* Reference to IRQ descriptor for this bucket. */
-/*0x08*/struct irq_desc *irq_info;
-
-        /* Sun5 Interrupt Clear Register. */
-/*0x10*/unsigned long iclr;
-
-        /* Sun5 Interrupt Mapping Register. */
-/*0x18*/unsigned long imap;
-
-};
-
 /* IMAP/ICLR register defines */
 #define IMAP_VALID              0x80000000      /* IRQ Enabled          */
 #define IMAP_TID_UPA            0x7c000000      /* UPA TargetID         */
@@ -85,19 +33,6 @@ struct ino_bucket {
 #define ICLR_TRANSMIT           0x00000001      /* Transmit state       */
 #define ICLR_PENDING            0x00000003      /* Pending state        */
 
-/* Only 8-bits are available, be careful.  -DaveM */
-#define IBF_PCI         0x02    /* PSYCHO/SABRE/SCHIZO PCI interrupt.    */
-#define IBF_ACTIVE      0x04    /* Interrupt is active and has a handler.*/
-#define IBF_INPROGRESS  0x10    /* IRQ is being serviced.                */
-
-#define NUM_IVECS       (IMAP_INR + 1)
-extern struct ino_bucket ivector_table[NUM_IVECS];
-
-#define __irq_ino(irq) \
-        (((struct ino_bucket *)(unsigned long)(irq)) - &ivector_table[0])
-#define __bucket(irq) ((struct ino_bucket *)(unsigned long)(irq))
-#define __irq(bucket) ((unsigned int)(unsigned long)(bucket))
-
 /* The largest number of unique interrupt sources we support.
  * If this needs to ever be larger than 255, you need to change
  * the type of ino_bucket->virt_irq as appropriate.
@@ -107,14 +42,11 @@ extern struct ino_bucket ivector_table[NUM_IVECS];
 #define NR_IRQS    255
 
 extern void irq_install_pre_handler(int virt_irq,
-                                    void (*func)(struct ino_bucket *, void *, void *),
+                                    void (*func)(unsigned int, void *, void *),
                                     void *arg1, void *arg2);
 #define irq_canonicalize(irq)   (irq)
-extern void disable_irq(unsigned int);
-#define disable_irq_nosync disable_irq
-extern void enable_irq(unsigned int);
-extern unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap, unsigned char flags);
-extern unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino, unsigned char flags);
+extern unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap);
+extern unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino);
 extern unsigned int sbus_build_irq(void *sbus, unsigned int ino);
 
 static __inline__ void set_softint(unsigned long bits)
@@ -140,8 +72,4 @@ static __inline__ unsigned long get_softint(void)
         return retval;
 }
 
-struct irqaction;
-struct pt_regs;
-int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *);
-
 #endif