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-rw-r--r--include/asm-sh/io.h68
1 files changed, 40 insertions, 28 deletions
diff --git a/include/asm-sh/io.h b/include/asm-sh/io.h
index 6ed34d8eac5f..94900c089519 100644
--- a/include/asm-sh/io.h
+++ b/include/asm-sh/io.h
@@ -191,6 +191,8 @@ __BUILD_MEMORY_STRING(w, u16)
191 191
192#define mmiowb() wmb() /* synco on SH-4A, otherwise a nop */ 192#define mmiowb() wmb() /* synco on SH-4A, otherwise a nop */
193 193
194#define IO_SPACE_LIMIT 0xffffffff
195
194/* 196/*
195 * This function provides a method for the generic case where a board-specific 197 * This function provides a method for the generic case where a board-specific
196 * ioport_map simply needs to return the port + some arbitrary port base. 198 * ioport_map simply needs to return the port + some arbitrary port base.
@@ -226,6 +228,11 @@ static inline unsigned int ctrl_inl(unsigned long addr)
226 return *(volatile unsigned long*)addr; 228 return *(volatile unsigned long*)addr;
227} 229}
228 230
231static inline unsigned long long ctrl_inq(unsigned long addr)
232{
233 return *(volatile unsigned long long*)addr;
234}
235
229static inline void ctrl_outb(unsigned char b, unsigned long addr) 236static inline void ctrl_outb(unsigned char b, unsigned long addr)
230{ 237{
231 *(volatile unsigned char*)addr = b; 238 *(volatile unsigned char*)addr = b;
@@ -241,49 +248,52 @@ static inline void ctrl_outl(unsigned int b, unsigned long addr)
241 *(volatile unsigned long*)addr = b; 248 *(volatile unsigned long*)addr = b;
242} 249}
243 250
251static inline void ctrl_outq(unsigned long long b, unsigned long addr)
252{
253 *(volatile unsigned long long*)addr = b;
254}
255
244static inline void ctrl_delay(void) 256static inline void ctrl_delay(void)
245{ 257{
258#ifdef P2SEG
246 ctrl_inw(P2SEG); 259 ctrl_inw(P2SEG);
260#endif
247} 261}
248 262
249#define IO_SPACE_LIMIT 0xffffffff 263/* Quad-word real-mode I/O, don't ask.. */
264unsigned long long peek_real_address_q(unsigned long long addr);
265unsigned long long poke_real_address_q(unsigned long long addr,
266 unsigned long long val);
250 267
251#ifdef CONFIG_MMU 268/* arch/sh/mm/ioremap_64.c */
252/* 269unsigned long onchip_remap(unsigned long addr, unsigned long size,
253 * Change virtual addresses to physical addresses and vv. 270 const char *name);
254 * These are trivial on the 1:1 Linux/SuperH mapping 271extern void onchip_unmap(unsigned long vaddr);
255 */
256static inline unsigned long virt_to_phys(volatile void *address)
257{
258 return PHYSADDR(address);
259}
260 272
261static inline void *phys_to_virt(unsigned long address) 273#if !defined(CONFIG_MMU)
262{
263 return (void *)P1SEGADDR(address);
264}
265#else
266#define phys_to_virt(address) ((void *)(address))
267#define virt_to_phys(address) ((unsigned long)(address)) 274#define virt_to_phys(address) ((unsigned long)(address))
275#define phys_to_virt(address) ((void *)(address))
276#else
277#define virt_to_phys(address) (__pa(address))
278#define phys_to_virt(address) (__va(address))
268#endif 279#endif
269 280
270/* 281/*
271 * readX/writeX() are used to access memory mapped devices. On some 282 * On 32-bit SH, we traditionally have the whole physical address space
272 * architectures the memory mapped IO stuff needs to be accessed 283 * mapped at all times (as MIPS does), so "ioremap()" and "iounmap()" do
273 * differently. On the x86 architecture, we just read/write the 284 * not need to do anything but place the address in the proper segment.
274 * memory location directly. 285 * This is true for P1 and P2 addresses, as well as some P3 ones.
286 * However, most of the P3 addresses and newer cores using extended
287 * addressing need to map through page tables, so the ioremap()
288 * implementation becomes a bit more complicated.
275 * 289 *
276 * On SH, we traditionally have the whole physical address space mapped 290 * See arch/sh/mm/ioremap.c for additional notes on this.
277 * at all times (as MIPS does), so "ioremap()" and "iounmap()" do not
278 * need to do anything but place the address in the proper segment. This
279 * is true for P1 and P2 addresses, as well as some P3 ones. However,
280 * most of the P3 addresses and newer cores using extended addressing
281 * need to map through page tables, so the ioremap() implementation
282 * becomes a bit more complicated. See arch/sh/mm/ioremap.c for
283 * additional notes on this.
284 * 291 *
285 * We cheat a bit and always return uncachable areas until we've fixed 292 * We cheat a bit and always return uncachable areas until we've fixed
286 * the drivers to handle caching properly. 293 * the drivers to handle caching properly.
294 *
295 * On the SH-5 the concept of segmentation in the 1:1 PXSEG sense simply
296 * doesn't exist, so everything must go through page tables.
287 */ 297 */
288#ifdef CONFIG_MMU 298#ifdef CONFIG_MMU
289void __iomem *__ioremap(unsigned long offset, unsigned long size, 299void __iomem *__ioremap(unsigned long offset, unsigned long size,
@@ -297,6 +307,7 @@ void __iounmap(void __iomem *addr);
297static inline void __iomem * 307static inline void __iomem *
298__ioremap_mode(unsigned long offset, unsigned long size, unsigned long flags) 308__ioremap_mode(unsigned long offset, unsigned long size, unsigned long flags)
299{ 309{
310#ifdef CONFIG_SUPERH32
300 unsigned long last_addr = offset + size - 1; 311 unsigned long last_addr = offset + size - 1;
301 312
302 /* 313 /*
@@ -311,6 +322,7 @@ __ioremap_mode(unsigned long offset, unsigned long size, unsigned long flags)
311 322
312 return (void __iomem *)P2SEGADDR(offset); 323 return (void __iomem *)P2SEGADDR(offset);
313 } 324 }
325#endif
314 326
315 return __ioremap(offset, size, flags); 327 return __ioremap(offset, size, flags);
316} 328}