3 files changed, 28 insertions, 0 deletions

diff --git a/include/asm-ppc/irq.h b/include/asm-ppc/irq.h
index 55752474d0d9..bd9674807f05 100644
--- a/include/asm-ppc/irq.h
+++ b/include/asm-ppc/irq.h
@@ -138,6 +138,16 @@ irq_canonicalize(int irq)
 #define SIU_IRQ7        (14)
 #define SIU_LEVEL7      (15)
 
+#define MPC8xx_INT_FEC1         SIU_LEVEL1
+#define MPC8xx_INT_FEC2         SIU_LEVEL3
+
+#define MPC8xx_INT_SCC1         (CPM_IRQ_OFFSET + CPMVEC_SCC1)
+#define MPC8xx_INT_SCC2         (CPM_IRQ_OFFSET + CPMVEC_SCC2)
+#define MPC8xx_INT_SCC3         (CPM_IRQ_OFFSET + CPMVEC_SCC3)
+#define MPC8xx_INT_SCC4         (CPM_IRQ_OFFSET + CPMVEC_SCC4)
+#define MPC8xx_INT_SMC1         (CPM_IRQ_OFFSET + CPMVEC_SMC1)
+#define MPC8xx_INT_SMC2         (CPM_IRQ_OFFSET + CPMVEC_SMC2)
+
 /* The internal interrupts we can configure as we see fit.
  * My personal preference is CPM at level 2, which puts it above the
  * MBX PCI/ISA/IDE interrupts.
diff --git a/include/asm-ppc/mpc8xx.h b/include/asm-ppc/mpc8xx.h
index dc8e59896050..208a2e11daee 100644
--- a/include/asm-ppc/mpc8xx.h
+++ b/include/asm-ppc/mpc8xx.h
@@ -97,6 +97,22 @@ extern unsigned char __res[];
 
 struct pt_regs;
 
+enum ppc_sys_devices {
+        MPC8xx_CPM_FEC1,
+        MPC8xx_CPM_FEC2,
+        MPC8xx_CPM_I2C,
+        MPC8xx_CPM_SCC1,
+        MPC8xx_CPM_SCC2,
+        MPC8xx_CPM_SCC3,
+        MPC8xx_CPM_SCC4,
+        MPC8xx_CPM_SPI,
+        MPC8xx_CPM_MCC1,
+        MPC8xx_CPM_MCC2,
+        MPC8xx_CPM_SMC1,
+        MPC8xx_CPM_SMC2,
+        MPC8xx_CPM_USB,
+};
+
 #endif /* !__ASSEMBLY__ */
 #endif /* CONFIG_8xx */
 #endif /* __CONFIG_8xx_DEFS */
diff --git a/include/asm-ppc/ppc_sys.h b/include/asm-ppc/ppc_sys.h
index 048f7c8596ee..549f44843c5e 100644
--- a/include/asm-ppc/ppc_sys.h
+++ b/include/asm-ppc/ppc_sys.h
@@ -27,6 +27,8 @@
 #include <asm/mpc83xx.h>
 #elif defined(CONFIG_85xx)
 #include <asm/mpc85xx.h>
+#elif defined(CONFIG_8xx)
+#include <asm/mpc8xx.h>
 #elif defined(CONFIG_PPC_MPC52xx)
 #include <asm/mpc52xx.h>
 #elif defined(CONFIG_MPC10X_BRIDGE)