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-rw-r--r--include/asm-ppc/cpm2.h95
1 files changed, 95 insertions, 0 deletions
diff --git a/include/asm-ppc/cpm2.h b/include/asm-ppc/cpm2.h
index c70344b91049..f6a7ff04ffe5 100644
--- a/include/asm-ppc/cpm2.h
+++ b/include/asm-ppc/cpm2.h
@@ -1093,5 +1093,100 @@ typedef struct im_idma {
1093 1093
1094#define FCC_PSMR_RMII ((uint)0x00020000) /* Use RMII interface */ 1094#define FCC_PSMR_RMII ((uint)0x00020000) /* Use RMII interface */
1095 1095
1096/* FCC iop & clock configuration. BSP code is responsible to define Fx_RXCLK & Fx_TXCLK
1097 * in order to use clock-computing stuff below for the FCC x
1098 */
1099
1100/* Automatically generates register configurations */
1101#define PC_CLK(x) ((uint)(1<<(x-1))) /* FCC CLK I/O ports */
1102
1103#define CMXFCR_RF1CS(x) ((uint)((x-5)<<27)) /* FCC1 Receive Clock Source */
1104#define CMXFCR_TF1CS(x) ((uint)((x-5)<<24)) /* FCC1 Transmit Clock Source */
1105#define CMXFCR_RF2CS(x) ((uint)((x-9)<<19)) /* FCC2 Receive Clock Source */
1106#define CMXFCR_TF2CS(x) ((uint)((x-9)<<16)) /* FCC2 Transmit Clock Source */
1107#define CMXFCR_RF3CS(x) ((uint)((x-9)<<11)) /* FCC3 Receive Clock Source */
1108#define CMXFCR_TF3CS(x) ((uint)((x-9)<<8)) /* FCC3 Transmit Clock Source */
1109
1110#define PC_F1RXCLK PC_CLK(F1_RXCLK)
1111#define PC_F1TXCLK PC_CLK(F1_TXCLK)
1112#define CMX1_CLK_ROUTE (CMXFCR_RF1CS(F1_RXCLK) | CMXFCR_TF1CS(F1_TXCLK))
1113#define CMX1_CLK_MASK ((uint)0xff000000)
1114
1115#define PC_F2RXCLK PC_CLK(F2_RXCLK)
1116#define PC_F2TXCLK PC_CLK(F2_TXCLK)
1117#define CMX2_CLK_ROUTE (CMXFCR_RF2CS(F2_RXCLK) | CMXFCR_TF2CS(F2_TXCLK))
1118#define CMX2_CLK_MASK ((uint)0x00ff0000)
1119
1120#define PC_F3RXCLK PC_CLK(F3_RXCLK)
1121#define PC_F3TXCLK PC_CLK(F3_TXCLK)
1122#define CMX3_CLK_ROUTE (CMXFCR_RF3CS(F3_RXCLK) | CMXFCR_TF3CS(F3_TXCLK))
1123#define CMX3_CLK_MASK ((uint)0x0000ff00)
1124
1125#define CPMUX_CLK_MASK (CMX3_CLK_MASK | CMX2_CLK_MASK)
1126#define CPMUX_CLK_ROUTE (CMX3_CLK_ROUTE | CMX2_CLK_ROUTE)
1127
1128#define CLK_TRX (PC_F3TXCLK | PC_F3RXCLK | PC_F2TXCLK | PC_F2RXCLK)
1129
1130/* I/O Pin assignment for FCC1. I don't yet know the best way to do this,
1131 * but there is little variation among the choices.
1132 */
1133#define PA1_COL 0x00000001U
1134#define PA1_CRS 0x00000002U
1135#define PA1_TXER 0x00000004U
1136#define PA1_TXEN 0x00000008U
1137#define PA1_RXDV 0x00000010U
1138#define PA1_RXER 0x00000020U
1139#define PA1_TXDAT 0x00003c00U
1140#define PA1_RXDAT 0x0003c000U
1141#define PA1_PSORA0 (PA1_RXDAT | PA1_TXDAT)
1142#define PA1_PSORA1 (PA1_COL | PA1_CRS | PA1_TXER | PA1_TXEN | \
1143 PA1_RXDV | PA1_RXER)
1144#define PA1_DIRA0 (PA1_RXDAT | PA1_CRS | PA1_COL | PA1_RXER | PA1_RXDV)
1145#define PA1_DIRA1 (PA1_TXDAT | PA1_TXEN | PA1_TXER)
1146
1147
1148/* I/O Pin assignment for FCC2. I don't yet know the best way to do this,
1149 * but there is little variation among the choices.
1150 */
1151#define PB2_TXER 0x00000001U
1152#define PB2_RXDV 0x00000002U
1153#define PB2_TXEN 0x00000004U
1154#define PB2_RXER 0x00000008U
1155#define PB2_COL 0x00000010U
1156#define PB2_CRS 0x00000020U
1157#define PB2_TXDAT 0x000003c0U
1158#define PB2_RXDAT 0x00003c00U
1159#define PB2_PSORB0 (PB2_RXDAT | PB2_TXDAT | PB2_CRS | PB2_COL | \
1160 PB2_RXER | PB2_RXDV | PB2_TXER)
1161#define PB2_PSORB1 (PB2_TXEN)
1162#define PB2_DIRB0 (PB2_RXDAT | PB2_CRS | PB2_COL | PB2_RXER | PB2_RXDV)
1163#define PB2_DIRB1 (PB2_TXDAT | PB2_TXEN | PB2_TXER)
1164
1165
1166/* I/O Pin assignment for FCC3. I don't yet know the best way to do this,
1167 * but there is little variation among the choices.
1168 */
1169#define PB3_RXDV 0x00004000U
1170#define PB3_RXER 0x00008000U
1171#define PB3_TXER 0x00010000U
1172#define PB3_TXEN 0x00020000U
1173#define PB3_COL 0x00040000U
1174#define PB3_CRS 0x00080000U
1175#define PB3_TXDAT 0x0f000000U
1176#define PC3_TXDAT 0x00000010U
1177#define PB3_RXDAT 0x00f00000U
1178#define PB3_PSORB0 (PB3_RXDAT | PB3_TXDAT | PB3_CRS | PB3_COL | \
1179 PB3_RXER | PB3_RXDV | PB3_TXER | PB3_TXEN)
1180#define PB3_PSORB1 0
1181#define PB3_DIRB0 (PB3_RXDAT | PB3_CRS | PB3_COL | PB3_RXER | PB3_RXDV)
1182#define PB3_DIRB1 (PB3_TXDAT | PB3_TXEN | PB3_TXER)
1183#define PC3_DIRC1 (PC3_TXDAT)
1184
1185/* Handy macro to specify mem for FCCs*/
1186#define FCC_MEM_OFFSET(x) (CPM_FCC_SPECIAL_BASE + (x*128))
1187#define FCC1_MEM_OFFSET FCC_MEM_OFFSET(0)
1188#define FCC2_MEM_OFFSET FCC_MEM_OFFSET(1)
1189#define FCC2_MEM_OFFSET FCC_MEM_OFFSET(2)
1190
1096#endif /* __CPM2__ */ 1191#endif /* __CPM2__ */
1097#endif /* __KERNEL__ */ 1192#endif /* __KERNEL__ */