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-rw-r--r--include/asm-powerpc/reg_booke.h62
1 files changed, 0 insertions, 62 deletions
diff --git a/include/asm-powerpc/reg_booke.h b/include/asm-powerpc/reg_booke.h
index 0405ef479814..cf54a3f31753 100644
--- a/include/asm-powerpc/reg_booke.h
+++ b/include/asm-powerpc/reg_booke.h
@@ -9,68 +9,6 @@
9#ifndef __ASM_POWERPC_REG_BOOKE_H__ 9#ifndef __ASM_POWERPC_REG_BOOKE_H__
10#define __ASM_POWERPC_REG_BOOKE_H__ 10#define __ASM_POWERPC_REG_BOOKE_H__
11 11
12#ifndef __ASSEMBLY__
13/* Performance Monitor Registers */
14#define mfpmr(rn) ({unsigned int rval; \
15 asm volatile("mfpmr %0," __stringify(rn) \
16 : "=r" (rval)); rval;})
17#define mtpmr(rn, v) asm volatile("mtpmr " __stringify(rn) ",%0" : : "r" (v))
18#endif /* __ASSEMBLY__ */
19
20/* Freescale Book E Performance Monitor APU Registers */
21#define PMRN_PMC0 0x010 /* Performance Monitor Counter 0 */
22#define PMRN_PMC1 0x011 /* Performance Monitor Counter 1 */
23#define PMRN_PMC2 0x012 /* Performance Monitor Counter 1 */
24#define PMRN_PMC3 0x013 /* Performance Monitor Counter 1 */
25#define PMRN_PMLCA0 0x090 /* PM Local Control A0 */
26#define PMRN_PMLCA1 0x091 /* PM Local Control A1 */
27#define PMRN_PMLCA2 0x092 /* PM Local Control A2 */
28#define PMRN_PMLCA3 0x093 /* PM Local Control A3 */
29
30#define PMLCA_FC 0x80000000 /* Freeze Counter */
31#define PMLCA_FCS 0x40000000 /* Freeze in Supervisor */
32#define PMLCA_FCU 0x20000000 /* Freeze in User */
33#define PMLCA_FCM1 0x10000000 /* Freeze when PMM==1 */
34#define PMLCA_FCM0 0x08000000 /* Freeze when PMM==0 */
35#define PMLCA_CE 0x04000000 /* Condition Enable */
36
37#define PMLCA_EVENT_MASK 0x007f0000 /* Event field */
38#define PMLCA_EVENT_SHIFT 16
39
40#define PMRN_PMLCB0 0x110 /* PM Local Control B0 */
41#define PMRN_PMLCB1 0x111 /* PM Local Control B1 */
42#define PMRN_PMLCB2 0x112 /* PM Local Control B2 */
43#define PMRN_PMLCB3 0x113 /* PM Local Control B3 */
44
45#define PMLCB_THRESHMUL_MASK 0x0700 /* Threshhold Multiple Field */
46#define PMLCB_THRESHMUL_SHIFT 8
47
48#define PMLCB_THRESHOLD_MASK 0x003f /* Threshold Field */
49#define PMLCB_THRESHOLD_SHIFT 0
50
51#define PMRN_PMGC0 0x190 /* PM Global Control 0 */
52
53#define PMGC0_FAC 0x80000000 /* Freeze all Counters */
54#define PMGC0_PMIE 0x40000000 /* Interrupt Enable */
55#define PMGC0_FCECE 0x20000000 /* Freeze countes on
56 Enabled Condition or
57 Event */
58
59#define PMRN_UPMC0 0x000 /* User Performance Monitor Counter 0 */
60#define PMRN_UPMC1 0x001 /* User Performance Monitor Counter 1 */
61#define PMRN_UPMC2 0x002 /* User Performance Monitor Counter 1 */
62#define PMRN_UPMC3 0x003 /* User Performance Monitor Counter 1 */
63#define PMRN_UPMLCA0 0x080 /* User PM Local Control A0 */
64#define PMRN_UPMLCA1 0x081 /* User PM Local Control A1 */
65#define PMRN_UPMLCA2 0x082 /* User PM Local Control A2 */
66#define PMRN_UPMLCA3 0x083 /* User PM Local Control A3 */
67#define PMRN_UPMLCB0 0x100 /* User PM Local Control B0 */
68#define PMRN_UPMLCB1 0x101 /* User PM Local Control B1 */
69#define PMRN_UPMLCB2 0x102 /* User PM Local Control B2 */
70#define PMRN_UPMLCB3 0x103 /* User PM Local Control B3 */
71#define PMRN_UPMGC0 0x180 /* User PM Global Control 0 */
72
73
74/* Machine State Register (MSR) Fields */ 12/* Machine State Register (MSR) Fields */
75#define MSR_UCLE (1<<26) /* User-mode cache lock enable */ 13#define MSR_UCLE (1<<26) /* User-mode cache lock enable */
76#define MSR_SPE (1<<25) /* Enable SPE */ 14#define MSR_SPE (1<<25) /* Enable SPE */