1 files changed, 2 insertions, 2 deletions
diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h
index c4a704121343..04ee53b34c2e 100644
--- a/include/asm-mips/war.h
+++ b/include/asm-mips/war.h
@@ -113,7 +113,7 @@
 */
 #define BCM1250_M3_WAR 1
-/* 
+/*
 * This is a DUART workaround related to glitches around register accesses
 */
 #define SIBYTE_1956_WAR 1
@@ -122,7 +122,7 @@
 /*
 * Fill buffers not flushed on CACHE instructions
- * 
+ *
 * Hit_Invalidate_I cacheops invalidate an icache line but the refill
 * for that line can get stale data from the fill buffer instead of
 * accessing memory if the previous icache miss was also to that line.

diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h index c4a704121343..04ee53b34c2e 100644 --- a/include/asm-mips/war.h +++ b/include/asm-mips/war.h
@@ -113,7 +113,7 @@
113	*/	113	*/
114	#define BCM1250_M3_WAR 1	114	#define BCM1250_M3_WAR 1
115		115
116	/*	116	/*
117	* This is a DUART workaround related to glitches around register accesses	117	* This is a DUART workaround related to glitches around register accesses
118	*/	118	*/
119	#define SIBYTE_1956_WAR 1	119	#define SIBYTE_1956_WAR 1
@@ -122,7 +122,7 @@
122		122
123	/*	123	/*
124	* Fill buffers not flushed on CACHE instructions	124	* Fill buffers not flushed on CACHE instructions
125	*	125	*
126	* Hit_Invalidate_I cacheops invalidate an icache line but the refill	126	* Hit_Invalidate_I cacheops invalidate an icache line but the refill
127	* for that line can get stale data from the fill buffer instead of	127	* for that line can get stale data from the fill buffer instead of
128	* accessing memory if the previous icache miss was also to that line.	128	* accessing memory if the previous icache miss was also to that line.