diff options
Diffstat (limited to 'include/asm-mips/mach-sibyte')
| -rw-r--r-- | include/asm-mips/mach-sibyte/cpu-feature-overrides.h | 47 | ||||
| -rw-r--r-- | include/asm-mips/mach-sibyte/war.h | 37 |
2 files changed, 0 insertions, 84 deletions
diff --git a/include/asm-mips/mach-sibyte/cpu-feature-overrides.h b/include/asm-mips/mach-sibyte/cpu-feature-overrides.h deleted file mode 100644 index 1c1f92415b9a..000000000000 --- a/include/asm-mips/mach-sibyte/cpu-feature-overrides.h +++ /dev/null | |||
| @@ -1,47 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 3 | * License. See the file "COPYING" in the main directory of this archive | ||
| 4 | * for more details. | ||
| 5 | * | ||
| 6 | * Copyright (C) 2003, 04, 07 Ralf Baechle (ralf@linux-mips.org) | ||
| 7 | */ | ||
| 8 | #ifndef __ASM_MACH_SIBYTE_CPU_FEATURE_OVERRIDES_H | ||
| 9 | #define __ASM_MACH_SIBYTE_CPU_FEATURE_OVERRIDES_H | ||
| 10 | |||
| 11 | /* | ||
| 12 | * Sibyte are MIPS64 processors wired to a specific configuration | ||
| 13 | */ | ||
| 14 | #define cpu_has_watch 1 | ||
| 15 | #define cpu_has_mips16 0 | ||
| 16 | #define cpu_has_divec 1 | ||
| 17 | #define cpu_has_vce 0 | ||
| 18 | #define cpu_has_cache_cdex_p 0 | ||
| 19 | #define cpu_has_cache_cdex_s 0 | ||
| 20 | #define cpu_has_prefetch 1 | ||
| 21 | #define cpu_has_mcheck 1 | ||
| 22 | #define cpu_has_ejtag 1 | ||
| 23 | |||
| 24 | #define cpu_has_llsc 1 | ||
| 25 | #define cpu_has_vtag_icache 1 | ||
| 26 | #define cpu_has_dc_aliases 0 | ||
| 27 | #define cpu_has_ic_fills_f_dc 0 | ||
| 28 | #define cpu_has_dsp 0 | ||
| 29 | #define cpu_has_mipsmt 0 | ||
| 30 | #define cpu_has_userlocal 0 | ||
| 31 | #define cpu_icache_snoops_remote_store 0 | ||
| 32 | |||
| 33 | #define cpu_has_nofpuex 0 | ||
| 34 | #define cpu_has_64bits 1 | ||
| 35 | |||
| 36 | #define cpu_has_mips32r1 1 | ||
| 37 | #define cpu_has_mips32r2 0 | ||
| 38 | #define cpu_has_mips64r1 1 | ||
| 39 | #define cpu_has_mips64r2 0 | ||
| 40 | |||
| 41 | #define cpu_has_inclusive_pcaches 0 | ||
| 42 | |||
| 43 | #define cpu_dcache_line_size() 32 | ||
| 44 | #define cpu_icache_line_size() 32 | ||
| 45 | #define cpu_scache_line_size() 32 | ||
| 46 | |||
| 47 | #endif /* __ASM_MACH_SIBYTE_CPU_FEATURE_OVERRIDES_H */ | ||
diff --git a/include/asm-mips/mach-sibyte/war.h b/include/asm-mips/mach-sibyte/war.h deleted file mode 100644 index 7950ef4f032c..000000000000 --- a/include/asm-mips/mach-sibyte/war.h +++ /dev/null | |||
| @@ -1,37 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * This file is subject to the terms and conditions of the GNU General Public | ||
| 3 | * License. See the file "COPYING" in the main directory of this archive | ||
| 4 | * for more details. | ||
| 5 | * | ||
| 6 | * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> | ||
| 7 | */ | ||
| 8 | #ifndef __ASM_MIPS_MACH_SIBYTE_WAR_H | ||
| 9 | #define __ASM_MIPS_MACH_SIBYTE_WAR_H | ||
| 10 | |||
| 11 | #define R4600_V1_INDEX_ICACHEOP_WAR 0 | ||
| 12 | #define R4600_V1_HIT_CACHEOP_WAR 0 | ||
| 13 | #define R4600_V2_HIT_CACHEOP_WAR 0 | ||
| 14 | #define R5432_CP0_INTERRUPT_WAR 0 | ||
| 15 | |||
| 16 | #if defined(CONFIG_SB1_PASS_1_WORKAROUNDS) || \ | ||
| 17 | defined(CONFIG_SB1_PASS_2_WORKAROUNDS) | ||
| 18 | |||
| 19 | #define BCM1250_M3_WAR 1 | ||
| 20 | #define SIBYTE_1956_WAR 1 | ||
| 21 | |||
| 22 | #else | ||
| 23 | |||
| 24 | #define BCM1250_M3_WAR 0 | ||
| 25 | #define SIBYTE_1956_WAR 0 | ||
| 26 | |||
| 27 | #endif | ||
| 28 | |||
| 29 | #define MIPS4K_ICACHE_REFILL_WAR 0 | ||
| 30 | #define MIPS_CACHE_SYNC_WAR 0 | ||
| 31 | #define TX49XX_ICACHE_INDEX_INV_WAR 0 | ||
| 32 | #define RM9000_CDEX_SMP_WAR 0 | ||
| 33 | #define ICACHE_REFILLS_WORKAROUND_WAR 0 | ||
| 34 | #define R10000_LLSC_WAR 0 | ||
| 35 | #define MIPS34K_MISSED_ITLB_WAR 0 | ||
| 36 | |||
| 37 | #endif /* __ASM_MIPS_MACH_SIBYTE_WAR_H */ | ||