diff options
Diffstat (limited to 'include/asm-m32r/system.h')
| -rw-r--r-- | include/asm-m32r/system.h | 22 | 
1 files changed, 16 insertions, 6 deletions
| diff --git a/include/asm-m32r/system.h b/include/asm-m32r/system.h index 5eee832b73a0..06c12a037cba 100644 --- a/include/asm-m32r/system.h +++ b/include/asm-m32r/system.h | |||
| @@ -68,13 +68,23 @@ | |||
| 68 | last = __last; \ | 68 | last = __last; \ | 
| 69 | } while(0) | 69 | } while(0) | 
| 70 | 70 | ||
| 71 | /* | ||
| 72 | * On SMP systems, when the scheduler does migration-cost autodetection, | ||
| 73 | * it needs a way to flush as much of the CPU's caches as possible. | ||
| 74 | * | ||
| 75 | * TODO: fill this in! | ||
| 76 | */ | ||
| 77 | static inline void sched_cacheflush(void) | ||
| 78 | { | ||
| 79 | } | ||
| 80 | |||
| 71 | /* Interrupt Control */ | 81 | /* Interrupt Control */ | 
| 72 | #if !defined(CONFIG_CHIP_M32102) | 82 | #if !defined(CONFIG_CHIP_M32102) && !defined(CONFIG_CHIP_M32104) | 
| 73 | #define local_irq_enable() \ | 83 | #define local_irq_enable() \ | 
| 74 | __asm__ __volatile__ ("setpsw #0x40 -> nop": : :"memory") | 84 | __asm__ __volatile__ ("setpsw #0x40 -> nop": : :"memory") | 
| 75 | #define local_irq_disable() \ | 85 | #define local_irq_disable() \ | 
| 76 | __asm__ __volatile__ ("clrpsw #0x40 -> nop": : :"memory") | 86 | __asm__ __volatile__ ("clrpsw #0x40 -> nop": : :"memory") | 
| 77 | #else /* CONFIG_CHIP_M32102 */ | 87 | #else /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */ | 
| 78 | static inline void local_irq_enable(void) | 88 | static inline void local_irq_enable(void) | 
| 79 | { | 89 | { | 
| 80 | unsigned long tmpreg; | 90 | unsigned long tmpreg; | 
| @@ -96,7 +106,7 @@ static inline void local_irq_disable(void) | |||
| 96 | "mvtc %0, psw \n\t" | 106 | "mvtc %0, psw \n\t" | 
| 97 | : "=&r" (tmpreg0), "=&r" (tmpreg1) : : "cbit", "memory"); | 107 | : "=&r" (tmpreg0), "=&r" (tmpreg1) : : "cbit", "memory"); | 
| 98 | } | 108 | } | 
| 99 | #endif /* CONFIG_CHIP_M32102 */ | 109 | #endif /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */ | 
| 100 | 110 | ||
| 101 | #define local_save_flags(x) \ | 111 | #define local_save_flags(x) \ | 
| 102 | __asm__ __volatile__("mvfc %0,psw" : "=r"(x) : /* no input */) | 112 | __asm__ __volatile__("mvfc %0,psw" : "=r"(x) : /* no input */) | 
| @@ -105,13 +115,13 @@ static inline void local_irq_disable(void) | |||
| 105 | __asm__ __volatile__("mvtc %0,psw" : /* no outputs */ \ | 115 | __asm__ __volatile__("mvtc %0,psw" : /* no outputs */ \ | 
| 106 | : "r" (x) : "cbit", "memory") | 116 | : "r" (x) : "cbit", "memory") | 
| 107 | 117 | ||
| 108 | #if !defined(CONFIG_CHIP_M32102) | 118 | #if !(defined(CONFIG_CHIP_M32102) || defined(CONFIG_CHIP_M32104)) | 
| 109 | #define local_irq_save(x) \ | 119 | #define local_irq_save(x) \ | 
| 110 | __asm__ __volatile__( \ | 120 | __asm__ __volatile__( \ | 
| 111 | "mvfc %0, psw; \n\t" \ | 121 | "mvfc %0, psw; \n\t" \ | 
| 112 | "clrpsw #0x40 -> nop; \n\t" \ | 122 | "clrpsw #0x40 -> nop; \n\t" \ | 
| 113 | : "=r" (x) : /* no input */ : "memory") | 123 | : "=r" (x) : /* no input */ : "memory") | 
| 114 | #else /* CONFIG_CHIP_M32102 */ | 124 | #else /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */ | 
| 115 | #define local_irq_save(x) \ | 125 | #define local_irq_save(x) \ | 
| 116 | ({ \ | 126 | ({ \ | 
| 117 | unsigned long tmpreg; \ | 127 | unsigned long tmpreg; \ | 
| @@ -124,7 +134,7 @@ static inline void local_irq_disable(void) | |||
| 124 | : "=r" (x), "=&r" (tmpreg) \ | 134 | : "=r" (x), "=&r" (tmpreg) \ | 
| 125 | : : "cbit", "memory"); \ | 135 | : : "cbit", "memory"); \ | 
| 126 | }) | 136 | }) | 
| 127 | #endif /* CONFIG_CHIP_M32102 */ | 137 | #endif /* CONFIG_CHIP_M32102 || CONFIG_CHIP_M32104 */ | 
| 128 | 138 | ||
| 129 | #define irqs_disabled() \ | 139 | #define irqs_disabled() \ | 
| 130 | ({ \ | 140 | ({ \ | 
