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diff --git a/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_macros.h b/include/asm-cris/arch-v32/hwregs/iop/iop_mpu_macros.h
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1/* ************************************************************************* */
2/* This file is autogenerated by IOPASM Version 1.2 */
3/* DO NOT EDIT THIS FILE - All changes will be lost! */
4/* ************************************************************************* */
5
6
7
8#ifndef __IOP_MPU_MACROS_H__
9#define __IOP_MPU_MACROS_H__
10
11
12/* ************************************************************************* */
13/* REGISTER DEFINITIONS */
14/* ************************************************************************* */
15#define MPU_R0 (0x0)
16#define MPU_R1 (0x1)
17#define MPU_R2 (0x2)
18#define MPU_R3 (0x3)
19#define MPU_R4 (0x4)
20#define MPU_R5 (0x5)
21#define MPU_R6 (0x6)
22#define MPU_R7 (0x7)
23#define MPU_R8 (0x8)
24#define MPU_R9 (0x9)
25#define MPU_R10 (0xa)
26#define MPU_R11 (0xb)
27#define MPU_R12 (0xc)
28#define MPU_R13 (0xd)
29#define MPU_R14 (0xe)
30#define MPU_R15 (0xf)
31#define MPU_PC (0x2)
32#define MPU_WSTS (0x3)
33#define MPU_JADDR (0x4)
34#define MPU_IRP (0x5)
35#define MPU_SRP (0x6)
36#define MPU_T0 (0x8)
37#define MPU_T1 (0x9)
38#define MPU_T2 (0xa)
39#define MPU_T3 (0xb)
40#define MPU_I0 (0x10)
41#define MPU_I1 (0x11)
42#define MPU_I2 (0x12)
43#define MPU_I3 (0x13)
44#define MPU_I4 (0x14)
45#define MPU_I5 (0x15)
46#define MPU_I6 (0x16)
47#define MPU_I7 (0x17)
48#define MPU_I8 (0x18)
49#define MPU_I9 (0x19)
50#define MPU_I10 (0x1a)
51#define MPU_I11 (0x1b)
52#define MPU_I12 (0x1c)
53#define MPU_I13 (0x1d)
54#define MPU_I14 (0x1e)
55#define MPU_I15 (0x1f)
56#define MPU_P2 (0x2)
57#define MPU_P3 (0x3)
58#define MPU_P5 (0x5)
59#define MPU_P6 (0x6)
60#define MPU_P8 (0x8)
61#define MPU_P9 (0x9)
62#define MPU_P10 (0xa)
63#define MPU_P11 (0xb)
64#define MPU_P16 (0x10)
65#define MPU_P17 (0x12)
66#define MPU_P18 (0x12)
67#define MPU_P19 (0x13)
68#define MPU_P20 (0x14)
69#define MPU_P21 (0x15)
70#define MPU_P22 (0x16)
71#define MPU_P23 (0x17)
72#define MPU_P24 (0x18)
73#define MPU_P25 (0x19)
74#define MPU_P26 (0x1a)
75#define MPU_P27 (0x1b)
76#define MPU_P28 (0x1c)
77#define MPU_P29 (0x1d)
78#define MPU_P30 (0x1e)
79#define MPU_P31 (0x1f)
80#define MPU_P1 (0x1)
81#define MPU_REGA (0x1)
82
83
84
85/* ************************************************************************* */
86/* ADDRESS MACROS */
87/* ************************************************************************* */
88#define MK_DWORD_ADDR(ADDR) (ADDR >> 2)
89#define MK_BYTE_ADDR(ADDR) (ADDR)
90
91
92
93/* ************************************************************************* */
94/* INSTRUCTION MACROS */
95/* ************************************************************************* */
96#define MPU_ADD_RRR(S,N,D) (0x4000008C | ((S & ((1 << 5) - 1)) << 16)\
97 | ((N & ((1 << 5) - 1)) << 11)\
98 | ((D & ((1 << 5) - 1)) << 21))
99
100#define MPU_ADD_RRS(S,N,D) (0x4000048C | ((S & ((1 << 5) - 1)) << 16)\
101 | ((N & ((1 << 5) - 1)) << 11)\
102 | ((D & ((1 << 5) - 1)) << 21))
103
104#define MPU_ADD_RSR(S,N,D) (0x4000018C | ((S & ((1 << 5) - 1)) << 16)\
105 | ((N & ((1 << 5) - 1)) << 11)\
106 | ((D & ((1 << 5) - 1)) << 21))
107
108#define MPU_ADD_RSS(S,N,D) (0x4000058C | ((S & ((1 << 5) - 1)) << 16)\
109 | ((N & ((1 << 5) - 1)) << 11)\
110 | ((D & ((1 << 5) - 1)) << 21))
111
112#define MPU_ADD_SRR(S,N,D) (0x4000028C | ((S & ((1 << 5) - 1)) << 16)\
113 | ((N & ((1 << 5) - 1)) << 11)\
114 | ((D & ((1 << 5) - 1)) << 21))
115
116#define MPU_ADD_SRS(S,N,D) (0x4000068C | ((S & ((1 << 5) - 1)) << 16)\
117 | ((N & ((1 << 5) - 1)) << 11)\
118 | ((D & ((1 << 5) - 1)) << 21))
119
120#define MPU_ADD_SSR(S,N,D) (0x4000038C | ((S & ((1 << 5) - 1)) << 16)\
121 | ((N & ((1 << 5) - 1)) << 11)\
122 | ((D & ((1 << 5) - 1)) << 21))
123
124#define MPU_ADD_SSS(S,N,D) (0x4000078C | ((S & ((1 << 5) - 1)) << 16)\
125 | ((N & ((1 << 5) - 1)) << 11)\
126 | ((D & ((1 << 5) - 1)) << 21))
127
128#define MPU_ADDQ_RIR(S,N,D) (0x10000000 | ((S & ((1 << 5) - 1)) << 16)\
129 | ((N & ((1 << 16) - 1)) << 0)\
130 | ((D & ((1 << 5) - 1)) << 21))
131
132#define MPU_ADDQ_IRR(S,N,D) (0x10000000 | ((S & ((1 << 16) - 1)) << 0)\
133 | ((N & ((1 << 5) - 1)) << 16)\
134 | ((D & ((1 << 5) - 1)) << 21))
135
136#define MPU_ADDX_IRR_INSTR(S,N,D) (0xC000008C | ((N & ((1 << 5) - 1)) << 16)\
137 | ((D & ((1 << 5) - 1)) << 21))
138
139#define MPU_ADDX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF)
140
141#define MPU_ADDX_RIR_INSTR(S,N,D) (0xC000008C | ((S & ((1 << 5) - 1)) << 16)\
142 | ((D & ((1 << 5) - 1)) << 21))
143
144#define MPU_ADDX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF)
145
146#define MPU_ADDX_ISR_INSTR(S,N,D) (0xC000028C | ((N & ((1 << 5) - 1)) << 16)\
147 | ((D & ((1 << 5) - 1)) << 21))
148
149#define MPU_ADDX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF)
150
151#define MPU_ADDX_SIR_INSTR(S,N,D) (0xC000028C | ((S & ((1 << 5) - 1)) << 16)\
152 | ((D & ((1 << 5) - 1)) << 21))
153
154#define MPU_ADDX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF)
155
156#define MPU_ADDX_IRS_INSTR(S,N,D) (0xC000048C | ((N & ((1 << 5) - 1)) << 16)\
157 | ((D & ((1 << 5) - 1)) << 21))
158
159#define MPU_ADDX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF)
160
161#define MPU_ADDX_RIS_INSTR(S,N,D) (0xC000048C | ((S & ((1 << 5) - 1)) << 16)\
162 | ((D & ((1 << 5) - 1)) << 21))
163
164#define MPU_ADDX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF)
165
166#define MPU_ADDX_ISS_INSTR(S,N,D) (0xC000068C | ((N & ((1 << 5) - 1)) << 16)\
167 | ((D & ((1 << 5) - 1)) << 21))
168
169#define MPU_ADDX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF)
170
171#define MPU_ADDX_SIS_INSTR(S,N,D) (0xC000068C | ((S & ((1 << 5) - 1)) << 16)\
172 | ((D & ((1 << 5) - 1)) << 21))
173
174#define MPU_ADDX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF)
175
176#define MPU_AND_RRR(S,N,D) (0x4000008A | ((S & ((1 << 5) - 1)) << 16)\
177 | ((N & ((1 << 5) - 1)) << 11)\
178 | ((D & ((1 << 5) - 1)) << 21))
179
180#define MPU_AND_RRS(S,N,D) (0x4000048A | ((S & ((1 << 5) - 1)) << 16)\
181 | ((N & ((1 << 5) - 1)) << 11)\
182 | ((D & ((1 << 5) - 1)) << 21))
183
184#define MPU_AND_RSR(S,N,D) (0x4000018A | ((S & ((1 << 5) - 1)) << 16)\
185 | ((N & ((1 << 5) - 1)) << 11)\
186 | ((D & ((1 << 5) - 1)) << 21))
187
188#define MPU_AND_RSS(S,N,D) (0x4000058A | ((S & ((1 << 5) - 1)) << 16)\
189 | ((N & ((1 << 5) - 1)) << 11)\
190 | ((D & ((1 << 5) - 1)) << 21))
191
192#define MPU_AND_SRR(S,N,D) (0x4000028A | ((S & ((1 << 5) - 1)) << 16)\
193 | ((N & ((1 << 5) - 1)) << 11)\
194 | ((D & ((1 << 5) - 1)) << 21))
195
196#define MPU_AND_SRS(S,N,D) (0x4000068A | ((S & ((1 << 5) - 1)) << 16)\
197 | ((N & ((1 << 5) - 1)) << 11)\
198 | ((D & ((1 << 5) - 1)) << 21))
199
200#define MPU_AND_SSR(S,N,D) (0x4000038A | ((S & ((1 << 5) - 1)) << 16)\
201 | ((N & ((1 << 5) - 1)) << 11)\
202 | ((D & ((1 << 5) - 1)) << 21))
203
204#define MPU_AND_SSS(S,N,D) (0x4000078A | ((S & ((1 << 5) - 1)) << 16)\
205 | ((N & ((1 << 5) - 1)) << 11)\
206 | ((D & ((1 << 5) - 1)) << 21))
207
208#define MPU_ANDQ_RIR(S,N,D) (0x08000000 | ((S & ((1 << 5) - 1)) << 16)\
209 | ((N & ((1 << 16) - 1)) << 0)\
210 | ((D & ((1 << 5) - 1)) << 21))
211
212#define MPU_ANDQ_IRR(S,N,D) (0x08000000 | ((S & ((1 << 16) - 1)) << 0)\
213 | ((N & ((1 << 5) - 1)) << 16)\
214 | ((D & ((1 << 5) - 1)) << 21))
215
216#define MPU_ANDX_RIR_INSTR(S,N,D) (0xC000008A | ((S & ((1 << 5) - 1)) << 16)\
217 | ((D & ((1 << 5) - 1)) << 21))
218
219#define MPU_ANDX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF)
220
221#define MPU_ANDX_IRR_INSTR(S,N,D) (0xC000008A | ((N & ((1 << 5) - 1)) << 16)\
222 | ((D & ((1 << 5) - 1)) << 21))
223
224#define MPU_ANDX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF)
225
226#define MPU_ANDX_ISR_INSTR(S,N,D) (0xC000028A | ((N & ((1 << 5) - 1)) << 16)\
227 | ((D & ((1 << 5) - 1)) << 21))
228
229#define MPU_ANDX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF)
230
231#define MPU_ANDX_SIR_INSTR(S,N,D) (0xC000028A | ((S & ((1 << 5) - 1)) << 16)\
232 | ((D & ((1 << 5) - 1)) << 21))
233
234#define MPU_ANDX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF)
235
236#define MPU_ANDX_IRS_INSTR(S,N,D) (0xC000048A | ((N & ((1 << 5) - 1)) << 16)\
237 | ((D & ((1 << 5) - 1)) << 21))
238
239#define MPU_ANDX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF)
240
241#define MPU_ANDX_ISS_INSTR(S,N,D) (0xC000068A | ((N & ((1 << 5) - 1)) << 16)\
242 | ((D & ((1 << 5) - 1)) << 21))
243
244#define MPU_ANDX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF)
245
246#define MPU_ANDX_RIS_INSTR(S,N,D) (0xC000048A | ((S & ((1 << 5) - 1)) << 16)\
247 | ((D & ((1 << 5) - 1)) << 21))
248
249#define MPU_ANDX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF)
250
251#define MPU_ANDX_SIS_INSTR(S,N,D) (0xC000068A | ((S & ((1 << 5) - 1)) << 16)\
252 | ((D & ((1 << 5) - 1)) << 21))
253
254#define MPU_ANDX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF)
255
256#define MPU_BA_I(S) (0x60000000 | ((S & ((1 << 16) - 1)) << 0))
257
258#define MPU_BAR_R(S) (0x62000000 | ((S & ((1 << 5) - 1)) << 11))
259
260#define MPU_BAR_S(S) (0x63000000 | ((S & ((1 << 5) - 1)) << 11))
261
262#define MPU_BBC_RII(S,N,D) (0x78000000 | ((S & ((1 << 5) - 1)) << 16)\
263 | ((N & ((1 << 5) - 1)) << 21)\
264 | ((D & ((1 << 16) - 1)) << 0))
265
266#define MPU_BBS_RII(S,N,D) (0x7C000000 | ((S & ((1 << 5) - 1)) << 16)\
267 | ((N & ((1 << 5) - 1)) << 21)\
268 | ((D & ((1 << 16) - 1)) << 0))
269
270#define MPU_BNZ_RI(S,D) (0x74400000 | ((S & ((1 << 5) - 1)) << 16)\
271 | ((D & ((1 << 16) - 1)) << 0))
272
273#define MPU_BMI_RI(S,D) (0x7FE00000 | ((S & ((1 << 5) - 1)) << 16)\
274 | ((D & ((1 << 16) - 1)) << 0))
275
276#define MPU_BPL_RI(S,D) (0x7BE00000 | ((S & ((1 << 5) - 1)) << 16)\
277 | ((D & ((1 << 16) - 1)) << 0))
278
279#define MPU_BZ_RI(S,D) (0x74000000 | ((S & ((1 << 5) - 1)) << 16)\
280 | ((D & ((1 << 16) - 1)) << 0))
281
282#define MPU_DI() (0x40000001)
283
284#define MPU_EI() (0x40000003)
285
286#define MPU_HALT() (0x40000002)
287
288#define MPU_JIR_I(S) (0x60200000 | ((S & ((1 << 16) - 1)) << 0))
289
290#define MPU_JIR_R(S) (0x62200000 | ((S & ((1 << 5) - 1)) << 11))
291
292#define MPU_JIR_S(S) (0x63200000 | ((S & ((1 << 5) - 1)) << 11))
293
294#define MPU_JNT() (0x61000000)
295
296#define MPU_JSR_I(S) (0x60400000 | ((S & ((1 << 16) - 1)) << 0))
297
298#define MPU_JSR_R(S) (0x62400000 | ((S & ((1 << 5) - 1)) << 11))
299
300#define MPU_JSR_S(S) (0x63400000 | ((S & ((1 << 5) - 1)) << 11))
301
302#define MPU_LSL_RRR(S,N,D) (0x4000008E | ((S & ((1 << 5) - 1)) << 16)\
303 | ((N & ((1 << 5) - 1)) << 11)\
304 | ((D & ((1 << 5) - 1)) << 21))
305
306#define MPU_LSL_RRS(S,N,D) (0x4000048E | ((S & ((1 << 5) - 1)) << 16)\
307 | ((N & ((1 << 5) - 1)) << 11)\
308 | ((D & ((1 << 5) - 1)) << 21))
309
310#define MPU_LSL_RSR(S,N,D) (0x4000018E | ((S & ((1 << 5) - 1)) << 16)\
311 | ((N & ((1 << 5) - 1)) << 11)\
312 | ((D & ((1 << 5) - 1)) << 21))
313
314#define MPU_LSL_RSS(S,N,D) (0x4000058E | ((S & ((1 << 5) - 1)) << 16)\
315 | ((N & ((1 << 5) - 1)) << 11)\
316 | ((D & ((1 << 5) - 1)) << 21))
317
318#define MPU_LSL_SRR(S,N,D) (0x4000028E | ((S & ((1 << 5) - 1)) << 16)\
319 | ((N & ((1 << 5) - 1)) << 11)\
320 | ((D & ((1 << 5) - 1)) << 21))
321
322#define MPU_LSL_SRS(S,N,D) (0x4000068E | ((S & ((1 << 5) - 1)) << 16)\
323 | ((N & ((1 << 5) - 1)) << 11)\
324 | ((D & ((1 << 5) - 1)) << 21))
325
326#define MPU_LSL_SSR(S,N,D) (0x4000038E | ((S & ((1 << 5) - 1)) << 16)\
327 | ((N & ((1 << 5) - 1)) << 11)\
328 | ((D & ((1 << 5) - 1)) << 21))
329
330#define MPU_LSL_SSS(S,N,D) (0x4000078E | ((S & ((1 << 5) - 1)) << 16)\
331 | ((N & ((1 << 5) - 1)) << 11)\
332 | ((D & ((1 << 5) - 1)) << 21))
333
334#define MPU_LSLQ_RIR(S,N,D) (0x18000000 | ((S & ((1 << 5) - 1)) << 16)\
335 | ((N & ((1 << 16) - 1)) << 0)\
336 | ((D & ((1 << 5) - 1)) << 21))
337
338#define MPU_LSR_RRR(S,N,D) (0x4000008F | ((S & ((1 << 5) - 1)) << 16)\
339 | ((N & ((1 << 5) - 1)) << 11)\
340 | ((D & ((1 << 5) - 1)) << 21))
341
342#define MPU_LSR_RRS(S,N,D) (0x4000048F | ((S & ((1 << 5) - 1)) << 16)\
343 | ((N & ((1 << 5) - 1)) << 11)\
344 | ((D & ((1 << 5) - 1)) << 21))
345
346#define MPU_LSR_RSR(S,N,D) (0x4000018F | ((S & ((1 << 5) - 1)) << 16)\
347 | ((N & ((1 << 5) - 1)) << 11)\
348 | ((D & ((1 << 5) - 1)) << 21))
349
350#define MPU_LSR_RSS(S,N,D) (0x4000058F | ((S & ((1 << 5) - 1)) << 16)\
351 | ((N & ((1 << 5) - 1)) << 11)\
352 | ((D & ((1 << 5) - 1)) << 21))
353
354#define MPU_LSR_SRR(S,N,D) (0x4000028F | ((S & ((1 << 5) - 1)) << 16)\
355 | ((N & ((1 << 5) - 1)) << 11)\
356 | ((D & ((1 << 5) - 1)) << 21))
357
358#define MPU_LSR_SRS(S,N,D) (0x4000068F | ((S & ((1 << 5) - 1)) << 16)\
359 | ((N & ((1 << 5) - 1)) << 11)\
360 | ((D & ((1 << 5) - 1)) << 21))
361
362#define MPU_LSR_SSR(S,N,D) (0x4000038F | ((S & ((1 << 5) - 1)) << 16)\
363 | ((N & ((1 << 5) - 1)) << 11)\
364 | ((D & ((1 << 5) - 1)) << 21))
365
366#define MPU_LSR_SSS(S,N,D) (0x4000078F | ((S & ((1 << 5) - 1)) << 16)\
367 | ((N & ((1 << 5) - 1)) << 11)\
368 | ((D & ((1 << 5) - 1)) << 21))
369
370#define MPU_LSRQ_RIR(S,N,D) (0x1C000000 | ((S & ((1 << 5) - 1)) << 16)\
371 | ((N & ((1 << 16) - 1)) << 0)\
372 | ((D & ((1 << 5) - 1)) << 21))
373
374#define MPU_LW_IR(S,D) (0x64400000 | ((S & ((1 << 16) - 1)) << 0)\
375 | ((D & ((1 << 5) - 1)) << 16))
376
377#define MPU_LW_IS(S,D) (0x64600000 | ((S & ((1 << 16) - 1)) << 0)\
378 | ((D & ((1 << 5) - 1)) << 16))
379
380#define MPU_LW_RR(S,D) (0x66400000 | ((S & ((1 << 5) - 1)) << 11)\
381 | ((D & ((1 << 5) - 1)) << 16))
382
383#define MPU_LW_RS(S,D) (0x66600000 | ((S & ((1 << 5) - 1)) << 11)\
384 | ((D & ((1 << 5) - 1)) << 16))
385
386#define MPU_LW_SR(S,D) (0x67400000 | ((S & ((1 << 5) - 1)) << 11)\
387 | ((D & ((1 << 5) - 1)) << 16))
388
389#define MPU_LW_SS(S,D) (0x67600000 | ((S & ((1 << 5) - 1)) << 11)\
390 | ((D & ((1 << 5) - 1)) << 16))
391
392#define MPU_LW_RIR(S,N,D) (0x66400000 | ((S & ((1 << 5) - 1)) << 11)\
393 | ((N & ((1 << 8) - 1)) << 0)\
394 | ((D & ((1 << 5) - 1)) << 16))
395
396#define MPU_LW_RIS(S,N,D) (0x66600000 | ((S & ((1 << 5) - 1)) << 11)\
397 | ((N & ((1 << 8) - 1)) << 0)\
398 | ((D & ((1 << 5) - 1)) << 16))
399
400#define MPU_LW_SIR(S,N,D) (0x67400000 | ((S & ((1 << 5) - 1)) << 11)\
401 | ((N & ((1 << 8) - 1)) << 0)\
402 | ((D & ((1 << 5) - 1)) << 16))
403
404#define MPU_LW_SIS(S,N,D) (0x67600000 | ((S & ((1 << 5) - 1)) << 11)\
405 | ((N & ((1 << 8) - 1)) << 0)\
406 | ((D & ((1 << 5) - 1)) << 16))
407
408#define MPU_MOVE_RR(S,D) (0x40000081 | ((S & ((1 << 5) - 1)) << 11)\
409 | ((D & ((1 << 5) - 1)) << 21))
410
411#define MPU_MOVE_RS(S,D) (0x40000481 | ((S & ((1 << 5) - 1)) << 11)\
412 | ((D & ((1 << 5) - 1)) << 21))
413
414#define MPU_MOVE_SR(S,D) (0x40000181 | ((S & ((1 << 5) - 1)) << 11)\
415 | ((D & ((1 << 5) - 1)) << 21))
416
417#define MPU_MOVE_SS(S,D) (0x40000581 | ((S & ((1 << 5) - 1)) << 11)\
418 | ((D & ((1 << 5) - 1)) << 21))
419
420#define MPU_MOVEQ_IR(S,D) (0x24000000 | ((S & ((1 << 16) - 1)) << 0)\
421 | ((D & ((1 << 5) - 1)) << 21))
422
423#define MPU_MOVEQ_IS(S,D) (0x2C000000 | ((S & ((1 << 16) - 1)) << 0)\
424 | ((D & ((1 << 5) - 1)) << 21))
425
426#define MPU_MOVEX_IR_INSTR(S,D) (0xC0000081 | ((D & ((1 << 5) - 1)) << 21))
427
428#define MPU_MOVEX_IR_IMM(S,D) (S & 0xFFFFFFFF)
429
430#define MPU_MOVEX_IS_INSTR(S,D) (0xC0000481 | ((D & ((1 << 5) - 1)) << 21))
431
432#define MPU_MOVEX_IS_IMM(S,D) (S & 0xFFFFFFFF)
433
434#define MPU_NOP() (0x40000000)
435
436#define MPU_NOT_RR(S,D) (0x40100081 | ((S & ((1 << 5) - 1)) << 11)\
437 | ((D & ((1 << 5) - 1)) << 21))
438
439#define MPU_NOT_RS(S,D) (0x40100481 | ((S & ((1 << 5) - 1)) << 11)\
440 | ((D & ((1 << 5) - 1)) << 21))
441
442#define MPU_NOT_SR(S,D) (0x40100181 | ((S & ((1 << 5) - 1)) << 11)\
443 | ((D & ((1 << 5) - 1)) << 21))
444
445#define MPU_NOT_SS(S,D) (0x40100581 | ((S & ((1 << 5) - 1)) << 11)\
446 | ((D & ((1 << 5) - 1)) << 21))
447
448#define MPU_OR_RRR(S,N,D) (0x4000008B | ((S & ((1 << 5) - 1)) << 16)\
449 | ((N & ((1 << 5) - 1)) << 11)\
450 | ((D & ((1 << 5) - 1)) << 21))
451
452#define MPU_OR_RRS(S,N,D) (0x4000048B | ((S & ((1 << 5) - 1)) << 16)\
453 | ((N & ((1 << 5) - 1)) << 11)\
454 | ((D & ((1 << 5) - 1)) << 21))
455
456#define MPU_OR_RSR(S,N,D) (0x4000018B | ((S & ((1 << 5) - 1)) << 16)\
457 | ((N & ((1 << 5) - 1)) << 11)\
458 | ((D & ((1 << 5) - 1)) << 21))
459
460#define MPU_OR_RSS(S,N,D) (0x4000058B | ((S & ((1 << 5) - 1)) << 16)\
461 | ((N & ((1 << 5) - 1)) << 11)\
462 | ((D & ((1 << 5) - 1)) << 21))
463
464#define MPU_OR_SRR(S,N,D) (0x4000028B | ((S & ((1 << 5) - 1)) << 16)\
465 | ((N & ((1 << 5) - 1)) << 11)\
466 | ((D & ((1 << 5) - 1)) << 21))
467
468#define MPU_OR_SRS(S,N,D) (0x4000068B | ((S & ((1 << 5) - 1)) << 16)\
469 | ((N & ((1 << 5) - 1)) << 11)\
470 | ((D & ((1 << 5) - 1)) << 21))
471
472#define MPU_OR_SSR(S,N,D) (0x4000038B | ((S & ((1 << 5) - 1)) << 16)\
473 | ((N & ((1 << 5) - 1)) << 11)\
474 | ((D & ((1 << 5) - 1)) << 21))
475
476#define MPU_OR_SSS(S,N,D) (0x4000078B | ((S & ((1 << 5) - 1)) << 16)\
477 | ((N & ((1 << 5) - 1)) << 11)\
478 | ((D & ((1 << 5) - 1)) << 21))
479
480#define MPU_ORQ_RIR(S,N,D) (0x0C000000 | ((S & ((1 << 5) - 1)) << 16)\
481 | ((N & ((1 << 16) - 1)) << 0)\
482 | ((D & ((1 << 5) - 1)) << 21))
483
484#define MPU_ORQ_IRR(S,N,D) (0x0C000000 | ((S & ((1 << 16) - 1)) << 0)\
485 | ((N & ((1 << 5) - 1)) << 16)\
486 | ((D & ((1 << 5) - 1)) << 21))
487
488#define MPU_ORX_RIR_INSTR(S,N,D) (0xC000008B | ((S & ((1 << 5) - 1)) << 16)\
489 | ((D & ((1 << 5) - 1)) << 21))
490
491#define MPU_ORX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF)
492
493#define MPU_ORX_IRR_INSTR(S,N,D) (0xC000008B | ((N & ((1 << 5) - 1)) << 16)\
494 | ((D & ((1 << 5) - 1)) << 21))
495
496#define MPU_ORX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF)
497
498#define MPU_ORX_SIR_INSTR(S,N,D) (0xC000028B | ((S & ((1 << 5) - 1)) << 16)\
499 | ((D & ((1 << 5) - 1)) << 21))
500
501#define MPU_ORX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF)
502
503#define MPU_ORX_ISR_INSTR(S,N,D) (0xC000028B | ((N & ((1 << 5) - 1)) << 16)\
504 | ((D & ((1 << 5) - 1)) << 21))
505
506#define MPU_ORX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF)
507
508#define MPU_ORX_RIS_INSTR(S,N,D) (0xC000048B | ((S & ((1 << 5) - 1)) << 16)\
509 | ((D & ((1 << 5) - 1)) << 21))
510
511#define MPU_ORX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF)
512
513#define MPU_ORX_IRS_INSTR(S,N,D) (0xC000048B | ((N & ((1 << 5) - 1)) << 16)\
514 | ((D & ((1 << 5) - 1)) << 21))
515
516#define MPU_ORX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF)
517
518#define MPU_ORX_SIS_INSTR(S,N,D) (0xC000068B | ((S & ((1 << 5) - 1)) << 16)\
519 | ((D & ((1 << 5) - 1)) << 21))
520
521#define MPU_ORX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF)
522
523#define MPU_ORX_ISS_INSTR(S,N,D) (0xC000068B | ((N & ((1 << 5) - 1)) << 16)\
524 | ((D & ((1 << 5) - 1)) << 21))
525
526#define MPU_ORX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF)
527
528#define MPU_RET() (0x63003000)
529
530#define MPU_RETI() (0x63602800)
531
532#define MPU_RR_IR(S,D) (0x50000000 | ((S & ((1 << 11) - 1)) << 0)\
533 | ((D & ((1 << 5) - 1)) << 21))
534
535#define MPU_RR_SR(S,D) (0x50008000 | ((S & ((1 << 5) - 1)) << 16)\
536 | ((D & ((1 << 5) - 1)) << 21))
537
538#define MPU_RW_RI(S,D) (0x56000000 | ((S & ((1 << 5) - 1)) << 11)\
539 | ((D & ((1 << 11) - 1)) << 0))
540
541#define MPU_RW_RS(S,D) (0x57000000 | ((S & ((1 << 5) - 1)) << 11)\
542 | ((D & ((1 << 5) - 1)) << 16))
543
544#define MPU_RWQ_II(S,D) (0x58000000 | ((S & ((1 << 16) - 1)) << 11)\
545 | ((D & ((1 << 11) - 1)) << 0))
546
547#define MPU_RWQ_IS(S,D) (0x55000000 | ((S & ((1 << 16) - 1)) << 0)\
548 | ((D & ((1 << 5) - 1)) << 16))
549
550#define MPU_RWX_II_INSTR(S,D) (0xD4000000 | ((D & ((1 << 11) - 1)) << 0))
551
552#define MPU_RWX_II_IMM(S,D) (S & 0xFFFFFFFF)
553
554#define MPU_RWX_IS_INSTR(S,D) (0xD5000000 | ((D & ((1 << 5) - 1)) << 16))
555
556#define MPU_RWX_IS_IMM(S,D) (S & 0xFFFFFFFF)
557
558#define MPU_SUB_RRR(S,N,D) (0x4000008D | ((S & ((1 << 5) - 1)) << 16)\
559 | ((N & ((1 << 5) - 1)) << 11)\
560 | ((D & ((1 << 5) - 1)) << 21))
561
562#define MPU_SUB_RRS(S,N,D) (0x4000048D | ((S & ((1 << 5) - 1)) << 16)\
563 | ((N & ((1 << 5) - 1)) << 11)\
564 | ((D & ((1 << 5) - 1)) << 21))
565
566#define MPU_SUB_RSR(S,N,D) (0x4000018D | ((S & ((1 << 5) - 1)) << 16)\
567 | ((N & ((1 << 5) - 1)) << 11)\
568 | ((D & ((1 << 5) - 1)) << 21))
569
570#define MPU_SUB_RSS(S,N,D) (0x4000058D | ((S & ((1 << 5) - 1)) << 16)\
571 | ((N & ((1 << 5) - 1)) << 11)\
572 | ((D & ((1 << 5) - 1)) << 21))
573
574#define MPU_SUB_SRR(S,N,D) (0x4000028D | ((S & ((1 << 5) - 1)) << 16)\
575 | ((N & ((1 << 5) - 1)) << 11)\
576 | ((D & ((1 << 5) - 1)) << 21))
577
578#define MPU_SUB_SRS(S,N,D) (0x4000068D | ((S & ((1 << 5) - 1)) << 16)\
579 | ((N & ((1 << 5) - 1)) << 11)\
580 | ((D & ((1 << 5) - 1)) << 21))
581
582#define MPU_SUB_SSR(S,N,D) (0x4000038D | ((S & ((1 << 5) - 1)) << 16)\
583 | ((N & ((1 << 5) - 1)) << 11)\
584 | ((D & ((1 << 5) - 1)) << 21))
585
586#define MPU_SUB_SSS(S,N,D) (0x4000078D | ((S & ((1 << 5) - 1)) << 16)\
587 | ((N & ((1 << 5) - 1)) << 11)\
588 | ((D & ((1 << 5) - 1)) << 21))
589
590#define MPU_SUBQ_RIR(S,N,D) (0x14000000 | ((S & ((1 << 5) - 1)) << 16)\
591 | ((N & ((1 << 16) - 1)) << 0)\
592 | ((D & ((1 << 5) - 1)) << 21))
593
594#define MPU_SUBX_RIR_INSTR(S,N,D) (0xC000008D | ((S & ((1 << 5) - 1)) << 16)\
595 | ((D & ((1 << 5) - 1)) << 21))
596
597#define MPU_SUBX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF)
598
599#define MPU_SUBX_SIR_INSTR(S,N,D) (0xC000028D | ((S & ((1 << 5) - 1)) << 16)\
600 | ((D & ((1 << 5) - 1)) << 21))
601
602#define MPU_SUBX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF)
603
604#define MPU_SUBX_RIS_INSTR(S,N,D) (0xC000048D | ((S & ((1 << 5) - 1)) << 16)\
605 | ((D & ((1 << 5) - 1)) << 21))
606
607#define MPU_SUBX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF)
608
609#define MPU_SUBX_SIS_INSTR(S,N,D) (0xC000068D | ((S & ((1 << 5) - 1)) << 16)\
610 | ((D & ((1 << 5) - 1)) << 21))
611
612#define MPU_SUBX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF)
613
614#define MPU_SW_RI(S,D) (0x64000000 | ((S & ((1 << 5) - 1)) << 16)\
615 | ((D & ((1 << 16) - 1)) << 0))
616
617#define MPU_SW_SI(S,D) (0x64200000 | ((S & ((1 << 5) - 1)) << 16)\
618 | ((D & ((1 << 16) - 1)) << 0))
619
620#define MPU_SW_RR(S,D) (0x66000000 | ((S & ((1 << 5) - 1)) << 16)\
621 | ((D & ((1 << 5) - 1)) << 11))
622
623#define MPU_SW_SR(S,D) (0x66200000 | ((S & ((1 << 5) - 1)) << 16)\
624 | ((D & ((1 << 5) - 1)) << 11))
625
626#define MPU_SW_RS(S,D) (0x67000000 | ((S & ((1 << 5) - 1)) << 16)\
627 | ((D & ((1 << 5) - 1)) << 11))
628
629#define MPU_SW_SS(S,D) (0x67200000 | ((S & ((1 << 5) - 1)) << 16)\
630 | ((D & ((1 << 5) - 1)) << 11))
631
632#define MPU_SW_RIR(S,N,D) (0x66000000 | ((S & ((1 << 5) - 1)) << 16)\
633 | ((N & ((1 << 8) - 1)) << 0)\
634 | ((D & ((1 << 5) - 1)) << 11))
635
636#define MPU_SW_SIR(S,N,D) (0x66200000 | ((S & ((1 << 5) - 1)) << 16)\
637 | ((N & ((1 << 8) - 1)) << 0)\
638 | ((D & ((1 << 5) - 1)) << 11))
639
640#define MPU_SW_RIS(S,N,D) (0x67000000 | ((S & ((1 << 5) - 1)) << 16)\
641 | ((N & ((1 << 8) - 1)) << 0)\
642 | ((D & ((1 << 5) - 1)) << 11))
643
644#define MPU_SW_SIS(S,N,D) (0x67200000 | ((S & ((1 << 5) - 1)) << 16)\
645 | ((N & ((1 << 8) - 1)) << 0)\
646 | ((D & ((1 << 5) - 1)) << 11))
647
648#define MPU_SWX_II_INSTR(S,D) (0xE4000000 | ((D & ((1 << 16) - 1)) << 0))
649
650#define MPU_SWX_II_IMM(S,D) (S & 0xFFFFFFFF)
651
652#define MPU_SWX_IR_INSTR(S,D) (0xE6000000 | ((D & ((1 << 5) - 1)) << 11))
653
654#define MPU_SWX_IR_IMM(S,D) (S & 0xFFFFFFFF)
655
656#define MPU_SWX_IS_INSTR(S,D) (0xE7000000 | ((D & ((1 << 5) - 1)) << 11))
657
658#define MPU_SWX_IS_IMM(S,D) (S & 0xFFFFFFFF)
659
660#define MPU_SWX_IIR_INSTR(S,N,D) (0xE6000000 | ((N & ((1 << 8) - 1)) << 0)\
661 | ((D & ((1 << 5) - 1)) << 11))
662
663#define MPU_SWX_IIR_IMM(S,N,D) (S & 0xFFFFFFFF)
664
665#define MPU_SWX_IIS_INSTR(S,N,D) (0xE7000000 | ((N & ((1 << 8) - 1)) << 0)\
666 | ((D & ((1 << 5) - 1)) << 11))
667
668#define MPU_SWX_IIS_IMM(S,N,D) (S & 0xFFFFFFFF)
669
670#define MPU_XOR_RRR(S,N,D) (0x40000089 | ((S & ((1 << 5) - 1)) << 16)\
671 | ((N & ((1 << 5) - 1)) << 11)\
672 | ((D & ((1 << 5) - 1)) << 21))
673
674#define MPU_XOR_RRS(S,N,D) (0x40000489 | ((S & ((1 << 5) - 1)) << 16)\
675 | ((N & ((1 << 5) - 1)) << 11)\
676 | ((D & ((1 << 5) - 1)) << 21))
677
678#define MPU_XOR_RSR(S,N,D) (0x40000189 | ((S & ((1 << 5) - 1)) << 16)\
679 | ((N & ((1 << 5) - 1)) << 11)\
680 | ((D & ((1 << 5) - 1)) << 21))
681
682#define MPU_XOR_RSS(S,N,D) (0x40000589 | ((S & ((1 << 5) - 1)) << 16)\
683 | ((N & ((1 << 5) - 1)) << 11)\
684 | ((D & ((1 << 5) - 1)) << 21))
685
686#define MPU_XOR_SRR(S,N,D) (0x40000289 | ((S & ((1 << 5) - 1)) << 16)\
687 | ((N & ((1 << 5) - 1)) << 11)\
688 | ((D & ((1 << 5) - 1)) << 21))
689
690#define MPU_XOR_SRS(S,N,D) (0x40000689 | ((S & ((1 << 5) - 1)) << 16)\
691 | ((N & ((1 << 5) - 1)) << 11)\
692 | ((D & ((1 << 5) - 1)) << 21))
693
694#define MPU_XOR_SSR(S,N,D) (0x40000389 | ((S & ((1 << 5) - 1)) << 16)\
695 | ((N & ((1 << 5) - 1)) << 11)\
696 | ((D & ((1 << 5) - 1)) << 21))
697
698#define MPU_XOR_SSS(S,N,D) (0x40000789 | ((S & ((1 << 5) - 1)) << 16)\
699 | ((N & ((1 << 5) - 1)) << 11)\
700 | ((D & ((1 << 5) - 1)) << 21))
701
702#define MPU_XOR_RR(S,D) (0x40000088 | ((S & ((1 << 5) - 1)) << 11)\
703 | ((D & ((1 << 5) - 1)) << 21))
704
705#define MPU_XOR_RS(S,D) (0x40000488 | ((S & ((1 << 5) - 1)) << 11)\
706 | ((D & ((1 << 5) - 1)) << 21))
707
708#define MPU_XOR_SR(S,D) (0x40000188 | ((S & ((1 << 5) - 1)) << 11)\
709 | ((D & ((1 << 5) - 1)) << 21))
710
711#define MPU_XOR_SS(S,D) (0x40000588 | ((S & ((1 << 5) - 1)) << 11)\
712 | ((D & ((1 << 5) - 1)) << 21))
713
714#define MPU_XORQ_RIR(S,N,D) (0x04000000 | ((S & ((1 << 5) - 1)) << 16)\
715 | ((N & ((1 << 16) - 1)) << 0)\
716 | ((D & ((1 << 5) - 1)) << 21))
717
718#define MPU_XORQ_IRR(S,N,D) (0x04000000 | ((S & ((1 << 16) - 1)) << 0)\
719 | ((N & ((1 << 5) - 1)) << 16)\
720 | ((D & ((1 << 5) - 1)) << 21))
721
722#define MPU_XORX_RIR_INSTR(S,N,D) (0xC0000089 | ((S & ((1 << 5) - 1)) << 16)\
723 | ((D & ((1 << 5) - 1)) << 21))
724
725#define MPU_XORX_RIR_IMM(S,N,D) (N & 0xFFFFFFFF)
726
727#define MPU_XORX_IRR_INSTR(S,N,D) (0xC0000089 | ((N & ((1 << 5) - 1)) << 16)\
728 | ((D & ((1 << 5) - 1)) << 21))
729
730#define MPU_XORX_IRR_IMM(S,N,D) (S & 0xFFFFFFFF)
731
732#define MPU_XORX_SIR_INSTR(S,N,D) (0xC0000289 | ((S & ((1 << 5) - 1)) << 16)\
733 | ((D & ((1 << 5) - 1)) << 21))
734
735#define MPU_XORX_SIR_IMM(S,N,D) (N & 0xFFFFFFFF)
736
737#define MPU_XORX_ISR_INSTR(S,N,D) (0xC0000289 | ((N & ((1 << 5) - 1)) << 16)\
738 | ((D & ((1 << 5) - 1)) << 21))
739
740#define MPU_XORX_ISR_IMM(S,N,D) (S & 0xFFFFFFFF)
741
742#define MPU_XORX_RIS_INSTR(S,N,D) (0xC0000489 | ((S & ((1 << 5) - 1)) << 16)\
743 | ((D & ((1 << 5) - 1)) << 21))
744
745#define MPU_XORX_RIS_IMM(S,N,D) (N & 0xFFFFFFFF)
746
747#define MPU_XORX_IRS_INSTR(S,N,D) (0xC0000489 | ((N & ((1 << 5) - 1)) << 16)\
748 | ((D & ((1 << 5) - 1)) << 21))
749
750#define MPU_XORX_IRS_IMM(S,N,D) (S & 0xFFFFFFFF)
751
752#define MPU_XORX_SIS_INSTR(S,N,D) (0xC0000689 | ((S & ((1 << 5) - 1)) << 16)\
753 | ((D & ((1 << 5) - 1)) << 21))
754
755#define MPU_XORX_SIS_IMM(S,N,D) (N & 0xFFFFFFFF)
756
757#define MPU_XORX_ISS_INSTR(S,N,D) (0xC0000689 | ((N & ((1 << 5) - 1)) << 16)\
758 | ((D & ((1 << 5) - 1)) << 21))
759
760#define MPU_XORX_ISS_IMM(S,N,D) (S & 0xFFFFFFFF)
761
762
763#endif /* end of __IOP_MPU_MACROS_H__ */
764/* End of iop_mpu_macros.h */
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