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-rw-r--r--include/asm-blackfin/mach-bf537/bfin_sir.h21
-rw-r--r--include/asm-blackfin/mach-bf537/defBF537.h1
-rw-r--r--include/asm-blackfin/mach-bf537/mem_init.h27
3 files changed, 16 insertions, 33 deletions
diff --git a/include/asm-blackfin/mach-bf537/bfin_sir.h b/include/asm-blackfin/mach-bf537/bfin_sir.h
index 0612d0c9501c..cfd8ad4f1f2c 100644
--- a/include/asm-blackfin/mach-bf537/bfin_sir.h
+++ b/include/asm-blackfin/mach-bf537/bfin_sir.h
@@ -118,16 +118,25 @@ static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port)
118 118
119#define DRIVER_NAME "bfin_sir" 119#define DRIVER_NAME "bfin_sir"
120 120
121static void bfin_sir_hw_init(void) 121static int bfin_sir_hw_init(void)
122{ 122{
123 int ret = -ENODEV;
123#ifdef CONFIG_BFIN_SIR0 124#ifdef CONFIG_BFIN_SIR0
124 peripheral_request(P_UART0_TX, DRIVER_NAME); 125 ret = peripheral_request(P_UART0_TX, DRIVER_NAME);
125 peripheral_request(P_UART0_RX, DRIVER_NAME); 126 if (ret)
127 return ret;
128 ret = peripheral_request(P_UART0_RX, DRIVER_NAME);
129 if (ret)
130 return ret;
126#endif 131#endif
127 132
128#ifdef CONFIG_BFIN_SIR1 133#ifdef CONFIG_BFIN_SIR1
129 peripheral_request(P_UART1_TX, DRIVER_NAME); 134 ret = peripheral_request(P_UART1_TX, DRIVER_NAME);
130 peripheral_request(P_UART1_RX, DRIVER_NAME); 135 if (ret)
136 return ret;
137 ret = peripheral_request(P_UART1_RX, DRIVER_NAME);
138 if (ret)
139 return ret;
131#endif 140#endif
132 SSYNC(); 141 return ret;
133} 142}
diff --git a/include/asm-blackfin/mach-bf537/defBF537.h b/include/asm-blackfin/mach-bf537/defBF537.h
index 3f455909c418..abde24c6d3b1 100644
--- a/include/asm-blackfin/mach-bf537/defBF537.h
+++ b/include/asm-blackfin/mach-bf537/defBF537.h
@@ -290,6 +290,7 @@
290#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */ 290#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */
291#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */ 291#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */
292#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */ 292#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
293#define TXDWA 0x00000010 /* Transmit Frame DMA Word Alignment (Odd/Even*) */
293#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */ 294#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
294 295
295#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */ 296#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */
diff --git a/include/asm-blackfin/mach-bf537/mem_init.h b/include/asm-blackfin/mach-bf537/mem_init.h
index 9ad979d416c6..f67698f670ca 100644
--- a/include/asm-blackfin/mach-bf537/mem_init.h
+++ b/include/asm-blackfin/mach-bf537/mem_init.h
@@ -139,33 +139,6 @@
139#define SDRAM_CL CL_3 139#define SDRAM_CL CL_3
140#endif 140#endif
141 141
142#if (CONFIG_MEM_SIZE == 128)
143#define SDRAM_SIZE EBSZ_128
144#endif
145#if (CONFIG_MEM_SIZE == 64)
146#define SDRAM_SIZE EBSZ_64
147#endif
148#if (CONFIG_MEM_SIZE == 32)
149#define SDRAM_SIZE EBSZ_32
150#endif
151#if (CONFIG_MEM_SIZE == 16)
152#define SDRAM_SIZE EBSZ_16
153#endif
154#if (CONFIG_MEM_ADD_WIDTH == 11)
155#define SDRAM_WIDTH EBCAW_11
156#endif
157#if (CONFIG_MEM_ADD_WIDTH == 10)
158#define SDRAM_WIDTH EBCAW_10
159#endif
160#if (CONFIG_MEM_ADD_WIDTH == 9)
161#define SDRAM_WIDTH EBCAW_9
162#endif
163#if (CONFIG_MEM_ADD_WIDTH == 8)
164#define SDRAM_WIDTH EBCAW_8
165#endif
166
167#define mem_SDBCTL (SDRAM_WIDTH | SDRAM_SIZE | EBE)
168
169/* Equation from section 17 (p17-46) of BF533 HRM */ 142/* Equation from section 17 (p17-46) of BF533 HRM */
170#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num) 143#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
171 144