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-rw-r--r--include/asm-arm/arch-pxa/pxa3xx-regs.h86
1 files changed, 86 insertions, 0 deletions
diff --git a/include/asm-arm/arch-pxa/pxa3xx-regs.h b/include/asm-arm/arch-pxa/pxa3xx-regs.h
index 3900a0ca0bc0..66d54119757c 100644
--- a/include/asm-arm/arch-pxa/pxa3xx-regs.h
+++ b/include/asm-arm/arch-pxa/pxa3xx-regs.h
@@ -14,6 +14,92 @@
14#define __ASM_ARCH_PXA3XX_REGS_H 14#define __ASM_ARCH_PXA3XX_REGS_H
15 15
16/* 16/*
17 * Slave Power Managment Unit
18 */
19#define ASCR __REG(0x40f40000) /* Application Subsystem Power Status/Configuration */
20#define ARSR __REG(0x40f40004) /* Application Subsystem Reset Status */
21#define AD3ER __REG(0x40f40008) /* Application Subsystem Wake-Up from D3 Enable */
22#define AD3SR __REG(0x40f4000c) /* Application Subsystem Wake-Up from D3 Status */
23#define AD2D0ER __REG(0x40f40010) /* Application Subsystem Wake-Up from D2 to D0 Enable */
24#define AD2D0SR __REG(0x40f40014) /* Application Subsystem Wake-Up from D2 to D0 Status */
25#define AD2D1ER __REG(0x40f40018) /* Application Subsystem Wake-Up from D2 to D1 Enable */
26#define AD2D1SR __REG(0x40f4001c) /* Application Subsystem Wake-Up from D2 to D1 Status */
27#define AD1D0ER __REG(0x40f40020) /* Application Subsystem Wake-Up from D1 to D0 Enable */
28#define AD1D0SR __REG(0x40f40024) /* Application Subsystem Wake-Up from D1 to D0 Status */
29#define AGENP __REG(0x40f4002c) /* Application Subsystem General Purpose */
30#define AD3R __REG(0x40f40030) /* Application Subsystem D3 Configuration */
31#define AD2R __REG(0x40f40034) /* Application Subsystem D2 Configuration */
32#define AD1R __REG(0x40f40038) /* Application Subsystem D1 Configuration */
33
34/*
35 * Application Subsystem Configuration bits.
36 */
37#define ASCR_RDH (1 << 31)
38#define ASCR_D1S (1 << 2)
39#define ASCR_D2S (1 << 1)
40#define ASCR_D3S (1 << 0)
41
42/*
43 * Application Reset Status bits.
44 */
45#define ARSR_GPR (1 << 3)
46#define ARSR_LPMR (1 << 2)
47#define ARSR_WDT (1 << 1)
48#define ARSR_HWR (1 << 0)
49
50/*
51 * Application Subsystem Wake-Up bits.
52 */
53#define ADXER_WRTC (1 << 31) /* RTC */
54#define ADXER_WOST (1 << 30) /* OS Timer */
55#define ADXER_WTSI (1 << 29) /* Touchscreen */
56#define ADXER_WUSBH (1 << 28) /* USB host */
57#define ADXER_WUSB2 (1 << 26) /* USB client 2.0 */
58#define ADXER_WMSL0 (1 << 24) /* MSL port 0*/
59#define ADXER_WDMUX3 (1 << 23) /* USB EDMUX3 */
60#define ADXER_WDMUX2 (1 << 22) /* USB EDMUX2 */
61#define ADXER_WKP (1 << 21) /* Keypad */
62#define ADXER_WUSIM1 (1 << 20) /* USIM Port 1 */
63#define ADXER_WUSIM0 (1 << 19) /* USIM Port 0 */
64#define ADXER_WOTG (1 << 16) /* USBOTG input */
65#define ADXER_MFP_WFLASH (1 << 15) /* MFP: Data flash busy */
66#define ADXER_MFP_GEN12 (1 << 14) /* MFP: MMC3/GPIO/OST inputs */
67#define ADXER_MFP_WMMC2 (1 << 13) /* MFP: MMC2 */
68#define ADXER_MFP_WMMC1 (1 << 12) /* MFP: MMC1 */
69#define ADXER_MFP_WI2C (1 << 11) /* MFP: I2C */
70#define ADXER_MFP_WSSP4 (1 << 10) /* MFP: SSP4 */
71#define ADXER_MFP_WSSP3 (1 << 9) /* MFP: SSP3 */
72#define ADXER_MFP_WMAXTRIX (1 << 8) /* MFP: matrix keypad */
73#define ADXER_MFP_WUART3 (1 << 7) /* MFP: UART3 */
74#define ADXER_MFP_WUART2 (1 << 6) /* MFP: UART2 */
75#define ADXER_MFP_WUART1 (1 << 5) /* MFP: UART1 */
76#define ADXER_MFP_WSSP2 (1 << 4) /* MFP: SSP2 */
77#define ADXER_MFP_WSSP1 (1 << 3) /* MFP: SSP1 */
78#define ADXER_MFP_WAC97 (1 << 2) /* MFP: AC97 */
79#define ADXER_WEXTWAKE1 (1 << 1) /* External Wake 1 */
80#define ADXER_WEXTWAKE0 (1 << 0) /* External Wake 0 */
81
82/*
83 * AD3R/AD2R/AD1R bits. R2-R5 are only defined for PXA320.
84 */
85#define ADXR_L2 (1 << 8)
86#define ADXR_R5 (1 << 5)
87#define ADXR_R4 (1 << 4)
88#define ADXR_R3 (1 << 3)
89#define ADXR_R2 (1 << 2)
90#define ADXR_R1 (1 << 1)
91#define ADXR_R0 (1 << 0)
92
93/*
94 * Values for PWRMODE CP15 register
95 */
96#define PXA3xx_PM_S3D4C4 0x07 /* aka deep sleep */
97#define PXA3xx_PM_S2D3C4 0x06 /* aka sleep */
98#define PXA3xx_PM_S0D2C2 0x03 /* aka standby */
99#define PXA3xx_PM_S0D1C2 0x02 /* aka LCD refresh */
100#define PXA3xx_PM_S0D0C1 0x01
101
102/*
17 * Application Subsystem Clock 103 * Application Subsystem Clock
18 */ 104 */
19#define ACCR __REG(0x41340000) /* Application Subsystem Clock Configuration Register */ 105#define ACCR __REG(0x41340000) /* Application Subsystem Clock Configuration Register */