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-rw-r--r--include/asm-arm/arch-at91/at91_adc.h61
-rw-r--r--include/asm-arm/arch-at91/board.h12
-rw-r--r--include/asm-arm/arch-imx/imx-regs.h118
-rw-r--r--include/asm-arm/arch-iop13xx/iop13xx.h24
-rw-r--r--include/asm-arm/arch-iop13xx/time.h56
-rw-r--r--include/asm-arm/arch-iop32x/iop32x.h9
-rw-r--r--include/asm-arm/arch-iop32x/memory.h4
-rw-r--r--include/asm-arm/arch-iop33x/iop33x.h10
-rw-r--r--include/asm-arm/arch-iop33x/memory.h4
-rw-r--r--include/asm-arm/arch-netx/netx-regs.h4
-rw-r--r--include/asm-arm/arch-ns9xxx/board.h2
-rw-r--r--include/asm-arm/arch-ns9xxx/clock.h34
-rw-r--r--include/asm-arm/arch-ns9xxx/hardware.h5
-rw-r--r--include/asm-arm/arch-ns9xxx/processor.h3
-rw-r--r--include/asm-arm/arch-ns9xxx/regs-sys.h6
-rw-r--r--include/asm-arm/arch-pxa/i2c.h1
-rw-r--r--include/asm-arm/arch-pxa/pxa-regs.h58
-rw-r--r--include/asm-arm/arch-s3c2410/regs-ac97.h56
-rw-r--r--include/asm-arm/arch-s3c2410/regs-udc.h6
-rw-r--r--include/asm-arm/ecard.h52
-rw-r--r--include/asm-arm/hardware/iop3xx.h24
-rw-r--r--include/asm-arm/plat-s3c24xx/clock.h1
-rw-r--r--include/asm-arm/plat-s3c24xx/cpu.h16
-rw-r--r--include/asm-arm/ptrace.h10
-rw-r--r--include/asm-arm/thread_info.h1
25 files changed, 319 insertions, 258 deletions
diff --git a/include/asm-arm/arch-at91/at91_adc.h b/include/asm-arm/arch-at91/at91_adc.h
new file mode 100644
index 000000000000..1ed66eaaf83a
--- /dev/null
+++ b/include/asm-arm/arch-at91/at91_adc.h
@@ -0,0 +1,61 @@
1/*
2 * include/asm-arm/arch-at91/at91_adc.h
3 *
4 * Copyright (C) SAN People
5 *
6 * Analog-to-Digital Converter (ADC) registers.
7 * Based on AT91SAM9260 datasheet revision D.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#ifndef AT91_ADC_H
16#define AT91_ADC_H
17
18#define AT91_ADC_CR 0x00 /* Control Register */
19#define AT91_ADC_SWRST (1 << 0) /* Software Reset */
20#define AT91_ADC_START (1 << 1) /* Start Conversion */
21
22#define AT91_ADC_MR 0x04 /* Mode Register */
23#define AT91_ADC_TRGEN (1 << 0) /* Trigger Enable */
24#define AT91_ADC_TRGSEL (7 << 1) /* Trigger Selection */
25#define AT91_ADC_TRGSEL_TC0 (0 << 1)
26#define AT91_ADC_TRGSEL_TC1 (1 << 1)
27#define AT91_ADC_TRGSEL_TC2 (2 << 1)
28#define AT91_ADC_TRGSEL_EXTERNAL (6 << 1)
29#define AT91_ADC_LOWRES (1 << 4) /* Low Resolution */
30#define AT91_ADC_SLEEP (1 << 5) /* Sleep Mode */
31#define AT91_ADC_PRESCAL (0x3f << 8) /* Prescalar Rate Selection */
32#define AT91_ADC_PRESCAL_(x) ((x) << 8)
33#define AT91_ADC_STARTUP (0x1f << 16) /* Startup Up Time */
34#define AT91_ADC_STARTUP_(x) ((x) << 16)
35#define AT91_ADC_SHTIM (0xf << 24) /* Sample & Hold Time */
36#define AT91_ADC_SHTIM_(x) ((x) << 24)
37
38#define AT91_ADC_CHER 0x10 /* Channel Enable Register */
39#define AT91_ADC_CHDR 0x14 /* Channel Disable Register */
40#define AT91_ADC_CHSR 0x18 /* Channel Status Register */
41#define AT91_ADC_CH(n) (1 << (n)) /* Channel Number */
42
43#define AT91_ADC_SR 0x1C /* Status Register */
44#define AT91_ADC_EOC(n) (1 << (n)) /* End of Conversion on Channel N */
45#define AT91_ADC_OVRE(n) (1 << ((n) + 8))/* Overrun Error on Channel N */
46#define AT91_ADC_DRDY (1 << 16) /* Data Ready */
47#define AT91_ADC_GOVRE (1 << 17) /* General Overrun Error */
48#define AT91_ADC_ENDRX (1 << 18) /* End of RX Buffer */
49#define AT91_ADC_RXFUFF (1 << 19) /* RX Buffer Full */
50
51#define AT91_ADC_LCDR 0x20 /* Last Converted Data Register */
52#define AT91_ADC_LDATA (0x3ff)
53
54#define AT91_ADC_IER 0x24 /* Interrupt Enable Register */
55#define AT91_ADC_IDR 0x28 /* Interrupt Disable Register */
56#define AT91_ADC_IMR 0x2C /* Interrupt Mask Register */
57
58#define AT91_ADC_CHR(n) (0x30 + ((n) * 4) /* Channel Data Register N */
59#define AT91_ADC_DATA (0x3ff)
60
61#endif
diff --git a/include/asm-arm/arch-at91/board.h b/include/asm-arm/arch-at91/board.h
index 7b9903c2c447..7a34a5b1fed0 100644
--- a/include/asm-arm/arch-at91/board.h
+++ b/include/asm-arm/arch-at91/board.h
@@ -62,7 +62,7 @@ struct at91_mmc_data {
62}; 62};
63extern void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data); 63extern void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data);
64 64
65 /* Ethernet */ 65 /* Ethernet (EMAC & MACB) */
66struct at91_eth_data { 66struct at91_eth_data {
67 u8 phy_irq_pin; /* PHY IRQ */ 67 u8 phy_irq_pin; /* PHY IRQ */
68 u8 is_rmii; /* using RMII interface? */ 68 u8 is_rmii; /* using RMII interface? */
@@ -114,6 +114,16 @@ struct atmel_uart_data {
114}; 114};
115extern void __init at91_add_device_serial(void); 115extern void __init at91_add_device_serial(void);
116 116
117 /* LCD Controller */
118struct atmel_lcdfb_info;
119extern void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data);
120
121 /* AC97 */
122struct atmel_ac97_data {
123 u8 reset_pin; /* reset */
124}
125extern void __init at91_add_device_ac97(struct atmel_ac97_data *data);
126
117 /* LEDs */ 127 /* LEDs */
118extern u8 at91_leds_cpu; 128extern u8 at91_leds_cpu;
119extern u8 at91_leds_timer; 129extern u8 at91_leds_timer;
diff --git a/include/asm-arm/arch-imx/imx-regs.h b/include/asm-arm/arch-imx/imx-regs.h
index e56a4e247d62..de6494a4dc6b 100644
--- a/include/asm-arm/arch-imx/imx-regs.h
+++ b/include/asm-arm/arch-imx/imx-regs.h
@@ -477,122 +477,4 @@
477#define LCDISR_EOF (1<<1) 477#define LCDISR_EOF (1<<1)
478#define LCDISR_BOF (1<<0) 478#define LCDISR_BOF (1<<0)
479 479
480/*
481 * UART Module. Takes the UART base address as argument
482 */
483#define URXD0(x) __REG( 0x0 + (x)) /* Receiver Register */
484#define URTX0(x) __REG( 0x40 + (x)) /* Transmitter Register */
485#define UCR1(x) __REG( 0x80 + (x)) /* Control Register 1 */
486#define UCR2(x) __REG( 0x84 + (x)) /* Control Register 2 */
487#define UCR3(x) __REG( 0x88 + (x)) /* Control Register 3 */
488#define UCR4(x) __REG( 0x8c + (x)) /* Control Register 4 */
489#define UFCR(x) __REG( 0x90 + (x)) /* FIFO Control Register */
490#define USR1(x) __REG( 0x94 + (x)) /* Status Register 1 */
491#define USR2(x) __REG( 0x98 + (x)) /* Status Register 2 */
492#define UESC(x) __REG( 0x9c + (x)) /* Escape Character Register */
493#define UTIM(x) __REG( 0xa0 + (x)) /* Escape Timer Register */
494#define UBIR(x) __REG( 0xa4 + (x)) /* BRM Incremental Register */
495#define UBMR(x) __REG( 0xa8 + (x)) /* BRM Modulator Register */
496#define UBRC(x) __REG( 0xac + (x)) /* Baud Rate Count Register */
497#define BIPR1(x) __REG( 0xb0 + (x)) /* Incremental Preset Register 1 */
498#define BIPR2(x) __REG( 0xb4 + (x)) /* Incremental Preset Register 2 */
499#define BIPR3(x) __REG( 0xb8 + (x)) /* Incremental Preset Register 3 */
500#define BIPR4(x) __REG( 0xbc + (x)) /* Incremental Preset Register 4 */
501#define BMPR1(x) __REG( 0xc0 + (x)) /* BRM Modulator Register 1 */
502#define BMPR2(x) __REG( 0xc4 + (x)) /* BRM Modulator Register 2 */
503#define BMPR3(x) __REG( 0xc8 + (x)) /* BRM Modulator Register 3 */
504#define BMPR4(x) __REG( 0xcc + (x)) /* BRM Modulator Register 4 */
505#define UTS(x) __REG( 0xd0 + (x)) /* UART Test Register */
506
507/* UART Control Register Bit Fields.*/
508#define URXD_CHARRDY (1<<15)
509#define URXD_ERR (1<<14)
510#define URXD_OVRRUN (1<<13)
511#define URXD_FRMERR (1<<12)
512#define URXD_BRK (1<<11)
513#define URXD_PRERR (1<<10)
514#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
515#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
516#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
517#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
518#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
519#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
520#define UCR1_IREN (1<<7) /* Infrared interface enable */
521#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
522#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
523#define UCR1_SNDBRK (1<<4) /* Send break */
524#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
525#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
526#define UCR1_DOZE (1<<1) /* Doze */
527#define UCR1_UARTEN (1<<0) /* UART enabled */
528#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
529#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
530#define UCR2_CTSC (1<<13) /* CTS pin control */
531#define UCR2_CTS (1<<12) /* Clear to send */
532#define UCR2_ESCEN (1<<11) /* Escape enable */
533#define UCR2_PREN (1<<8) /* Parity enable */
534#define UCR2_PROE (1<<7) /* Parity odd/even */
535#define UCR2_STPB (1<<6) /* Stop */
536#define UCR2_WS (1<<5) /* Word size */
537#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
538#define UCR2_TXEN (1<<2) /* Transmitter enabled */
539#define UCR2_RXEN (1<<1) /* Receiver enabled */
540#define UCR2_SRST (1<<0) /* SW reset */
541#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
542#define UCR3_PARERREN (1<<12) /* Parity enable */
543#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
544#define UCR3_DSR (1<<10) /* Data set ready */
545#define UCR3_DCD (1<<9) /* Data carrier detect */
546#define UCR3_RI (1<<8) /* Ring indicator */
547#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
548#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
549#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
550#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
551#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
552#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
553#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
554#define UCR3_BPEN (1<<0) /* Preset registers enable */
555#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
556#define UCR4_INVR (1<<9) /* Inverted infrared reception */
557#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
558#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
559#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
560#define UCR4_IRSC (1<<5) /* IR special case */
561#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
562#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
563#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
564#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
565#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
566#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
567#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
568#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
569#define USR1_RTSS (1<<14) /* RTS pin status */
570#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
571#define USR1_RTSD (1<<12) /* RTS delta */
572#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
573#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
574#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
575#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
576#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
577#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
578#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
579#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
580#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
581#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
582#define USR2_IDLE (1<<12) /* Idle condition */
583#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
584#define USR2_WAKE (1<<7) /* Wake */
585#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
586#define USR2_TXDC (1<<3) /* Transmitter complete */
587#define USR2_BRCD (1<<2) /* Break condition */
588#define USR2_ORE (1<<1) /* Overrun error */
589#define USR2_RDR (1<<0) /* Recv data ready */
590#define UTS_FRCPERR (1<<13) /* Force parity error */
591#define UTS_LOOP (1<<12) /* Loop tx and rx */
592#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
593#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
594#define UTS_TXFULL (1<<4) /* TxFIFO full */
595#define UTS_RXFULL (1<<3) /* RxFIFO full */
596#define UTS_SOFTRST (1<<0) /* Software reset */
597
598#endif // _IMX_REGS_H 480#endif // _IMX_REGS_H
diff --git a/include/asm-arm/arch-iop13xx/iop13xx.h b/include/asm-arm/arch-iop13xx/iop13xx.h
index d26b755a9879..85707e9c3325 100644
--- a/include/asm-arm/arch-iop13xx/iop13xx.h
+++ b/include/asm-arm/arch-iop13xx/iop13xx.h
@@ -8,6 +8,7 @@ extern u32 iop13xx_atue_pmmr_offset;
8void iop13xx_init_irq(void); 8void iop13xx_init_irq(void);
9void iop13xx_map_io(void); 9void iop13xx_map_io(void);
10void iop13xx_platform_init(void); 10void iop13xx_platform_init(void);
11void iop13xx_add_tpmi_devices(void);
11void iop13xx_init_irq(void); 12void iop13xx_init_irq(void);
12 13
13/* CPUID CP6 R0 Page 0 */ 14/* CPUID CP6 R0 Page 0 */
@@ -27,19 +28,24 @@ static inline int iop13xx_cpu_id(void)
27#define IOP13XX_PCI_OFFSET IOP13XX_MAX_RAM_SIZE 28#define IOP13XX_PCI_OFFSET IOP13XX_MAX_RAM_SIZE
28 29
29/* PCI MAP 30/* PCI MAP
30 * 0x0000.0000 - 0x8000.0000 1:1 mapping with Physical RAM 31 * bus range cpu phys cpu virt note
31 * 0x8000.0000 - 0x8800.0000 PCIX/PCIE memory window (128MB) 32 * 0x0000.0000 + 2GB (n/a) (n/a) inbound, 1:1 mapping with Physical RAM
32*/ 33 * 0x8000.0000 + 928M 0x1.8000.0000 (ioremap) PCIX outbound memory window
34 * 0x8000.0000 + 928M 0x2.8000.0000 (ioremap) PCIE outbound memory window
35 *
36 * IO MAP
37 * 0x1000 + 64K 0x0.fffb.1000 0xfec6.1000 PCIX outbound i/o window
38 * 0x1000 + 64K 0x0.fffd.1000 0xfed7.1000 PCIE outbound i/o window
39 */
33#define IOP13XX_PCIX_IO_WINDOW_SIZE 0x10000UL 40#define IOP13XX_PCIX_IO_WINDOW_SIZE 0x10000UL
34#define IOP13XX_PCIX_LOWER_IO_PA 0xfffb0000UL 41#define IOP13XX_PCIX_LOWER_IO_PA 0xfffb0000UL
35#define IOP13XX_PCIX_LOWER_IO_VA 0xfec60000UL 42#define IOP13XX_PCIX_LOWER_IO_VA 0xfec60000UL
36#define IOP13XX_PCIX_LOWER_IO_BA 0x0fff0000UL 43#define IOP13XX_PCIX_LOWER_IO_BA 0x0UL /* OIOTVR */
44#define IOP13XX_PCIX_IO_BUS_OFFSET 0x1000UL
37#define IOP13XX_PCIX_UPPER_IO_PA (IOP13XX_PCIX_LOWER_IO_PA +\ 45#define IOP13XX_PCIX_UPPER_IO_PA (IOP13XX_PCIX_LOWER_IO_PA +\
38 IOP13XX_PCIX_IO_WINDOW_SIZE - 1) 46 IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
39#define IOP13XX_PCIX_UPPER_IO_VA (IOP13XX_PCIX_LOWER_IO_VA +\ 47#define IOP13XX_PCIX_UPPER_IO_VA (IOP13XX_PCIX_LOWER_IO_VA +\
40 IOP13XX_PCIX_IO_WINDOW_SIZE - 1) 48 IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
41#define IOP13XX_PCIX_IO_OFFSET (IOP13XX_PCIX_LOWER_IO_VA -\
42 IOP13XX_PCIX_LOWER_IO_BA)
43#define IOP13XX_PCIX_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\ 49#define IOP13XX_PCIX_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
44 (IOP13XX_PCIX_LOWER_IO_PA\ 50 (IOP13XX_PCIX_LOWER_IO_PA\
45 - IOP13XX_PCIX_LOWER_IO_VA)) 51 - IOP13XX_PCIX_LOWER_IO_VA))
@@ -65,15 +71,14 @@ static inline int iop13xx_cpu_id(void)
65#define IOP13XX_PCIE_IO_WINDOW_SIZE 0x10000UL 71#define IOP13XX_PCIE_IO_WINDOW_SIZE 0x10000UL
66#define IOP13XX_PCIE_LOWER_IO_PA 0xfffd0000UL 72#define IOP13XX_PCIE_LOWER_IO_PA 0xfffd0000UL
67#define IOP13XX_PCIE_LOWER_IO_VA 0xfed70000UL 73#define IOP13XX_PCIE_LOWER_IO_VA 0xfed70000UL
68#define IOP13XX_PCIE_LOWER_IO_BA 0x0fff0000UL 74#define IOP13XX_PCIE_LOWER_IO_BA 0x0UL /* OIOTVR */
75#define IOP13XX_PCIE_IO_BUS_OFFSET 0x1000UL
69#define IOP13XX_PCIE_UPPER_IO_PA (IOP13XX_PCIE_LOWER_IO_PA +\ 76#define IOP13XX_PCIE_UPPER_IO_PA (IOP13XX_PCIE_LOWER_IO_PA +\
70 IOP13XX_PCIE_IO_WINDOW_SIZE - 1) 77 IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
71#define IOP13XX_PCIE_UPPER_IO_VA (IOP13XX_PCIE_LOWER_IO_VA +\ 78#define IOP13XX_PCIE_UPPER_IO_VA (IOP13XX_PCIE_LOWER_IO_VA +\
72 IOP13XX_PCIE_IO_WINDOW_SIZE - 1) 79 IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
73#define IOP13XX_PCIE_UPPER_IO_BA (IOP13XX_PCIE_LOWER_IO_BA +\ 80#define IOP13XX_PCIE_UPPER_IO_BA (IOP13XX_PCIE_LOWER_IO_BA +\
74 IOP13XX_PCIE_IO_WINDOW_SIZE - 1) 81 IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
75#define IOP13XX_PCIE_IO_OFFSET (IOP13XX_PCIE_LOWER_IO_VA -\
76 IOP13XX_PCIE_LOWER_IO_BA)
77#define IOP13XX_PCIE_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\ 82#define IOP13XX_PCIE_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
78 (IOP13XX_PCIE_LOWER_IO_PA\ 83 (IOP13XX_PCIE_LOWER_IO_PA\
79 - IOP13XX_PCIE_LOWER_IO_VA)) 84 - IOP13XX_PCIE_LOWER_IO_VA))
@@ -451,4 +456,5 @@ static inline int iop13xx_cpu_id(void)
451#define IOP13XX_PBI_BAR1 IOP13XX_PBI_OFFSET(0x10) 456#define IOP13XX_PBI_BAR1 IOP13XX_PBI_OFFSET(0x10)
452#define IOP13XX_PBI_LR1 IOP13XX_PBI_OFFSET(0x14) 457#define IOP13XX_PBI_LR1 IOP13XX_PBI_OFFSET(0x14)
453 458
459#define IOP13XX_PROCESSOR_FREQ IOP13XX_REG_ADDR32(0x2180)
454#endif /* _IOP13XX_HW_H_ */ 460#endif /* _IOP13XX_HW_H_ */
diff --git a/include/asm-arm/arch-iop13xx/time.h b/include/asm-arm/arch-iop13xx/time.h
index 77a837a02dec..49213d9d7cad 100644
--- a/include/asm-arm/arch-iop13xx/time.h
+++ b/include/asm-arm/arch-iop13xx/time.h
@@ -7,9 +7,65 @@
7#define IOP_TMR_PRIVILEGED 0x08 7#define IOP_TMR_PRIVILEGED 0x08
8#define IOP_TMR_RATIO_1_1 0x00 8#define IOP_TMR_RATIO_1_1 0x00
9 9
10#define IOP13XX_XSI_FREQ_RATIO_MASK (3 << 19)
11#define IOP13XX_XSI_FREQ_RATIO_2 (0 << 19)
12#define IOP13XX_XSI_FREQ_RATIO_3 (1 << 19)
13#define IOP13XX_XSI_FREQ_RATIO_4 (2 << 19)
14#define IOP13XX_CORE_FREQ_MASK (7 << 16)
15#define IOP13XX_CORE_FREQ_600 (0 << 16)
16#define IOP13XX_CORE_FREQ_667 (1 << 16)
17#define IOP13XX_CORE_FREQ_800 (2 << 16)
18#define IOP13XX_CORE_FREQ_933 (3 << 16)
19#define IOP13XX_CORE_FREQ_1000 (4 << 16)
20#define IOP13XX_CORE_FREQ_1200 (5 << 16)
21
10void iop_init_time(unsigned long tickrate); 22void iop_init_time(unsigned long tickrate);
11unsigned long iop_gettimeoffset(void); 23unsigned long iop_gettimeoffset(void);
12 24
25static inline unsigned long iop13xx_core_freq(void)
26{
27 unsigned long freq = __raw_readl(IOP13XX_PROCESSOR_FREQ);
28 freq &= IOP13XX_CORE_FREQ_MASK;
29 switch (freq) {
30 case IOP13XX_CORE_FREQ_600:
31 return 600000000;
32 case IOP13XX_CORE_FREQ_667:
33 return 667000000;
34 case IOP13XX_CORE_FREQ_800:
35 return 800000000;
36 case IOP13XX_CORE_FREQ_933:
37 return 933000000;
38 case IOP13XX_CORE_FREQ_1000:
39 return 1000000000;
40 case IOP13XX_CORE_FREQ_1200:
41 return 1200000000;
42 default:
43 printk("%s: warning unknown frequency, defaulting to 800Mhz\n",
44 __FUNCTION__);
45 }
46
47 return 800000000;
48}
49
50static inline unsigned long iop13xx_xsi_bus_ratio(void)
51{
52 unsigned long ratio = __raw_readl(IOP13XX_PROCESSOR_FREQ);
53 ratio &= IOP13XX_XSI_FREQ_RATIO_MASK;
54 switch (ratio) {
55 case IOP13XX_XSI_FREQ_RATIO_2:
56 return 2;
57 case IOP13XX_XSI_FREQ_RATIO_3:
58 return 3;
59 case IOP13XX_XSI_FREQ_RATIO_4:
60 return 4;
61 default:
62 printk("%s: warning unknown ratio, defaulting to 2\n",
63 __FUNCTION__);
64 }
65
66 return 2;
67}
68
13static inline void write_tmr0(u32 val) 69static inline void write_tmr0(u32 val)
14{ 70{
15 asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (val)); 71 asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (val));
diff --git a/include/asm-arm/arch-iop32x/iop32x.h b/include/asm-arm/arch-iop32x/iop32x.h
index 2e9469047eb1..0d8af57221a1 100644
--- a/include/asm-arm/arch-iop32x/iop32x.h
+++ b/include/asm-arm/arch-iop32x/iop32x.h
@@ -24,5 +24,14 @@
24 24
25#include <asm/hardware/iop3xx.h> 25#include <asm/hardware/iop3xx.h>
26 26
27/* ATU Parameters
28 * set up a 1:1 bus to physical ram relationship
29 * w/ physical ram on top of pci in the memory map
30 */
31#define IOP32X_MAX_RAM_SIZE 0x40000000UL
32#define IOP3XX_MAX_RAM_SIZE IOP32X_MAX_RAM_SIZE
33#define IOP3XX_PCI_LOWER_MEM_BA 0x80000000
34#define IOP32X_PCI_MEM_WINDOW_SIZE 0x04000000
35#define IOP3XX_PCI_MEM_WINDOW_SIZE IOP32X_PCI_MEM_WINDOW_SIZE
27 36
28#endif 37#endif
diff --git a/include/asm-arm/arch-iop32x/memory.h b/include/asm-arm/arch-iop32x/memory.h
index 764cd3f0d416..c51072af214e 100644
--- a/include/asm-arm/arch-iop32x/memory.h
+++ b/include/asm-arm/arch-iop32x/memory.h
@@ -19,8 +19,8 @@
19 * bus_to_virt: Used to convert an address for DMA operations 19 * bus_to_virt: Used to convert an address for DMA operations
20 * to an address that the kernel can use. 20 * to an address that the kernel can use.
21 */ 21 */
22#define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP3XX_IATVR2)) | ((*IOP3XX_IABAR2) & 0xfffffff0)) 22#define __virt_to_bus(x) (__virt_to_phys(x))
23#define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP3XX_IALR2)) | ( *IOP3XX_IATVR2))) 23#define __bus_to_virt(x) (__phys_to_virt(x))
24 24
25 25
26#endif 26#endif
diff --git a/include/asm-arm/arch-iop33x/iop33x.h b/include/asm-arm/arch-iop33x/iop33x.h
index 7ac6e93db5ff..766985b9a723 100644
--- a/include/asm-arm/arch-iop33x/iop33x.h
+++ b/include/asm-arm/arch-iop33x/iop33x.h
@@ -29,5 +29,15 @@
29#define IOP33X_UART1_PHYS (IOP3XX_PERIPHERAL_PHYS_BASE + 0x1740) 29#define IOP33X_UART1_PHYS (IOP3XX_PERIPHERAL_PHYS_BASE + 0x1740)
30#define IOP33X_UART1_VIRT (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1740) 30#define IOP33X_UART1_VIRT (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1740)
31 31
32/* ATU Parameters
33 * set up a 1:1 bus to physical ram relationship
34 * w/ pci on top of physical ram in memory map
35 */
36#define IOP33X_MAX_RAM_SIZE 0x80000000UL
37#define IOP3XX_MAX_RAM_SIZE IOP33X_MAX_RAM_SIZE
38#define IOP3XX_PCI_LOWER_MEM_BA (PHYS_OFFSET + IOP33X_MAX_RAM_SIZE)
39#define IOP33X_PCI_MEM_WINDOW_SIZE 0x08000000
40#define IOP3XX_PCI_MEM_WINDOW_SIZE IOP33X_PCI_MEM_WINDOW_SIZE
41
32 42
33#endif 43#endif
diff --git a/include/asm-arm/arch-iop33x/memory.h b/include/asm-arm/arch-iop33x/memory.h
index 0d39139b241e..c8749127d6ab 100644
--- a/include/asm-arm/arch-iop33x/memory.h
+++ b/include/asm-arm/arch-iop33x/memory.h
@@ -19,8 +19,8 @@
19 * bus_to_virt: Used to convert an address for DMA operations 19 * bus_to_virt: Used to convert an address for DMA operations
20 * to an address that the kernel can use. 20 * to an address that the kernel can use.
21 */ 21 */
22#define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP3XX_IATVR2)) | ((*IOP3XX_IABAR2) & 0xfffffff0)) 22#define __virt_to_bus(x) (__virt_to_phys(x))
23#define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP3XX_IALR2)) | ( *IOP3XX_IATVR2))) 23#define __bus_to_virt(x) (__phys_to_virt(x))
24 24
25 25
26#endif 26#endif
diff --git a/include/asm-arm/arch-netx/netx-regs.h b/include/asm-arm/arch-netx/netx-regs.h
index 8ab45bea83ca..fc9aa21f360c 100644
--- a/include/asm-arm/arch-netx/netx-regs.h
+++ b/include/asm-arm/arch-netx/netx-regs.h
@@ -121,8 +121,8 @@
121#define NETX_SYSTEM_IOC_MR NETX_SYSTEM_REG(0x08) 121#define NETX_SYSTEM_IOC_MR NETX_SYSTEM_REG(0x08)
122 122
123/* FIXME: Docs are not consistent */ 123/* FIXME: Docs are not consistent */
124#define NETX_SYSTEM_RES_CR NETX_SYSTEM_REG(0x08) 124/* #define NETX_SYSTEM_RES_CR NETX_SYSTEM_REG(0x08) */
125/* #define NETX_SYSTEM_RES_CR NETX_SYSTEM_REG(0x0c) */ 125#define NETX_SYSTEM_RES_CR NETX_SYSTEM_REG(0x0c)
126 126
127#define NETX_SYSTEM_PHY_CONTROL NETX_SYSTEM_REG(0x10) 127#define NETX_SYSTEM_PHY_CONTROL NETX_SYSTEM_REG(0x10)
128#define NETX_SYSTEM_REV NETX_SYSTEM_REG(0x34) 128#define NETX_SYSTEM_REV NETX_SYSTEM_REG(0x34)
diff --git a/include/asm-arm/arch-ns9xxx/board.h b/include/asm-arm/arch-ns9xxx/board.h
index 91dc8fb1027f..716f34fdb716 100644
--- a/include/asm-arm/arch-ns9xxx/board.h
+++ b/include/asm-arm/arch-ns9xxx/board.h
@@ -15,4 +15,6 @@
15 15
16#define board_is_a9m9750dev() (machine_is_cc9p9360dev()) 16#define board_is_a9m9750dev() (machine_is_cc9p9360dev())
17 17
18#define board_is_jscc9p9360() (machine_is_cc9p9360js())
19
18#endif /* ifndef __ASM_ARCH_BOARD_H */ 20#endif /* ifndef __ASM_ARCH_BOARD_H */
diff --git a/include/asm-arm/arch-ns9xxx/clock.h b/include/asm-arm/arch-ns9xxx/clock.h
index a7c5ab3d9011..bf30cbdcc2bf 100644
--- a/include/asm-arm/arch-ns9xxx/clock.h
+++ b/include/asm-arm/arch-ns9xxx/clock.h
@@ -11,13 +11,43 @@
11#ifndef __ASM_ARCH_CLOCK_H 11#ifndef __ASM_ARCH_CLOCK_H
12#define __ASM_ARCH_CLOCK_H 12#define __ASM_ARCH_CLOCK_H
13 13
14#include <asm/arch-ns9xxx/regs-sys.h>
15
16#define CRYSTAL 29491200 /* Hz */
17
18/* The HRM calls this value f_vco */
14static inline u32 ns9xxx_systemclock(void) __attribute__((const)); 19static inline u32 ns9xxx_systemclock(void) __attribute__((const));
15static inline u32 ns9xxx_systemclock(void) 20static inline u32 ns9xxx_systemclock(void)
16{ 21{
22 u32 pll = SYS_PLL;
23
17 /* 24 /*
18 * This should be a multiple of HZ * TIMERCLOCKSELECT (in time.c) 25 * The system clock should be a multiple of HZ * TIMERCLOCKSELECT (in
26 * time.c).
27 *
28 * The following values are given:
29 * - TIMERCLOCKSELECT == 2^i for an i in {0 .. 6}
30 * - CRYSTAL == 29491200 == 2^17 * 3^2 * 5^2
31 * - ND in {0 .. 31}
32 * - FS in {0 .. 3}
33 *
34 * Assuming the worst, we consider:
35 * - TIMERCLOCKSELECT == 64
36 * - ND == 0
37 * - FS == 3
38 *
39 * So HZ should be a divisor of:
40 * (CRYSTAL * (ND + 1) >> FS) / TIMERCLOCKSELECT
41 * == (2^17 * 3^2 * 5^2 * 1 >> 3) / 64
42 * == 2^8 * 3^2 * 5^2
43 * == 57600
44 *
45 * Currently HZ is defined to be 100 for this platform.
46 *
47 * Fine.
19 */ 48 */
20 return 353894400; 49 return CRYSTAL * (REGGET(pll, SYS_PLL, ND) + 1)
50 >> REGGET(pll, SYS_PLL, FS);
21} 51}
22 52
23static inline u32 ns9xxx_cpuclock(void) __attribute__((const)); 53static inline u32 ns9xxx_cpuclock(void) __attribute__((const));
diff --git a/include/asm-arm/arch-ns9xxx/hardware.h b/include/asm-arm/arch-ns9xxx/hardware.h
index 6819da7c48d4..25600554c4fe 100644
--- a/include/asm-arm/arch-ns9xxx/hardware.h
+++ b/include/asm-arm/arch-ns9xxx/hardware.h
@@ -51,8 +51,9 @@
51 ~(__REGVAL(reg ## _ ## field, value)))) \ 51 ~(__REGVAL(reg ## _ ## field, value)))) \
52 | (__REGVAL(reg ## _ ## field, value)))) 52 | (__REGVAL(reg ## _ ## field, value))))
53 53
54# define REGGET(reg, field) \ 54# define REGGET(var, reg, field) \
55 ((reg & (reg ## _ ## field)) / (field & (-field))) 55 ((var & (reg ## _ ## field)) / \
56 ((reg ## _ ## field) & (-(reg ## _ ## field))))
56 57
57#else 58#else
58 59
diff --git a/include/asm-arm/arch-ns9xxx/processor.h b/include/asm-arm/arch-ns9xxx/processor.h
index 716c106ac0bf..223e51b8e104 100644
--- a/include/asm-arm/arch-ns9xxx/processor.h
+++ b/include/asm-arm/arch-ns9xxx/processor.h
@@ -13,6 +13,7 @@
13 13
14#include <asm/mach-types.h> 14#include <asm/mach-types.h>
15 15
16#define processor_is_ns9360() (machine_is_cc9p9360dev()) 16#define processor_is_ns9360() (machine_is_cc9p9360dev() \
17 || machine_is_cc9p9360js())
17 18
18#endif /* ifndef __ASM_ARCH_PROCESSOR_H */ 19#endif /* ifndef __ASM_ARCH_PROCESSOR_H */
diff --git a/include/asm-arm/arch-ns9xxx/regs-sys.h b/include/asm-arm/arch-ns9xxx/regs-sys.h
index 8162a50bb273..a42546aeb92a 100644
--- a/include/asm-arm/arch-ns9xxx/regs-sys.h
+++ b/include/asm-arm/arch-ns9xxx/regs-sys.h
@@ -48,6 +48,12 @@
48/* PLL Configuration register */ 48/* PLL Configuration register */
49#define SYS_PLL __REG(0xa0900188) 49#define SYS_PLL __REG(0xa0900188)
50 50
51/* PLL FS status */
52#define SYS_PLL_FS __REGBITS(24, 23)
53
54/* PLL ND status */
55#define SYS_PLL_ND __REGBITS(20, 16)
56
51/* PLL Configuration register: PLL SW change */ 57/* PLL Configuration register: PLL SW change */
52#define SYS_PLL_SWC __REGBIT(15) 58#define SYS_PLL_SWC __REGBIT(15)
53#define SYS_PLL_SWC_NO __REGVAL(SYS_PLL_SWC, 0) 59#define SYS_PLL_SWC_NO __REGVAL(SYS_PLL_SWC, 0)
diff --git a/include/asm-arm/arch-pxa/i2c.h b/include/asm-arm/arch-pxa/i2c.h
index 46ec2243974a..e404b233d8a8 100644
--- a/include/asm-arm/arch-pxa/i2c.h
+++ b/include/asm-arm/arch-pxa/i2c.h
@@ -64,6 +64,7 @@ struct i2c_slave_client;
64struct i2c_pxa_platform_data { 64struct i2c_pxa_platform_data {
65 unsigned int slave_addr; 65 unsigned int slave_addr;
66 struct i2c_slave_client *slave; 66 struct i2c_slave_client *slave;
67 unsigned int class;
67}; 68};
68 69
69extern void pxa_set_i2c_info(struct i2c_pxa_platform_data *info); 70extern void pxa_set_i2c_info(struct i2c_pxa_platform_data *info);
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index 139c9d954818..dbcc9298b0c8 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -1801,35 +1801,35 @@
1801#define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */ 1801#define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */
1802#define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */ 1802#define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */
1803 1803
1804#define CKEN24_CAMERA (1 << 24) /* Camera Interface Clock Enable */ 1804#define CKEN_CAMERA (24) /* Camera Interface Clock Enable */
1805#define CKEN23_SSP1 (1 << 23) /* SSP1 Unit Clock Enable */ 1805#define CKEN_SSP1 (23) /* SSP1 Unit Clock Enable */
1806#define CKEN22_MEMC (1 << 22) /* Memory Controller Clock Enable */ 1806#define CKEN_MEMC (22) /* Memory Controller Clock Enable */
1807#define CKEN21_MEMSTK (1 << 21) /* Memory Stick Host Controller */ 1807#define CKEN_MEMSTK (21) /* Memory Stick Host Controller */
1808#define CKEN20_IM (1 << 20) /* Internal Memory Clock Enable */ 1808#define CKEN_IM (20) /* Internal Memory Clock Enable */
1809#define CKEN19_KEYPAD (1 << 19) /* Keypad Interface Clock Enable */ 1809#define CKEN_KEYPAD (19) /* Keypad Interface Clock Enable */
1810#define CKEN18_USIM (1 << 18) /* USIM Unit Clock Enable */ 1810#define CKEN_USIM (18) /* USIM Unit Clock Enable */
1811#define CKEN17_MSL (1 << 17) /* MSL Unit Clock Enable */ 1811#define CKEN_MSL (17) /* MSL Unit Clock Enable */
1812#define CKEN16_LCD (1 << 16) /* LCD Unit Clock Enable */ 1812#define CKEN_LCD (16) /* LCD Unit Clock Enable */
1813#define CKEN15_PWRI2C (1 << 15) /* PWR I2C Unit Clock Enable */ 1813#define CKEN_PWRI2C (15) /* PWR I2C Unit Clock Enable */
1814#define CKEN14_I2C (1 << 14) /* I2C Unit Clock Enable */ 1814#define CKEN_I2C (14) /* I2C Unit Clock Enable */
1815#define CKEN13_FICP (1 << 13) /* FICP Unit Clock Enable */ 1815#define CKEN_FICP (13) /* FICP Unit Clock Enable */
1816#define CKEN12_MMC (1 << 12) /* MMC Unit Clock Enable */ 1816#define CKEN_MMC (12) /* MMC Unit Clock Enable */
1817#define CKEN11_USB (1 << 11) /* USB Unit Clock Enable */ 1817#define CKEN_USB (11) /* USB Unit Clock Enable */
1818#define CKEN10_ASSP (1 << 10) /* ASSP (SSP3) Clock Enable */ 1818#define CKEN_ASSP (10) /* ASSP (SSP3) Clock Enable */
1819#define CKEN10_USBHOST (1 << 10) /* USB Host Unit Clock Enable */ 1819#define CKEN_USBHOST (10) /* USB Host Unit Clock Enable */
1820#define CKEN9_OSTIMER (1 << 9) /* OS Timer Unit Clock Enable */ 1820#define CKEN_OSTIMER (9) /* OS Timer Unit Clock Enable */
1821#define CKEN9_NSSP (1 << 9) /* NSSP (SSP2) Clock Enable */ 1821#define CKEN_NSSP (9) /* NSSP (SSP2) Clock Enable */
1822#define CKEN8_I2S (1 << 8) /* I2S Unit Clock Enable */ 1822#define CKEN_I2S (8) /* I2S Unit Clock Enable */
1823#define CKEN7_BTUART (1 << 7) /* BTUART Unit Clock Enable */ 1823#define CKEN_BTUART (7) /* BTUART Unit Clock Enable */
1824#define CKEN6_FFUART (1 << 6) /* FFUART Unit Clock Enable */ 1824#define CKEN_FFUART (6) /* FFUART Unit Clock Enable */
1825#define CKEN5_STUART (1 << 5) /* STUART Unit Clock Enable */ 1825#define CKEN_STUART (5) /* STUART Unit Clock Enable */
1826#define CKEN4_HWUART (1 << 4) /* HWUART Unit Clock Enable */ 1826#define CKEN_HWUART (4) /* HWUART Unit Clock Enable */
1827#define CKEN4_SSP3 (1 << 4) /* SSP3 Unit Clock Enable */ 1827#define CKEN_SSP3 (4) /* SSP3 Unit Clock Enable */
1828#define CKEN3_SSP (1 << 3) /* SSP Unit Clock Enable */ 1828#define CKEN_SSP (3) /* SSP Unit Clock Enable */
1829#define CKEN3_SSP2 (1 << 3) /* SSP2 Unit Clock Enable */ 1829#define CKEN_SSP2 (3) /* SSP2 Unit Clock Enable */
1830#define CKEN2_AC97 (1 << 2) /* AC97 Unit Clock Enable */ 1830#define CKEN_AC97 (2) /* AC97 Unit Clock Enable */
1831#define CKEN1_PWM1 (1 << 1) /* PWM1 Clock Enable */ 1831#define CKEN_PWM1 (1) /* PWM1 Clock Enable */
1832#define CKEN0_PWM0 (1 << 0) /* PWM0 Clock Enable */ 1832#define CKEN_PWM0 (0) /* PWM0 Clock Enable */
1833 1833
1834#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */ 1834#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */
1835#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */ 1835#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */
diff --git a/include/asm-arm/arch-s3c2410/regs-ac97.h b/include/asm-arm/arch-s3c2410/regs-ac97.h
index bdd6a4f93d7f..b004dee6bcaf 100644
--- a/include/asm-arm/arch-s3c2410/regs-ac97.h
+++ b/include/asm-arm/arch-s3c2410/regs-ac97.h
@@ -13,11 +13,55 @@
13#ifndef __ASM_ARCH_REGS_AC97_H 13#ifndef __ASM_ARCH_REGS_AC97_H
14#define __ASM_ARCH_REGS_AC97_H __FILE__ 14#define __ASM_ARCH_REGS_AC97_H __FILE__
15 15
16#define S3C_AC97_GLBCTRL (0x00) 16#define S3C_AC97_GLBCTRL (0x00)
17#define S3C_AC97_GLBSTAT (0x04) 17
18#define S3C_AC97_CODEC_CMD (0x08) 18#define S3C_AC97_GLBCTRL_CODECREADYIE (1<<22)
19#define S3C_AC97_PCM_ADDR (0x10) 19#define S3C_AC97_GLBCTRL_PCMOUTURIE (1<<21)
20#define S3C_AC97_PCM_DATA (0x18) 20#define S3C_AC97_GLBCTRL_PCMINORIE (1<<20)
21#define S3C_AC97_MIC_DATA (0x1C) 21#define S3C_AC97_GLBCTRL_MICINORIE (1<<19)
22#define S3C_AC97_GLBCTRL_PCMOUTTIE (1<<18)
23#define S3C_AC97_GLBCTRL_PCMINTIE (1<<17)
24#define S3C_AC97_GLBCTRL_MICINTIE (1<<16)
25#define S3C_AC97_GLBCTRL_PCMOUTTM_OFF (0<<12)
26#define S3C_AC97_GLBCTRL_PCMOUTTM_PIO (1<<12)
27#define S3C_AC97_GLBCTRL_PCMOUTTM_DMA (2<<12)
28#define S3C_AC97_GLBCTRL_PCMOUTTM_MASK (3<<12)
29#define S3C_AC97_GLBCTRL_PCMINTM_OFF (0<<10)
30#define S3C_AC97_GLBCTRL_PCMINTM_PIO (1<<10)
31#define S3C_AC97_GLBCTRL_PCMINTM_DMA (2<<10)
32#define S3C_AC97_GLBCTRL_PCMINTM_MASK (3<<10)
33#define S3C_AC97_GLBCTRL_MICINTM_OFF (0<<8)
34#define S3C_AC97_GLBCTRL_MICINTM_PIO (1<<8)
35#define S3C_AC97_GLBCTRL_MICINTM_DMA (2<<8)
36#define S3C_AC97_GLBCTRL_MICINTM_MASK (3<<8)
37#define S3C_AC97_GLBCTRL_TRANSFERDATAENABLE (1<<3)
38#define S3C_AC97_GLBCTRL_ACLINKON (1<<2)
39#define S3C_AC97_GLBCTRL_WARMRESET (1<<1)
40#define S3C_AC97_GLBCTRL_COLDRESET (1<<0)
41
42#define S3C_AC97_GLBSTAT (0x04)
43
44#define S3C_AC97_GLBSTAT_CODECREADY (1<<22)
45#define S3C_AC97_GLBSTAT_PCMOUTUR (1<<21)
46#define S3C_AC97_GLBSTAT_PCMINORI (1<<20)
47#define S3C_AC97_GLBSTAT_MICINORI (1<<19)
48#define S3C_AC97_GLBSTAT_PCMOUTTI (1<<18)
49#define S3C_AC97_GLBSTAT_PCMINTI (1<<17)
50#define S3C_AC97_GLBSTAT_MICINTI (1<<16)
51#define S3C_AC97_GLBSTAT_MAINSTATE_IDLE (0<<0)
52#define S3C_AC97_GLBSTAT_MAINSTATE_INIT (1<<0)
53#define S3C_AC97_GLBSTAT_MAINSTATE_READY (2<<0)
54#define S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE (3<<0)
55#define S3C_AC97_GLBSTAT_MAINSTATE_LP (4<<0)
56#define S3C_AC97_GLBSTAT_MAINSTATE_WARM (5<<0)
57
58#define S3C_AC97_CODEC_CMD (0x08)
59
60#define S3C_AC97_CODEC_CMD_READ (1<<23)
61
62#define S3C_AC97_STAT (0x0c)
63#define S3C_AC97_PCM_ADDR (0x10)
64#define S3C_AC97_PCM_DATA (0x18)
65#define S3C_AC97_MIC_DATA (0x1C)
22 66
23#endif /* __ASM_ARCH_REGS_AC97_H */ 67#endif /* __ASM_ARCH_REGS_AC97_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-udc.h b/include/asm-arm/arch-s3c2410/regs-udc.h
index 3c8354619b60..e1e9805d2d9a 100644
--- a/include/asm-arm/arch-s3c2410/regs-udc.h
+++ b/include/asm-arm/arch-s3c2410/regs-udc.h
@@ -75,7 +75,7 @@
75#define S3C2410_UDC_OUT_FIFO_CNT1_REG S3C2410_USBDREG(0x0198) 75#define S3C2410_UDC_OUT_FIFO_CNT1_REG S3C2410_USBDREG(0x0198)
76#define S3C2410_UDC_OUT_FIFO_CNT2_REG S3C2410_USBDREG(0x019c) 76#define S3C2410_UDC_OUT_FIFO_CNT2_REG S3C2410_USBDREG(0x019c)
77 77
78 78#define S3C2410_UDC_FUNCADDR_UPDATE (1<<7)
79 79
80#define S3C2410_UDC_PWR_ISOUP (1<<7) // R/W 80#define S3C2410_UDC_PWR_ISOUP (1<<7) // R/W
81#define S3C2410_UDC_PWR_RESET (1<<3) // R 81#define S3C2410_UDC_PWR_RESET (1<<3) // R
@@ -135,10 +135,6 @@
135#define S3C2410_UDC_OCSR2_ISO (1<<6) // R/W 135#define S3C2410_UDC_OCSR2_ISO (1<<6) // R/W
136#define S3C2410_UDC_OCSR2_DMAIEN (1<<5) // R/W 136#define S3C2410_UDC_OCSR2_DMAIEN (1<<5) // R/W
137 137
138#define S3C2410_UDC_SETIX(base,x) \
139 writel(S3C2410_UDC_INDEX_ ## x, base+S3C2410_UDC_INDEX_REG);
140
141
142#define S3C2410_UDC_EP0_CSR_OPKRDY (1<<0) 138#define S3C2410_UDC_EP0_CSR_OPKRDY (1<<0)
143#define S3C2410_UDC_EP0_CSR_IPKRDY (1<<1) 139#define S3C2410_UDC_EP0_CSR_IPKRDY (1<<1)
144#define S3C2410_UDC_EP0_CSR_SENTSTL (1<<2) 140#define S3C2410_UDC_EP0_CSR_SENTSTL (1<<2)
diff --git a/include/asm-arm/ecard.h b/include/asm-arm/ecard.h
index a0ae2b954d29..3a6d3eb27622 100644
--- a/include/asm-arm/ecard.h
+++ b/include/asm-arm/ecard.h
@@ -160,6 +160,7 @@ struct expansion_card {
160 unsigned char irqmask; /* IRQ mask */ 160 unsigned char irqmask; /* IRQ mask */
161 unsigned char fiqmask; /* FIQ mask */ 161 unsigned char fiqmask; /* FIQ mask */
162 unsigned char claimed; /* Card claimed? */ 162 unsigned char claimed; /* Card claimed? */
163 unsigned char easi; /* EASI card */
163 164
164 void *irq_data; /* Data for use for IRQ by card */ 165 void *irq_data; /* Data for use for IRQ by card */
165 void *fiq_data; /* Data for use for FIQ by card */ 166 void *fiq_data; /* Data for use for FIQ by card */
@@ -169,7 +170,6 @@ struct expansion_card {
169 CONST unsigned int dma; /* DMA number (for request_dma) */ 170 CONST unsigned int dma; /* DMA number (for request_dma) */
170 CONST unsigned int irq; /* IRQ number (for request_irq) */ 171 CONST unsigned int irq; /* IRQ number (for request_irq) */
171 CONST unsigned int fiq; /* FIQ number (for request_irq) */ 172 CONST unsigned int fiq; /* FIQ number (for request_irq) */
172 CONST card_type_t type; /* Type of card */
173 CONST struct in_ecid cid; /* Card Identification */ 173 CONST struct in_ecid cid; /* Card Identification */
174 174
175 /* Private internal data */ 175 /* Private internal data */
@@ -224,56 +224,6 @@ ecard_address(struct expansion_card *ec, card_type_t type, card_speed_t speed)
224extern int ecard_request_resources(struct expansion_card *ec); 224extern int ecard_request_resources(struct expansion_card *ec);
225extern void ecard_release_resources(struct expansion_card *ec); 225extern void ecard_release_resources(struct expansion_card *ec);
226 226
227#ifdef ECARD_C
228/* Definitions internal to ecard.c - for it's use only!!
229 *
230 * External expansion card header as read from the card
231 */
232struct ex_ecid {
233 unsigned char r_irq:1;
234 unsigned char r_zero:1;
235 unsigned char r_fiq:1;
236 unsigned char r_id:4;
237 unsigned char r_a:1;
238
239 unsigned char r_cd:1;
240 unsigned char r_is:1;
241 unsigned char r_w:2;
242 unsigned char r_r1:4;
243
244 unsigned char r_r2:8;
245
246 unsigned char r_prod[2];
247
248 unsigned char r_manu[2];
249
250 unsigned char r_country;
251
252 unsigned char r_fiqmask;
253 unsigned char r_fiqoff[3];
254
255 unsigned char r_irqmask;
256 unsigned char r_irqoff[3];
257};
258
259/*
260 * Chunk directory entry as read from the card
261 */
262struct ex_chunk_dir {
263 unsigned char r_id;
264 unsigned char r_len[3];
265 unsigned long r_start;
266 union {
267 char string[256];
268 char data[1];
269 } d;
270#define c_id(x) ((x)->r_id)
271#define c_len(x) ((x)->r_len[0]|((x)->r_len[1]<<8)|((x)->r_len[2]<<16))
272#define c_start(x) ((x)->r_start)
273};
274
275#endif
276
277extern struct bus_type ecard_bus_type; 227extern struct bus_type ecard_bus_type;
278 228
279#define ECARD_DEV(_d) container_of((_d), struct expansion_card, dev) 229#define ECARD_DEV(_d) container_of((_d), struct expansion_card, dev)
diff --git a/include/asm-arm/hardware/iop3xx.h b/include/asm-arm/hardware/iop3xx.h
index 15141a9caca8..63feceb7ede5 100644
--- a/include/asm-arm/hardware/iop3xx.h
+++ b/include/asm-arm/hardware/iop3xx.h
@@ -28,6 +28,7 @@
28extern void gpio_line_config(int line, int direction); 28extern void gpio_line_config(int line, int direction);
29extern int gpio_line_get(int line); 29extern int gpio_line_get(int line);
30extern void gpio_line_set(int line, int value); 30extern void gpio_line_set(int line, int value);
31extern int init_atu;
31#endif 32#endif
32 33
33 34
@@ -41,7 +42,7 @@ extern void gpio_line_set(int line, int value);
41 IOP3XX_PERIPHERAL_SIZE - 1) 42 IOP3XX_PERIPHERAL_SIZE - 1)
42#define IOP3XX_PERIPHERAL_UPPER_VA (IOP3XX_PERIPHERAL_VIRT_BASE +\ 43#define IOP3XX_PERIPHERAL_UPPER_VA (IOP3XX_PERIPHERAL_VIRT_BASE +\
43 IOP3XX_PERIPHERAL_SIZE - 1) 44 IOP3XX_PERIPHERAL_SIZE - 1)
44#define IOP3XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\ 45#define IOP3XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) (addr) -\
45 (IOP3XX_PERIPHERAL_PHYS_BASE\ 46 (IOP3XX_PERIPHERAL_PHYS_BASE\
46 - IOP3XX_PERIPHERAL_VIRT_BASE)) 47 - IOP3XX_PERIPHERAL_VIRT_BASE))
47#define IOP3XX_REG_ADDR(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + (reg)) 48#define IOP3XX_REG_ADDR(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + (reg))
@@ -103,6 +104,21 @@ extern void gpio_line_set(int line, int value);
103#define IOP3XX_PCIXCMD (volatile u16 *)IOP3XX_REG_ADDR(0x01e2) 104#define IOP3XX_PCIXCMD (volatile u16 *)IOP3XX_REG_ADDR(0x01e2)
104#define IOP3XX_PCIXSR (volatile u32 *)IOP3XX_REG_ADDR(0x01e4) 105#define IOP3XX_PCIXSR (volatile u32 *)IOP3XX_REG_ADDR(0x01e4)
105#define IOP3XX_PCIIRSR (volatile u32 *)IOP3XX_REG_ADDR(0x01ec) 106#define IOP3XX_PCIIRSR (volatile u32 *)IOP3XX_REG_ADDR(0x01ec)
107#define IOP3XX_PCSR_OUT_Q_BUSY (1 << 15)
108#define IOP3XX_PCSR_IN_Q_BUSY (1 << 14)
109#define IOP3XX_ATUCR_OUT_EN (1 << 1)
110
111#define IOP3XX_INIT_ATU_DEFAULT 0
112#define IOP3XX_INIT_ATU_DISABLE -1
113#define IOP3XX_INIT_ATU_ENABLE 1
114
115#ifdef CONFIG_IOP3XX_ATU
116#define iop3xx_get_init_atu(x) (init_atu == IOP3XX_INIT_ATU_DEFAULT ?\
117 IOP3XX_INIT_ATU_ENABLE : init_atu)
118#else
119#define iop3xx_get_init_atu(x) (init_atu == IOP3XX_INIT_ATU_DEFAULT ?\
120 IOP3XX_INIT_ATU_DISABLE : init_atu)
121#endif
106 122
107/* Messaging Unit */ 123/* Messaging Unit */
108#define IOP3XX_IMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0310) 124#define IOP3XX_IMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0310)
@@ -253,14 +269,12 @@ extern void gpio_line_set(int line, int value);
253/* 269/*
254 * IOP3XX I/O and Mem space regions for PCI autoconfiguration 270 * IOP3XX I/O and Mem space regions for PCI autoconfiguration
255 */ 271 */
256#define IOP3XX_PCI_MEM_WINDOW_SIZE 0x04000000 272#define IOP3XX_PCI_LOWER_MEM_PA 0x80000000
257#define IOP3XX_PCI_LOWER_MEM_PA 0x80000000
258#define IOP3XX_PCI_LOWER_MEM_BA (*IOP3XX_OMWTVR0)
259 273
260#define IOP3XX_PCI_IO_WINDOW_SIZE 0x00010000 274#define IOP3XX_PCI_IO_WINDOW_SIZE 0x00010000
261#define IOP3XX_PCI_LOWER_IO_PA 0x90000000 275#define IOP3XX_PCI_LOWER_IO_PA 0x90000000
262#define IOP3XX_PCI_LOWER_IO_VA 0xfe000000 276#define IOP3XX_PCI_LOWER_IO_VA 0xfe000000
263#define IOP3XX_PCI_LOWER_IO_BA (*IOP3XX_OIOWTVR) 277#define IOP3XX_PCI_LOWER_IO_BA 0x90000000
264#define IOP3XX_PCI_UPPER_IO_PA (IOP3XX_PCI_LOWER_IO_PA +\ 278#define IOP3XX_PCI_UPPER_IO_PA (IOP3XX_PCI_LOWER_IO_PA +\
265 IOP3XX_PCI_IO_WINDOW_SIZE - 1) 279 IOP3XX_PCI_IO_WINDOW_SIZE - 1)
266#define IOP3XX_PCI_UPPER_IO_VA (IOP3XX_PCI_LOWER_IO_VA +\ 280#define IOP3XX_PCI_UPPER_IO_VA (IOP3XX_PCI_LOWER_IO_VA +\
diff --git a/include/asm-arm/plat-s3c24xx/clock.h b/include/asm-arm/plat-s3c24xx/clock.h
index f6135dbb9fa9..235b753cd877 100644
--- a/include/asm-arm/plat-s3c24xx/clock.h
+++ b/include/asm-arm/plat-s3c24xx/clock.h
@@ -56,6 +56,7 @@ extern struct mutex clocks_mutex;
56extern int s3c2410_clkcon_enable(struct clk *clk, int enable); 56extern int s3c2410_clkcon_enable(struct clk *clk, int enable);
57 57
58extern int s3c24xx_register_clock(struct clk *clk); 58extern int s3c24xx_register_clock(struct clk *clk);
59extern int s3c24xx_register_clocks(struct clk **clk, int nr_clks);
59 60
60extern int s3c24xx_setup_clocks(unsigned long xtal, 61extern int s3c24xx_setup_clocks(unsigned long xtal,
61 unsigned long fclk, 62 unsigned long fclk,
diff --git a/include/asm-arm/plat-s3c24xx/cpu.h b/include/asm-arm/plat-s3c24xx/cpu.h
index 15dd18810905..23e420e8bd5b 100644
--- a/include/asm-arm/plat-s3c24xx/cpu.h
+++ b/include/asm-arm/plat-s3c24xx/cpu.h
@@ -40,22 +40,6 @@ extern void s3c24xx_init_uartdevs(char *name,
40 struct s3c24xx_uart_resources *res, 40 struct s3c24xx_uart_resources *res,
41 struct s3c2410_uartcfg *cfg, int no); 41 struct s3c2410_uartcfg *cfg, int no);
42 42
43/* the board structure is used at first initialsation time
44 * to get info such as the devices to register for this
45 * board. This is done because platfrom_add_devices() cannot
46 * be called from the map_io entry.
47*/
48
49struct s3c24xx_board {
50 struct platform_device **devices;
51 unsigned int devices_count;
52
53 struct clk **clocks;
54 unsigned int clocks_count;
55};
56
57extern void s3c24xx_set_board(struct s3c24xx_board *board);
58
59/* timer for 2410/2440 */ 43/* timer for 2410/2440 */
60 44
61struct sys_timer; 45struct sys_timer;
diff --git a/include/asm-arm/ptrace.h b/include/asm-arm/ptrace.h
index 5a8ef787dbf8..2d0dad8c10ac 100644
--- a/include/asm-arm/ptrace.h
+++ b/include/asm-arm/ptrace.h
@@ -10,23 +10,19 @@
10#ifndef __ASM_ARM_PTRACE_H 10#ifndef __ASM_ARM_PTRACE_H
11#define __ASM_ARM_PTRACE_H 11#define __ASM_ARM_PTRACE_H
12 12
13
14#define PTRACE_GETREGS 12 13#define PTRACE_GETREGS 12
15#define PTRACE_SETREGS 13 14#define PTRACE_SETREGS 13
16#define PTRACE_GETFPREGS 14 15#define PTRACE_GETFPREGS 14
17#define PTRACE_SETFPREGS 15 16#define PTRACE_SETFPREGS 15
18 17/* PTRACE_ATTACH is 16 */
18/* PTRACE_DETACH is 17 */
19#define PTRACE_GETWMMXREGS 18 19#define PTRACE_GETWMMXREGS 18
20#define PTRACE_SETWMMXREGS 19 20#define PTRACE_SETWMMXREGS 19
21 21/* 20 is unused */
22#define PTRACE_OLDSETOPTIONS 21 22#define PTRACE_OLDSETOPTIONS 21
23
24#define PTRACE_GET_THREAD_AREA 22 23#define PTRACE_GET_THREAD_AREA 22
25
26#define PTRACE_SET_SYSCALL 23 24#define PTRACE_SET_SYSCALL 23
27
28/* PTRACE_SYSCALL is 24 */ 25/* PTRACE_SYSCALL is 24 */
29
30#define PTRACE_GETCRUNCHREGS 25 26#define PTRACE_GETCRUNCHREGS 25
31#define PTRACE_SETCRUNCHREGS 26 27#define PTRACE_SETCRUNCHREGS 26
32 28
diff --git a/include/asm-arm/thread_info.h b/include/asm-arm/thread_info.h
index 5014794f9eb3..eae85b09db2e 100644
--- a/include/asm-arm/thread_info.h
+++ b/include/asm-arm/thread_info.h
@@ -57,6 +57,7 @@ struct thread_info {
57 __u32 cpu; /* cpu */ 57 __u32 cpu; /* cpu */
58 __u32 cpu_domain; /* cpu domain */ 58 __u32 cpu_domain; /* cpu domain */
59 struct cpu_context_save cpu_context; /* cpu context */ 59 struct cpu_context_save cpu_context; /* cpu context */
60 __u32 syscall; /* syscall number */
60 __u8 used_cp[16]; /* thread used copro */ 61 __u8 used_cp[16]; /* thread used copro */
61 unsigned long tp_value; 62 unsigned long tp_value;
62 struct crunch_state crunchstate; 63 struct crunch_state crunchstate;
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-29 00:09:43 -0500