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-rw-r--r--include/asm-arm/arch-imx/imxfb.h1
-rw-r--r--include/asm-arm/arch-ixp2000/gpio.h31
-rw-r--r--include/asm-arm/arch-ixp2000/io.h96
-rw-r--r--include/asm-arm/arch-ixp2000/ixdp2x00.h4
-rw-r--r--include/asm-arm/arch-ixp2000/ixdp2x01.h4
-rw-r--r--include/asm-arm/arch-ixp2000/ixp2000-regs.h21
-rw-r--r--include/asm-arm/arch-ixp2000/platform.h23
-rw-r--r--include/asm-arm/arch-ixp2000/vmalloc.h2
-rw-r--r--include/asm-arm/arch-ixp4xx/debug-macro.S1
-rw-r--r--include/asm-arm/arch-ixp4xx/io.h176
-rw-r--r--include/asm-arm/arch-ixp4xx/ixp4xx-regs.h10
-rw-r--r--include/asm-arm/arch-omap/board-h2.h5
-rw-r--r--include/asm-arm/arch-omap/board-h3.h5
-rw-r--r--include/asm-arm/arch-omap/board-osk.h5
-rw-r--r--include/asm-arm/arch-omap/board.h12
-rw-r--r--include/asm-arm/arch-omap/common.h36
-rw-r--r--include/asm-arm/arch-omap/dma.h1
-rw-r--r--include/asm-arm/arch-omap/hardware.h24
-rw-r--r--include/asm-arm/arch-omap/irqs.h3
-rw-r--r--include/asm-arm/arch-omap/mux.h28
-rw-r--r--include/asm-arm/arch-omap/omap16xx.h32
-rw-r--r--include/asm-arm/arch-omap/system.h21
-rw-r--r--include/asm-arm/arch-omap/tps65010.h76
-rw-r--r--include/asm-arm/arch-omap/usb.h9
-rw-r--r--include/asm-arm/arch-pxa/debug-macro.S2
-rw-r--r--include/asm-arm/arch-pxa/mtd-xip.h37
-rw-r--r--include/asm-arm/arch-pxa/pxa-regs.h2
-rw-r--r--include/asm-arm/arch-s3c2410/audio.h49
-rw-r--r--include/asm-arm/arch-s3c2410/regs-iis.h10
-rw-r--r--include/asm-arm/arch-sa1100/mtd-xip.h26
-rw-r--r--include/asm-arm/arch-shark/io.h147
-rw-r--r--include/asm-arm/bitops.h9
-rw-r--r--include/asm-arm/emergency-restart.h6
-rw-r--r--include/asm-arm/hardware/arm_timer.h21
-rw-r--r--include/asm-arm/ide.h2
-rw-r--r--include/asm-arm/io.h4
-rw-r--r--include/asm-arm/locks.h40
-rw-r--r--include/asm-arm/mach/arch.h34
-rw-r--r--include/asm-arm/mach/time.h23
-rw-r--r--include/asm-arm/mtd-xip.h26
-rw-r--r--include/asm-arm/pci.h16
-rw-r--r--include/asm-arm/pgalloc.h24
-rw-r--r--include/asm-arm/signal.h1
-rw-r--r--include/asm-arm/smp.h3
-rw-r--r--include/asm-arm/spinlock.h82
-rw-r--r--include/asm-arm/stat.h2
-rw-r--r--include/asm-arm/system.h130
-rw-r--r--include/asm-arm/thread_info.h2
-rw-r--r--include/asm-arm/tlbflush.h28
49 files changed, 950 insertions, 402 deletions
diff --git a/include/asm-arm/arch-imx/imxfb.h b/include/asm-arm/arch-imx/imxfb.h
index 2346d454ab9c..7dbc7bbba65d 100644
--- a/include/asm-arm/arch-imx/imxfb.h
+++ b/include/asm-arm/arch-imx/imxfb.h
@@ -25,6 +25,7 @@ struct imxfb_mach_info {
25 u_int pcr; 25 u_int pcr;
26 u_int pwmr; 26 u_int pwmr;
27 u_int lscr1; 27 u_int lscr1;
28 u_int dmacr;
28 29
29 u_char * fixed_screen_cpu; 30 u_char * fixed_screen_cpu;
30 dma_addr_t fixed_screen_dma; 31 dma_addr_t fixed_screen_dma;
diff --git a/include/asm-arm/arch-ixp2000/gpio.h b/include/asm-arm/arch-ixp2000/gpio.h
index 84634af5cc64..03cbbe1fd9d8 100644
--- a/include/asm-arm/arch-ixp2000/gpio.h
+++ b/include/asm-arm/arch-ixp2000/gpio.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * include/asm-arm/arch-ixp2000/ixp2000-gpio.h 2 * include/asm-arm/arch-ixp2000/gpio.h
3 * 3 *
4 * Copyright (C) 2002 Intel Corporation. 4 * Copyright (C) 2002 Intel Corporation.
5 * 5 *
@@ -16,26 +16,18 @@
16 * Use this instead of directly setting the GPIO registers. 16 * Use this instead of directly setting the GPIO registers.
17 * GPIOs may also be used as GPIOs (e.g. for emulating i2c/smb) 17 * GPIOs may also be used as GPIOs (e.g. for emulating i2c/smb)
18 */ 18 */
19#ifndef _ASM_ARCH_IXP2000_GPIO_H_ 19#ifndef __ASM_ARCH_GPIO_H
20#define _ASM_ARCH_IXP2000_GPIO_H_ 20#define __ASM_ARCH_GPIO_H
21 21
22#ifndef __ASSEMBLY__ 22#ifndef __ASSEMBLY__
23#define GPIO_OUT 0x0 23
24#define GPIO_IN 0x80 24#define GPIO_IN 0
25#define GPIO_OUT 1
25 26
26#define IXP2000_GPIO_LOW 0 27#define IXP2000_GPIO_LOW 0
27#define IXP2000_GPIO_HIGH 1 28#define IXP2000_GPIO_HIGH 1
28 29
29#define GPIO_NO_EDGES 0 30extern void gpio_line_config(int line, int direction);
30#define GPIO_FALLING_EDGE 1
31#define GPIO_RISING_EDGE 2
32#define GPIO_BOTH_EDGES 3
33#define GPIO_LEVEL_LOW 4
34#define GPIO_LEVEL_HIGH 8
35
36extern void set_GPIO_IRQ_edge(int gpio_nr, int edge);
37extern void set_GPIO_IRQ_level(int gpio_nr, int level);
38extern void gpio_line_config(int line, int style);
39 31
40static inline int gpio_line_get(int line) 32static inline int gpio_line_get(int line)
41{ 33{
@@ -45,11 +37,12 @@ static inline int gpio_line_get(int line)
45static inline void gpio_line_set(int line, int value) 37static inline void gpio_line_set(int line, int value)
46{ 38{
47 if (value == IXP2000_GPIO_HIGH) { 39 if (value == IXP2000_GPIO_HIGH) {
48 ixp_reg_write(IXP2000_GPIO_POSR, BIT(line)); 40 ixp2000_reg_write(IXP2000_GPIO_POSR, 1 << line);
49 } else if (value == IXP2000_GPIO_LOW) 41 } else if (value == IXP2000_GPIO_LOW) {
50 ixp_reg_write(IXP2000_GPIO_POCR, BIT(line)); 42 ixp2000_reg_write(IXP2000_GPIO_POCR, 1 << line);
43 }
51} 44}
52 45
53#endif /* !__ASSEMBLY__ */ 46#endif /* !__ASSEMBLY__ */
54#endif /* ASM_ARCH_IXP2000_GPIO_H_ */
55 47
48#endif /* ASM_ARCH_IXP2000_GPIO_H_ */
diff --git a/include/asm-arm/arch-ixp2000/io.h b/include/asm-arm/arch-ixp2000/io.h
index 083462668e18..3241cd6f0778 100644
--- a/include/asm-arm/arch-ixp2000/io.h
+++ b/include/asm-arm/arch-ixp2000/io.h
@@ -17,18 +17,23 @@
17 17
18#define IO_SPACE_LIMIT 0xffffffff 18#define IO_SPACE_LIMIT 0xffffffff
19#define __mem_pci(a) (a) 19#define __mem_pci(a) (a)
20#define ___io(p) ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE))
21 20
22/* 21/*
23 * The IXP2400 before revision B0 asserts byte lanes for PCI I/O 22 * The A? revisions of the IXP2000s assert byte lanes for PCI I/O
24 * transactions the other way round (MEM transactions don't have this 23 * transactions the other way round (MEM transactions don't have this
25 * issue), so we need to override the standard functions. B0 and later 24 * issue), so if we want to support those models, we need to override
26 * have a bit that can be set to 1 to get the 'proper' behavior, but 25 * the standard I/O functions.
27 * since that isn't available on the A? revisions we just keep doing 26 *
28 * things manually. 27 * B0 and later have a bit that can be set to 1 to get the proper
28 * behavior for I/O transactions, which then allows us to use the
29 * standard I/O functions. This is what we do if the user does not
30 * explicitly ask for support for pre-B0.
29 */ 31 */
30#define alignb(addr) (void __iomem *)((unsigned long)addr ^ 3) 32#ifdef CONFIG_IXP2000_SUPPORT_BROKEN_PCI_IO
31#define alignw(addr) (void __iomem *)((unsigned long)addr ^ 2) 33#define ___io(p) ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE))
34
35#define alignb(addr) (void __iomem *)((unsigned long)(addr) ^ 3)
36#define alignw(addr) (void __iomem *)((unsigned long)(addr) ^ 2)
32 37
33#define outb(v,p) __raw_writeb((v),alignb(___io(p))) 38#define outb(v,p) __raw_writeb((v),alignb(___io(p)))
34#define outw(v,p) __raw_writew((v),alignw(___io(p))) 39#define outw(v,p) __raw_writew((v),alignw(___io(p)))
@@ -48,6 +53,81 @@
48#define insw(p,d,l) __raw_readsw(alignw(___io(p)),d,l) 53#define insw(p,d,l) __raw_readsw(alignw(___io(p)),d,l)
49#define insl(p,d,l) __raw_readsl(___io(p),d,l) 54#define insl(p,d,l) __raw_readsl(___io(p),d,l)
50 55
56#define __is_io_address(p) ((((unsigned long)(p)) & ~(IXP2000_PCI_IO_SIZE - 1)) == IXP2000_PCI_IO_VIRT_BASE)
57
58#define ioread8(p) \
59 ({ \
60 unsigned int __v; \
61 \
62 if (__is_io_address(p)) { \
63 __v = __raw_readb(alignb(p)); \
64 } else { \
65 __v = __raw_readb(p); \
66 } \
67 \
68 __v; \
69 }) \
70
71#define ioread16(p) \
72 ({ \
73 unsigned int __v; \
74 \
75 if (__is_io_address(p)) { \
76 __v = __raw_readw(alignw(p)); \
77 } else { \
78 __v = le16_to_cpu(__raw_readw(p)); \
79 } \
80 \
81 __v; \
82 })
83
84#define ioread32(p) \
85 ({ \
86 unsigned int __v; \
87 \
88 if (__is_io_address(p)) { \
89 __v = __raw_readl(p); \
90 } else { \
91 __v = le32_to_cpu(__raw_readl(p)); \
92 } \
93 \
94 __v; \
95 })
96
97#define iowrite8(v,p) \
98 ({ \
99 if (__is_io_address(p)) { \
100 __raw_writeb((v), alignb(p)); \
101 } else { \
102 __raw_writeb((v), p); \
103 } \
104 })
105
106#define iowrite16(v,p) \
107 ({ \
108 if (__is_io_address(p)) { \
109 __raw_writew((v), alignw(p)); \
110 } else { \
111 __raw_writew(cpu_to_le16(v), p); \
112 } \
113 })
114
115#define iowrite32(v,p) \
116 ({ \
117 if (__is_io_address(p)) { \
118 __raw_writel((v), p); \
119 } else { \
120 __raw_writel(cpu_to_le32(v), p); \
121 } \
122 })
123
124#define ioport_map(port, nr) ___io(port)
125
126#define ioport_unmap(addr)
127#else
128#define __io(p) ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE))
129#endif
130
51 131
52#ifdef CONFIG_ARCH_IXDP2X01 132#ifdef CONFIG_ARCH_IXDP2X01
53/* 133/*
diff --git a/include/asm-arm/arch-ixp2000/ixdp2x00.h b/include/asm-arm/arch-ixp2000/ixdp2x00.h
index 3a398dfbf125..229381c64283 100644
--- a/include/asm-arm/arch-ixp2000/ixdp2x00.h
+++ b/include/asm-arm/arch-ixp2000/ixdp2x00.h
@@ -21,8 +21,8 @@
21 * On board CPLD memory map 21 * On board CPLD memory map
22 */ 22 */
23#define IXDP2X00_PHYS_CPLD_BASE 0xc7000000 23#define IXDP2X00_PHYS_CPLD_BASE 0xc7000000
24#define IXDP2X00_VIRT_CPLD_BASE 0xfafff000 24#define IXDP2X00_VIRT_CPLD_BASE 0xfe000000
25#define IXDP2X00_CPLD_SIZE 0x00001000 25#define IXDP2X00_CPLD_SIZE 0x00100000
26 26
27 27
28#define IXDP2X00_CPLD_REG(x) \ 28#define IXDP2X00_CPLD_REG(x) \
diff --git a/include/asm-arm/arch-ixp2000/ixdp2x01.h b/include/asm-arm/arch-ixp2000/ixdp2x01.h
index b3a1bcda8d01..b768009c3a51 100644
--- a/include/asm-arm/arch-ixp2000/ixdp2x01.h
+++ b/include/asm-arm/arch-ixp2000/ixdp2x01.h
@@ -18,8 +18,8 @@
18#define __IXDP2X01_H__ 18#define __IXDP2X01_H__
19 19
20#define IXDP2X01_PHYS_CPLD_BASE 0xc6024000 20#define IXDP2X01_PHYS_CPLD_BASE 0xc6024000
21#define IXDP2X01_VIRT_CPLD_BASE 0xfafff000 21#define IXDP2X01_VIRT_CPLD_BASE 0xfe000000
22#define IXDP2X01_CPLD_REGION_SIZE 0x00001000 22#define IXDP2X01_CPLD_REGION_SIZE 0x00100000
23 23
24#define IXDP2X01_CPLD_VIRT_REG(reg) (volatile unsigned long*)(IXDP2X01_VIRT_CPLD_BASE | reg) 24#define IXDP2X01_CPLD_VIRT_REG(reg) (volatile unsigned long*)(IXDP2X01_VIRT_CPLD_BASE | reg)
25#define IXDP2X01_CPLD_PHYS_REG(reg) (volatile u32*)(IXDP2X01_PHYS_CPLD_BASE | reg) 25#define IXDP2X01_CPLD_PHYS_REG(reg) (volatile u32*)(IXDP2X01_PHYS_CPLD_BASE | reg)
diff --git a/include/asm-arm/arch-ixp2000/ixp2000-regs.h b/include/asm-arm/arch-ixp2000/ixp2000-regs.h
index a1d9e181b10f..75623f81ef75 100644
--- a/include/asm-arm/arch-ixp2000/ixp2000-regs.h
+++ b/include/asm-arm/arch-ixp2000/ixp2000-regs.h
@@ -18,6 +18,21 @@
18#ifndef _IXP2000_REGS_H_ 18#ifndef _IXP2000_REGS_H_
19#define _IXP2000_REGS_H_ 19#define _IXP2000_REGS_H_
20 20
21/*
22 * IXP2000 linux memory map:
23 *
24 * virt phys size
25 * fb000000 db000000 16M PCI CFG1
26 * fc000000 da000000 16M PCI CFG0
27 * fd000000 d8000000 16M PCI I/O
28 * fe[0-7]00000 8M per-platform mappings
29 * feb00000 c8000000 1M MSF
30 * fec00000 df000000 1M PCI CSRs
31 * fed00000 de000000 1M PCI CREG
32 * fee00000 d6000000 1M INTCTL
33 * fef00000 c0000000 1M CAP
34 */
35
21/* 36/*
22 * Static I/O regions. 37 * Static I/O regions.
23 * 38 *
@@ -71,6 +86,10 @@
71#define IXP2000_PCI_CSR_VIRT_BASE 0xfec00000 86#define IXP2000_PCI_CSR_VIRT_BASE 0xfec00000
72#define IXP2000_PCI_CSR_SIZE 0x00100000 87#define IXP2000_PCI_CSR_SIZE 0x00100000
73 88
89#define IXP2000_MSF_PHYS_BASE 0xc8000000
90#define IXP2000_MSF_VIRT_BASE 0xfeb00000
91#define IXP2000_MSF_SIZE 0x00100000
92
74#define IXP2000_PCI_IO_PHYS_BASE 0xd8000000 93#define IXP2000_PCI_IO_PHYS_BASE 0xd8000000
75#define IXP2000_PCI_IO_VIRT_BASE 0xfd000000 94#define IXP2000_PCI_IO_VIRT_BASE 0xfd000000
76#define IXP2000_PCI_IO_SIZE 0x01000000 95#define IXP2000_PCI_IO_SIZE 0x01000000
@@ -241,7 +260,7 @@
241#define PCI_CONTROL_BE_DEI (1 << 21) /* Big Endian Data Enable In */ 260#define PCI_CONTROL_BE_DEI (1 << 21) /* Big Endian Data Enable In */
242#define PCI_CONTROL_BE_BEO (1 << 20) /* Big Endian Byte Enable Out */ 261#define PCI_CONTROL_BE_BEO (1 << 20) /* Big Endian Byte Enable Out */
243#define PCI_CONTROL_BE_BEI (1 << 19) /* Big Endian Byte Enable In */ 262#define PCI_CONTROL_BE_BEI (1 << 19) /* Big Endian Byte Enable In */
244#define PCI_CONTROL_PNR (1 << 17) /* PCI Not Reset bit */ 263#define PCI_CONTROL_IEE (1 << 17) /* I/O cycle Endian swap Enable */
245 264
246#define IXP2000_PCI_RST_REL (1 << 2) 265#define IXP2000_PCI_RST_REL (1 << 2)
247#define CFG_RST_DIR (*IXP2000_PCI_CONTROL & IXP2000_PCICNTL_PCF) 266#define CFG_RST_DIR (*IXP2000_PCI_CONTROL & IXP2000_PCICNTL_PCF)
diff --git a/include/asm-arm/arch-ixp2000/platform.h b/include/asm-arm/arch-ixp2000/platform.h
index 901bba6d02b4..c0caf3e3e6fd 100644
--- a/include/asm-arm/arch-ixp2000/platform.h
+++ b/include/asm-arm/arch-ixp2000/platform.h
@@ -115,6 +115,7 @@ static inline unsigned int ixp2000_is_pcimaster(void)
115} 115}
116 116
117void ixp2000_map_io(void); 117void ixp2000_map_io(void);
118void ixp2000_uart_init(void);
118void ixp2000_init_irq(void); 119void ixp2000_init_irq(void);
119void ixp2000_init_time(unsigned long); 120void ixp2000_init_time(unsigned long);
120unsigned long ixp2000_gettimeoffset(void); 121unsigned long ixp2000_gettimeoffset(void);
@@ -138,30 +139,10 @@ struct ixp2000_flash_data {
138 unsigned long (*bank_setup)(unsigned long); 139 unsigned long (*bank_setup)(unsigned long);
139}; 140};
140 141
141/*
142 * GPIO helper functions
143 */
144#define GPIO_IN 0
145#define GPIO_OUT 1
146
147extern void gpio_line_config(int line, int style);
148
149static inline int gpio_line_get(int line)
150{
151 return (((*IXP2000_GPIO_PLR) >> line) & 1);
152}
153
154static inline void gpio_line_set(int line, int value)
155{
156 if (value)
157 ixp2000_reg_write(IXP2000_GPIO_POSR, (1 << line));
158 else
159 ixp2000_reg_write(IXP2000_GPIO_POCR, (1 << line));
160}
161
162struct ixp2000_i2c_pins { 142struct ixp2000_i2c_pins {
163 unsigned long sda_pin; 143 unsigned long sda_pin;
164 unsigned long scl_pin; 144 unsigned long scl_pin;
165}; 145};
166 146
147
167#endif /* !__ASSEMBLY__ */ 148#endif /* !__ASSEMBLY__ */
diff --git a/include/asm-arm/arch-ixp2000/vmalloc.h b/include/asm-arm/arch-ixp2000/vmalloc.h
index 473dff4ec561..275136963a0c 100644
--- a/include/asm-arm/arch-ixp2000/vmalloc.h
+++ b/include/asm-arm/arch-ixp2000/vmalloc.h
@@ -17,4 +17,4 @@
17 * The vmalloc() routines leaves a hole of 4kB between each vmalloced 17 * The vmalloc() routines leaves a hole of 4kB between each vmalloced
18 * area for the same reason. ;) 18 * area for the same reason. ;)
19 */ 19 */
20#define VMALLOC_END 0xfaffefff 20#define VMALLOC_END 0xfb000000
diff --git a/include/asm-arm/arch-ixp4xx/debug-macro.S b/include/asm-arm/arch-ixp4xx/debug-macro.S
index 4499ae8e4b44..2e23651e217f 100644
--- a/include/asm-arm/arch-ixp4xx/debug-macro.S
+++ b/include/asm-arm/arch-ixp4xx/debug-macro.S
@@ -15,6 +15,7 @@
15 tst \rx, #1 @ MMU enabled? 15 tst \rx, #1 @ MMU enabled?
16 moveq \rx, #0xc8000000 16 moveq \rx, #0xc8000000
17 movne \rx, #0xff000000 17 movne \rx, #0xff000000
18 orrne \rx, \rx, #0x00b00000
18 add \rx,\rx,#3 @ Uart regs are at off set of 3 if 19 add \rx,\rx,#3 @ Uart regs are at off set of 3 if
19 @ byte writes used - Big Endian. 20 @ byte writes used - Big Endian.
20 .endm 21 .endm
diff --git a/include/asm-arm/arch-ixp4xx/io.h b/include/asm-arm/arch-ixp4xx/io.h
index c27b9d3079a7..7495026e2c18 100644
--- a/include/asm-arm/arch-ixp4xx/io.h
+++ b/include/asm-arm/arch-ixp4xx/io.h
@@ -3,7 +3,7 @@
3 * 3 *
4 * Author: Deepak Saxena <dsaxena@plexity.net> 4 * Author: Deepak Saxena <dsaxena@plexity.net>
5 * 5 *
6 * Copyright (C) 2002-2004 MontaVista Software, Inc. 6 * Copyright (C) 2002-2005 MontaVista Software, Inc.
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
@@ -383,6 +383,180 @@ __ixp4xx_insl(u32 io_addr, u32 *vaddr, u32 count)
383 *vaddr++ = inl(io_addr); 383 *vaddr++ = inl(io_addr);
384} 384}
385 385
386#define __is_io_address(p) (((unsigned long)p >= 0x0) && \
387 ((unsigned long)p <= 0x0000ffff))
388static inline unsigned int
389__ixp4xx_ioread8(void __iomem *port)
390{
391 if (__is_io_address(port))
392 return (unsigned int)__ixp4xx_inb((unsigned int)port);
393 else
394#ifndef CONFIG_IXP4XX_INDIRECT_PCI
395 return (unsigned int)__raw_readb((u32)port);
396#else
397 return (unsigned int)__ixp4xx_readb((u32)port);
398#endif
399}
400
401static inline void
402__ixp4xx_ioread8_rep(u32 port, u8 *vaddr, u32 count)
403{
404 if (__is_io_address(port))
405 __ixp4xx_insb(port, vaddr, count);
406 else
407#ifndef CONFIG_IXP4XX_INDIRECT_PCI
408 __raw_readsb((void __iomem *)port, vaddr, count);
409#else
410 __ixp4xx_readsb(port, vaddr, count);
411#endif
412}
413
414static inline unsigned int
415__ixp4xx_ioread16(void __iomem *port)
416{
417 if (__is_io_address(port))
418 return (unsigned int)__ixp4xx_inw((unsigned int)port);
419 else
420#ifndef CONFIG_IXP4XX_INDIRECT_PCI
421 return le16_to_cpu(__raw_readw((u32)port));
422#else
423 return (unsigned int)__ixp4xx_readw((u32)port);
424#endif
425}
426
427static inline void
428__ixp4xx_ioread16_rep(u32 port, u16 *vaddr, u32 count)
429{
430 if (__is_io_address(port))
431 __ixp4xx_insw(port, vaddr, count);
432 else
433#ifndef CONFIG_IXP4XX_INDIRECT_PCI
434 __raw_readsw((void __iomem *)port, vaddr, count);
435#else
436 __ixp4xx_readsw(port, vaddr, count);
437#endif
438}
439
440static inline unsigned int
441__ixp4xx_ioread32(void __iomem *port)
442{
443 if (__is_io_address(port))
444 return (unsigned int)__ixp4xx_inl((unsigned int)port);
445 else {
446#ifndef CONFIG_IXP4XX_INDIRECT_PCI
447 return le32_to_cpu(__raw_readl((u32)port));
448#else
449 return (unsigned int)__ixp4xx_readl((u32)port);
450#endif
451 }
452}
453
454static inline void
455__ixp4xx_ioread32_rep(u32 port, u32 *vaddr, u32 count)
456{
457 if (__is_io_address(port))
458 __ixp4xx_insl(port, vaddr, count);
459 else
460#ifndef CONFIG_IXP4XX_INDIRECT_PCI
461 __raw_readsl((void __iomem *)port, vaddr, count);
462#else
463 __ixp4xx_readsl(port, vaddr, count);
464#endif
465}
466
467static inline void
468__ixp4xx_iowrite8(u8 value, void __iomem *port)
469{
470 if (__is_io_address(port))
471 __ixp4xx_outb(value, (unsigned int)port);
472 else
473#ifndef CONFIG_IXP4XX_INDIRECT_PCI
474 __raw_writeb(value, (u32)port);
475#else
476 __ixp4xx_writeb(value, (u32)port);
477#endif
478}
479
480static inline void
481__ixp4xx_iowrite8_rep(u32 port, u8 *vaddr, u32 count)
482{
483 if (__is_io_address(port))
484 __ixp4xx_outsb(port, vaddr, count);
485#ifndef CONFIG_IXP4XX_INDIRECT_PCI
486 __raw_writesb((void __iomem *)port, vaddr, count);
487#else
488 __ixp4xx_writesb(port, vaddr, count);
489#endif
490}
491
492static inline void
493__ixp4xx_iowrite16(u16 value, void __iomem *port)
494{
495 if (__is_io_address(port))
496 __ixp4xx_outw(value, (unsigned int)port);
497 else
498#ifndef CONFIG_IXP4XX_INDIRECT_PCI
499 __raw_writew(cpu_to_le16(value), (u32)port);
500#else
501 __ixp4xx_writew(value, (u32)port);
502#endif
503}
504
505static inline void
506__ixp4xx_iowrite16_rep(u32 port, u16 *vaddr, u32 count)
507{
508 if (__is_io_address(port))
509 __ixp4xx_outsw(port, vaddr, count);
510#ifndef CONFIG_IXP4XX_INDIRECT_PCI
511 __raw_readsw((void __iomem *)port, vaddr, count);
512#else
513 __ixp4xx_writesw(port, vaddr, count);
514#endif
515}
516
517static inline void
518__ixp4xx_iowrite32(u32 value, void __iomem *port)
519{
520 if (__is_io_address(port))
521 __ixp4xx_outl(value, (unsigned int)port);
522 else
523#ifndef CONFIG_IXP4XX_INDIRECT_PCI
524 __raw_writel(cpu_to_le32(value), (u32)port);
525#else
526 __ixp4xx_writel(value, (u32)port);
527#endif
528}
529
530static inline void
531__ixp4xx_iowrite32_rep(u32 port, u32 *vaddr, u32 count)
532{
533 if (__is_io_address(port))
534 __ixp4xx_outsl(port, vaddr, count);
535#ifndef CONFIG_IXP4XX_INDIRECT_PCI
536 __raw_readsl((void __iomem *)port, vaddr, count);
537#else
538 __ixp4xx_outsl(port, vaddr, count);
539#endif
540}
541
542#define ioread8(p) __ixp4xx_ioread8(p)
543#define ioread16(p) __ixp4xx_ioread16(p)
544#define ioread32(p) __ixp4xx_ioread32(p)
545
546#define ioread8_rep(p, v, c) __ixp4xx_ioread8_rep(p, v, c)
547#define ioread16_rep(p, v, c) __ixp4xx_ioread16_rep(p, v, c)
548#define ioread32_rep(p, v, c) __ixp4xx_ioread32_rep(p, v, c)
549
550#define iowrite8(v,p) __ixp4xx_iowrite8(v,p)
551#define iowrite16(v,p) __ixp4xx_iowrite16(v,p)
552#define iowrite32(v,p) __ixp4xx_iowrite32(v,p)
553
554#define iowrite8_rep(p, v, c) __ixp4xx_iowrite8_rep(p, v, c)
555#define iowrite16_rep(p, v, c) __ixp4xx_iowrite16_rep(p, v, c)
556#define iowrite32_rep(p, v, c) __ixp4xx_iowrite32_rep(p, v, c)
557
558#define ioport_map(port, nr) ((void __iomem*)port)
559#define ioport_unmap(addr)
386 560
387#endif // __ASM_ARM_ARCH_IO_H 561#endif // __ASM_ARM_ARCH_IO_H
388 562
diff --git a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
index 8eeb1db6309d..004696a95bdb 100644
--- a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
+++ b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
@@ -69,6 +69,16 @@
69#define IXP4XX_PERIPHERAL_BASE_VIRT (0xFFBF2000) 69#define IXP4XX_PERIPHERAL_BASE_VIRT (0xFFBF2000)
70#define IXP4XX_PERIPHERAL_REGION_SIZE (0x0000C000) 70#define IXP4XX_PERIPHERAL_REGION_SIZE (0x0000C000)
71 71
72/*
73 * Debug UART
74 *
75 * This is basically a remap of UART1 into a region that is section
76 * aligned so that it * can be used with the low-level debug code.
77 */
78#define IXP4XX_DEBUG_UART_BASE_PHYS (0xC8000000)
79#define IXP4XX_DEBUG_UART_BASE_VIRT (0xffb00000)
80#define IXP4XX_DEBUG_UART_REGION_SIZE (0x00001000)
81
72#define IXP4XX_EXP_CS0_OFFSET 0x00 82#define IXP4XX_EXP_CS0_OFFSET 0x00
73#define IXP4XX_EXP_CS1_OFFSET 0x04 83#define IXP4XX_EXP_CS1_OFFSET 0x04
74#define IXP4XX_EXP_CS2_OFFSET 0x08 84#define IXP4XX_EXP_CS2_OFFSET 0x08
diff --git a/include/asm-arm/arch-omap/board-h2.h b/include/asm-arm/arch-omap/board-h2.h
index 60f002b72983..39ca5a31aeea 100644
--- a/include/asm-arm/arch-omap/board-h2.h
+++ b/include/asm-arm/arch-omap/board-h2.h
@@ -34,11 +34,6 @@
34/* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */ 34/* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
35#define OMAP1610_ETHR_START 0x04000300 35#define OMAP1610_ETHR_START 0x04000300
36 36
37/* Intel STRATA NOR flash at CS3 or CS2B(NAND Boot) */
38#define OMAP_NOR_FLASH_SIZE SZ_32M
39#define OMAP_NOR_FLASH_START1 0x0C000000 /* CS3 */
40#define OMAP_NOR_FLASH_START2 0x0A000000 /* CS2B */
41
42/* Samsung NAND flash at CS2B or CS3(NAND Boot) */ 37/* Samsung NAND flash at CS2B or CS3(NAND Boot) */
43#define OMAP_NAND_FLASH_START1 0x0A000000 /* CS2B */ 38#define OMAP_NAND_FLASH_START1 0x0A000000 /* CS2B */
44#define OMAP_NAND_FLASH_START2 0x0C000000 /* CS3 */ 39#define OMAP_NAND_FLASH_START2 0x0C000000 /* CS3 */
diff --git a/include/asm-arm/arch-omap/board-h3.h b/include/asm-arm/arch-omap/board-h3.h
index e4d1cd231731..1b12c1dcc2fa 100644
--- a/include/asm-arm/arch-omap/board-h3.h
+++ b/include/asm-arm/arch-omap/board-h3.h
@@ -30,11 +30,6 @@
30/* In OMAP1710 H3 the Ethernet is directly connected to CS1 */ 30/* In OMAP1710 H3 the Ethernet is directly connected to CS1 */
31#define OMAP1710_ETHR_START 0x04000300 31#define OMAP1710_ETHR_START 0x04000300
32 32
33/* Intel STRATA NOR flash at CS3 or CS2B(NAND Boot) */
34#define OMAP_NOR_FLASH_SIZE SZ_32M
35#define OMAP_NOR_FLASH_START1 0x0C000000 /* CS3 */
36#define OMAP_NOR_FLASH_START2 0x0A000000 /* CS2B */
37
38/* Samsung NAND flash at CS2B or CS3(NAND Boot) */ 33/* Samsung NAND flash at CS2B or CS3(NAND Boot) */
39#define OMAP_NAND_FLASH_START1 0x0A000000 /* CS2B */ 34#define OMAP_NAND_FLASH_START1 0x0A000000 /* CS2B */
40#define OMAP_NAND_FLASH_START2 0x0C000000 /* CS3 */ 35#define OMAP_NAND_FLASH_START2 0x0C000000 /* CS3 */
diff --git a/include/asm-arm/arch-omap/board-osk.h b/include/asm-arm/arch-omap/board-osk.h
index aaa49a0fbd21..2b1a8a4fe44e 100644
--- a/include/asm-arm/arch-omap/board-osk.h
+++ b/include/asm-arm/arch-omap/board-osk.h
@@ -32,10 +32,5 @@
32/* At OMAP5912 OSK the Ethernet is directly connected to CS1 */ 32/* At OMAP5912 OSK the Ethernet is directly connected to CS1 */
33#define OMAP_OSK_ETHR_START 0x04800300 33#define OMAP_OSK_ETHR_START 0x04800300
34 34
35/* Micron NOR flash at CS3 mapped to address 0x0 if BM bit is 1 */
36#define OMAP_OSK_NOR_FLASH_BASE 0xD8000000
37#define OMAP_OSK_NOR_FLASH_SIZE SZ_32M
38#define OMAP_OSK_NOR_FLASH_START 0x00000000
39
40#endif /* __ASM_ARCH_OMAP_OSK_H */ 35#endif /* __ASM_ARCH_OMAP_OSK_H */
41 36
diff --git a/include/asm-arm/arch-omap/board.h b/include/asm-arm/arch-omap/board.h
index 1cefd60b6f2a..95bd625480c1 100644
--- a/include/asm-arm/arch-omap/board.h
+++ b/include/asm-arm/arch-omap/board.h
@@ -16,10 +16,11 @@
16/* Different peripheral ids */ 16/* Different peripheral ids */
17#define OMAP_TAG_CLOCK 0x4f01 17#define OMAP_TAG_CLOCK 0x4f01
18#define OMAP_TAG_MMC 0x4f02 18#define OMAP_TAG_MMC 0x4f02
19#define OMAP_TAG_UART 0x4f03 19#define OMAP_TAG_SERIAL_CONSOLE 0x4f03
20#define OMAP_TAG_USB 0x4f04 20#define OMAP_TAG_USB 0x4f04
21#define OMAP_TAG_LCD 0x4f05 21#define OMAP_TAG_LCD 0x4f05
22#define OMAP_TAG_GPIO_SWITCH 0x4f06 22#define OMAP_TAG_GPIO_SWITCH 0x4f06
23#define OMAP_TAG_UART 0x4f07
23 24
24#define OMAP_TAG_BOOT_REASON 0x4f80 25#define OMAP_TAG_BOOT_REASON 0x4f80
25#define OMAP_TAG_FLASH_PART 0x4f81 26#define OMAP_TAG_FLASH_PART 0x4f81
@@ -35,7 +36,7 @@ struct omap_mmc_config {
35 s16 mmc1_switch_pin, mmc2_switch_pin; 36 s16 mmc1_switch_pin, mmc2_switch_pin;
36}; 37};
37 38
38struct omap_uart_config { 39struct omap_serial_console_config {
39 u8 console_uart; 40 u8 console_uart;
40 u32 console_speed; 41 u32 console_speed;
41}; 42};
@@ -82,7 +83,8 @@ struct omap_lcd_config {
82 */ 83 */
83#define OMAP_GPIO_SWITCH_TYPE_COVER 0x0000 84#define OMAP_GPIO_SWITCH_TYPE_COVER 0x0000
84#define OMAP_GPIO_SWITCH_TYPE_CONNECTION 0x0001 85#define OMAP_GPIO_SWITCH_TYPE_CONNECTION 0x0001
85#define OMAP_GPIO_SWITCH_FLAG_INVERTED 0x0001 86#define OMAP_GPIO_SWITCH_FLAG_INVERTED 0x0001
87#define OMAP_GPIO_SWITCH_FLAG_OUTPUT 0x0002
86struct omap_gpio_switch_config { 88struct omap_gpio_switch_config {
87 char name[12]; 89 char name[12];
88 u16 gpio; 90 u16 gpio;
@@ -99,6 +101,10 @@ struct omap_boot_reason_config {
99 char reason_str[12]; 101 char reason_str[12];
100}; 102};
101 103
104struct omap_uart_config {
105 /* Bit field of UARTs present; bit 0 --> UART1 */
106 unsigned int enabled_uarts;
107};
102 108
103struct omap_board_config_entry { 109struct omap_board_config_entry {
104 u16 tag; 110 u16 tag;
diff --git a/include/asm-arm/arch-omap/common.h b/include/asm-arm/arch-omap/common.h
new file mode 100644
index 000000000000..2a676b4f13b5
--- /dev/null
+++ b/include/asm-arm/arch-omap/common.h
@@ -0,0 +1,36 @@
1/*
2 * linux/include/asm-arm/arch-omap/common.h
3 *
4 * Header for code common to all OMAP machines.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27#ifndef __ARCH_ARM_MACH_OMAP_COMMON_H
28#define __ARCH_ARM_MACH_OMAP_COMMON_H
29
30struct sys_timer;
31
32extern void omap_map_common_io(void);
33extern struct sys_timer omap_timer;
34extern void omap_serial_init(int ports[]);
35
36#endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */
diff --git a/include/asm-arm/arch-omap/dma.h b/include/asm-arm/arch-omap/dma.h
index d785248377db..ce114ce5af5d 100644
--- a/include/asm-arm/arch-omap/dma.h
+++ b/include/asm-arm/arch-omap/dma.h
@@ -241,6 +241,7 @@ extern void omap_dma_unlink_lch (int lch_head, int lch_queue);
241extern dma_addr_t omap_get_dma_src_pos(int lch); 241extern dma_addr_t omap_get_dma_src_pos(int lch);
242extern dma_addr_t omap_get_dma_dst_pos(int lch); 242extern dma_addr_t omap_get_dma_dst_pos(int lch);
243extern void omap_clear_dma(int lch); 243extern void omap_clear_dma(int lch);
244extern int omap_dma_running(void);
244 245
245/* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */ 246/* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
246extern int omap_dma_in_1510_mode(void); 247extern int omap_dma_in_1510_mode(void);
diff --git a/include/asm-arm/arch-omap/hardware.h b/include/asm-arm/arch-omap/hardware.h
index 37e06c782bdf..48258c7f6541 100644
--- a/include/asm-arm/arch-omap/hardware.h
+++ b/include/asm-arm/arch-omap/hardware.h
@@ -54,6 +54,19 @@
54 54
55/* 55/*
56 * ---------------------------------------------------------------------------- 56 * ----------------------------------------------------------------------------
57 * Timers
58 * ----------------------------------------------------------------------------
59 */
60#define OMAP_MPU_TIMER1_BASE (0xfffec500)
61#define OMAP_MPU_TIMER2_BASE (0xfffec600)
62#define OMAP_MPU_TIMER3_BASE (0xfffec700)
63#define MPU_TIMER_FREE (1 << 6)
64#define MPU_TIMER_CLOCK_ENABLE (1 << 5)
65#define MPU_TIMER_AR (1 << 1)
66#define MPU_TIMER_ST (1 << 0)
67
68/*
69 * ----------------------------------------------------------------------------
57 * Clocks 70 * Clocks
58 * ---------------------------------------------------------------------------- 71 * ----------------------------------------------------------------------------
59 */ 72 */
@@ -78,6 +91,7 @@
78 91
79/* DSP clock control */ 92/* DSP clock control */
80#define DSP_CONFIG_REG_BASE (0xe1008000) 93#define DSP_CONFIG_REG_BASE (0xe1008000)
94#define DSP_CKCTL (DSP_CONFIG_REG_BASE + 0x0)
81#define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4) 95#define DSP_IDLECT1 (DSP_CONFIG_REG_BASE + 0x4)
82#define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8) 96#define DSP_IDLECT2 (DSP_CONFIG_REG_BASE + 0x8)
83 97
@@ -88,6 +102,7 @@
88 */ 102 */
89#define ULPD_REG_BASE (0xfffe0800) 103#define ULPD_REG_BASE (0xfffe0800)
90#define ULPD_IT_STATUS (ULPD_REG_BASE + 0x14) 104#define ULPD_IT_STATUS (ULPD_REG_BASE + 0x14)
105#define ULPD_SETUP_ANALOG_CELL_3 (ULPD_REG_BASE + 0x24)
91#define ULPD_CLOCK_CTRL (ULPD_REG_BASE + 0x30) 106#define ULPD_CLOCK_CTRL (ULPD_REG_BASE + 0x30)
92# define DIS_USB_PVCI_CLK (1 << 5) /* no USB/FAC synch */ 107# define DIS_USB_PVCI_CLK (1 << 5) /* no USB/FAC synch */
93# define USB_MCLK_EN (1 << 4) /* enable W4_USB_CLKO */ 108# define USB_MCLK_EN (1 << 4) /* enable W4_USB_CLKO */
@@ -268,17 +283,10 @@
268 * Processor specific defines 283 * Processor specific defines
269 * --------------------------------------------------------------------------- 284 * ---------------------------------------------------------------------------
270 */ 285 */
271#ifdef CONFIG_ARCH_OMAP730
272#include "omap730.h"
273#endif
274 286
275#ifdef CONFIG_ARCH_OMAP1510 287#include "omap730.h"
276#include "omap1510.h" 288#include "omap1510.h"
277#endif
278
279#ifdef CONFIG_ARCH_OMAP16XX
280#include "omap16xx.h" 289#include "omap16xx.h"
281#endif
282 290
283/* 291/*
284 * --------------------------------------------------------------------------- 292 * ---------------------------------------------------------------------------
diff --git a/include/asm-arm/arch-omap/irqs.h b/include/asm-arm/arch-omap/irqs.h
index 6701fd9e5f9b..0d05a7c957d1 100644
--- a/include/asm-arm/arch-omap/irqs.h
+++ b/include/asm-arm/arch-omap/irqs.h
@@ -159,6 +159,7 @@
159#define INT_1610_GPIO_BANK3 (41 + IH2_BASE) 159#define INT_1610_GPIO_BANK3 (41 + IH2_BASE)
160#define INT_1610_MMC2 (42 + IH2_BASE) 160#define INT_1610_MMC2 (42 + IH2_BASE)
161#define INT_1610_CF (43 + IH2_BASE) 161#define INT_1610_CF (43 + IH2_BASE)
162#define INT_1610_WAKE_UP_REQ (46 + IH2_BASE)
162#define INT_1610_GPIO_BANK4 (48 + IH2_BASE) 163#define INT_1610_GPIO_BANK4 (48 + IH2_BASE)
163#define INT_1610_SPI (49 + IH2_BASE) 164#define INT_1610_SPI (49 + IH2_BASE)
164#define INT_1610_DMA_CH6 (53 + IH2_BASE) 165#define INT_1610_DMA_CH6 (53 + IH2_BASE)
@@ -238,6 +239,8 @@
238#define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE) 239#define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
239#define IH_BOARD_BASE (16 + IH_MPUIO_BASE) 240#define IH_BOARD_BASE (16 + IH_MPUIO_BASE)
240 241
242#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32))
243
241#ifndef __ASSEMBLY__ 244#ifndef __ASSEMBLY__
242extern void omap_init_irq(void); 245extern void omap_init_irq(void);
243#endif 246#endif
diff --git a/include/asm-arm/arch-omap/mux.h b/include/asm-arm/arch-omap/mux.h
index 39f99decbb7b..5bd3f0097fc6 100644
--- a/include/asm-arm/arch-omap/mux.h
+++ b/include/asm-arm/arch-omap/mux.h
@@ -231,7 +231,7 @@ typedef enum {
231 J19_1610_ETM_D6, 231 J19_1610_ETM_D6,
232 J18_1610_ETM_D7, 232 J18_1610_ETM_D7,
233 233
234 /* OMAP-1610 GPIO */ 234 /* OMAP16XX GPIO */
235 P20_1610_GPIO4, 235 P20_1610_GPIO4,
236 V9_1610_GPIO7, 236 V9_1610_GPIO7,
237 W8_1610_GPIO9, 237 W8_1610_GPIO9,
@@ -241,6 +241,9 @@ typedef enum {
241 AA20_1610_GPIO_41, 241 AA20_1610_GPIO_41,
242 W19_1610_GPIO48, 242 W19_1610_GPIO48,
243 M7_1610_GPIO62, 243 M7_1610_GPIO62,
244 V14_16XX_GPIO37,
245 R9_16XX_GPIO18,
246 L14_16XX_GPIO49,
244 247
245 /* OMAP-1610 uWire */ 248 /* OMAP-1610 uWire */
246 V19_1610_UWIRE_SCLK, 249 V19_1610_UWIRE_SCLK,
@@ -285,12 +288,13 @@ typedef enum {
285 V6_USB2_TXD, 288 V6_USB2_TXD,
286 W5_USB2_SE0, 289 W5_USB2_SE0,
287 290
288 /* UART1 1610 */ 291 /* 16XX UART */
289
290 R13_1610_UART1_TX, 292 R13_1610_UART1_TX,
291 V14_1610_UART1_RX, 293 V14_16XX_UART1_RX,
292 R14_1610_UART1_CTS, 294 R14_1610_UART1_CTS,
293 AA15_1610_UART1_RTS, 295 AA15_1610_UART1_RTS,
296 R9_16XX_UART2_RX,
297 L14_16XX_UART3_RX,
294 298
295 /* I2C OMAP-1610 */ 299 /* I2C OMAP-1610 */
296 I2C_SCL, 300 I2C_SCL,
@@ -332,7 +336,7 @@ typedef enum {
332 * Table of various FUNC_MUX and PULL_DWN combinations for each device. 336 * Table of various FUNC_MUX and PULL_DWN combinations for each device.
333 * See also reg_cfg_t above for the lookup table. 337 * See also reg_cfg_t above for the lookup table.
334 */ 338 */
335static reg_cfg_set __initdata_or_module 339static const reg_cfg_set __initdata_or_module
336reg_cfg_table[] = { 340reg_cfg_table[] = {
337/* 341/*
338 * description mux mode mux pull pull pull pu_pd pu dbg 342 * description mux mode mux pull pull pull pu_pd pu dbg
@@ -455,7 +459,7 @@ MUX_CFG("L19_1610_ETM_D0", 5, 18, 1, 0, 26, 0, 0, 0, 1)
455MUX_CFG("J19_1610_ETM_D6", 5, 0, 1, 0, 20, 0, 0, 0, 1) 459MUX_CFG("J19_1610_ETM_D6", 5, 0, 1, 0, 20, 0, 0, 0, 1)
456MUX_CFG("J18_1610_ETM_D7", 5, 27, 1, 0, 19, 0, 0, 0, 1) 460MUX_CFG("J18_1610_ETM_D7", 5, 27, 1, 0, 19, 0, 0, 0, 1)
457 461
458/* OMAP-1610 GPIO */ 462/* OMAP16XX GPIO */
459MUX_CFG("P20_1610_GPIO4", 6, 27, 0, 1, 7, 0, 1, 1, 1) 463MUX_CFG("P20_1610_GPIO4", 6, 27, 0, 1, 7, 0, 1, 1, 1)
460MUX_CFG("V9_1610_GPIO7", B, 12, 1, 2, 20, 0, 2, 1, 1) 464MUX_CFG("V9_1610_GPIO7", B, 12, 1, 2, 20, 0, 2, 1, 1)
461MUX_CFG("W8_1610_GPIO9", B, 21, 0, 2, 23, 0, 2, 1, 1) 465MUX_CFG("W8_1610_GPIO9", B, 21, 0, 2, 23, 0, 2, 1, 1)
@@ -465,6 +469,9 @@ MUX_CFG("V5_1610_GPIO24", B, 15, 7, 2, 21, 0, 2, 1, 1)
465MUX_CFG("AA20_1610_GPIO_41", 9, 9, 7, 1, 31, 0, 1, 1, 1) 469MUX_CFG("AA20_1610_GPIO_41", 9, 9, 7, 1, 31, 0, 1, 1, 1)
466MUX_CFG("W19_1610_GPIO48", 8, 15, 7, 1, 23, 1, 1, 0, 1) 470MUX_CFG("W19_1610_GPIO48", 8, 15, 7, 1, 23, 1, 1, 0, 1)
467MUX_CFG("M7_1610_GPIO62", 10, 0, 0, 4, 24, 0, 4, 0, 1) 471MUX_CFG("M7_1610_GPIO62", 10, 0, 0, 4, 24, 0, 4, 0, 1)
472MUX_CFG("V14_16XX_GPIO37", 9, 18, 7, 2, 2, 0, 2, 2, 0)
473MUX_CFG("R9_16XX_GPIO18", C, 18, 7, 3, 0, 0, 3, 0, 0)
474MUX_CFG("L14_16XX_GPIO49", 6, 3, 7, 0, 31, 0, 0, 31, 0)
468 475
469/* OMAP-1610 uWire */ 476/* OMAP-1610 uWire */
470MUX_CFG("V19_1610_UWIRE_SCLK", 8, 6, 0, 1, 20, 0, 1, 1, 1) 477MUX_CFG("V19_1610_UWIRE_SCLK", 8, 6, 0, 1, 20, 0, 1, 1, 1)
@@ -503,16 +510,17 @@ MUX_CFG("Y10_USB0_SUSP", B, 3, 5, 2, 17, 0, 2, 0, 1)
503MUX_CFG("W9_USB2_TXEN", B, 9, 1, NA, 0, 0, NA, 0, 1) 510MUX_CFG("W9_USB2_TXEN", B, 9, 1, NA, 0, 0, NA, 0, 1)
504MUX_CFG("AA9_USB2_VP", B, 6, 1, NA, 0, 0, NA, 0, 1) 511MUX_CFG("AA9_USB2_VP", B, 6, 1, NA, 0, 0, NA, 0, 1)
505MUX_CFG("Y5_USB2_RCV", C, 21, 1, NA, 0, 0, NA, 0, 1) 512MUX_CFG("Y5_USB2_RCV", C, 21, 1, NA, 0, 0, NA, 0, 1)
506MUX_CFG("R8_USB2_VM", C, 18, 1, NA, 0, 0, NA, 0, 1) 513MUX_CFG("R9_USB2_VM", C, 18, 1, NA, 0, 0, NA, 0, 1)
507MUX_CFG("V6_USB2_TXD", C, 27, 2, NA, 0, 0, NA, 0, 1) 514MUX_CFG("V6_USB2_TXD", C, 27, 2, NA, 0, 0, NA, 0, 1)
508MUX_CFG("W5_USB2_SE0", C, 24, 2, NA, 0, 0, NA, 0, 1) 515MUX_CFG("W5_USB2_SE0", C, 24, 2, NA, 0, 0, NA, 0, 1)
509 516
510 517/* 16XX UART */
511/* UART1 */
512MUX_CFG("R13_1610_UART1_TX", A, 12, 6, 2, 10, 0, 2, 10, 1) 518MUX_CFG("R13_1610_UART1_TX", A, 12, 6, 2, 10, 0, 2, 10, 1)
513MUX_CFG("V14_1610_UART1_RX", 9, 18, 0, 2, 2, 0, 2, 2, 1) 519MUX_CFG("V14_16XX_UART1_RX", 9, 18, 0, 2, 2, 0, 2, 2, 1)
514MUX_CFG("R14_1610_UART1_CTS", 9, 15, 0, 2, 1, 0, 2, 1, 1) 520MUX_CFG("R14_1610_UART1_CTS", 9, 15, 0, 2, 1, 0, 2, 1, 1)
515MUX_CFG("AA15_1610_UART1_RTS", 9, 12, 1, 2, 0, 0, 2, 0, 1) 521MUX_CFG("AA15_1610_UART1_RTS", 9, 12, 1, 2, 0, 0, 2, 0, 1)
522MUX_CFG("R9_16XX_UART2_RX", C, 18, 0, 3, 0, 0, 3, 0, 1)
523MUX_CFG("L14_16XX_UART3_RX", 6, 3, 0, 0, 31, 0, 0, 31, 1)
516 524
517/* I2C interface */ 525/* I2C interface */
518MUX_CFG("I2C_SCL", 7, 24, 0, NA, 0, 0, NA, 0, 0) 526MUX_CFG("I2C_SCL", 7, 24, 0, NA, 0, 0, NA, 0, 0)
diff --git a/include/asm-arm/arch-omap/omap16xx.h b/include/asm-arm/arch-omap/omap16xx.h
index 88b1fe43ae9e..38a9b95e6a33 100644
--- a/include/asm-arm/arch-omap/omap16xx.h
+++ b/include/asm-arm/arch-omap/omap16xx.h
@@ -183,5 +183,37 @@
183#define OMAP16XX_PWL_ENABLE (OMAP16XX_PWL_BASE + 0x00) 183#define OMAP16XX_PWL_ENABLE (OMAP16XX_PWL_BASE + 0x00)
184#define OMAP16XX_PWL_CLK_ENABLE (OMAP16XX_PWL_BASE + 0x04) 184#define OMAP16XX_PWL_CLK_ENABLE (OMAP16XX_PWL_BASE + 0x04)
185 185
186/*
187 * ---------------------------------------------------------------------------
188 * Watchdog timer
189 * ---------------------------------------------------------------------------
190 */
191
192/* 32-bit Watchdog timer in OMAP 16XX */
193#define OMAP_16XX_WATCHDOG_BASE (0xfffeb000)
194#define OMAP_16XX_WIDR (OMAP_16XX_WATCHDOG_BASE + 0x00)
195#define OMAP_16XX_WD_SYSCONFIG (OMAP_16XX_WATCHDOG_BASE + 0x10)
196#define OMAP_16XX_WD_SYSSTATUS (OMAP_16XX_WATCHDOG_BASE + 0x14)
197#define OMAP_16XX_WCLR (OMAP_16XX_WATCHDOG_BASE + 0x24)
198#define OMAP_16XX_WCRR (OMAP_16XX_WATCHDOG_BASE + 0x28)
199#define OMAP_16XX_WLDR (OMAP_16XX_WATCHDOG_BASE + 0x2c)
200#define OMAP_16XX_WTGR (OMAP_16XX_WATCHDOG_BASE + 0x30)
201#define OMAP_16XX_WWPS (OMAP_16XX_WATCHDOG_BASE + 0x34)
202#define OMAP_16XX_WSPR (OMAP_16XX_WATCHDOG_BASE + 0x48)
203
204#define WCLR_PRE_SHIFT 5
205#define WCLR_PTV_SHIFT 2
206
207#define WWPS_W_PEND_WSPR (1 << 4)
208#define WWPS_W_PEND_WTGR (1 << 3)
209#define WWPS_W_PEND_WLDR (1 << 2)
210#define WWPS_W_PEND_WCRR (1 << 1)
211#define WWPS_W_PEND_WCLR (1 << 0)
212
213#define WSPR_ENABLE_0 (0x0000bbbb)
214#define WSPR_ENABLE_1 (0x00004444)
215#define WSPR_DISABLE_0 (0x0000aaaa)
216#define WSPR_DISABLE_1 (0x00005555)
217
186#endif /* __ASM_ARCH_OMAP16XX_H */ 218#endif /* __ASM_ARCH_OMAP16XX_H */
187 219
diff --git a/include/asm-arm/arch-omap/system.h b/include/asm-arm/arch-omap/system.h
index 17a2c4825f07..ff37bc27e603 100644
--- a/include/asm-arm/arch-omap/system.h
+++ b/include/asm-arm/arch-omap/system.h
@@ -5,7 +5,9 @@
5#ifndef __ASM_ARCH_SYSTEM_H 5#ifndef __ASM_ARCH_SYSTEM_H
6#define __ASM_ARCH_SYSTEM_H 6#define __ASM_ARCH_SYSTEM_H
7#include <linux/config.h> 7#include <linux/config.h>
8#include <asm/mach-types.h>
8#include <asm/arch/hardware.h> 9#include <asm/arch/hardware.h>
10#include <asm/mach-types.h>
9 11
10static inline void arch_idle(void) 12static inline void arch_idle(void)
11{ 13{
@@ -14,7 +16,24 @@ static inline void arch_idle(void)
14 16
15static inline void arch_reset(char mode) 17static inline void arch_reset(char mode)
16{ 18{
17 omap_writew(1, ARM_RSTCT1); 19
20#ifdef CONFIG_ARCH_OMAP16XX
21 /*
22 * Workaround for 5912/1611b bug mentioned in sprz209d.pdf p. 28
23 * "Global Software Reset Affects Traffic Controller Frequency".
24 */
25 if (cpu_is_omap5912()) {
26 omap_writew(omap_readw(DPLL_CTL) & ~(1 << 4),
27 DPLL_CTL);
28 omap_writew(0x8, ARM_RSTCT1);
29 }
30#endif
31#ifdef CONFIG_MACH_VOICEBLUE
32 if (machine_is_voiceblue())
33 voiceblue_reset();
34 else
35#endif
36 omap_writew(1, ARM_RSTCT1);
18} 37}
19 38
20#endif 39#endif
diff --git a/include/asm-arm/arch-omap/tps65010.h b/include/asm-arm/arch-omap/tps65010.h
index 0f97bb2e8fce..b9aa2b3a3909 100644
--- a/include/asm-arm/arch-omap/tps65010.h
+++ b/include/asm-arm/arch-omap/tps65010.h
@@ -30,6 +30,66 @@
30 30
31/* 31/*
32 * ---------------------------------------------------------------------------- 32 * ----------------------------------------------------------------------------
33 * Registers, all 8 bits
34 * ----------------------------------------------------------------------------
35 */
36
37#define TPS_CHGSTATUS 0x01
38# define TPS_CHG_USB (1 << 7)
39# define TPS_CHG_AC (1 << 6)
40# define TPS_CHG_THERM (1 << 5)
41# define TPS_CHG_TERM (1 << 4)
42# define TPS_CHG_TAPER_TMO (1 << 3)
43# define TPS_CHG_CHG_TMO (1 << 2)
44# define TPS_CHG_PRECHG_TMO (1 << 1)
45# define TPS_CHG_TEMP_ERR (1 << 0)
46#define TPS_REGSTATUS 0x02
47# define TPS_REG_ONOFF (1 << 7)
48# define TPS_REG_COVER (1 << 6)
49# define TPS_REG_UVLO (1 << 5)
50# define TPS_REG_NO_CHG (1 << 4) /* tps65013 */
51# define TPS_REG_PG_LD02 (1 << 3)
52# define TPS_REG_PG_LD01 (1 << 2)
53# define TPS_REG_PG_MAIN (1 << 1)
54# define TPS_REG_PG_CORE (1 << 0)
55#define TPS_MASK1 0x03
56#define TPS_MASK2 0x04
57#define TPS_ACKINT1 0x05
58#define TPS_ACKINT2 0x06
59#define TPS_CHGCONFIG 0x07
60# define TPS_CHARGE_POR (1 << 7) /* 65010/65012 */
61# define TPS65013_AUA (1 << 7) /* 65011/65013 */
62# define TPS_CHARGE_RESET (1 << 6)
63# define TPS_CHARGE_FAST (1 << 5)
64# define TPS_CHARGE_CURRENT (3 << 3)
65# define TPS_VBUS_500MA (1 << 2)
66# define TPS_VBUS_CHARGING (1 << 1)
67# define TPS_CHARGE_ENABLE (1 << 0)
68#define TPS_LED1_ON 0x08
69#define TPS_LED1_PER 0x09
70#define TPS_LED2_ON 0x0a
71#define TPS_LED2_PER 0x0b
72#define TPS_VDCDC1 0x0c
73# define TPS_ENABLE_LP (1 << 3)
74#define TPS_VDCDC2 0x0d
75#define TPS_VREGS1 0x0e
76# define TPS_LDO2_ENABLE (1 << 7)
77# define TPS_LDO2_OFF (1 << 6)
78# define TPS_VLDO2_3_0V (3 << 4)
79# define TPS_VLDO2_2_75V (2 << 4)
80# define TPS_VLDO2_2_5V (1 << 4)
81# define TPS_VLDO2_1_8V (0 << 4)
82# define TPS_LDO1_ENABLE (1 << 3)
83# define TPS_LDO1_OFF (1 << 2)
84# define TPS_VLDO1_3_0V (3 << 0)
85# define TPS_VLDO1_2_75V (2 << 0)
86# define TPS_VLDO1_2_5V (1 << 0)
87# define TPS_VLDO1_ADJ (0 << 0)
88#define TPS_MASK3 0x0f
89#define TPS_DEFGPIO 0x10
90
91/*
92 * ----------------------------------------------------------------------------
33 * Macros used by exported functions 93 * Macros used by exported functions
34 * ---------------------------------------------------------------------------- 94 * ----------------------------------------------------------------------------
35 */ 95 */
@@ -71,10 +131,26 @@ extern int tps65010_set_gpio_out_value(unsigned gpio, unsigned value);
71 */ 131 */
72extern int tps65010_set_led(unsigned led, unsigned mode); 132extern int tps65010_set_led(unsigned led, unsigned mode);
73 133
134/* tps65010_set_vib parameter:
135 * value: ON or OFF
136 */
137extern int tps65010_set_vib(unsigned value);
138
74/* tps65010_set_low_pwr parameter: 139/* tps65010_set_low_pwr parameter:
75 * mode: ON or OFF 140 * mode: ON or OFF
76 */ 141 */
77extern int tps65010_set_low_pwr(unsigned mode); 142extern int tps65010_set_low_pwr(unsigned mode);
78 143
144/* tps65010_config_vregs1 parameter:
145 * value to be written to VREGS1 register
146 * Note: The complete register is written, set all bits you need
147 */
148extern int tps65010_config_vregs1(unsigned value);
149
150/* tps65013_set_low_pwr parameter:
151 * mode: ON or OFF
152 */
153extern int tps65013_set_low_pwr(unsigned mode);
154
79#endif /* __ASM_ARCH_TPS65010_H */ 155#endif /* __ASM_ARCH_TPS65010_H */
80 156
diff --git a/include/asm-arm/arch-omap/usb.h b/include/asm-arm/arch-omap/usb.h
index 1438c6cef0ca..054fb9a8e0c6 100644
--- a/include/asm-arm/arch-omap/usb.h
+++ b/include/asm-arm/arch-omap/usb.h
@@ -47,6 +47,15 @@
47# define HMC_TLLATTACH (1 << 6) 47# define HMC_TLLATTACH (1 << 6)
48# define OTG_HMC(w) (((w)>>0)&0x3f) 48# define OTG_HMC(w) (((w)>>0)&0x3f)
49#define OTG_CTRL_REG OTG_REG32(0x0c) 49#define OTG_CTRL_REG OTG_REG32(0x0c)
50# define OTG_USB2_EN (1 << 29)
51# define OTG_USB2_DP (1 << 28)
52# define OTG_USB2_DM (1 << 27)
53# define OTG_USB1_EN (1 << 26)
54# define OTG_USB1_DP (1 << 25)
55# define OTG_USB1_DM (1 << 24)
56# define OTG_USB0_EN (1 << 23)
57# define OTG_USB0_DP (1 << 22)
58# define OTG_USB0_DM (1 << 21)
50# define OTG_ASESSVLD (1 << 20) 59# define OTG_ASESSVLD (1 << 20)
51# define OTG_BSESSEND (1 << 19) 60# define OTG_BSESSEND (1 << 19)
52# define OTG_BSESSVLD (1 << 18) 61# define OTG_BSESSVLD (1 << 18)
diff --git a/include/asm-arm/arch-pxa/debug-macro.S b/include/asm-arm/arch-pxa/debug-macro.S
index f288e74b67c2..b6ec68879176 100644
--- a/include/asm-arm/arch-pxa/debug-macro.S
+++ b/include/asm-arm/arch-pxa/debug-macro.S
@@ -11,6 +11,8 @@
11 * 11 *
12*/ 12*/
13 13
14#include "hardware.h"
15
14 .macro addruart,rx 16 .macro addruart,rx
15 mrc p15, 0, \rx, c1, c0 17 mrc p15, 0, \rx, c1, c0
16 tst \rx, #1 @ MMU enabled? 18 tst \rx, #1 @ MMU enabled?
diff --git a/include/asm-arm/arch-pxa/mtd-xip.h b/include/asm-arm/arch-pxa/mtd-xip.h
new file mode 100644
index 000000000000..8704dbceb432
--- /dev/null
+++ b/include/asm-arm/arch-pxa/mtd-xip.h
@@ -0,0 +1,37 @@
1/*
2 * MTD primitives for XIP support. Architecture specific functions
3 *
4 * Do not include this file directly. It's included from linux/mtd/xip.h
5 *
6 * Author: Nicolas Pitre
7 * Created: Nov 2, 2004
8 * Copyright: (C) 2004 MontaVista Software, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * $Id: xip.h,v 1.2 2004/12/01 15:49:10 nico Exp $
15 */
16
17#ifndef __ARCH_PXA_MTD_XIP_H__
18#define __ARCH_PXA_MTD_XIP_H__
19
20#include <asm/arch/pxa-regs.h>
21
22#define xip_irqpending() (ICIP & ICMR)
23
24/* we sample OSCR and convert desired delta to usec (1/4 ~= 1000000/3686400) */
25#define xip_currtime() (OSCR)
26#define xip_elapsed_since(x) (signed)((OSCR - (x)) / 4)
27
28/*
29 * xip_cpu_idle() is used when waiting for a delay equal or larger than
30 * the system timer tick period. This should put the CPU into idle mode
31 * to save power and to be woken up only when some interrupts are pending.
32 * As above, this should not rely upon standard kernel code.
33 */
34
35#define xip_cpu_idle() asm volatile ("mcr p14, 0, %0, c7, c0, 0" :: "r" (1))
36
37#endif /* __ARCH_PXA_MTD_XIP_H__ */
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index b5e54a9e9fa7..51f0fe0ac165 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -1505,6 +1505,7 @@
1505#define PSSR_OTGPH (1 << 6) /* OTG Peripheral control Hold */ 1505#define PSSR_OTGPH (1 << 6) /* OTG Peripheral control Hold */
1506#define PSSR_RDH (1 << 5) /* Read Disable Hold */ 1506#define PSSR_RDH (1 << 5) /* Read Disable Hold */
1507#define PSSR_PH (1 << 4) /* Peripheral Control Hold */ 1507#define PSSR_PH (1 << 4) /* Peripheral Control Hold */
1508#define PSSR_STS (1 << 3) /* Standby Mode Status */
1508#define PSSR_VFS (1 << 2) /* VDD Fault Status */ 1509#define PSSR_VFS (1 << 2) /* VDD Fault Status */
1509#define PSSR_BFS (1 << 1) /* Battery Fault Status */ 1510#define PSSR_BFS (1 << 1) /* Battery Fault Status */
1510#define PSSR_SSS (1 << 0) /* Software Sleep Status */ 1511#define PSSR_SSS (1 << 0) /* Software Sleep Status */
@@ -1965,6 +1966,7 @@
1965#define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */ 1966#define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */
1966#define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */ 1967#define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */
1967 1968
1969#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */
1968#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */ 1970#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
1969#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */ 1971#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
1970#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */ 1972#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */
diff --git a/include/asm-arm/arch-s3c2410/audio.h b/include/asm-arm/arch-s3c2410/audio.h
new file mode 100644
index 000000000000..0d276e67f2fb
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/audio.h
@@ -0,0 +1,49 @@
1/* linux/include/asm-arm/arch-s3c2410/audio.h
2 *
3 * (c) 2004-2005 Simtec Electronics
4 * http://www.simtec.co.uk/products/SWLINUX/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C24XX - Audio platfrom_device info
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 * Changelog:
14 * 20-Nov-2004 BJD Created file
15 * 07-Mar-2005 BJD Added suspend/resume calls
16*/
17
18#ifndef __ASM_ARCH_AUDIO_H
19#define __ASM_ARCH_AUDIO_H __FILE__
20
21/* struct s3c24xx_iis_ops
22 *
23 * called from the s3c24xx audio core to deal with the architecture
24 * or the codec's setup and control.
25 *
26 * the pointer to itself is passed through in case the caller wants to
27 * embed this in an larger structure for easy reference to it's context.
28*/
29
30struct s3c24xx_iis_ops {
31 struct module *owner;
32
33 int (*startup)(struct s3c24xx_iis_ops *me);
34 void (*shutdown)(struct s3c24xx_iis_ops *me);
35 int (*suspend)(struct s3c24xx_iis_ops *me);
36 int (*resume)(struct s3c24xx_iis_ops *me);
37
38 int (*open)(struct s3c24xx_iis_ops *me, snd_pcm_substream_t *strm);
39 int (*close)(struct s3c24xx_iis_ops *me, snd_pcm_substream_t *strm);
40 int (*prepare)(struct s3c24xx_iis_ops *me, snd_pcm_substream_t *strm, snd_pcm_runtime_t *rt);
41};
42
43struct s3c24xx_platdata_iis {
44 const char *codec_clk;
45 struct s3c24xx_iis_ops *ops;
46 int (*match_dev)(struct device *dev);
47};
48
49#endif /* __ASM_ARCH_AUDIO_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-iis.h b/include/asm-arm/arch-s3c2410/regs-iis.h
index 385b07d510da..fdd62e8cd6cb 100644
--- a/include/asm-arm/arch-s3c2410/regs-iis.h
+++ b/include/asm-arm/arch-s3c2410/regs-iis.h
@@ -15,6 +15,9 @@
15 * 12-03-2004 BJD Updated include protection 15 * 12-03-2004 BJD Updated include protection
16 * 07-03-2005 BJD Added FIFO size flags and S3C2440 MPLL 16 * 07-03-2005 BJD Added FIFO size flags and S3C2440 MPLL
17 * 05-04-2005 LCVR Added IISFCON definitions for the S3C2400 17 * 05-04-2005 LCVR Added IISFCON definitions for the S3C2400
18 * 18-07-2005 DA Change IISCON_MPLL to IISMOD_MPLL
19 * Correct IISMOD_256FS and IISMOD_384FS
20 * Add IISCON_PSCEN
18 */ 21 */
19 22
20#ifndef __ASM_ARCH_REGS_IIS_H 23#ifndef __ASM_ARCH_REGS_IIS_H
@@ -22,7 +25,6 @@
22 25
23#define S3C2410_IISCON (0x00) 26#define S3C2410_IISCON (0x00)
24 27
25#define S3C2440_IISCON_MPLL (1<<9)
26#define S3C2410_IISCON_LRINDEX (1<<8) 28#define S3C2410_IISCON_LRINDEX (1<<8)
27#define S3C2410_IISCON_TXFIFORDY (1<<7) 29#define S3C2410_IISCON_TXFIFORDY (1<<7)
28#define S3C2410_IISCON_RXFIFORDY (1<<6) 30#define S3C2410_IISCON_RXFIFORDY (1<<6)
@@ -30,10 +32,12 @@
30#define S3C2410_IISCON_RXDMAEN (1<<4) 32#define S3C2410_IISCON_RXDMAEN (1<<4)
31#define S3C2410_IISCON_TXIDLE (1<<3) 33#define S3C2410_IISCON_TXIDLE (1<<3)
32#define S3C2410_IISCON_RXIDLE (1<<2) 34#define S3C2410_IISCON_RXIDLE (1<<2)
35#define S3C2410_IISCON_PSCEN (1<<1)
33#define S3C2410_IISCON_IISEN (1<<0) 36#define S3C2410_IISCON_IISEN (1<<0)
34 37
35#define S3C2410_IISMOD (0x04) 38#define S3C2410_IISMOD (0x04)
36 39
40#define S3C2440_IISMOD_MPLL (1<<9)
37#define S3C2410_IISMOD_SLAVE (1<<8) 41#define S3C2410_IISMOD_SLAVE (1<<8)
38#define S3C2410_IISMOD_NOXFER (0<<6) 42#define S3C2410_IISMOD_NOXFER (0<<6)
39#define S3C2410_IISMOD_RXMODE (1<<6) 43#define S3C2410_IISMOD_RXMODE (1<<6)
@@ -46,8 +50,8 @@
46#define S3C2410_IISMOD_8BIT (0<<3) 50#define S3C2410_IISMOD_8BIT (0<<3)
47#define S3C2410_IISMOD_16BIT (1<<3) 51#define S3C2410_IISMOD_16BIT (1<<3)
48#define S3C2410_IISMOD_BITMASK (1<<3) 52#define S3C2410_IISMOD_BITMASK (1<<3)
49#define S3C2410_IISMOD_256FS (0<<1) 53#define S3C2410_IISMOD_256FS (0<<2)
50#define S3C2410_IISMOD_384FS (1<<1) 54#define S3C2410_IISMOD_384FS (1<<2)
51#define S3C2410_IISMOD_16FS (0<<0) 55#define S3C2410_IISMOD_16FS (0<<0)
52#define S3C2410_IISMOD_32FS (1<<0) 56#define S3C2410_IISMOD_32FS (1<<0)
53#define S3C2410_IISMOD_48FS (2<<0) 57#define S3C2410_IISMOD_48FS (2<<0)
diff --git a/include/asm-arm/arch-sa1100/mtd-xip.h b/include/asm-arm/arch-sa1100/mtd-xip.h
new file mode 100644
index 000000000000..80cfdac2b944
--- /dev/null
+++ b/include/asm-arm/arch-sa1100/mtd-xip.h
@@ -0,0 +1,26 @@
1/*
2 * MTD primitives for XIP support. Architecture specific functions
3 *
4 * Do not include this file directly. It's included from linux/mtd/xip.h
5 *
6 * Author: Nicolas Pitre
7 * Created: Nov 2, 2004
8 * Copyright: (C) 2004 MontaVista Software, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * $Id: xip.h,v 1.2 2004/12/01 15:49:10 nico Exp $
15 */
16
17#ifndef __ARCH_SA1100_MTD_XIP_H__
18#define __ARCH_SA1100_MTD_XIP_H__
19
20#define xip_irqpending() (ICIP & ICMR)
21
22/* we sample OSCR and convert desired delta to usec (1/4 ~= 1000000/3686400) */
23#define xip_currtime() (OSCR)
24#define xip_elapsed_since(x) (signed)((OSCR - (x)) / 4)
25
26#endif /* __ARCH_SA1100_MTD_XIP_H__ */
diff --git a/include/asm-arm/arch-shark/io.h b/include/asm-arm/arch-shark/io.h
index 1e7f26bc2e1d..5e6ed0038b2b 100644
--- a/include/asm-arm/arch-shark/io.h
+++ b/include/asm-arm/arch-shark/io.h
@@ -21,38 +21,8 @@
21 */ 21 */
22#define __PORT_PCIO(x) (!((x) & 0x80000000)) 22#define __PORT_PCIO(x) (!((x) & 0x80000000))
23 23
24/* 24#define __io(a) ((void __iomem *)(PCIO_BASE + (a)))
25 * Dynamic IO functions - let the compiler
26 * optimize the expressions
27 */
28#define DECLARE_DYN_OUT(fnsuffix,instr) \
29static inline void __out##fnsuffix (unsigned int value, unsigned int port) \
30{ \
31 unsigned long temp; \
32 __asm__ __volatile__( \
33 "tst %2, #0x80000000\n\t" \
34 "mov %0, %4\n\t" \
35 "addeq %0, %0, %3\n\t" \
36 "str" instr " %1, [%0, %2] @ out" #fnsuffix \
37 : "=&r" (temp) \
38 : "r" (value), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE) \
39 : "cc"); \
40}
41 25
42#define DECLARE_DYN_IN(sz,fnsuffix,instr) \
43static inline unsigned sz __in##fnsuffix (unsigned int port) \
44{ \
45 unsigned long temp, value; \
46 __asm__ __volatile__( \
47 "tst %2, #0x80000000\n\t" \
48 "mov %0, %4\n\t" \
49 "addeq %0, %0, %3\n\t" \
50 "ldr" instr " %1, [%0, %2] @ in" #fnsuffix \
51 : "=&r" (temp), "=r" (value) \
52 : "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE) \
53 : "cc"); \
54 return (unsigned sz)value; \
55}
56 26
57static inline unsigned int __ioaddr (unsigned int port) \ 27static inline unsigned int __ioaddr (unsigned int port) \
58{ \ 28{ \
@@ -62,123 +32,8 @@ static inline unsigned int __ioaddr (unsigned int port) \
62 return (unsigned int)(IO_BASE + (port)); \ 32 return (unsigned int)(IO_BASE + (port)); \
63} 33}
64 34
65#define DECLARE_IO(sz,fnsuffix,instr) \
66 DECLARE_DYN_OUT(fnsuffix,instr) \
67 DECLARE_DYN_IN(sz,fnsuffix,instr)
68
69DECLARE_IO(char,b,"b")
70DECLARE_IO(short,w,"h")
71DECLARE_IO(long,l,"")
72
73#undef DECLARE_IO
74#undef DECLARE_DYN_OUT
75#undef DECLARE_DYN_IN
76
77/*
78 * Constant address IO functions
79 *
80 * These have to be macros for the 'J' constraint to work -
81 * +/-4096 immediate operand.
82 */
83#define __outbc(value,port) \
84({ \
85 if (__PORT_PCIO((port))) \
86 __asm__ __volatile__( \
87 "strb %0, [%1, %2] @ outbc" \
88 : : "r" (value), "r" (PCIO_BASE), "Jr" (port)); \
89 else \
90 __asm__ __volatile__( \
91 "strb %0, [%1, %2] @ outbc" \
92 : : "r" (value), "r" (IO_BASE), "r" (port)); \
93})
94
95#define __inbc(port) \
96({ \
97 unsigned char result; \
98 if (__PORT_PCIO((port))) \
99 __asm__ __volatile__( \
100 "ldrb %0, [%1, %2] @ inbc" \
101 : "=r" (result) : "r" (PCIO_BASE), "Jr" (port)); \
102 else \
103 __asm__ __volatile__( \
104 "ldrb %0, [%1, %2] @ inbc" \
105 : "=r" (result) : "r" (IO_BASE), "r" (port)); \
106 result; \
107})
108
109#define __outwc(value,port) \
110({ \
111 unsigned long v = value; \
112 if (__PORT_PCIO((port))) \
113 __asm__ __volatile__( \
114 "strh %0, [%1, %2] @ outwc" \
115 : : "r" (v|v<<16), "r" (PCIO_BASE), "Jr" (port)); \
116 else \
117 __asm__ __volatile__( \
118 "strh %0, [%1, %2] @ outwc" \
119 : : "r" (v|v<<16), "r" (IO_BASE), "r" (port)); \
120})
121
122#define __inwc(port) \
123({ \
124 unsigned short result; \
125 if (__PORT_PCIO((port))) \
126 __asm__ __volatile__( \
127 "ldrh %0, [%1, %2] @ inwc" \
128 : "=r" (result) : "r" (PCIO_BASE), "Jr" (port)); \
129 else \
130 __asm__ __volatile__( \
131 "ldrh %0, [%1, %2] @ inwc" \
132 : "=r" (result) : "r" (IO_BASE), "r" (port)); \
133 result & 0xffff; \
134})
135
136#define __outlc(value,port) \
137({ \
138 unsigned long v = value; \
139 if (__PORT_PCIO((port))) \
140 __asm__ __volatile__( \
141 "str %0, [%1, %2] @ outlc" \
142 : : "r" (v), "r" (PCIO_BASE), "Jr" (port)); \
143 else \
144 __asm__ __volatile__( \
145 "str %0, [%1, %2] @ outlc" \
146 : : "r" (v), "r" (IO_BASE), "r" (port)); \
147})
148
149#define __inlc(port) \
150({ \
151 unsigned long result; \
152 if (__PORT_PCIO((port))) \
153 __asm__ __volatile__( \
154 "ldr %0, [%1, %2] @ inlc" \
155 : "=r" (result) : "r" (PCIO_BASE), "Jr" (port)); \
156 else \
157 __asm__ __volatile__( \
158 "ldr %0, [%1, %2] @ inlc" \
159 : "=r" (result) : "r" (IO_BASE), "r" (port)); \
160 result; \
161})
162
163#define __ioaddrc(port) \
164({ \
165 unsigned long addr; \
166 if (__PORT_PCIO((port))) \
167 addr = PCIO_BASE + (port); \
168 else \
169 addr = IO_BASE + (port); \
170 addr; \
171})
172
173#define __mem_pci(addr) (addr) 35#define __mem_pci(addr) (addr)
174 36
175#define inb(p) (__builtin_constant_p((p)) ? __inbc(p) : __inb(p))
176#define inw(p) (__builtin_constant_p((p)) ? __inwc(p) : __inw(p))
177#define inl(p) (__builtin_constant_p((p)) ? __inlc(p) : __inl(p))
178#define outb(v,p) (__builtin_constant_p((p)) ? __outbc(v,p) : __outb(v,p))
179#define outw(v,p) (__builtin_constant_p((p)) ? __outwc(v,p) : __outw(v,p))
180#define outl(v,p) (__builtin_constant_p((p)) ? __outlc(v,p) : __outl(v,p))
181
182/* 37/*
183 * Translated address IO functions 38 * Translated address IO functions
184 * 39 *
diff --git a/include/asm-arm/bitops.h b/include/asm-arm/bitops.h
index 4edd4dc40c5b..aad7aad026b3 100644
--- a/include/asm-arm/bitops.h
+++ b/include/asm-arm/bitops.h
@@ -21,8 +21,8 @@
21 21
22#include <asm/system.h> 22#include <asm/system.h>
23 23
24#define smp_mb__before_clear_bit() do { } while (0) 24#define smp_mb__before_clear_bit() mb()
25#define smp_mb__after_clear_bit() do { } while (0) 25#define smp_mb__after_clear_bit() mb()
26 26
27/* 27/*
28 * These functions are the basis of our bit ops. 28 * These functions are the basis of our bit ops.
@@ -229,6 +229,7 @@ extern int _find_next_zero_bit_be(const void * p, int size, int offset);
229extern int _find_first_bit_be(const unsigned long *p, unsigned size); 229extern int _find_first_bit_be(const unsigned long *p, unsigned size);
230extern int _find_next_bit_be(const unsigned long *p, int size, int offset); 230extern int _find_next_bit_be(const unsigned long *p, int size, int offset);
231 231
232#ifndef CONFIG_SMP
232/* 233/*
233 * The __* form of bitops are non-atomic and may be reordered. 234 * The __* form of bitops are non-atomic and may be reordered.
234 */ 235 */
@@ -241,6 +242,10 @@ extern int _find_next_bit_be(const unsigned long *p, int size, int offset);
241 (__builtin_constant_p(nr) ? \ 242 (__builtin_constant_p(nr) ? \
242 ____atomic_##name(nr, p) : \ 243 ____atomic_##name(nr, p) : \
243 _##name##_be(nr,p)) 244 _##name##_be(nr,p))
245#else
246#define ATOMIC_BITOP_LE(name,nr,p) _##name##_le(nr,p)
247#define ATOMIC_BITOP_BE(name,nr,p) _##name##_be(nr,p)
248#endif
244 249
245#define NONATOMIC_BITOP(name,nr,p) \ 250#define NONATOMIC_BITOP(name,nr,p) \
246 (____nonatomic_##name(nr, p)) 251 (____nonatomic_##name(nr, p))
diff --git a/include/asm-arm/emergency-restart.h b/include/asm-arm/emergency-restart.h
new file mode 100644
index 000000000000..108d8c48e42e
--- /dev/null
+++ b/include/asm-arm/emergency-restart.h
@@ -0,0 +1,6 @@
1#ifndef _ASM_EMERGENCY_RESTART_H
2#define _ASM_EMERGENCY_RESTART_H
3
4#include <asm-generic/emergency-restart.h>
5
6#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/include/asm-arm/hardware/arm_timer.h b/include/asm-arm/hardware/arm_timer.h
new file mode 100644
index 000000000000..04be3bdf46b8
--- /dev/null
+++ b/include/asm-arm/hardware/arm_timer.h
@@ -0,0 +1,21 @@
1#ifndef __ASM_ARM_HARDWARE_ARM_TIMER_H
2#define __ASM_ARM_HARDWARE_ARM_TIMER_H
3
4#define TIMER_LOAD 0x00
5#define TIMER_VALUE 0x04
6#define TIMER_CTRL 0x08
7#define TIMER_CTRL_ONESHOT (1 << 0)
8#define TIMER_CTRL_32BIT (1 << 1)
9#define TIMER_CTRL_DIV1 (0 << 2)
10#define TIMER_CTRL_DIV16 (1 << 2)
11#define TIMER_CTRL_DIV256 (2 << 2)
12#define TIMER_CTRL_IE (1 << 5) /* Interrupt Enable (versatile only) */
13#define TIMER_CTRL_PERIODIC (1 << 6)
14#define TIMER_CTRL_ENABLE (1 << 7)
15
16#define TIMER_INTCLR 0x0c
17#define TIMER_RIS 0x10
18#define TIMER_MIS 0x14
19#define TIMER_BGLOAD 0x18
20
21#endif
diff --git a/include/asm-arm/ide.h b/include/asm-arm/ide.h
index 2114acb3d237..4f68c8a5a199 100644
--- a/include/asm-arm/ide.h
+++ b/include/asm-arm/ide.h
@@ -5,7 +5,7 @@
5 */ 5 */
6 6
7/* 7/*
8 * This file contains the i386 architecture specific IDE code. 8 * This file contains the ARM architecture specific IDE code.
9 */ 9 */
10 10
11#ifndef __ASMARM_IDE_H 11#ifndef __ASMARM_IDE_H
diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h
index 08a46302d265..cfa71a0dffb6 100644
--- a/include/asm-arm/io.h
+++ b/include/asm-arm/io.h
@@ -82,7 +82,7 @@ extern void __readwrite_bug(const char *fn);
82 * only. Their primary purpose is to access PCI and ISA peripherals. 82 * only. Their primary purpose is to access PCI and ISA peripherals.
83 * 83 *
84 * Note that for a big endian machine, this implies that the following 84 * Note that for a big endian machine, this implies that the following
85 * big endian mode connectivity is in place, as described by numerious 85 * big endian mode connectivity is in place, as described by numerous
86 * ARM documents: 86 * ARM documents:
87 * 87 *
88 * PCI: D0-D7 D8-D15 D16-D23 D24-D31 88 * PCI: D0-D7 D8-D15 D16-D23 D24-D31
@@ -275,6 +275,7 @@ extern void __iounmap(void __iomem *addr);
275/* 275/*
276 * io{read,write}{8,16,32} macros 276 * io{read,write}{8,16,32} macros
277 */ 277 */
278#ifndef ioread8
278#define ioread8(p) ({ unsigned int __v = __raw_readb(p); __v; }) 279#define ioread8(p) ({ unsigned int __v = __raw_readb(p); __v; })
279#define ioread16(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(p)); __v; }) 280#define ioread16(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(p)); __v; })
280#define ioread32(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(p)); __v; }) 281#define ioread32(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(p)); __v; })
@@ -293,6 +294,7 @@ extern void __iounmap(void __iomem *addr);
293 294
294extern void __iomem *ioport_map(unsigned long port, unsigned int nr); 295extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
295extern void ioport_unmap(void __iomem *addr); 296extern void ioport_unmap(void __iomem *addr);
297#endif
296 298
297struct pci_dev; 299struct pci_dev;
298 300
diff --git a/include/asm-arm/locks.h b/include/asm-arm/locks.h
index c26298f3891f..f08dc8447913 100644
--- a/include/asm-arm/locks.h
+++ b/include/asm-arm/locks.h
@@ -28,7 +28,8 @@
28" blmi " #fail \ 28" blmi " #fail \
29 : \ 29 : \
30 : "r" (ptr), "I" (1) \ 30 : "r" (ptr), "I" (1) \
31 : "ip", "lr", "cc", "memory"); \ 31 : "ip", "lr", "cc"); \
32 smp_mb(); \
32 }) 33 })
33 34
34#define __down_op_ret(ptr,fail) \ 35#define __down_op_ret(ptr,fail) \
@@ -48,12 +49,14 @@
48" mov %0, ip" \ 49" mov %0, ip" \
49 : "=&r" (ret) \ 50 : "=&r" (ret) \
50 : "r" (ptr), "I" (1) \ 51 : "r" (ptr), "I" (1) \
51 : "ip", "lr", "cc", "memory"); \ 52 : "ip", "lr", "cc"); \
53 smp_mb(); \
52 ret; \ 54 ret; \
53 }) 55 })
54 56
55#define __up_op(ptr,wake) \ 57#define __up_op(ptr,wake) \
56 ({ \ 58 ({ \
59 smp_mb(); \
57 __asm__ __volatile__( \ 60 __asm__ __volatile__( \
58 "@ up_op\n" \ 61 "@ up_op\n" \
59"1: ldrex lr, [%0]\n" \ 62"1: ldrex lr, [%0]\n" \
@@ -61,12 +64,12 @@
61" strex ip, lr, [%0]\n" \ 64" strex ip, lr, [%0]\n" \
62" teq ip, #0\n" \ 65" teq ip, #0\n" \
63" bne 1b\n" \ 66" bne 1b\n" \
64" teq lr, #0\n" \ 67" cmp lr, #0\n" \
65" movle ip, %0\n" \ 68" movle ip, %0\n" \
66" blle " #wake \ 69" blle " #wake \
67 : \ 70 : \
68 : "r" (ptr), "I" (1) \ 71 : "r" (ptr), "I" (1) \
69 : "ip", "lr", "cc", "memory"); \ 72 : "ip", "lr", "cc"); \
70 }) 73 })
71 74
72/* 75/*
@@ -92,15 +95,17 @@
92" blne " #fail \ 95" blne " #fail \
93 : \ 96 : \
94 : "r" (ptr), "I" (RW_LOCK_BIAS) \ 97 : "r" (ptr), "I" (RW_LOCK_BIAS) \
95 : "ip", "lr", "cc", "memory"); \ 98 : "ip", "lr", "cc"); \
99 smp_mb(); \
96 }) 100 })
97 101
98#define __up_op_write(ptr,wake) \ 102#define __up_op_write(ptr,wake) \
99 ({ \ 103 ({ \
104 smp_mb(); \
100 __asm__ __volatile__( \ 105 __asm__ __volatile__( \
101 "@ up_op_read\n" \ 106 "@ up_op_read\n" \
102"1: ldrex lr, [%0]\n" \ 107"1: ldrex lr, [%0]\n" \
103" add lr, lr, %1\n" \ 108" adds lr, lr, %1\n" \
104" strex ip, lr, [%0]\n" \ 109" strex ip, lr, [%0]\n" \
105" teq ip, #0\n" \ 110" teq ip, #0\n" \
106" bne 1b\n" \ 111" bne 1b\n" \
@@ -108,7 +113,7 @@
108" blcs " #wake \ 113" blcs " #wake \
109 : \ 114 : \
110 : "r" (ptr), "I" (RW_LOCK_BIAS) \ 115 : "r" (ptr), "I" (RW_LOCK_BIAS) \
111 : "ip", "lr", "cc", "memory"); \ 116 : "ip", "lr", "cc"); \
112 }) 117 })
113 118
114#define __down_op_read(ptr,fail) \ 119#define __down_op_read(ptr,fail) \
@@ -116,6 +121,7 @@
116 121
117#define __up_op_read(ptr,wake) \ 122#define __up_op_read(ptr,wake) \
118 ({ \ 123 ({ \
124 smp_mb(); \
119 __asm__ __volatile__( \ 125 __asm__ __volatile__( \
120 "@ up_op_read\n" \ 126 "@ up_op_read\n" \
121"1: ldrex lr, [%0]\n" \ 127"1: ldrex lr, [%0]\n" \
@@ -128,7 +134,7 @@
128" bleq " #wake \ 134" bleq " #wake \
129 : \ 135 : \
130 : "r" (ptr), "I" (1) \ 136 : "r" (ptr), "I" (1) \
131 : "ip", "lr", "cc", "memory"); \ 137 : "ip", "lr", "cc"); \
132 }) 138 })
133 139
134#else 140#else
@@ -148,7 +154,8 @@
148" blmi " #fail \ 154" blmi " #fail \
149 : \ 155 : \
150 : "r" (ptr), "I" (1) \ 156 : "r" (ptr), "I" (1) \
151 : "ip", "lr", "cc", "memory"); \ 157 : "ip", "lr", "cc"); \
158 smp_mb(); \
152 }) 159 })
153 160
154#define __down_op_ret(ptr,fail) \ 161#define __down_op_ret(ptr,fail) \
@@ -169,12 +176,14 @@
169" mov %0, ip" \ 176" mov %0, ip" \
170 : "=&r" (ret) \ 177 : "=&r" (ret) \
171 : "r" (ptr), "I" (1) \ 178 : "r" (ptr), "I" (1) \
172 : "ip", "lr", "cc", "memory"); \ 179 : "ip", "lr", "cc"); \
180 smp_mb(); \
173 ret; \ 181 ret; \
174 }) 182 })
175 183
176#define __up_op(ptr,wake) \ 184#define __up_op(ptr,wake) \
177 ({ \ 185 ({ \
186 smp_mb(); \
178 __asm__ __volatile__( \ 187 __asm__ __volatile__( \
179 "@ up_op\n" \ 188 "@ up_op\n" \
180" mrs ip, cpsr\n" \ 189" mrs ip, cpsr\n" \
@@ -188,7 +197,7 @@
188" blle " #wake \ 197" blle " #wake \
189 : \ 198 : \
190 : "r" (ptr), "I" (1) \ 199 : "r" (ptr), "I" (1) \
191 : "ip", "lr", "cc", "memory"); \ 200 : "ip", "lr", "cc"); \
192 }) 201 })
193 202
194/* 203/*
@@ -215,7 +224,8 @@
215" blne " #fail \ 224" blne " #fail \
216 : \ 225 : \
217 : "r" (ptr), "I" (RW_LOCK_BIAS) \ 226 : "r" (ptr), "I" (RW_LOCK_BIAS) \
218 : "ip", "lr", "cc", "memory"); \ 227 : "ip", "lr", "cc"); \
228 smp_mb(); \
219 }) 229 })
220 230
221#define __up_op_write(ptr,wake) \ 231#define __up_op_write(ptr,wake) \
@@ -233,7 +243,8 @@
233" blcs " #wake \ 243" blcs " #wake \
234 : \ 244 : \
235 : "r" (ptr), "I" (RW_LOCK_BIAS) \ 245 : "r" (ptr), "I" (RW_LOCK_BIAS) \
236 : "ip", "lr", "cc", "memory"); \ 246 : "ip", "lr", "cc"); \
247 smp_mb(); \
237 }) 248 })
238 249
239#define __down_op_read(ptr,fail) \ 250#define __down_op_read(ptr,fail) \
@@ -241,6 +252,7 @@
241 252
242#define __up_op_read(ptr,wake) \ 253#define __up_op_read(ptr,wake) \
243 ({ \ 254 ({ \
255 smp_mb(); \
244 __asm__ __volatile__( \ 256 __asm__ __volatile__( \
245 "@ up_op_read\n" \ 257 "@ up_op_read\n" \
246" mrs ip, cpsr\n" \ 258" mrs ip, cpsr\n" \
@@ -254,7 +266,7 @@
254" bleq " #wake \ 266" bleq " #wake \
255 : \ 267 : \
256 : "r" (ptr), "I" (1) \ 268 : "r" (ptr), "I" (1) \
257 : "ip", "lr", "cc", "memory"); \ 269 : "ip", "lr", "cc"); \
258 }) 270 })
259 271
260#endif 272#endif
diff --git a/include/asm-arm/mach/arch.h b/include/asm-arm/mach/arch.h
index 3a32e929ec8c..56c6bf4ab0c3 100644
--- a/include/asm-arm/mach/arch.h
+++ b/include/asm-arm/mach/arch.h
@@ -26,7 +26,7 @@ struct machine_desc {
26 * page tabe entry */ 26 * page tabe entry */
27 27
28 const char *name; /* architecture name */ 28 const char *name; /* architecture name */
29 unsigned int param_offset; /* parameter page */ 29 unsigned long boot_params; /* tagged list */
30 30
31 unsigned int video_start; /* start of video RAM */ 31 unsigned int video_start; /* start of video RAM */
32 unsigned int video_end; /* end of video RAM */ 32 unsigned int video_end; /* end of video RAM */
@@ -54,38 +54,6 @@ const struct machine_desc __mach_desc_##_type \
54 .nr = MACH_TYPE_##_type, \ 54 .nr = MACH_TYPE_##_type, \
55 .name = _name, 55 .name = _name,
56 56
57#define MAINTAINER(n)
58
59#define BOOT_MEM(_pram,_pio,_vio) \
60 .phys_ram = _pram, \
61 .phys_io = _pio, \
62 .io_pg_offst = ((_vio)>>18)&0xfffc,
63
64#define BOOT_PARAMS(_params) \
65 .param_offset = _params,
66
67#define VIDEO(_start,_end) \
68 .video_start = _start, \
69 .video_end = _end,
70
71#define DISABLE_PARPORT(_n) \
72 .reserve_lp##_n = 1,
73
74#define SOFT_REBOOT \
75 .soft_reboot = 1,
76
77#define FIXUP(_func) \
78 .fixup = _func,
79
80#define MAPIO(_func) \
81 .map_io = _func,
82
83#define INITIRQ(_func) \
84 .init_irq = _func,
85
86#define INIT_MACHINE(_func) \
87 .init_machine = _func,
88
89#define MACHINE_END \ 57#define MACHINE_END \
90}; 58};
91 59
diff --git a/include/asm-arm/mach/time.h b/include/asm-arm/mach/time.h
index 5cf4fd659fd5..2cf279a44017 100644
--- a/include/asm-arm/mach/time.h
+++ b/include/asm-arm/mach/time.h
@@ -39,8 +39,31 @@ struct sys_timer {
39 void (*suspend)(void); 39 void (*suspend)(void);
40 void (*resume)(void); 40 void (*resume)(void);
41 unsigned long (*offset)(void); 41 unsigned long (*offset)(void);
42
43#ifdef CONFIG_NO_IDLE_HZ
44 struct dyn_tick_timer *dyn_tick;
45#endif
46};
47
48#ifdef CONFIG_NO_IDLE_HZ
49
50#define DYN_TICK_SKIPPING (1 << 2)
51#define DYN_TICK_ENABLED (1 << 1)
52#define DYN_TICK_SUITABLE (1 << 0)
53
54struct dyn_tick_timer {
55 unsigned int state; /* Current state */
56 int (*enable)(void); /* Enables dynamic tick */
57 int (*disable)(void); /* Disables dynamic tick */
58 void (*reprogram)(unsigned long); /* Reprograms the timer */
59 int (*handler)(int, void *, struct pt_regs *);
42}; 60};
43 61
62void timer_dyn_reprogram(void);
63#else
64#define timer_dyn_reprogram() do { } while (0)
65#endif
66
44extern struct sys_timer *system_timer; 67extern struct sys_timer *system_timer;
45extern void timer_tick(struct pt_regs *); 68extern void timer_tick(struct pt_regs *);
46 69
diff --git a/include/asm-arm/mtd-xip.h b/include/asm-arm/mtd-xip.h
new file mode 100644
index 000000000000..9eb127cc7db2
--- /dev/null
+++ b/include/asm-arm/mtd-xip.h
@@ -0,0 +1,26 @@
1/*
2 * MTD primitives for XIP support. Architecture specific functions
3 *
4 * Do not include this file directly. It's included from linux/mtd/xip.h
5 *
6 * Author: Nicolas Pitre
7 * Created: Nov 2, 2004
8 * Copyright: (C) 2004 MontaVista Software, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * $Id: xip.h,v 1.2 2004/12/01 15:49:10 nico Exp $
15 */
16
17#ifndef __ARM_MTD_XIP_H__
18#define __ARM_MTD_XIP_H__
19
20#include <asm/hardware.h>
21#include <asm/arch/mtd-xip.h>
22
23/* fill instruction prefetch */
24#define xip_iprefetch() do { asm volatile (".rep 8; nop; .endr"); } while (0)
25
26#endif /* __ARM_MTD_XIP_H__ */
diff --git a/include/asm-arm/pci.h b/include/asm-arm/pci.h
index 40ffaefbeb1a..38ea5899a580 100644
--- a/include/asm-arm/pci.h
+++ b/include/asm-arm/pci.h
@@ -14,7 +14,7 @@ static inline void pcibios_set_master(struct pci_dev *dev)
14 /* No special bus mastering setup handling */ 14 /* No special bus mastering setup handling */
15} 15}
16 16
17static inline void pcibios_penalize_isa_irq(int irq) 17static inline void pcibios_penalize_isa_irq(int irq, int active)
18{ 18{
19 /* We don't do dynamic PCI IRQ allocation */ 19 /* We don't do dynamic PCI IRQ allocation */
20} 20}
@@ -42,6 +42,16 @@ static inline void pcibios_penalize_isa_irq(int irq)
42#define pci_unmap_len(PTR, LEN_NAME) ((PTR)->LEN_NAME) 42#define pci_unmap_len(PTR, LEN_NAME) ((PTR)->LEN_NAME)
43#define pci_unmap_len_set(PTR, LEN_NAME, VAL) (((PTR)->LEN_NAME) = (VAL)) 43#define pci_unmap_len_set(PTR, LEN_NAME, VAL) (((PTR)->LEN_NAME) = (VAL))
44 44
45#ifdef CONFIG_PCI
46static inline void pci_dma_burst_advice(struct pci_dev *pdev,
47 enum pci_dma_burst_strategy *strat,
48 unsigned long *strategy_parameter)
49{
50 *strat = PCI_DMA_BURST_INFINITY;
51 *strategy_parameter = ~0UL;
52}
53#endif
54
45#define HAVE_PCI_MMAP 55#define HAVE_PCI_MMAP
46extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, 56extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
47 enum pci_mmap_state mmap_state, int write_combine); 57 enum pci_mmap_state mmap_state, int write_combine);
@@ -50,6 +60,10 @@ extern void
50pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, 60pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
51 struct resource *res); 61 struct resource *res);
52 62
63extern void
64pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
65 struct pci_bus_region *region);
66
53static inline void pcibios_add_platform_entries(struct pci_dev *dev) 67static inline void pcibios_add_platform_entries(struct pci_dev *dev)
54{ 68{
55} 69}
diff --git a/include/asm-arm/pgalloc.h b/include/asm-arm/pgalloc.h
index e814f8144f8b..bc18ff405181 100644
--- a/include/asm-arm/pgalloc.h
+++ b/include/asm-arm/pgalloc.h
@@ -89,6 +89,13 @@ static inline void pte_free(struct page *pte)
89 __free_page(pte); 89 __free_page(pte);
90} 90}
91 91
92static inline void __pmd_populate(pmd_t *pmdp, unsigned long pmdval)
93{
94 pmdp[0] = __pmd(pmdval);
95 pmdp[1] = __pmd(pmdval + 256 * sizeof(pte_t));
96 flush_pmd_entry(pmdp);
97}
98
92/* 99/*
93 * Populate the pmdp entry with a pointer to the pte. This pmd is part 100 * Populate the pmdp entry with a pointer to the pte. This pmd is part
94 * of the mm address space. 101 * of the mm address space.
@@ -99,32 +106,19 @@ static inline void
99pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmdp, pte_t *ptep) 106pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmdp, pte_t *ptep)
100{ 107{
101 unsigned long pte_ptr = (unsigned long)ptep; 108 unsigned long pte_ptr = (unsigned long)ptep;
102 unsigned long pmdval;
103
104 BUG_ON(mm != &init_mm);
105 109
106 /* 110 /*
107 * The pmd must be loaded with the physical 111 * The pmd must be loaded with the physical
108 * address of the PTE table 112 * address of the PTE table
109 */ 113 */
110 pte_ptr -= PTRS_PER_PTE * sizeof(void *); 114 pte_ptr -= PTRS_PER_PTE * sizeof(void *);
111 pmdval = __pa(pte_ptr) | _PAGE_KERNEL_TABLE; 115 __pmd_populate(pmdp, __pa(pte_ptr) | _PAGE_KERNEL_TABLE);
112 pmdp[0] = __pmd(pmdval);
113 pmdp[1] = __pmd(pmdval + 256 * sizeof(pte_t));
114 flush_pmd_entry(pmdp);
115} 116}
116 117
117static inline void 118static inline void
118pmd_populate(struct mm_struct *mm, pmd_t *pmdp, struct page *ptep) 119pmd_populate(struct mm_struct *mm, pmd_t *pmdp, struct page *ptep)
119{ 120{
120 unsigned long pmdval; 121 __pmd_populate(pmdp, page_to_pfn(ptep) << PAGE_SHIFT | _PAGE_USER_TABLE);
121
122 BUG_ON(mm == &init_mm);
123
124 pmdval = page_to_pfn(ptep) << PAGE_SHIFT | _PAGE_USER_TABLE;
125 pmdp[0] = __pmd(pmdval);
126 pmdp[1] = __pmd(pmdval + 256 * sizeof(pte_t));
127 flush_pmd_entry(pmdp);
128} 122}
129 123
130#endif 124#endif
diff --git a/include/asm-arm/signal.h b/include/asm-arm/signal.h
index 46e69ae395af..760f6e65af05 100644
--- a/include/asm-arm/signal.h
+++ b/include/asm-arm/signal.h
@@ -114,6 +114,7 @@ typedef unsigned long sigset_t;
114#define SIGSTKSZ 8192 114#define SIGSTKSZ 8192
115 115
116#ifdef __KERNEL__ 116#ifdef __KERNEL__
117#define SA_TIMER 0x40000000
117#define SA_IRQNOMASK 0x08000000 118#define SA_IRQNOMASK 0x08000000
118#endif 119#endif
119 120
diff --git a/include/asm-arm/smp.h b/include/asm-arm/smp.h
index 6c6c60adbbaa..dbb4d859c586 100644
--- a/include/asm-arm/smp.h
+++ b/include/asm-arm/smp.h
@@ -23,9 +23,6 @@
23 23
24#define raw_smp_processor_id() (current_thread_info()->cpu) 24#define raw_smp_processor_id() (current_thread_info()->cpu)
25 25
26extern cpumask_t cpu_present_mask;
27#define cpu_possible_map cpu_present_mask
28
29/* 26/*
30 * at the moment, there's not a big penalty for changing CPUs 27 * at the moment, there's not a big penalty for changing CPUs
31 * (the >big< penalty is running SMP in the first place) 28 * (the >big< penalty is running SMP in the first place)
diff --git a/include/asm-arm/spinlock.h b/include/asm-arm/spinlock.h
index 182323619caa..1f906d09b688 100644
--- a/include/asm-arm/spinlock.h
+++ b/include/asm-arm/spinlock.h
@@ -8,9 +8,10 @@
8/* 8/*
9 * ARMv6 Spin-locking. 9 * ARMv6 Spin-locking.
10 * 10 *
11 * We (exclusively) read the old value, and decrement it. If it 11 * We exclusively read the old value. If it is zero, we may have
12 * hits zero, we may have won the lock, so we try (exclusively) 12 * won the lock, so we try exclusively storing it. A memory barrier
13 * storing it. 13 * is required after we get a lock, and before we release it, because
14 * V6 CPUs are assumed to have weakly ordered memory.
14 * 15 *
15 * Unlocked value: 0 16 * Unlocked value: 0
16 * Locked value: 1 17 * Locked value: 1
@@ -41,7 +42,9 @@ static inline void _raw_spin_lock(spinlock_t *lock)
41" bne 1b" 42" bne 1b"
42 : "=&r" (tmp) 43 : "=&r" (tmp)
43 : "r" (&lock->lock), "r" (1) 44 : "r" (&lock->lock), "r" (1)
44 : "cc", "memory"); 45 : "cc");
46
47 smp_mb();
45} 48}
46 49
47static inline int _raw_spin_trylock(spinlock_t *lock) 50static inline int _raw_spin_trylock(spinlock_t *lock)
@@ -54,18 +57,25 @@ static inline int _raw_spin_trylock(spinlock_t *lock)
54" strexeq %0, %2, [%1]" 57" strexeq %0, %2, [%1]"
55 : "=&r" (tmp) 58 : "=&r" (tmp)
56 : "r" (&lock->lock), "r" (1) 59 : "r" (&lock->lock), "r" (1)
57 : "cc", "memory"); 60 : "cc");
58 61
59 return tmp == 0; 62 if (tmp == 0) {
63 smp_mb();
64 return 1;
65 } else {
66 return 0;
67 }
60} 68}
61 69
62static inline void _raw_spin_unlock(spinlock_t *lock) 70static inline void _raw_spin_unlock(spinlock_t *lock)
63{ 71{
72 smp_mb();
73
64 __asm__ __volatile__( 74 __asm__ __volatile__(
65" str %1, [%0]" 75" str %1, [%0]"
66 : 76 :
67 : "r" (&lock->lock), "r" (0) 77 : "r" (&lock->lock), "r" (0)
68 : "cc", "memory"); 78 : "cc");
69} 79}
70 80
71/* 81/*
@@ -79,7 +89,8 @@ typedef struct {
79} rwlock_t; 89} rwlock_t;
80 90
81#define RW_LOCK_UNLOCKED (rwlock_t) { 0 } 91#define RW_LOCK_UNLOCKED (rwlock_t) { 0 }
82#define rwlock_init(x) do { *(x) + RW_LOCK_UNLOCKED; } while (0) 92#define rwlock_init(x) do { *(x) = RW_LOCK_UNLOCKED; } while (0)
93#define rwlock_is_locked(x) (*((volatile unsigned int *)(x)) != 0)
83 94
84/* 95/*
85 * Write locks are easy - we just set bit 31. When unlocking, we can 96 * Write locks are easy - we just set bit 31. When unlocking, we can
@@ -97,16 +108,40 @@ static inline void _raw_write_lock(rwlock_t *rw)
97" bne 1b" 108" bne 1b"
98 : "=&r" (tmp) 109 : "=&r" (tmp)
99 : "r" (&rw->lock), "r" (0x80000000) 110 : "r" (&rw->lock), "r" (0x80000000)
100 : "cc", "memory"); 111 : "cc");
112
113 smp_mb();
114}
115
116static inline int _raw_write_trylock(rwlock_t *rw)
117{
118 unsigned long tmp;
119
120 __asm__ __volatile__(
121"1: ldrex %0, [%1]\n"
122" teq %0, #0\n"
123" strexeq %0, %2, [%1]"
124 : "=&r" (tmp)
125 : "r" (&rw->lock), "r" (0x80000000)
126 : "cc");
127
128 if (tmp == 0) {
129 smp_mb();
130 return 1;
131 } else {
132 return 0;
133 }
101} 134}
102 135
103static inline void _raw_write_unlock(rwlock_t *rw) 136static inline void _raw_write_unlock(rwlock_t *rw)
104{ 137{
138 smp_mb();
139
105 __asm__ __volatile__( 140 __asm__ __volatile__(
106 "str %1, [%0]" 141 "str %1, [%0]"
107 : 142 :
108 : "r" (&rw->lock), "r" (0) 143 : "r" (&rw->lock), "r" (0)
109 : "cc", "memory"); 144 : "cc");
110} 145}
111 146
112/* 147/*
@@ -133,11 +168,17 @@ static inline void _raw_read_lock(rwlock_t *rw)
133" bmi 1b" 168" bmi 1b"
134 : "=&r" (tmp), "=&r" (tmp2) 169 : "=&r" (tmp), "=&r" (tmp2)
135 : "r" (&rw->lock) 170 : "r" (&rw->lock)
136 : "cc", "memory"); 171 : "cc");
172
173 smp_mb();
137} 174}
138 175
139static inline void _raw_read_unlock(rwlock_t *rw) 176static inline void _raw_read_unlock(rwlock_t *rw)
140{ 177{
178 unsigned long tmp, tmp2;
179
180 smp_mb();
181
141 __asm__ __volatile__( 182 __asm__ __volatile__(
142"1: ldrex %0, [%2]\n" 183"1: ldrex %0, [%2]\n"
143" sub %0, %0, #1\n" 184" sub %0, %0, #1\n"
@@ -146,24 +187,9 @@ static inline void _raw_read_unlock(rwlock_t *rw)
146" bne 1b" 187" bne 1b"
147 : "=&r" (tmp), "=&r" (tmp2) 188 : "=&r" (tmp), "=&r" (tmp2)
148 : "r" (&rw->lock) 189 : "r" (&rw->lock)
149 : "cc", "memory"); 190 : "cc");
150} 191}
151 192
152#define _raw_read_trylock(lock) generic_raw_read_trylock(lock) 193#define _raw_read_trylock(lock) generic_raw_read_trylock(lock)
153 194
154static inline int _raw_write_trylock(rwlock_t *rw)
155{
156 unsigned long tmp;
157
158 __asm__ __volatile__(
159"1: ldrex %0, [%1]\n"
160" teq %0, #0\n"
161" strexeq %0, %2, [%1]"
162 : "=&r" (tmp)
163 : "r" (&rw->lock), "r" (0x80000000)
164 : "cc", "memory");
165
166 return tmp == 0;
167}
168
169#endif /* __ASM_SPINLOCK_H */ 195#endif /* __ASM_SPINLOCK_H */
diff --git a/include/asm-arm/stat.h b/include/asm-arm/stat.h
index ca8e7a8436da..ec4e2c2e3b47 100644
--- a/include/asm-arm/stat.h
+++ b/include/asm-arm/stat.h
@@ -89,6 +89,6 @@ struct stat64 {
89 unsigned long st_ctime_nsec; 89 unsigned long st_ctime_nsec;
90 90
91 unsigned long long st_ino; 91 unsigned long long st_ino;
92}; 92} __attribute__((packed));
93 93
94#endif 94#endif
diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h
index 39dd7008013c..8efa4ebdcacb 100644
--- a/include/asm-arm/system.h
+++ b/include/asm-arm/system.h
@@ -85,7 +85,9 @@ struct pt_regs;
85void die(const char *msg, struct pt_regs *regs, int err) 85void die(const char *msg, struct pt_regs *regs, int err)
86 __attribute__((noreturn)); 86 __attribute__((noreturn));
87 87
88void die_if_kernel(const char *str, struct pt_regs *regs, int err); 88struct siginfo;
89void notify_die(const char *str, struct pt_regs *regs, struct siginfo *info,
90 unsigned long err, unsigned long trap);
89 91
90void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int, 92void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
91 struct pt_regs *), 93 struct pt_regs *),
@@ -137,7 +139,12 @@ extern unsigned int user_debug;
137#define vectors_high() (0) 139#define vectors_high() (0)
138#endif 140#endif
139 141
142#if __LINUX_ARM_ARCH__ >= 6
143#define mb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \
144 : : "r" (0) : "memory")
145#else
140#define mb() __asm__ __volatile__ ("" : : : "memory") 146#define mb() __asm__ __volatile__ ("" : : : "memory")
147#endif
141#define rmb() mb() 148#define rmb() mb()
142#define wmb() mb() 149#define wmb() mb()
143#define read_barrier_depends() do { } while(0) 150#define read_barrier_depends() do { } while(0)
@@ -145,34 +152,12 @@ extern unsigned int user_debug;
145#define set_wmb(var, value) do { var = value; wmb(); } while (0) 152#define set_wmb(var, value) do { var = value; wmb(); } while (0)
146#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t"); 153#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
147 154
148#ifdef CONFIG_SMP
149/*
150 * Define our own context switch locking. This allows us to enable
151 * interrupts over the context switch, otherwise we end up with high
152 * interrupt latency. The real problem area is switch_mm() which may
153 * do a full cache flush.
154 */
155#define prepare_arch_switch(rq,next) \
156do { \
157 spin_lock(&(next)->switch_lock); \
158 spin_unlock_irq(&(rq)->lock); \
159} while (0)
160
161#define finish_arch_switch(rq,prev) \
162 spin_unlock(&(prev)->switch_lock)
163
164#define task_running(rq,p) \
165 ((rq)->curr == (p) || spin_is_locked(&(p)->switch_lock))
166#else
167/* 155/*
168 * Our UP-case is more simple, but we assume knowledge of how 156 * switch_mm() may do a full cache flush over the context switch,
169 * spin_unlock_irq() and friends are implemented. This avoids 157 * so enable interrupts over the context switch to avoid high
170 * us needlessly decrementing and incrementing the preempt count. 158 * latency.
171 */ 159 */
172#define prepare_arch_switch(rq,next) local_irq_enable() 160#define __ARCH_WANT_INTERRUPTS_ON_CTXSW
173#define finish_arch_switch(rq,prev) spin_unlock(&(rq)->lock)
174#define task_running(rq,p) ((rq)->curr == (p))
175#endif
176 161
177/* 162/*
178 * switch_to(prev, next) should switch from task `prev' to `next' 163 * switch_to(prev, next) should switch from task `prev' to `next'
@@ -312,7 +297,6 @@ do { \
312}) 297})
313 298
314#ifdef CONFIG_SMP 299#ifdef CONFIG_SMP
315#error SMP not supported
316 300
317#define smp_mb() mb() 301#define smp_mb() mb()
318#define smp_rmb() rmb() 302#define smp_rmb() rmb()
@@ -326,6 +310,8 @@ do { \
326#define smp_wmb() barrier() 310#define smp_wmb() barrier()
327#define smp_read_barrier_depends() do { } while(0) 311#define smp_read_barrier_depends() do { } while(0)
328 312
313#endif /* CONFIG_SMP */
314
329#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110) 315#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110)
330/* 316/*
331 * On the StrongARM, "swp" is terminally broken since it bypasses the 317 * On the StrongARM, "swp" is terminally broken since it bypasses the
@@ -338,6 +324,9 @@ do { \
338 * 324 *
339 * We choose (1) since its the "easiest" to achieve here and is not 325 * We choose (1) since its the "easiest" to achieve here and is not
340 * dependent on the processor type. 326 * dependent on the processor type.
327 *
328 * NOTE that this solution won't work on an SMP system, so explcitly
329 * forbid it here.
341 */ 330 */
342#define swp_is_buggy 331#define swp_is_buggy
343#endif 332#endif
@@ -349,42 +338,73 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size
349#ifdef swp_is_buggy 338#ifdef swp_is_buggy
350 unsigned long flags; 339 unsigned long flags;
351#endif 340#endif
341#if __LINUX_ARM_ARCH__ >= 6
342 unsigned int tmp;
343#endif
352 344
353 switch (size) { 345 switch (size) {
354#ifdef swp_is_buggy 346#if __LINUX_ARM_ARCH__ >= 6
355 case 1: 347 case 1:
356 local_irq_save(flags); 348 asm volatile("@ __xchg1\n"
357 ret = *(volatile unsigned char *)ptr; 349 "1: ldrexb %0, [%3]\n"
358 *(volatile unsigned char *)ptr = x; 350 " strexb %1, %2, [%3]\n"
359 local_irq_restore(flags); 351 " teq %1, #0\n"
360 break; 352 " bne 1b"
361 353 : "=&r" (ret), "=&r" (tmp)
362 case 4: 354 : "r" (x), "r" (ptr)
363 local_irq_save(flags); 355 : "memory", "cc");
364 ret = *(volatile unsigned long *)ptr; 356 break;
365 *(volatile unsigned long *)ptr = x; 357 case 4:
366 local_irq_restore(flags); 358 asm volatile("@ __xchg4\n"
367 break; 359 "1: ldrex %0, [%3]\n"
360 " strex %1, %2, [%3]\n"
361 " teq %1, #0\n"
362 " bne 1b"
363 : "=&r" (ret), "=&r" (tmp)
364 : "r" (x), "r" (ptr)
365 : "memory", "cc");
366 break;
367#elif defined(swp_is_buggy)
368#ifdef CONFIG_SMP
369#error SMP is not supported on this platform
370#endif
371 case 1:
372 local_irq_save(flags);
373 ret = *(volatile unsigned char *)ptr;
374 *(volatile unsigned char *)ptr = x;
375 local_irq_restore(flags);
376 break;
377
378 case 4:
379 local_irq_save(flags);
380 ret = *(volatile unsigned long *)ptr;
381 *(volatile unsigned long *)ptr = x;
382 local_irq_restore(flags);
383 break;
368#else 384#else
369 case 1: __asm__ __volatile__ ("swpb %0, %1, [%2]" 385 case 1:
370 : "=&r" (ret) 386 asm volatile("@ __xchg1\n"
371 : "r" (x), "r" (ptr) 387 " swpb %0, %1, [%2]"
372 : "memory", "cc"); 388 : "=&r" (ret)
373 break; 389 : "r" (x), "r" (ptr)
374 case 4: __asm__ __volatile__ ("swp %0, %1, [%2]" 390 : "memory", "cc");
375 : "=&r" (ret) 391 break;
376 : "r" (x), "r" (ptr) 392 case 4:
377 : "memory", "cc"); 393 asm volatile("@ __xchg4\n"
378 break; 394 " swp %0, %1, [%2]"
395 : "=&r" (ret)
396 : "r" (x), "r" (ptr)
397 : "memory", "cc");
398 break;
379#endif 399#endif
380 default: __bad_xchg(ptr, size), ret = 0; 400 default:
401 __bad_xchg(ptr, size), ret = 0;
402 break;
381 } 403 }
382 404
383 return ret; 405 return ret;
384} 406}
385 407
386#endif /* CONFIG_SMP */
387
388#endif /* __ASSEMBLY__ */ 408#endif /* __ASSEMBLY__ */
389 409
390#define arch_align_stack(x) (x) 410#define arch_align_stack(x) (x)
diff --git a/include/asm-arm/thread_info.h b/include/asm-arm/thread_info.h
index 66c585c50cf9..8252a4cd860f 100644
--- a/include/asm-arm/thread_info.h
+++ b/include/asm-arm/thread_info.h
@@ -49,7 +49,7 @@ struct cpu_context_save {
49 */ 49 */
50struct thread_info { 50struct thread_info {
51 unsigned long flags; /* low level flags */ 51 unsigned long flags; /* low level flags */
52 __s32 preempt_count; /* 0 => preemptable, <0 => bug */ 52 int preempt_count; /* 0 => preemptable, <0 => bug */
53 mm_segment_t addr_limit; /* address limit */ 53 mm_segment_t addr_limit; /* address limit */
54 struct task_struct *task; /* main task structure */ 54 struct task_struct *task; /* main task structure */
55 struct exec_domain *exec_domain; /* execution domain */ 55 struct exec_domain *exec_domain; /* execution domain */
diff --git a/include/asm-arm/tlbflush.h b/include/asm-arm/tlbflush.h
index 8a864b118569..9387a5e1ffe0 100644
--- a/include/asm-arm/tlbflush.h
+++ b/include/asm-arm/tlbflush.h
@@ -235,7 +235,7 @@ extern struct cpu_tlb_fns cpu_tlb;
235 235
236#define tlb_flag(f) ((always_tlb_flags & (f)) || (__tlb_flag & possible_tlb_flags & (f))) 236#define tlb_flag(f) ((always_tlb_flags & (f)) || (__tlb_flag & possible_tlb_flags & (f)))
237 237
238static inline void flush_tlb_all(void) 238static inline void local_flush_tlb_all(void)
239{ 239{
240 const int zero = 0; 240 const int zero = 0;
241 const unsigned int __tlb_flag = __cpu_tlb_flags; 241 const unsigned int __tlb_flag = __cpu_tlb_flags;
@@ -253,7 +253,7 @@ static inline void flush_tlb_all(void)
253 asm("mcr%? p15, 0, %0, c8, c5, 0" : : "r" (zero)); 253 asm("mcr%? p15, 0, %0, c8, c5, 0" : : "r" (zero));
254} 254}
255 255
256static inline void flush_tlb_mm(struct mm_struct *mm) 256static inline void local_flush_tlb_mm(struct mm_struct *mm)
257{ 257{
258 const int zero = 0; 258 const int zero = 0;
259 const int asid = ASID(mm); 259 const int asid = ASID(mm);
@@ -282,7 +282,7 @@ static inline void flush_tlb_mm(struct mm_struct *mm)
282} 282}
283 283
284static inline void 284static inline void
285flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) 285local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
286{ 286{
287 const int zero = 0; 287 const int zero = 0;
288 const unsigned int __tlb_flag = __cpu_tlb_flags; 288 const unsigned int __tlb_flag = __cpu_tlb_flags;
@@ -313,7 +313,7 @@ flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
313 asm("mcr%? p15, 0, %0, c8, c5, 1" : : "r" (uaddr)); 313 asm("mcr%? p15, 0, %0, c8, c5, 1" : : "r" (uaddr));
314} 314}
315 315
316static inline void flush_tlb_kernel_page(unsigned long kaddr) 316static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
317{ 317{
318 const int zero = 0; 318 const int zero = 0;
319 const unsigned int __tlb_flag = __cpu_tlb_flags; 319 const unsigned int __tlb_flag = __cpu_tlb_flags;
@@ -384,8 +384,24 @@ static inline void clean_pmd_entry(pmd_t *pmd)
384/* 384/*
385 * Convert calls to our calling convention. 385 * Convert calls to our calling convention.
386 */ 386 */
387#define flush_tlb_range(vma,start,end) __cpu_flush_user_tlb_range(start,end,vma) 387#define local_flush_tlb_range(vma,start,end) __cpu_flush_user_tlb_range(start,end,vma)
388#define flush_tlb_kernel_range(s,e) __cpu_flush_kern_tlb_range(s,e) 388#define local_flush_tlb_kernel_range(s,e) __cpu_flush_kern_tlb_range(s,e)
389
390#ifndef CONFIG_SMP
391#define flush_tlb_all local_flush_tlb_all
392#define flush_tlb_mm local_flush_tlb_mm
393#define flush_tlb_page local_flush_tlb_page
394#define flush_tlb_kernel_page local_flush_tlb_kernel_page
395#define flush_tlb_range local_flush_tlb_range
396#define flush_tlb_kernel_range local_flush_tlb_kernel_range
397#else
398extern void flush_tlb_all(void);
399extern void flush_tlb_mm(struct mm_struct *mm);
400extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr);
401extern void flush_tlb_kernel_page(unsigned long kaddr);
402extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
403extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
404#endif
389 405
390/* 406/*
391 * if PG_dcache_dirty is set for the page, we need to ensure that any 407 * if PG_dcache_dirty is set for the page, we need to ensure that any
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-22 07:15:01 -0500