diff options
Diffstat (limited to 'include/asm-arm/arch-s3c2410')
-rw-r--r-- | include/asm-arm/arch-s3c2410/anubis-map.h | 10 | ||||
-rw-r--r-- | include/asm-arm/arch-s3c2410/hardware.h | 7 | ||||
-rw-r--r-- | include/asm-arm/arch-s3c2410/io.h | 58 |
3 files changed, 54 insertions, 21 deletions
diff --git a/include/asm-arm/arch-s3c2410/anubis-map.h b/include/asm-arm/arch-s3c2410/anubis-map.h index 97741d6e506a..d529ffda8599 100644 --- a/include/asm-arm/arch-s3c2410/anubis-map.h +++ b/include/asm-arm/arch-s3c2410/anubis-map.h | |||
@@ -20,22 +20,22 @@ | |||
20 | 20 | ||
21 | /* start peripherals off after the S3C2410 */ | 21 | /* start peripherals off after the S3C2410 */ |
22 | 22 | ||
23 | #define ANUBIS_IOADDR(x) (S3C2410_ADDR((x) + 0x02000000)) | 23 | #define ANUBIS_IOADDR(x) (S3C2410_ADDR((x) + 0x01800000)) |
24 | 24 | ||
25 | #define ANUBIS_PA_CPLD (S3C2410_CS1 | (1<<26)) | 25 | #define ANUBIS_PA_CPLD (S3C2410_CS1 | (1<<26)) |
26 | 26 | ||
27 | /* we put the CPLD registers next, to get them out of the way */ | 27 | /* we put the CPLD registers next, to get them out of the way */ |
28 | 28 | ||
29 | #define ANUBIS_VA_CTRL1 ANUBIS_IOADDR(0x00000000) /* 0x01300000 */ | 29 | #define ANUBIS_VA_CTRL1 ANUBIS_IOADDR(0x00000000) /* 0x01800000 */ |
30 | #define ANUBIS_PA_CTRL1 (ANUBIS_PA_CPLD) | 30 | #define ANUBIS_PA_CTRL1 (ANUBIS_PA_CPLD) |
31 | 31 | ||
32 | #define ANUBIS_VA_CTRL2 ANUBIS_IOADDR(0x00100000) /* 0x01400000 */ | 32 | #define ANUBIS_VA_CTRL2 ANUBIS_IOADDR(0x00100000) /* 0x01900000 */ |
33 | #define ANUBIS_PA_CTRL2 (ANUBIS_PA_CPLD) | 33 | #define ANUBIS_PA_CTRL2 (ANUBIS_PA_CPLD) |
34 | 34 | ||
35 | #define ANUBIS_VA_CTRL3 ANUBIS_IOADDR(0x00200000) /* 0x01500000 */ | 35 | #define ANUBIS_VA_CTRL3 ANUBIS_IOADDR(0x00200000) /* 0x01A00000 */ |
36 | #define ANUBIS_PA_CTRL3 (ANUBIS_PA_CPLD) | 36 | #define ANUBIS_PA_CTRL3 (ANUBIS_PA_CPLD) |
37 | 37 | ||
38 | #define ANUBIS_VA_CTRL4 ANUBIS_IOADDR(0x00300000) /* 0x01600000 */ | 38 | #define ANUBIS_VA_CTRL4 ANUBIS_IOADDR(0x00300000) /* 0x01B00000 */ |
39 | #define ANUBIS_PA_CTRL4 (ANUBIS_PA_CPLD) | 39 | #define ANUBIS_PA_CTRL4 (ANUBIS_PA_CPLD) |
40 | 40 | ||
41 | #define ANUBIS_IDEPRI ANUBIS_IOADDR(0x01000000) | 41 | #define ANUBIS_IDEPRI ANUBIS_IOADDR(0x01000000) |
diff --git a/include/asm-arm/arch-s3c2410/hardware.h b/include/asm-arm/arch-s3c2410/hardware.h index 48a39918a760..1c9de29cafef 100644 --- a/include/asm-arm/arch-s3c2410/hardware.h +++ b/include/asm-arm/arch-s3c2410/hardware.h | |||
@@ -92,6 +92,13 @@ extern unsigned int s3c2410_gpio_getpin(unsigned int pin); | |||
92 | 92 | ||
93 | extern unsigned int s3c2410_modify_misccr(unsigned int clr, unsigned int chg); | 93 | extern unsigned int s3c2410_modify_misccr(unsigned int clr, unsigned int chg); |
94 | 94 | ||
95 | #ifdef CONFIG_CPU_S3C2440 | ||
96 | |||
97 | extern int s3c2440_set_dsc(unsigned int pin, unsigned int value); | ||
98 | |||
99 | #endif /* CONFIG_CPU_S3C2440 */ | ||
100 | |||
101 | |||
95 | #endif /* __ASSEMBLY__ */ | 102 | #endif /* __ASSEMBLY__ */ |
96 | 103 | ||
97 | #include <asm/sizes.h> | 104 | #include <asm/sizes.h> |
diff --git a/include/asm-arm/arch-s3c2410/io.h b/include/asm-arm/arch-s3c2410/io.h index 418233a7ee6f..4bf272ed9add 100644 --- a/include/asm-arm/arch-s3c2410/io.h +++ b/include/asm-arm/arch-s3c2410/io.h | |||
@@ -9,7 +9,7 @@ | |||
9 | * 06-Dec-1997 RMK Created. | 9 | * 06-Dec-1997 RMK Created. |
10 | * 02-Sep-2003 BJD Modified for S3C2410 | 10 | * 02-Sep-2003 BJD Modified for S3C2410 |
11 | * 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA | 11 | * 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA |
12 | * | 12 | * 13-Oct-2005 BJD Fixed problems with LDRH/STRH offset range |
13 | */ | 13 | */ |
14 | 14 | ||
15 | #ifndef __ASM_ARM_ARCH_IO_H | 15 | #ifndef __ASM_ARM_ARCH_IO_H |
@@ -97,7 +97,7 @@ DECLARE_IO(int,l,"") | |||
97 | else \ | 97 | else \ |
98 | __asm__ __volatile__( \ | 98 | __asm__ __volatile__( \ |
99 | "strb %0, [%1, #0] @ outbc" \ | 99 | "strb %0, [%1, #0] @ outbc" \ |
100 | : : "r" (value), "r" ((port))); \ | 100 | : : "r" (value), "r" ((port))); \ |
101 | }) | 101 | }) |
102 | 102 | ||
103 | #define __inbc(port) \ | 103 | #define __inbc(port) \ |
@@ -110,35 +110,61 @@ DECLARE_IO(int,l,"") | |||
110 | else \ | 110 | else \ |
111 | __asm__ __volatile__( \ | 111 | __asm__ __volatile__( \ |
112 | "ldrb %0, [%1, #0] @ inbc" \ | 112 | "ldrb %0, [%1, #0] @ inbc" \ |
113 | : "=r" (result) : "r" ((port))); \ | 113 | : "=r" (result) : "r" ((port))); \ |
114 | result; \ | 114 | result; \ |
115 | }) | 115 | }) |
116 | 116 | ||
117 | #define __outwc(value,port) \ | 117 | #define __outwc(value,port) \ |
118 | ({ \ | 118 | ({ \ |
119 | unsigned long v = value; \ | 119 | unsigned long v = value; \ |
120 | if (__PORT_PCIO((port))) \ | 120 | if (__PORT_PCIO((port))) { \ |
121 | __asm__ __volatile__( \ | 121 | if ((port) < 256 && (port) > -256) \ |
122 | "strh %0, [%1, %2] @ outwc" \ | 122 | __asm__ __volatile__( \ |
123 | : : "r" (v), "r" (PCIO_BASE), "Jr" ((port))); \ | 123 | "strh %0, [%1, %2] @ outwc" \ |
124 | else \ | 124 | : : "r" (v), "r" (PCIO_BASE), "Jr" ((port))); \ |
125 | else if ((port) > 0) \ | ||
126 | __asm__ __volatile__( \ | ||
127 | "strh %0, [%1, %2] @ outwc" \ | ||
128 | : : "r" (v), \ | ||
129 | "r" (PCIO_BASE + ((port) & ~0xff)), \ | ||
130 | "Jr" (((port) & 0xff))); \ | ||
131 | else \ | ||
132 | __asm__ __volatile__( \ | ||
133 | "strh %0, [%1, #0] @ outwc" \ | ||
134 | : : "r" (v), \ | ||
135 | "r" (PCIO_BASE + (port))); \ | ||
136 | } else \ | ||
125 | __asm__ __volatile__( \ | 137 | __asm__ __volatile__( \ |
126 | "strh %0, [%1, #0] @ outwc" \ | 138 | "strh %0, [%1, #0] @ outwc" \ |
127 | : : "r" (v), "r" ((port))); \ | 139 | : : "r" (v), "r" ((port))); \ |
128 | }) | 140 | }) |
129 | 141 | ||
130 | #define __inwc(port) \ | 142 | #define __inwc(port) \ |
131 | ({ \ | 143 | ({ \ |
132 | unsigned short result; \ | 144 | unsigned short result; \ |
133 | if (__PORT_PCIO((port))) \ | 145 | if (__PORT_PCIO((port))) { \ |
134 | __asm__ __volatile__( \ | 146 | if ((port) < 256 && (port) > -256 ) \ |
135 | "ldrh %0, [%1, %2] @ inwc" \ | 147 | __asm__ __volatile__( \ |
136 | : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port))); \ | 148 | "ldrh %0, [%1, %2] @ inwc" \ |
137 | else \ | 149 | : "=r" (result) \ |
150 | : "r" (PCIO_BASE), \ | ||
151 | "Jr" ((port))); \ | ||
152 | else if ((port) > 0) \ | ||
153 | __asm__ __volatile__( \ | ||
154 | "ldrh %0, [%1, %2] @ inwc" \ | ||
155 | : "=r" (result) \ | ||
156 | : "r" (PCIO_BASE + ((port) & ~0xff)), \ | ||
157 | "Jr" (((port) & 0xff))); \ | ||
158 | else \ | ||
159 | __asm__ __volatile__( \ | ||
160 | "ldrh %0, [%1, #0] @ inwc" \ | ||
161 | : "=r" (result) \ | ||
162 | : "r" (PCIO_BASE + ((port)))); \ | ||
163 | } else \ | ||
138 | __asm__ __volatile__( \ | 164 | __asm__ __volatile__( \ |
139 | "ldrh %0, [%1, #0] @ inwc" \ | 165 | "ldrh %0, [%1, #0] @ inwc" \ |
140 | : "=r" (result) : "r" ((port))); \ | 166 | : "=r" (result) : "r" ((port))); \ |
141 | result; \ | 167 | result; \ |
142 | }) | 168 | }) |
143 | 169 | ||
144 | #define __outlc(value,port) \ | 170 | #define __outlc(value,port) \ |