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-rw-r--r--include/asm-arm/arch-s3c2410/dma.h150
1 files changed, 67 insertions, 83 deletions
diff --git a/include/asm-arm/arch-s3c2410/dma.h b/include/asm-arm/arch-s3c2410/dma.h
index 7463fd5252ce..3661e465b0a5 100644
--- a/include/asm-arm/arch-s3c2410/dma.h
+++ b/include/asm-arm/arch-s3c2410/dma.h
@@ -1,18 +1,13 @@
1/* linux/include/asm-arm/arch-bast/dma.h 1/* linux/include/asm-arm/arch-s3c2410/dma.h
2 * 2 *
3 * Copyright (C) 2003,2004 Simtec Electronics 3 * Copyright (C) 2003,2004,2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk> 4 * Ben Dooks <ben@simtec.co.uk>
5 * 5 *
6 * Samsung S3C2410X DMA support 6 * Samsung S3C241XX DMA support
7 * 7 *
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11 *
12 * Changelog:
13 * ??-May-2003 BJD Created file
14 * ??-Jun-2003 BJD Added more dma functionality to go with arch
15 * 10-Nov-2004 BJD Added sys_device support
16*/ 11*/
17 12
18#ifndef __ASM_ARCH_DMA_H 13#ifndef __ASM_ARCH_DMA_H
@@ -21,28 +16,26 @@
21#include <linux/sysdev.h> 16#include <linux/sysdev.h>
22#include "hardware.h" 17#include "hardware.h"
23 18
24
25/* 19/*
26 * This is the maximum DMA address(physical address) that can be DMAd to. 20 * This is the maximum DMA address(physical address) that can be DMAd to.
27 * 21 *
28 */ 22 */
29#define MAX_DMA_ADDRESS 0x20000000 23#define MAX_DMA_ADDRESS 0x40000000
30#define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */ 24#define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */
31 25
32
33/* we have 4 dma channels */ 26/* we have 4 dma channels */
34#define S3C2410_DMA_CHANNELS (4) 27#define S3C2410_DMA_CHANNELS (4)
35 28
36/* types */ 29/* types */
37 30
38typedef enum { 31enum s3c2410_dma_state {
39 S3C2410_DMA_IDLE, 32 S3C2410_DMA_IDLE,
40 S3C2410_DMA_RUNNING, 33 S3C2410_DMA_RUNNING,
41 S3C2410_DMA_PAUSED 34 S3C2410_DMA_PAUSED
42} s3c2410_dma_state_t; 35};
43 36
44 37
45/* s3c2410_dma_loadst_t 38/* enum s3c2410_dma_loadst
46 * 39 *
47 * This represents the state of the DMA engine, wrt to the loaded / running 40 * This represents the state of the DMA engine, wrt to the loaded / running
48 * transfers. Since we don't have any way of knowing exactly the state of 41 * transfers. Since we don't have any way of knowing exactly the state of
@@ -70,45 +63,40 @@ typedef enum {
70 * currently running. 63 * currently running.
71*/ 64*/
72 65
73typedef enum { 66enum s3c2410_dma_loadst {
74 S3C2410_DMALOAD_NONE, 67 S3C2410_DMALOAD_NONE,
75 S3C2410_DMALOAD_1LOADED, 68 S3C2410_DMALOAD_1LOADED,
76 S3C2410_DMALOAD_1RUNNING, 69 S3C2410_DMALOAD_1RUNNING,
77 S3C2410_DMALOAD_1LOADED_1RUNNING, 70 S3C2410_DMALOAD_1LOADED_1RUNNING,
78} s3c2410_dma_loadst_t; 71};
79 72
80typedef enum { 73enum s3c2410_dma_buffresult {
81 S3C2410_RES_OK, 74 S3C2410_RES_OK,
82 S3C2410_RES_ERR, 75 S3C2410_RES_ERR,
83 S3C2410_RES_ABORT 76 S3C2410_RES_ABORT
84} s3c2410_dma_buffresult_t; 77};
85
86
87typedef enum s3c2410_dmasrc_e s3c2410_dmasrc_t;
88 78
89enum s3c2410_dmasrc_e { 79enum s3c2410_dmasrc {
90 S3C2410_DMASRC_HW, /* source is memory */ 80 S3C2410_DMASRC_HW, /* source is memory */
91 S3C2410_DMASRC_MEM /* source is hardware */ 81 S3C2410_DMASRC_MEM /* source is hardware */
92}; 82};
93 83
94/* enum s3c2410_chan_op_e 84/* enum s3c2410_chan_op
95 * 85 *
96 * operation codes passed to the DMA code by the user, and also used 86 * operation codes passed to the DMA code by the user, and also used
97 * to inform the current channel owner of any changes to the system state 87 * to inform the current channel owner of any changes to the system state
98*/ 88*/
99 89
100enum s3c2410_chan_op_e { 90enum s3c2410_chan_op {
101 S3C2410_DMAOP_START, 91 S3C2410_DMAOP_START,
102 S3C2410_DMAOP_STOP, 92 S3C2410_DMAOP_STOP,
103 S3C2410_DMAOP_PAUSE, 93 S3C2410_DMAOP_PAUSE,
104 S3C2410_DMAOP_RESUME, 94 S3C2410_DMAOP_RESUME,
105 S3C2410_DMAOP_FLUSH, 95 S3C2410_DMAOP_FLUSH,
106 S3C2410_DMAOP_TIMEOUT, /* internal signal to handler */ 96 S3C2410_DMAOP_TIMEOUT, /* internal signal to handler */
107 S3C2410_DMAOP_STARTED, /* indicate channel started */ 97 S3C2410_DMAOP_STARTED, /* indicate channel started */
108}; 98};
109 99
110typedef enum s3c2410_chan_op_e s3c2410_chan_op_t;
111
112/* flags */ 100/* flags */
113 101
114#define S3C2410_DMAF_SLOW (1<<0) /* slow, so don't worry about 102#define S3C2410_DMAF_SLOW (1<<0) /* slow, so don't worry about
@@ -117,104 +105,100 @@ typedef enum s3c2410_chan_op_e s3c2410_chan_op_t;
117 105
118/* dma buffer */ 106/* dma buffer */
119 107
120typedef struct s3c2410_dma_buf_s s3c2410_dma_buf_t;
121
122struct s3c2410_dma_client { 108struct s3c2410_dma_client {
123 char *name; 109 char *name;
124}; 110};
125 111
126typedef struct s3c2410_dma_client s3c2410_dma_client_t;
127
128/* s3c2410_dma_buf_s 112/* s3c2410_dma_buf_s
129 * 113 *
130 * internally used buffer structure to describe a queued or running 114 * internally used buffer structure to describe a queued or running
131 * buffer. 115 * buffer.
132*/ 116*/
133 117
134struct s3c2410_dma_buf_s { 118struct s3c2410_dma_buf;
135 s3c2410_dma_buf_t *next; 119struct s3c2410_dma_buf {
136 int magic; /* magic */ 120 struct s3c2410_dma_buf *next;
137 int size; /* buffer size in bytes */ 121 int magic; /* magic */
138 dma_addr_t data; /* start of DMA data */ 122 int size; /* buffer size in bytes */
139 dma_addr_t ptr; /* where the DMA got to [1] */ 123 dma_addr_t data; /* start of DMA data */
140 void *id; /* client's id */ 124 dma_addr_t ptr; /* where the DMA got to [1] */
125 void *id; /* client's id */
141}; 126};
142 127
143/* [1] is this updated for both recv/send modes? */ 128/* [1] is this updated for both recv/send modes? */
144 129
145typedef struct s3c2410_dma_chan_s s3c2410_dma_chan_t; 130struct s3c2410_dma_chan;
146 131
147/* s3c2410_dma_cbfn_t 132/* s3c2410_dma_cbfn_t
148 * 133 *
149 * buffer callback routine type 134 * buffer callback routine type
150*/ 135*/
151 136
152typedef void (*s3c2410_dma_cbfn_t)(s3c2410_dma_chan_t *, void *buf, int size, 137typedef void (*s3c2410_dma_cbfn_t)(struct s3c2410_dma_chan *,
153 s3c2410_dma_buffresult_t result); 138 void *buf, int size,
139 enum s3c2410_dma_buffresult result);
154 140
155typedef int (*s3c2410_dma_opfn_t)(s3c2410_dma_chan_t *, 141typedef int (*s3c2410_dma_opfn_t)(struct s3c2410_dma_chan *,
156 s3c2410_chan_op_t ); 142 enum s3c2410_chan_op );
157 143
158struct s3c2410_dma_stats_s { 144struct s3c2410_dma_stats {
159 unsigned long loads; 145 unsigned long loads;
160 unsigned long timeout_longest; 146 unsigned long timeout_longest;
161 unsigned long timeout_shortest; 147 unsigned long timeout_shortest;
162 unsigned long timeout_avg; 148 unsigned long timeout_avg;
163 unsigned long timeout_failed; 149 unsigned long timeout_failed;
164}; 150};
165 151
166typedef struct s3c2410_dma_stats_s s3c2410_dma_stats_t; 152/* struct s3c2410_dma_chan
167
168/* struct s3c2410_dma_chan_s
169 * 153 *
170 * full state information for each DMA channel 154 * full state information for each DMA channel
171*/ 155*/
172 156
173struct s3c2410_dma_chan_s { 157struct s3c2410_dma_chan {
174 /* channel state flags and information */ 158 /* channel state flags and information */
175 unsigned char number; /* number of this dma channel */ 159 unsigned char number; /* number of this dma channel */
176 unsigned char in_use; /* channel allocated */ 160 unsigned char in_use; /* channel allocated */
177 unsigned char irq_claimed; /* irq claimed for channel */ 161 unsigned char irq_claimed; /* irq claimed for channel */
178 unsigned char irq_enabled; /* irq enabled for channel */ 162 unsigned char irq_enabled; /* irq enabled for channel */
179 unsigned char xfer_unit; /* size of an transfer */ 163 unsigned char xfer_unit; /* size of an transfer */
180 164
181 /* channel state */ 165 /* channel state */
182 166
183 s3c2410_dma_state_t state; 167 enum s3c2410_dma_state state;
184 s3c2410_dma_loadst_t load_state; 168 enum s3c2410_dma_loadst load_state;
185 s3c2410_dma_client_t *client; 169 struct s3c2410_dma_client *client;
186 170
187 /* channel configuration */ 171 /* channel configuration */
188 s3c2410_dmasrc_t source; 172 enum s3c2410_dmasrc source;
189 unsigned long dev_addr; 173 unsigned long dev_addr;
190 unsigned long load_timeout; 174 unsigned long load_timeout;
191 unsigned int flags; /* channel flags */ 175 unsigned int flags; /* channel flags */
192 176
193 /* channel's hardware position and configuration */ 177 /* channel's hardware position and configuration */
194 void __iomem *regs; /* channels registers */ 178 void __iomem *regs; /* channels registers */
195 void __iomem *addr_reg; /* data address register */ 179 void __iomem *addr_reg; /* data address register */
196 unsigned int irq; /* channel irq */ 180 unsigned int irq; /* channel irq */
197 unsigned long dcon; /* default value of DCON */ 181 unsigned long dcon; /* default value of DCON */
198 182
199 /* driver handles */ 183 /* driver handles */
200 s3c2410_dma_cbfn_t callback_fn; /* buffer done callback */ 184 s3c2410_dma_cbfn_t callback_fn; /* buffer done callback */
201 s3c2410_dma_opfn_t op_fn; /* channel operation callback */ 185 s3c2410_dma_opfn_t op_fn; /* channel op callback */
202 186
203 /* stats gathering */ 187 /* stats gathering */
204 s3c2410_dma_stats_t *stats; 188 struct s3c2410_dma_stats *stats;
205 s3c2410_dma_stats_t stats_store; 189 struct s3c2410_dma_stats stats_store;
206 190
207 /* buffer list and information */ 191 /* buffer list and information */
208 s3c2410_dma_buf_t *curr; /* current dma buffer */ 192 struct s3c2410_dma_buf *curr; /* current dma buffer */
209 s3c2410_dma_buf_t *next; /* next buffer to load */ 193 struct s3c2410_dma_buf *next; /* next buffer to load */
210 s3c2410_dma_buf_t *end; /* end of queue */ 194 struct s3c2410_dma_buf *end; /* end of queue */
211 195
212 /* system device */ 196 /* system device */
213 struct sys_device dev; 197 struct sys_device dev;
214}; 198};
215 199
216/* the currently allocated channel information */ 200/* the currently allocated channel information */
217extern s3c2410_dma_chan_t s3c2410_chans[]; 201extern struct s3c2410_dma_chan s3c2410_chans[];
218 202
219/* note, we don't really use dma_device_t at the moment */ 203/* note, we don't really use dma_device_t at the moment */
220typedef unsigned long dma_device_t; 204typedef unsigned long dma_device_t;
@@ -227,7 +211,7 @@ typedef unsigned long dma_device_t;
227*/ 211*/
228 212
229extern int s3c2410_dma_request(dmach_t channel, 213extern int s3c2410_dma_request(dmach_t channel,
230 s3c2410_dma_client_t *, void *dev); 214 struct s3c2410_dma_client *, void *dev);
231 215
232 216
233/* s3c2410_dma_ctrl 217/* s3c2410_dma_ctrl
@@ -235,7 +219,7 @@ extern int s3c2410_dma_request(dmach_t channel,
235 * change the state of the dma channel 219 * change the state of the dma channel
236*/ 220*/
237 221
238extern int s3c2410_dma_ctrl(dmach_t channel, s3c2410_chan_op_t op); 222extern int s3c2410_dma_ctrl(dmach_t channel, enum s3c2410_chan_op op);
239 223
240/* s3c2410_dma_setflags 224/* s3c2410_dma_setflags
241 * 225 *
@@ -250,7 +234,7 @@ extern int s3c2410_dma_setflags(dmach_t channel,
250 * free the dma channel (will also abort any outstanding operations) 234 * free the dma channel (will also abort any outstanding operations)
251*/ 235*/
252 236
253extern int s3c2410_dma_free(dmach_t channel, s3c2410_dma_client_t *); 237extern int s3c2410_dma_free(dmach_t channel, struct s3c2410_dma_client *);
254 238
255/* s3c2410_dma_enqueue 239/* s3c2410_dma_enqueue
256 * 240 *
@@ -274,7 +258,7 @@ extern int s3c2410_dma_config(dmach_t channel, int xferunit, int dcon);
274 * configure the device we're talking to 258 * configure the device we're talking to
275*/ 259*/
276 260
277extern int s3c2410_dma_devconfig(int channel, s3c2410_dmasrc_t source, 261extern int s3c2410_dma_devconfig(int channel, enum s3c2410_dmasrc source,
278 int hwcfg, unsigned long devaddr); 262 int hwcfg, unsigned long devaddr);
279 263
280/* s3c2410_dma_getposition 264/* s3c2410_dma_getposition