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-rw-r--r--include/asm-arm/arch-pxa/regs-ssp.h127
1 files changed, 0 insertions, 127 deletions
diff --git a/include/asm-arm/arch-pxa/regs-ssp.h b/include/asm-arm/arch-pxa/regs-ssp.h
deleted file mode 100644
index 3c04cde2cf1f..000000000000
--- a/include/asm-arm/arch-pxa/regs-ssp.h
+++ /dev/null
@@ -1,127 +0,0 @@
1#ifndef __ASM_ARCH_REGS_SSP_H
2#define __ASM_ARCH_REGS_SSP_H
3
4/*
5 * SSP Serial Port Registers
6 * PXA250, PXA255, PXA26x and PXA27x SSP controllers are all slightly different.
7 * PXA255, PXA26x and PXA27x have extra ports, registers and bits.
8 */
9
10#define SSCR0 (0x00) /* SSP Control Register 0 */
11#define SSCR1 (0x04) /* SSP Control Register 1 */
12#define SSSR (0x08) /* SSP Status Register */
13#define SSITR (0x0C) /* SSP Interrupt Test Register */
14#define SSDR (0x10) /* SSP Data Write/Data Read Register */
15
16#define SSTO (0x28) /* SSP Time Out Register */
17#define SSPSP (0x2C) /* SSP Programmable Serial Protocol */
18#define SSTSA (0x30) /* SSP Tx Timeslot Active */
19#define SSRSA (0x34) /* SSP Rx Timeslot Active */
20#define SSTSS (0x38) /* SSP Timeslot Status */
21#define SSACD (0x3C) /* SSP Audio Clock Divider */
22
23#if defined(CONFIG_PXA3xx)
24#define SSACDD (0x40) /* SSP Audio Clock Dither Divider */
25#endif
26
27/* Common PXA2xx bits first */
28#define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */
29#define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */
30#define SSCR0_FRF (0x00000030) /* FRame Format (mask) */
31#define SSCR0_Motorola (0x0 << 4) /* Motorola's Serial Peripheral Interface (SPI) */
32#define SSCR0_TI (0x1 << 4) /* Texas Instruments' Synchronous Serial Protocol (SSP) */
33#define SSCR0_National (0x2 << 4) /* National Microwire */
34#define SSCR0_ECS (1 << 6) /* External clock select */
35#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */
36
37#if defined(CONFIG_PXA25x)
38#define SSCR0_SCR (0x0000ff00) /* Serial Clock Rate (mask) */
39#define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */
40
41#elif defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
42#define SSCR0_SCR (0x000fff00) /* Serial Clock Rate (mask) */
43#define SSCR0_SerClkDiv(x) (((x) - 1) << 8) /* Divisor [1..4096] */
44#define SSCR0_EDSS (1 << 20) /* Extended data size select */
45#define SSCR0_NCS (1 << 21) /* Network clock select */
46#define SSCR0_RIM (1 << 22) /* Receive FIFO overrrun interrupt mask */
47#define SSCR0_TUM (1 << 23) /* Transmit FIFO underrun interrupt mask */
48#define SSCR0_FRDC (0x07000000) /* Frame rate divider control (mask) */
49#define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */
50#define SSCR0_ADC (1 << 30) /* Audio clock select */
51#define SSCR0_MOD (1 << 31) /* Mode (normal or network) */
52#endif
53
54#if defined(CONFIG_PXA3xx)
55#define SSCR0_FPCKE (1 << 29) /* FIFO packing enable */
56#endif
57
58#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */
59#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */
60#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */
61#define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity setting */
62#define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */
63#define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */
64#define SSCR1_TFT (0x000003c0) /* Transmit FIFO Threshold (mask) */
65#define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */
66#define SSCR1_RFT (0x00003c00) /* Receive FIFO Threshold (mask) */
67#define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */
68
69#define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */
70#define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */
71#define SSSR_BSY (1 << 4) /* SSP Busy */
72#define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */
73#define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */
74#define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */
75
76#define SSCR0_TIM (1 << 23) /* Transmit FIFO Under Run Interrupt Mask */
77#define SSCR0_RIM (1 << 22) /* Receive FIFO Over Run interrupt Mask */
78#define SSCR0_NCS (1 << 21) /* Network Clock Select */
79#define SSCR0_EDSS (1 << 20) /* Extended Data Size Select */
80
81/* extra bits in PXA255, PXA26x and PXA27x SSP ports */
82#define SSCR0_TISSP (1 << 4) /* TI Sync Serial Protocol */
83#define SSCR0_PSP (3 << 4) /* PSP - Programmable Serial Protocol */
84#define SSCR1_TTELP (1 << 31) /* TXD Tristate Enable Last Phase */
85#define SSCR1_TTE (1 << 30) /* TXD Tristate Enable */
86#define SSCR1_EBCEI (1 << 29) /* Enable Bit Count Error interrupt */
87#define SSCR1_SCFR (1 << 28) /* Slave Clock free Running */
88#define SSCR1_ECRA (1 << 27) /* Enable Clock Request A */
89#define SSCR1_ECRB (1 << 26) /* Enable Clock request B */
90#define SSCR1_SCLKDIR (1 << 25) /* Serial Bit Rate Clock Direction */
91#define SSCR1_SFRMDIR (1 << 24) /* Frame Direction */
92#define SSCR1_RWOT (1 << 23) /* Receive Without Transmit */
93#define SSCR1_TRAIL (1 << 22) /* Trailing Byte */
94#define SSCR1_TSRE (1 << 21) /* Transmit Service Request Enable */
95#define SSCR1_RSRE (1 << 20) /* Receive Service Request Enable */
96#define SSCR1_TINTE (1 << 19) /* Receiver Time-out Interrupt enable */
97#define SSCR1_PINTE (1 << 18) /* Peripheral Trailing Byte Interupt Enable */
98#define SSCR1_IFS (1 << 16) /* Invert Frame Signal */
99#define SSCR1_STRF (1 << 15) /* Select FIFO or EFWR */
100#define SSCR1_EFWR (1 << 14) /* Enable FIFO Write/Read */
101
102#define SSSR_BCE (1 << 23) /* Bit Count Error */
103#define SSSR_CSS (1 << 22) /* Clock Synchronisation Status */
104#define SSSR_TUR (1 << 21) /* Transmit FIFO Under Run */
105#define SSSR_EOC (1 << 20) /* End Of Chain */
106#define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */
107#define SSSR_PINT (1 << 18) /* Peripheral Trailing Byte Interrupt */
108
109#define SSPSP_FSRT (1 << 25) /* Frame Sync Relative Timing */
110#define SSPSP_DMYSTOP(x) ((x) << 23) /* Dummy Stop */
111#define SSPSP_SFRMWDTH(x) ((x) << 16) /* Serial Frame Width */
112#define SSPSP_SFRMDLY(x) ((x) << 9) /* Serial Frame Delay */
113#define SSPSP_DMYSTRT(x) ((x) << 7) /* Dummy Start */
114#define SSPSP_STRTDLY(x) ((x) << 4) /* Start Delay */
115#define SSPSP_ETDS (1 << 3) /* End of Transfer data State */
116#define SSPSP_SFRMP (1 << 2) /* Serial Frame Polarity */
117#define SSPSP_SCMODE(x) ((x) << 0) /* Serial Bit Rate Clock Mode */
118
119#define SSACD_SCDB (1 << 3) /* SSPSYSCLK Divider Bypass */
120#define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */
121#define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */
122#if defined(CONFIG_PXA3xx)
123#define SSACD_SCDX8 (1 << 7) /* SYSCLK division ratio select */
124#endif
125
126
127#endif /* __ASM_ARCH_REGS_SSP_H */
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