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-rw-r--r--include/asm-arm/arch-orion/orion.h165
1 files changed, 0 insertions, 165 deletions
diff --git a/include/asm-arm/arch-orion/orion.h b/include/asm-arm/arch-orion/orion.h
deleted file mode 100644
index 673a418a7419..000000000000
--- a/include/asm-arm/arch-orion/orion.h
+++ /dev/null
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1/*
2 * include/asm-arm/arch-orion/orion.h
3 *
4 * Generic definitions of Orion SoC flavors:
5 * Orion-1, Orion-NAS, Orion-VoIP, and Orion-2.
6 *
7 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __ASM_ARCH_ORION_H__
15#define __ASM_ARCH_ORION_H__
16
17/*****************************************************************************
18 * Orion Address Map
19 *
20 * virt phys size
21 * fdd00000 f1000000 1M on-chip peripheral registers
22 * fde00000 f2000000 1M PCIe I/O space
23 * fdf00000 f2100000 1M PCI I/O space
24 * fe000000 f0000000 16M PCIe WA space (Orion-NAS only)
25 ****************************************************************************/
26#define ORION_REGS_PHYS_BASE 0xf1000000
27#define ORION_REGS_VIRT_BASE 0xfdd00000
28#define ORION_REGS_SIZE SZ_1M
29
30#define ORION_PCIE_IO_PHYS_BASE 0xf2000000
31#define ORION_PCIE_IO_VIRT_BASE 0xfde00000
32#define ORION_PCIE_IO_BUS_BASE 0x00000000
33#define ORION_PCIE_IO_SIZE SZ_1M
34
35#define ORION_PCI_IO_PHYS_BASE 0xf2100000
36#define ORION_PCI_IO_VIRT_BASE 0xfdf00000
37#define ORION_PCI_IO_BUS_BASE 0x00100000
38#define ORION_PCI_IO_SIZE SZ_1M
39
40/* Relevant only for Orion-NAS */
41#define ORION_PCIE_WA_PHYS_BASE 0xf0000000
42#define ORION_PCIE_WA_VIRT_BASE 0xfe000000
43#define ORION_PCIE_WA_SIZE SZ_16M
44
45#define ORION_PCIE_MEM_PHYS_BASE 0xe0000000
46#define ORION_PCIE_MEM_SIZE SZ_128M
47
48#define ORION_PCI_MEM_PHYS_BASE 0xe8000000
49#define ORION_PCI_MEM_SIZE SZ_128M
50
51/*******************************************************************************
52 * Supported Devices & Revisions
53 ******************************************************************************/
54/* Orion-1 (88F5181) */
55#define MV88F5181_DEV_ID 0x5181
56#define MV88F5181_REV_B1 3
57/* Orion-NAS (88F5182) */
58#define MV88F5182_DEV_ID 0x5182
59#define MV88F5182_REV_A2 2
60/* Orion-2 (88F5281) */
61#define MV88F5281_DEV_ID 0x5281
62#define MV88F5281_REV_D1 5
63#define MV88F5281_REV_D2 6
64
65/*******************************************************************************
66 * Orion Registers Map
67 ******************************************************************************/
68#define ORION_DDR_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x00000)
69#define ORION_DDR_REG(x) (ORION_DDR_VIRT_BASE | (x))
70
71#define ORION_DEV_BUS_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x10000)
72#define ORION_DEV_BUS_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x10000)
73#define ORION_DEV_BUS_REG(x) (ORION_DEV_BUS_VIRT_BASE | (x))
74#define I2C_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x1000)
75#define UART0_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x2000)
76#define UART0_VIRT_BASE (ORION_DEV_BUS_VIRT_BASE | 0x2000)
77#define UART1_PHYS_BASE (ORION_DEV_BUS_PHYS_BASE | 0x2100)
78#define UART1_VIRT_BASE (ORION_DEV_BUS_VIRT_BASE | 0x2100)
79
80#define ORION_BRIDGE_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x20000)
81#define ORION_BRIDGE_REG(x) (ORION_BRIDGE_VIRT_BASE | (x))
82
83#define ORION_PCI_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x30000)
84#define ORION_PCI_REG(x) (ORION_PCI_VIRT_BASE | (x))
85
86#define ORION_PCIE_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x40000)
87#define ORION_PCIE_REG(x) (ORION_PCIE_VIRT_BASE | (x))
88
89#define ORION_USB0_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x50000)
90#define ORION_USB0_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x50000)
91#define ORION_USB0_REG(x) (ORION_USB0_VIRT_BASE | (x))
92
93#define ORION_ETH_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x70000)
94#define ORION_ETH_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x70000)
95#define ORION_ETH_REG(x) (ORION_ETH_VIRT_BASE | (x))
96
97#define ORION_SATA_PHYS_BASE (ORION_REGS_PHYS_BASE | 0x80000)
98#define ORION_SATA_VIRT_BASE (ORION_REGS_VIRT_BASE | 0x80000)
99#define ORION_SATA_REG(x) (ORION_SATA_VIRT_BASE | (x))
100
101#define ORION_USB1_PHYS_BASE (ORION_REGS_PHYS_BASE | 0xa0000)
102#define ORION_USB1_VIRT_BASE (ORION_REGS_VIRT_BASE | 0xa0000)
103#define ORION_USB1_REG(x) (ORION_USB1_VIRT_BASE | (x))
104
105/*******************************************************************************
106 * Device Bus Registers
107 ******************************************************************************/
108#define MPP_0_7_CTRL ORION_DEV_BUS_REG(0x000)
109#define MPP_8_15_CTRL ORION_DEV_BUS_REG(0x004)
110#define MPP_16_19_CTRL ORION_DEV_BUS_REG(0x050)
111#define MPP_DEV_CTRL ORION_DEV_BUS_REG(0x008)
112#define MPP_RESET_SAMPLE ORION_DEV_BUS_REG(0x010)
113#define GPIO_OUT ORION_DEV_BUS_REG(0x100)
114#define GPIO_IO_CONF ORION_DEV_BUS_REG(0x104)
115#define GPIO_BLINK_EN ORION_DEV_BUS_REG(0x108)
116#define GPIO_IN_POL ORION_DEV_BUS_REG(0x10c)
117#define GPIO_DATA_IN ORION_DEV_BUS_REG(0x110)
118#define GPIO_EDGE_CAUSE ORION_DEV_BUS_REG(0x114)
119#define GPIO_EDGE_MASK ORION_DEV_BUS_REG(0x118)
120#define GPIO_LEVEL_MASK ORION_DEV_BUS_REG(0x11c)
121#define DEV_BANK_0_PARAM ORION_DEV_BUS_REG(0x45c)
122#define DEV_BANK_1_PARAM ORION_DEV_BUS_REG(0x460)
123#define DEV_BANK_2_PARAM ORION_DEV_BUS_REG(0x464)
124#define DEV_BANK_BOOT_PARAM ORION_DEV_BUS_REG(0x46c)
125#define DEV_BUS_CTRL ORION_DEV_BUS_REG(0x4c0)
126#define DEV_BUS_INT_CAUSE ORION_DEV_BUS_REG(0x4d0)
127#define DEV_BUS_INT_MASK ORION_DEV_BUS_REG(0x4d4)
128#define GPIO_MAX 32
129
130/***************************************************************************
131 * Orion CPU Bridge Registers
132 **************************************************************************/
133#define CPU_CONF ORION_BRIDGE_REG(0x100)
134#define CPU_CTRL ORION_BRIDGE_REG(0x104)
135#define CPU_RESET_MASK ORION_BRIDGE_REG(0x108)
136#define CPU_SOFT_RESET ORION_BRIDGE_REG(0x10c)
137#define POWER_MNG_CTRL_REG ORION_BRIDGE_REG(0x11C)
138#define BRIDGE_CAUSE ORION_BRIDGE_REG(0x110)
139#define BRIDGE_MASK ORION_BRIDGE_REG(0x114)
140#define MAIN_IRQ_CAUSE ORION_BRIDGE_REG(0x200)
141#define MAIN_IRQ_MASK ORION_BRIDGE_REG(0x204)
142#define TIMER_CTRL ORION_BRIDGE_REG(0x300)
143#define TIMER_VAL(x) ORION_BRIDGE_REG(0x314 + ((x) * 8))
144#define TIMER_VAL_RELOAD(x) ORION_BRIDGE_REG(0x310 + ((x) * 8))
145
146#ifndef __ASSEMBLY__
147
148/*******************************************************************************
149 * Helpers to access Orion registers
150 ******************************************************************************/
151#include <asm/types.h>
152#include <asm/io.h>
153
154#define orion_read(r) __raw_readl(r)
155#define orion_write(r, val) __raw_writel(val, r)
156
157/*
158 * These are not preempt safe. Locks, if needed, must be taken care by caller.
159 */
160#define orion_setbits(r, mask) orion_write((r), orion_read(r) | (mask))
161#define orion_clrbits(r, mask) orion_write((r), orion_read(r) & ~(mask))
162
163#endif /* __ASSEMBLY__ */
164
165#endif /* __ASM_ARCH_ORION_H__ */
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