diff options
Diffstat (limited to 'include/asm-arm/arch-at91rm9200/at91sam926x_mc.h')
| -rw-r--r-- | include/asm-arm/arch-at91rm9200/at91sam926x_mc.h | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/include/asm-arm/arch-at91rm9200/at91sam926x_mc.h b/include/asm-arm/arch-at91rm9200/at91sam926x_mc.h index 7d94968b5d57..972e7531c7f4 100644 --- a/include/asm-arm/arch-at91rm9200/at91sam926x_mc.h +++ b/include/asm-arm/arch-at91rm9200/at91sam926x_mc.h | |||
| @@ -33,14 +33,14 @@ | |||
| 33 | #define AT91_SDRAMC_NC_9 (1 << 0) | 33 | #define AT91_SDRAMC_NC_9 (1 << 0) |
| 34 | #define AT91_SDRAMC_NC_10 (2 << 0) | 34 | #define AT91_SDRAMC_NC_10 (2 << 0) |
| 35 | #define AT91_SDRAMC_NC_11 (3 << 0) | 35 | #define AT91_SDRAMC_NC_11 (3 << 0) |
| 36 | #define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */ | 36 | #define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */ |
| 37 | #define AT91_SDRAMC_NR_11 (0 << 2) | 37 | #define AT91_SDRAMC_NR_11 (0 << 2) |
| 38 | #define AT91_SDRAMC_NR_12 (1 << 2) | 38 | #define AT91_SDRAMC_NR_12 (1 << 2) |
| 39 | #define AT91_SDRAMC_NR_13 (2 << 2) | 39 | #define AT91_SDRAMC_NR_13 (2 << 2) |
| 40 | #define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */ | 40 | #define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */ |
| 41 | #define AT91_SDRAMC_NB_2 (0 << 4) | 41 | #define AT91_SDRAMC_NB_2 (0 << 4) |
| 42 | #define AT91_SDRAMC_NB_4 (1 << 4) | 42 | #define AT91_SDRAMC_NB_4 (1 << 4) |
| 43 | #define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */ | 43 | #define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */ |
| 44 | #define AT91_SDRAMC_CAS_1 (1 << 5) | 44 | #define AT91_SDRAMC_CAS_1 (1 << 5) |
| 45 | #define AT91_SDRAMC_CAS_2 (2 << 5) | 45 | #define AT91_SDRAMC_CAS_2 (2 << 5) |
| 46 | #define AT91_SDRAMC_CAS_3 (3 << 5) | 46 | #define AT91_SDRAMC_CAS_3 (3 << 5) |
| @@ -110,10 +110,10 @@ | |||
| 110 | #define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ | 110 | #define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */ |
| 111 | #define AT91_SMC_READMODE (1 << 0) /* Read Mode */ | 111 | #define AT91_SMC_READMODE (1 << 0) /* Read Mode */ |
| 112 | #define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */ | 112 | #define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */ |
| 113 | #define AT91_SMC_EXNWMODE (3 << 5) /* NWAIT Mode */ | 113 | #define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */ |
| 114 | #define AT91_SMC_EXNWMODE_DISABLE (0 << 5) | 114 | #define AT91_SMC_EXNWMODE_DISABLE (0 << 4) |
| 115 | #define AT91_SMC_EXNWMODE_FROZEN (2 << 5) | 115 | #define AT91_SMC_EXNWMODE_FROZEN (2 << 4) |
| 116 | #define AT91_SMC_EXNWMODE_READY (3 << 5) | 116 | #define AT91_SMC_EXNWMODE_READY (3 << 4) |
| 117 | #define AT91_SMC_BAT (1 << 8) /* Byte Access Type */ | 117 | #define AT91_SMC_BAT (1 << 8) /* Byte Access Type */ |
| 118 | #define AT91_SMC_BAT_SELECT (0 << 8) | 118 | #define AT91_SMC_BAT_SELECT (0 << 8) |
| 119 | #define AT91_SMC_BAT_WRITE (1 << 8) | 119 | #define AT91_SMC_BAT_WRITE (1 << 8) |