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-rw-r--r--include/asm-arm/arch-at91rm9200/at91sam926x_mc.h134
1 files changed, 0 insertions, 134 deletions
diff --git a/include/asm-arm/arch-at91rm9200/at91sam926x_mc.h b/include/asm-arm/arch-at91rm9200/at91sam926x_mc.h
deleted file mode 100644
index 972e7531c7f4..000000000000
--- a/include/asm-arm/arch-at91rm9200/at91sam926x_mc.h
+++ /dev/null
@@ -1,134 +0,0 @@
1/*
2 * include/asm-arm/arch-at91rm9200/at91sam926x_mc.h
3 *
4 * Memory Controllers (SMC, SDRAMC) - System peripherals registers.
5 * Based on AT91SAM9261 datasheet revision D.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#ifndef AT91SAM926x_MC_H
14#define AT91SAM926x_MC_H
15
16/* SDRAM Controller (SDRAMC) registers */
17#define AT91_SDRAMC_MR (AT91_SDRAMC + 0x00) /* SDRAM Controller Mode Register */
18#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
19#define AT91_SDRAMC_MODE_NORMAL 0
20#define AT91_SDRAMC_MODE_NOP 1
21#define AT91_SDRAMC_MODE_PRECHARGE 2
22#define AT91_SDRAMC_MODE_LMR 3
23#define AT91_SDRAMC_MODE_REFRESH 4
24#define AT91_SDRAMC_MODE_EXT_LMR 5
25#define AT91_SDRAMC_MODE_DEEP 6
26
27#define AT91_SDRAMC_TR (AT91_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */
28#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */
29
30#define AT91_SDRAMC_CR (AT91_SDRAMC + 0x08) /* SDRAM Controller Configuration Register */
31#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */
32#define AT91_SDRAMC_NC_8 (0 << 0)
33#define AT91_SDRAMC_NC_9 (1 << 0)
34#define AT91_SDRAMC_NC_10 (2 << 0)
35#define AT91_SDRAMC_NC_11 (3 << 0)
36#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */
37#define AT91_SDRAMC_NR_11 (0 << 2)
38#define AT91_SDRAMC_NR_12 (1 << 2)
39#define AT91_SDRAMC_NR_13 (2 << 2)
40#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */
41#define AT91_SDRAMC_NB_2 (0 << 4)
42#define AT91_SDRAMC_NB_4 (1 << 4)
43#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */
44#define AT91_SDRAMC_CAS_1 (1 << 5)
45#define AT91_SDRAMC_CAS_2 (2 << 5)
46#define AT91_SDRAMC_CAS_3 (3 << 5)
47#define AT91_SDRAMC_DBW (1 << 7) /* Data Bus Width */
48#define AT91_SDRAMC_DBW_32 (0 << 7)
49#define AT91_SDRAMC_DBW_16 (1 << 7)
50#define AT91_SDRAMC_TWR (0xf << 8) /* Write Recovery Delay */
51#define AT91_SDRAMC_TRC (0xf << 12) /* Row Cycle Delay */
52#define AT91_SDRAMC_TRP (0xf << 16) /* Row Precharge Delay */
53#define AT91_SDRAMC_TRCD (0xf << 20) /* Row to Column Delay */
54#define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */
55#define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */
56
57#define AT91_SDRAMC_LPR (AT91_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */
58#define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */
59#define AT91_SDRAMC_LPCB_DISABLE 0
60#define AT91_SDRAMC_LPCB_SELF_REFRESH 1
61#define AT91_SDRAMC_LPCB_POWER_DOWN 2
62#define AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3
63#define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */
64#define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
65#define AT91_SDRAMC_DS (3 << 10) /* Drive Strenght */
66#define AT91_SDRAMC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
67#define AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES (0 << 12)
68#define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12)
69#define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12)
70
71#define AT91_SDRAMC_IER (AT91_SDRAMC + 0x14) /* SDRAM Controller Interrupt Enable Register */
72#define AT91_SDRAMC_IDR (AT91_SDRAMC + 0x18) /* SDRAM Controller Interrupt Disable Register */
73#define AT91_SDRAMC_IMR (AT91_SDRAMC + 0x1C) /* SDRAM Controller Interrupt Mask Register */
74#define AT91_SDRAMC_ISR (AT91_SDRAMC + 0x20) /* SDRAM Controller Interrupt Status Register */
75#define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */
76
77#define AT91_SDRAMC_MDR (AT91_SDRAMC + 0x24) /* SDRAM Memory Device Register */
78#define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */
79#define AT91_SDRAMC_MD_SDRAM 0
80#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1
81
82
83/* Static Memory Controller (SMC) registers */
84#define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
85#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */
86#define AT91_SMC_NWESETUP_(x) ((x) << 0)
87#define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */
88#define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8)
89#define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */
90#define AT91_SMC_NRDSETUP_(x) ((x) << 16)
91#define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */
92#define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24)
93
94#define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
95#define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */
96#define AT91_SMC_NWEPULSE_(x) ((x) << 0)
97#define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */
98#define AT91_SMC_NCS_WRPULSE_(x)((x) << 8)
99#define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */
100#define AT91_SMC_NRDPULSE_(x) ((x) << 16)
101#define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */
102#define AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
103
104#define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
105#define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */
106#define AT91_SMC_NWECYCLE_(x) ((x) << 0)
107#define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */
108#define AT91_SMC_NRDCYCLE_(x) ((x) << 16)
109
110#define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
111#define AT91_SMC_READMODE (1 << 0) /* Read Mode */
112#define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */
113#define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */
114#define AT91_SMC_EXNWMODE_DISABLE (0 << 4)
115#define AT91_SMC_EXNWMODE_FROZEN (2 << 4)
116#define AT91_SMC_EXNWMODE_READY (3 << 4)
117#define AT91_SMC_BAT (1 << 8) /* Byte Access Type */
118#define AT91_SMC_BAT_SELECT (0 << 8)
119#define AT91_SMC_BAT_WRITE (1 << 8)
120#define AT91_SMC_DBW (3 << 12) /* Data Bus Width */
121#define AT91_SMC_DBW_8 (0 << 12)
122#define AT91_SMC_DBW_16 (1 << 12)
123#define AT91_SMC_DBW_32 (2 << 12)
124#define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */
125#define AT91_SMC_TDF_(x) ((x) << 16)
126#define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */
127#define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */
128#define AT91_SMC_PS (3 << 28) /* Page Size */
129#define AT91_SMC_PS_4 (0 << 28)
130#define AT91_SMC_PS_8 (1 << 28)
131#define AT91_SMC_PS_16 (2 << 28)
132#define AT91_SMC_PS_32 (3 << 28)
133
134#endif
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