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1/*
2 * include/asm-arm/arch-at91/at91rm9200_mc.h
3 *
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 *
7 * Memory Controllers (MC, EBI, SMC, SDRAMC, BFC) - System peripherals registers.
8 * Based on AT91RM9200 datasheet revision E.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91RM9200_MC_H
17#define AT91RM9200_MC_H
18
19/* Memory Controller */
20#define AT91_MC_RCR (AT91_MC + 0x00) /* MC Remap Control Register */
21#define AT91_MC_RCB (1 << 0) /* Remap Command Bit */
22
23#define AT91_MC_ASR (AT91_MC + 0x04) /* MC Abort Status Register */
24#define AT91_MC_UNADD (1 << 0) /* Undefined Address Abort Status */
25#define AT91_MC_MISADD (1 << 1) /* Misaligned Address Abort Status */
26#define AT91_MC_ABTSZ (3 << 8) /* Abort Size Status */
27#define AT91_MC_ABTSZ_BYTE (0 << 8)
28#define AT91_MC_ABTSZ_HALFWORD (1 << 8)
29#define AT91_MC_ABTSZ_WORD (2 << 8)
30#define AT91_MC_ABTTYP (3 << 10) /* Abort Type Status */
31#define AT91_MC_ABTTYP_DATAREAD (0 << 10)
32#define AT91_MC_ABTTYP_DATAWRITE (1 << 10)
33#define AT91_MC_ABTTYP_FETCH (2 << 10)
34#define AT91_MC_MST0 (1 << 16) /* ARM920T Abort Source */
35#define AT91_MC_MST1 (1 << 17) /* PDC Abort Source */
36#define AT91_MC_MST2 (1 << 18) /* UHP Abort Source */
37#define AT91_MC_MST3 (1 << 19) /* EMAC Abort Source */
38#define AT91_MC_SVMST0 (1 << 24) /* Saved ARM920T Abort Source */
39#define AT91_MC_SVMST1 (1 << 25) /* Saved PDC Abort Source */
40#define AT91_MC_SVMST2 (1 << 26) /* Saved UHP Abort Source */
41#define AT91_MC_SVMST3 (1 << 27) /* Saved EMAC Abort Source */
42
43#define AT91_MC_AASR (AT91_MC + 0x08) /* MC Abort Address Status Register */
44
45#define AT91_MC_MPR (AT91_MC + 0x0c) /* MC Master Priority Register */
46#define AT91_MPR_MSTP0 (7 << 0) /* ARM920T Priority */
47#define AT91_MPR_MSTP1 (7 << 4) /* PDC Priority */
48#define AT91_MPR_MSTP2 (7 << 8) /* UHP Priority */
49#define AT91_MPR_MSTP3 (7 << 12) /* EMAC Priority */
50
51/* External Bus Interface (EBI) registers */
52#define AT91_EBI_CSA (AT91_MC + 0x60) /* Chip Select Assignment Register */
53#define AT91_EBI_CS0A (1 << 0) /* Chip Select 0 Assignment */
54#define AT91_EBI_CS0A_SMC (0 << 0)
55#define AT91_EBI_CS0A_BFC (1 << 0)
56#define AT91_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
57#define AT91_EBI_CS1A_SMC (0 << 1)
58#define AT91_EBI_CS1A_SDRAMC (1 << 1)
59#define AT91_EBI_CS3A (1 << 3) /* Chip Select 2 Assignment */
60#define AT91_EBI_CS3A_SMC (0 << 3)
61#define AT91_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
62#define AT91_EBI_CS4A (1 << 4) /* Chip Select 3 Assignment */
63#define AT91_EBI_CS4A_SMC (0 << 4)
64#define AT91_EBI_CS4A_SMC_COMPACTFLASH (1 << 4)
65#define AT91_EBI_CFGR (AT91_MC + 0x64) /* Configuration Register */
66#define AT91_EBI_DBPUC (1 << 0) /* Data Bus Pull-Up Configuration */
67
68/* Static Memory Controller (SMC) registers */
69#define AT91_SMC_CSR(n) (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */
70#define AT91_SMC_NWS (0x7f << 0) /* Number of Wait States */
71#define AT91_SMC_NWS_(x) ((x) << 0)
72#define AT91_SMC_WSEN (1 << 7) /* Wait State Enable */
73#define AT91_SMC_TDF (0xf << 8) /* Data Float Time */
74#define AT91_SMC_TDF_(x) ((x) << 8)
75#define AT91_SMC_BAT (1 << 12) /* Byte Access Type */
76#define AT91_SMC_DBW (3 << 13) /* Data Bus Width */
77#define AT91_SMC_DBW_16 (1 << 13)
78#define AT91_SMC_DBW_8 (2 << 13)
79#define AT91_SMC_DPR (1 << 15) /* Data Read Protocol */
80#define AT91_SMC_ACSS (3 << 16) /* Address to Chip Select Setup */
81#define AT91_SMC_ACSS_STD (0 << 16)
82#define AT91_SMC_ACSS_1 (1 << 16)
83#define AT91_SMC_ACSS_2 (2 << 16)
84#define AT91_SMC_ACSS_3 (3 << 16)
85#define AT91_SMC_RWSETUP (7 << 24) /* Read & Write Signal Time Setup */
86#define AT91_SMC_RWSETUP_(x) ((x) << 24)
87#define AT91_SMC_RWHOLD (7 << 28) /* Read & Write Signal Hold Time */
88#define AT91_SMC_RWHOLD_(x) ((x) << 28)
89
90/* SDRAM Controller registers */
91#define AT91_SDRAMC_MR (AT91_MC + 0x90) /* Mode Register */
92#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
93#define AT91_SDRAMC_MODE_NORMAL (0 << 0)
94#define AT91_SDRAMC_MODE_NOP (1 << 0)
95#define AT91_SDRAMC_MODE_PRECHARGE (2 << 0)
96#define AT91_SDRAMC_MODE_LMR (3 << 0)
97#define AT91_SDRAMC_MODE_REFRESH (4 << 0)
98#define AT91_SDRAMC_DBW (1 << 4) /* Data Bus Width */
99#define AT91_SDRAMC_DBW_32 (0 << 4)
100#define AT91_SDRAMC_DBW_16 (1 << 4)
101
102#define AT91_SDRAMC_TR (AT91_MC + 0x94) /* Refresh Timer Register */
103#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */
104
105#define AT91_SDRAMC_CR (AT91_MC + 0x98) /* Configuration Register */
106#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */
107#define AT91_SDRAMC_NC_8 (0 << 0)
108#define AT91_SDRAMC_NC_9 (1 << 0)
109#define AT91_SDRAMC_NC_10 (2 << 0)
110#define AT91_SDRAMC_NC_11 (3 << 0)
111#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */
112#define AT91_SDRAMC_NR_11 (0 << 2)
113#define AT91_SDRAMC_NR_12 (1 << 2)
114#define AT91_SDRAMC_NR_13 (2 << 2)
115#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */
116#define AT91_SDRAMC_NB_2 (0 << 4)
117#define AT91_SDRAMC_NB_4 (1 << 4)
118#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */
119#define AT91_SDRAMC_CAS_2 (2 << 5)
120#define AT91_SDRAMC_TWR (0xf << 7) /* Write Recovery Delay */
121#define AT91_SDRAMC_TRC (0xf << 11) /* Row Cycle Delay */
122#define AT91_SDRAMC_TRP (0xf << 15) /* Row Precharge Delay */
123#define AT91_SDRAMC_TRCD (0xf << 19) /* Row to Column Delay */
124#define AT91_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */
125#define AT91_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */
126
127#define AT91_SDRAMC_SRR (AT91_MC + 0x9c) /* Self Refresh Register */
128#define AT91_SDRAMC_LPR (AT91_MC + 0xa0) /* Low Power Register */
129#define AT91_SDRAMC_IER (AT91_MC + 0xa4) /* Interrupt Enable Register */
130#define AT91_SDRAMC_IDR (AT91_MC + 0xa8) /* Interrupt Disable Register */
131#define AT91_SDRAMC_IMR (AT91_MC + 0xac) /* Interrupt Mask Register */
132#define AT91_SDRAMC_ISR (AT91_MC + 0xb0) /* Interrupt Status Register */
133
134/* Burst Flash Controller register */
135#define AT91_BFC_MR (AT91_MC + 0xc0) /* Mode Register */
136#define AT91_BFC_BFCOM (3 << 0) /* Burst Flash Controller Operating Mode */
137#define AT91_BFC_BFCOM_DISABLED (0 << 0)
138#define AT91_BFC_BFCOM_ASYNC (1 << 0)
139#define AT91_BFC_BFCOM_BURST (2 << 0)
140#define AT91_BFC_BFCC (3 << 2) /* Burst Flash Controller Clock */
141#define AT91_BFC_BFCC_MCK (1 << 2)
142#define AT91_BFC_BFCC_DIV2 (2 << 2)
143#define AT91_BFC_BFCC_DIV4 (3 << 2)
144#define AT91_BFC_AVL (0xf << 4) /* Address Valid Latency */
145#define AT91_BFC_PAGES (7 << 8) /* Page Size */
146#define AT91_BFC_PAGES_NO_PAGE (0 << 8)
147#define AT91_BFC_PAGES_16 (1 << 8)
148#define AT91_BFC_PAGES_32 (2 << 8)
149#define AT91_BFC_PAGES_64 (3 << 8)
150#define AT91_BFC_PAGES_128 (4 << 8)
151#define AT91_BFC_PAGES_256 (5 << 8)
152#define AT91_BFC_PAGES_512 (6 << 8)
153#define AT91_BFC_PAGES_1024 (7 << 8)
154#define AT91_BFC_OEL (3 << 12) /* Output Enable Latency */
155#define AT91_BFC_BAAEN (1 << 16) /* Burst Address Advance Enable */
156#define AT91_BFC_BFOEH (1 << 17) /* Burst Flash Output Enable Handling */
157#define AT91_BFC_MUXEN (1 << 18) /* Multiplexed Bus Enable */
158#define AT91_BFC_RDYEN (1 << 19) /* Ready Enable Mode */
159
160#endif
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