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diff --git a/include/asm-arm/arch-aaec2000/aaec2000.h b/include/asm-arm/arch-aaec2000/aaec2000.h
deleted file mode 100644
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--- a/include/asm-arm/arch-aaec2000/aaec2000.h
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1/*
2 * linux/include/asm-arm/arch-aaec2000/aaec2000.h
3 *
4 * AAEC-2000 registers definition
5 *
6 * Copyright (c) 2005 Nicolas Bellido Y Ortega
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __ASM_ARCH_AAEC2000_H
14#define __ASM_ARCH_AAEC2000_H
15
16#ifndef __ASM_ARCH_HARDWARE_H
17#error You must include hardware.h not this file
18#endif /* __ASM_ARCH_HARDWARE_H */
19
20/* Chip selects */
21#define AAEC_CS0 0x00000000
22#define AAEC_CS1 0x10000000
23#define AAEC_CS2 0x20000000
24#define AAEC_CS3 0x30000000
25
26/* Flash */
27#define AAEC_FLASH_BASE AAEC_CS0
28#define AAEC_FLASH_SIZE SZ_64M
29
30/* Interrupt controller */
31#define IRQ_BASE __REG(0x80000500)
32#define IRQ_INTSR __REG(0x80000500) /* Int Status Register */
33#define IRQ_INTRSR __REG(0x80000504) /* Int Raw (unmasked) Status */
34#define IRQ_INTENS __REG(0x80000508) /* Int Enable Set */
35#define IRQ_INTENC __REG(0x8000050c) /* Int Enable Clear */
36
37/* UART 1 */
38#define UART1_BASE __REG(0x80000600)
39#define UART1_DR __REG(0x80000600) /* Data/FIFO Register */
40#define UART1_LCR __REG(0x80000604) /* Link Control Register */
41#define UART1_BRCR __REG(0x80000608) /* Baud Rate Control Register */
42#define UART1_CR __REG(0x8000060c) /* Control Register */
43#define UART1_SR __REG(0x80000610) /* Status Register */
44#define UART1_INT __REG(0x80000614) /* Interrupt Status Register */
45#define UART1_INTM __REG(0x80000618) /* Interrupt Mask Register */
46#define UART1_INTRES __REG(0x8000061c) /* Int Result (masked status) Register */
47
48/* UART 2 */
49#define UART2_BASE __REG(0x80000700)
50#define UART2_DR __REG(0x80000700) /* Data/FIFO Register */
51#define UART2_LCR __REG(0x80000704) /* Link Control Register */
52#define UART2_BRCR __REG(0x80000708) /* Baud Rate Control Register */
53#define UART2_CR __REG(0x8000070c) /* Control Register */
54#define UART2_SR __REG(0x80000710) /* Status Register */
55#define UART2_INT __REG(0x80000714) /* Interrupt Status Register */
56#define UART2_INTM __REG(0x80000718) /* Interrupt Mask Register */
57#define UART2_INTRES __REG(0x8000071c) /* Int Result (masked status) Register */
58
59/* UART 3 */
60#define UART3_BASE __REG(0x80000800)
61#define UART3_DR __REG(0x80000800) /* Data/FIFO Register */
62#define UART3_LCR __REG(0x80000804) /* Link Control Register */
63#define UART3_BRCR __REG(0x80000808) /* Baud Rate Control Register */
64#define UART3_CR __REG(0x8000080c) /* Control Register */
65#define UART3_SR __REG(0x80000810) /* Status Register */
66#define UART3_INT __REG(0x80000814) /* Interrupt Status Register */
67#define UART3_INTM __REG(0x80000818) /* Interrupt Mask Register */
68#define UART3_INTRES __REG(0x8000081c) /* Int Result (masked status) Register */
69
70/* These are used in some places */
71#define _UART1_BASE __PREG(UART1_BASE)
72#define _UART2_BASE __PREG(UART2_BASE)
73#define _UART3_BASE __PREG(UART3_BASE)
74
75/* UART Registers Offsets */
76#define UART_DR 0x00
77#define UART_LCR 0x04
78#define UART_BRCR 0x08
79#define UART_CR 0x0c
80#define UART_SR 0x10
81#define UART_INT 0x14
82#define UART_INTM 0x18
83#define UART_INTRES 0x1c
84
85/* UART_LCR Bitmask */
86#define UART_LCR_BRK (1 << 0) /* Send Break */
87#define UART_LCR_PEN (1 << 1) /* Parity Enable */
88#define UART_LCR_EP (1 << 2) /* Even/Odd Parity */
89#define UART_LCR_S2 (1 << 3) /* One/Two Stop bits */
90#define UART_LCR_FIFO (1 << 4) /* FIFO Enable */
91#define UART_LCR_WL5 (0 << 5) /* Word Length - 5 bits */
92#define UART_LCR_WL6 (1 << 5) /* Word Length - 6 bits */
93#define UART_LCR_WL7 (1 << 6) /* Word Length - 7 bits */
94#define UART_LCR_WL8 (1 << 7) /* Word Length - 8 bits */
95
96/* UART_CR Bitmask */
97#define UART_CR_EN (1 << 0) /* UART Enable */
98#define UART_CR_SIR (1 << 1) /* IrDA SIR Enable */
99#define UART_CR_SIRLP (1 << 2) /* Low Power IrDA Enable */
100#define UART_CR_RXP (1 << 3) /* Receive Pin Polarity */
101#define UART_CR_TXP (1 << 4) /* Transmit Pin Polarity */
102#define UART_CR_MXP (1 << 5) /* Modem Pin Polarity */
103#define UART_CR_LOOP (1 << 6) /* Loopback Mode */
104
105/* UART_SR Bitmask */
106#define UART_SR_CTS (1 << 0) /* Clear To Send Status */
107#define UART_SR_DSR (1 << 1) /* Data Set Ready Status */
108#define UART_SR_DCD (1 << 2) /* Data Carrier Detect Status */
109#define UART_SR_TxBSY (1 << 3) /* Transmitter Busy Status */
110#define UART_SR_RxFE (1 << 4) /* Receive FIFO Empty Status */
111#define UART_SR_TxFF (1 << 5) /* Transmit FIFO Full Status */
112#define UART_SR_RxFF (1 << 6) /* Receive FIFO Full Status */
113#define UART_SR_TxFE (1 << 7) /* Transmit FIFO Empty Status */
114
115/* UART_INT Bitmask */
116#define UART_INT_RIS (1 << 0) /* Rx Interrupt */
117#define UART_INT_TIS (1 << 1) /* Tx Interrupt */
118#define UART_INT_MIS (1 << 2) /* Modem Interrupt */
119#define UART_INT_RTIS (1 << 3) /* Receive Timeout Interrupt */
120
121/* Timer 1 */
122#define TIMER1_BASE __REG(0x80000c00)
123#define TIMER1_LOAD __REG(0x80000c00) /* Timer 1 Load Register */
124#define TIMER1_VAL __REG(0x80000c04) /* Timer 1 Value Register */
125#define TIMER1_CTRL __REG(0x80000c08) /* Timer 1 Control Register */
126#define TIMER1_CLEAR __REG(0x80000c0c) /* Timer 1 Clear Register */
127
128/* Timer 2 */
129#define TIMER2_BASE __REG(0x80000d00)
130#define TIMER2_LOAD __REG(0x80000d00) /* Timer 2 Load Register */
131#define TIMER2_VAL __REG(0x80000d04) /* Timer 2 Value Register */
132#define TIMER2_CTRL __REG(0x80000d08) /* Timer 2 Control Register */
133#define TIMER2_CLEAR __REG(0x80000d0c) /* Timer 2 Clear Register */
134
135/* Timer 3 */
136#define TIMER3_BASE __REG(0x80000e00)
137#define TIMER3_LOAD __REG(0x80000e00) /* Timer 3 Load Register */
138#define TIMER3_VAL __REG(0x80000e04) /* Timer 3 Value Register */
139#define TIMER3_CTRL __REG(0x80000e08) /* Timer 3 Control Register */
140#define TIMER3_CLEAR __REG(0x80000e0c) /* Timer 3 Clear Register */
141
142/* Timer Control register bits */
143#define TIMER_CTRL_ENABLE (1 << 7) /* Enable (Start Timer) */
144#define TIMER_CTRL_PERIODIC (1 << 6) /* Periodic Running Mode */
145#define TIMER_CTRL_FREE_RUNNING (0 << 6) /* Normal Running Mode */
146#define TIMER_CTRL_CLKSEL_508K (1 << 3) /* 508KHz Clock select (Timer 1, 2) */
147#define TIMER_CTRL_CLKSEL_2K (0 << 3) /* 2KHz Clock Select (Timer 1, 2) */
148
149/* Power and State Control */
150#define POWER_BASE __REG(0x80000400)
151#define POWER_PWRSR __REG(0x80000400) /* Power Status Register */
152#define POWER_PWRCNT __REG(0x80000404) /* Power/Clock control */
153#define POWER_HALT __REG(0x80000408) /* Power Idle Mode */
154#define POWER_STDBY __REG(0x8000040c) /* Power Standby Mode */
155#define POWER_BLEOI __REG(0x80000410) /* Battery Low End of Interrupt */
156#define POWER_MCEOI __REG(0x80000414) /* Media Changed EoI */
157#define POWER_TEOI __REG(0x80000418) /* Tick EoI */
158#define POWER_STFCLR __REG(0x8000041c) /* NbFlg, RSTFlg, PFFlg, CLDFlg Clear */
159#define POWER_CLKSET __REG(0x80000420) /* Clock Speed Control */
160
161/* GPIO Registers */
162#define AAEC_GPIO_PHYS 0x80000e00
163
164#define AAEC_GPIO_PADR __REG(AAEC_GPIO_PHYS + 0x00)
165#define AAEC_GPIO_PBDR __REG(AAEC_GPIO_PHYS + 0x04)
166#define AAEC_GPIO_PCDR __REG(AAEC_GPIO_PHYS + 0x08)
167#define AAEC_GPIO_PDDR __REG(AAEC_GPIO_PHYS + 0x0c)
168#define AAEC_GPIO_PADDR __REG(AAEC_GPIO_PHYS + 0x10)
169#define AAEC_GPIO_PBDDR __REG(AAEC_GPIO_PHYS + 0x14)
170#define AAEC_GPIO_PCDDR __REG(AAEC_GPIO_PHYS + 0x18)
171#define AAEC_GPIO_PDDDR __REG(AAEC_GPIO_PHYS + 0x1c)
172#define AAEC_GPIO_PEDR __REG(AAEC_GPIO_PHYS + 0x20)
173#define AAEC_GPIO_PEDDR __REG(AAEC_GPIO_PHYS + 0x24)
174#define AAEC_GPIO_KSCAN __REG(AAEC_GPIO_PHYS + 0x28)
175#define AAEC_GPIO_PINMUX __REG(AAEC_GPIO_PHYS + 0x2c)
176#define AAEC_GPIO_PFDR __REG(AAEC_GPIO_PHYS + 0x30)
177#define AAEC_GPIO_PFDDR __REG(AAEC_GPIO_PHYS + 0x34)
178#define AAEC_GPIO_PGDR __REG(AAEC_GPIO_PHYS + 0x38)
179#define AAEC_GPIO_PGDDR __REG(AAEC_GPIO_PHYS + 0x3c)
180#define AAEC_GPIO_PHDR __REG(AAEC_GPIO_PHYS + 0x40)
181#define AAEC_GPIO_PHDDR __REG(AAEC_GPIO_PHYS + 0x44)
182#define AAEC_GPIO_RAZ __REG(AAEC_GPIO_PHYS + 0x48)
183#define AAEC_GPIO_INTTYPE1 __REG(AAEC_GPIO_PHYS + 0x4c)
184#define AAEC_GPIO_INTTYPE2 __REG(AAEC_GPIO_PHYS + 0x50)
185#define AAEC_GPIO_FEOI __REG(AAEC_GPIO_PHYS + 0x54)
186#define AAEC_GPIO_INTEN __REG(AAEC_GPIO_PHYS + 0x58)
187#define AAEC_GPIO_INTSTATUS __REG(AAEC_GPIO_PHYS + 0x5c)
188#define AAEC_GPIO_RAWINTSTATUS __REG(AAEC_GPIO_PHYS + 0x60)
189#define AAEC_GPIO_DB __REG(AAEC_GPIO_PHYS + 0x64)
190#define AAEC_GPIO_PAPINDR __REG(AAEC_GPIO_PHYS + 0x68)
191#define AAEC_GPIO_PBPINDR __REG(AAEC_GPIO_PHYS + 0x6c)
192#define AAEC_GPIO_PCPINDR __REG(AAEC_GPIO_PHYS + 0x70)
193#define AAEC_GPIO_PDPINDR __REG(AAEC_GPIO_PHYS + 0x74)
194#define AAEC_GPIO_PEPINDR __REG(AAEC_GPIO_PHYS + 0x78)
195#define AAEC_GPIO_PFPINDR __REG(AAEC_GPIO_PHYS + 0x7c)
196#define AAEC_GPIO_PGPINDR __REG(AAEC_GPIO_PHYS + 0x80)
197#define AAEC_GPIO_PHPINDR __REG(AAEC_GPIO_PHYS + 0x84)
198
199#define AAEC_GPIO_PINMUX_PE0CON (1 << 0)
200#define AAEC_GPIO_PINMUX_PD0CON (1 << 1)
201#define AAEC_GPIO_PINMUX_CODECON (1 << 2)
202#define AAEC_GPIO_PINMUX_UART3CON (1 << 3)
203
204/* LCD Controller */
205#define AAEC_CLCD_PHYS 0x80003000
206
207#endif /* __ARM_ARCH_AAEC2000_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-17 21:22:46 -0500