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-rw-r--r--include/acpi/actbl71.h148
1 files changed, 69 insertions, 79 deletions
diff --git a/include/acpi/actbl71.h b/include/acpi/actbl71.h
index 7b4fb44261f3..10ac05bb36bc 100644
--- a/include/acpi/actbl71.h
+++ b/include/acpi/actbl71.h
@@ -27,7 +27,6 @@
27#ifndef __ACTBL71_H__ 27#ifndef __ACTBL71_H__
28#define __ACTBL71_H__ 28#define __ACTBL71_H__
29 29
30
31/* 0.71 FADT address_space data item bitmasks defines */ 30/* 0.71 FADT address_space data item bitmasks defines */
32/* If the associated bit is zero then it is in memory space else in io space */ 31/* If the associated bit is zero then it is in memory space else in io space */
33 32
@@ -40,105 +39,96 @@
40 39
41/* Only for clarity in declarations */ 40/* Only for clarity in declarations */
42 41
43typedef u64 IO_ADDRESS; 42typedef u64 IO_ADDRESS;
44
45 43
46#pragma pack(1) 44#pragma pack(1)
47struct /* Root System Descriptor Pointer */ 45struct { /* Root System Descriptor Pointer */
48{ 46 NATIVE_CHAR signature[8]; /* contains "RSD PTR " */
49 NATIVE_CHAR signature [8]; /* contains "RSD PTR " */ 47 u8 checksum; /* to make sum of struct == 0 */
50 u8 checksum; /* to make sum of struct == 0 */ 48 NATIVE_CHAR oem_id[6]; /* OEM identification */
51 NATIVE_CHAR oem_id [6]; /* OEM identification */ 49 u8 reserved; /* Must be 0 for 1.0, 2 for 2.0 */
52 u8 reserved; /* Must be 0 for 1.0, 2 for 2.0 */ 50 u64 rsdt_physical_address; /* 64-bit physical address of RSDT */
53 u64 rsdt_physical_address; /* 64-bit physical address of RSDT */
54}; 51};
55 52
56
57/*****************************************/ 53/*****************************************/
58/* IA64 Extensions to ACPI Spec Rev 0.71 */ 54/* IA64 Extensions to ACPI Spec Rev 0.71 */
59/* for the Root System Description Table */ 55/* for the Root System Description Table */
60/*****************************************/ 56/*****************************************/
61struct 57struct {
62{ 58 struct acpi_table_header header; /* Table header */
63 struct acpi_table_header header; /* Table header */ 59 u32 reserved_pad; /* IA64 alignment, must be 0 */
64 u32 reserved_pad; /* IA64 alignment, must be 0 */ 60 u64 table_offset_entry[1]; /* Array of pointers to other */
65 u64 table_offset_entry [1]; /* Array of pointers to other */ 61 /* tables' headers */
66 /* tables' headers */
67}; 62};
68 63
69
70/*******************************************/ 64/*******************************************/
71/* IA64 Extensions to ACPI Spec Rev 0.71 */ 65/* IA64 Extensions to ACPI Spec Rev 0.71 */
72/* for the Firmware ACPI Control Structure */ 66/* for the Firmware ACPI Control Structure */
73/*******************************************/ 67/*******************************************/
74struct 68struct {
75{ 69 NATIVE_CHAR signature[4]; /* signature "FACS" */
76 NATIVE_CHAR signature[4]; /* signature "FACS" */ 70 u32 length; /* length of structure, in bytes */
77 u32 length; /* length of structure, in bytes */ 71 u32 hardware_signature; /* hardware configuration signature */
78 u32 hardware_signature; /* hardware configuration signature */ 72 u32 reserved4; /* must be 0 */
79 u32 reserved4; /* must be 0 */ 73 u64 firmware_waking_vector; /* ACPI OS waking vector */
80 u64 firmware_waking_vector; /* ACPI OS waking vector */ 74 u64 global_lock; /* Global Lock */
81 u64 global_lock; /* Global Lock */ 75 u32 S4bios_f:1; /* Indicates if S4BIOS support is present */
82 u32 S4bios_f : 1; /* Indicates if S4BIOS support is present */ 76 u32 reserved1:31; /* must be 0 */
83 u32 reserved1 : 31; /* must be 0 */ 77 u8 reserved3[28]; /* reserved - must be zero */
84 u8 reserved3 [28]; /* reserved - must be zero */
85}; 78};
86 79
87
88/******************************************/ 80/******************************************/
89/* IA64 Extensions to ACPI Spec Rev 0.71 */ 81/* IA64 Extensions to ACPI Spec Rev 0.71 */
90/* for the Fixed ACPI Description Table */ 82/* for the Fixed ACPI Description Table */
91/******************************************/ 83/******************************************/
92struct 84struct {
93{ 85 struct acpi_table_header header; /* table header */
94 struct acpi_table_header header; /* table header */ 86 u32 reserved_pad; /* IA64 alignment, must be 0 */
95 u32 reserved_pad; /* IA64 alignment, must be 0 */ 87 u64 firmware_ctrl; /* 64-bit Physical address of FACS */
96 u64 firmware_ctrl; /* 64-bit Physical address of FACS */ 88 u64 dsdt; /* 64-bit Physical address of DSDT */
97 u64 dsdt; /* 64-bit Physical address of DSDT */ 89 u8 model; /* System Interrupt Model */
98 u8 model; /* System Interrupt Model */ 90 u8 address_space; /* Address Space Bitmask */
99 u8 address_space; /* Address Space Bitmask */ 91 u16 sci_int; /* System vector of SCI interrupt */
100 u16 sci_int; /* System vector of SCI interrupt */ 92 u8 acpi_enable; /* value to write to smi_cmd to enable ACPI */
101 u8 acpi_enable; /* value to write to smi_cmd to enable ACPI */ 93 u8 acpi_disable; /* value to write to smi_cmd to disable ACPI */
102 u8 acpi_disable; /* value to write to smi_cmd to disable ACPI */ 94 u8 S4bios_req; /* Value to write to SMI CMD to enter S4BIOS state */
103 u8 S4bios_req; /* Value to write to SMI CMD to enter S4BIOS state */ 95 u8 reserved2; /* reserved - must be zero */
104 u8 reserved2; /* reserved - must be zero */ 96 u64 smi_cmd; /* Port address of SMI command port */
105 u64 smi_cmd; /* Port address of SMI command port */ 97 u64 pm1a_evt_blk; /* Port address of Power Mgt 1a acpi_event Reg Blk */
106 u64 pm1a_evt_blk; /* Port address of Power Mgt 1a acpi_event Reg Blk */ 98 u64 pm1b_evt_blk; /* Port address of Power Mgt 1b acpi_event Reg Blk */
107 u64 pm1b_evt_blk; /* Port address of Power Mgt 1b acpi_event Reg Blk */ 99 u64 pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */
108 u64 pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */ 100 u64 pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */
109 u64 pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */ 101 u64 pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */
110 u64 pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */ 102 u64 pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */
111 u64 pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */ 103 u64 gpe0_blk; /* Port addr of General Purpose acpi_event 0 Reg Blk */
112 u64 gpe0_blk; /* Port addr of General Purpose acpi_event 0 Reg Blk */ 104 u64 gpe1_blk; /* Port addr of General Purpose acpi_event 1 Reg Blk */
113 u64 gpe1_blk; /* Port addr of General Purpose acpi_event 1 Reg Blk */ 105 u8 pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */
114 u8 pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */ 106 u8 pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */
115 u8 pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */ 107 u8 pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */
116 u8 pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */ 108 u8 pm_tm_len; /* Byte Length of ports at pm_tm_blk */
117 u8 pm_tm_len; /* Byte Length of ports at pm_tm_blk */ 109 u8 gpe0_blk_len; /* Byte Length of ports at gpe0_blk */
118 u8 gpe0_blk_len; /* Byte Length of ports at gpe0_blk */ 110 u8 gpe1_blk_len; /* Byte Length of ports at gpe1_blk */
119 u8 gpe1_blk_len; /* Byte Length of ports at gpe1_blk */ 111 u8 gpe1_base; /* offset in gpe model where gpe1 events start */
120 u8 gpe1_base; /* offset in gpe model where gpe1 events start */ 112 u8 reserved3; /* reserved */
121 u8 reserved3; /* reserved */ 113 u16 plvl2_lat; /* worst case HW latency to enter/exit C2 state */
122 u16 plvl2_lat; /* worst case HW latency to enter/exit C2 state */ 114 u16 plvl3_lat; /* worst case HW latency to enter/exit C3 state */
123 u16 plvl3_lat; /* worst case HW latency to enter/exit C3 state */ 115 u8 day_alrm; /* index to day-of-month alarm in RTC CMOS RAM */
124 u8 day_alrm; /* index to day-of-month alarm in RTC CMOS RAM */ 116 u8 mon_alrm; /* index to month-of-year alarm in RTC CMOS RAM */
125 u8 mon_alrm; /* index to month-of-year alarm in RTC CMOS RAM */ 117 u8 century; /* index to century in RTC CMOS RAM */
126 u8 century; /* index to century in RTC CMOS RAM */ 118 u8 reserved4; /* reserved */
127 u8 reserved4; /* reserved */ 119 u32 flush_cash:1; /* PAL_FLUSH_CACHE is correctly supported */
128 u32 flush_cash : 1; /* PAL_FLUSH_CACHE is correctly supported */ 120 u32 reserved5:1; /* reserved - must be zero */
129 u32 reserved5 : 1; /* reserved - must be zero */ 121 u32 proc_c1:1; /* all processors support C1 state */
130 u32 proc_c1 : 1; /* all processors support C1 state */ 122 u32 plvl2_up:1; /* C2 state works on MP system */
131 u32 plvl2_up : 1; /* C2 state works on MP system */ 123 u32 pwr_button:1; /* Power button is handled as a generic feature */
132 u32 pwr_button : 1; /* Power button is handled as a generic feature */ 124 u32 sleep_button:1; /* Sleep button is handled as a generic feature, or not present */
133 u32 sleep_button : 1; /* Sleep button is handled as a generic feature, or not present */ 125 u32 fixed_rTC:1; /* RTC wakeup stat not in fixed register space */
134 u32 fixed_rTC : 1; /* RTC wakeup stat not in fixed register space */ 126 u32 rtcs4:1; /* RTC wakeup stat not possible from S4 */
135 u32 rtcs4 : 1; /* RTC wakeup stat not possible from S4 */ 127 u32 tmr_val_ext:1; /* tmr_val is 32 bits */
136 u32 tmr_val_ext : 1; /* tmr_val is 32 bits */ 128 u32 dock_cap:1; /* Supports Docking */
137 u32 dock_cap : 1; /* Supports Docking */ 129 u32 reserved6:22; /* reserved - must be zero */
138 u32 reserved6 : 22; /* reserved - must be zero */
139}; 130};
140 131
141#pragma pack() 132#pragma pack()
142 133
143#endif /* __ACTBL71_H__ */ 134#endif /* __ACTBL71_H__ */
144
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-12 23:54:54 -0500