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-rw-r--r--drivers/clk/samsung/clk-s3c64xx.c4
-rw-r--r--drivers/dma/dmaengine.c35
-rw-r--r--drivers/dma/of-dma.c15
-rw-r--r--drivers/dma/pl330.c1
-rw-r--r--drivers/mfd/twl-core.c190
-rw-r--r--drivers/mfd/twl6040.c92
-rw-r--r--drivers/mfd/wm5110-tables.c145
-rw-r--r--drivers/spi/Kconfig2
8 files changed, 437 insertions, 47 deletions
diff --git a/drivers/clk/samsung/clk-s3c64xx.c b/drivers/clk/samsung/clk-s3c64xx.c
index 7d2c84265947..8e27aee6887e 100644
--- a/drivers/clk/samsung/clk-s3c64xx.c
+++ b/drivers/clk/samsung/clk-s3c64xx.c
@@ -331,8 +331,8 @@ static struct samsung_clock_alias s3c64xx_clock_aliases[] = {
331 ALIAS(HCLK_HSMMC1, "s3c-sdhci.1", "mmc_busclk.0"), 331 ALIAS(HCLK_HSMMC1, "s3c-sdhci.1", "mmc_busclk.0"),
332 ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "hsmmc"), 332 ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "hsmmc"),
333 ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "mmc_busclk.0"), 333 ALIAS(HCLK_HSMMC0, "s3c-sdhci.0", "mmc_busclk.0"),
334 ALIAS(HCLK_DMA1, NULL, "dma1"), 334 ALIAS(HCLK_DMA1, "dma-pl080s.1", "apb_pclk"),
335 ALIAS(HCLK_DMA0, NULL, "dma0"), 335 ALIAS(HCLK_DMA0, "dma-pl080s.0", "apb_pclk"),
336 ALIAS(HCLK_CAMIF, "s3c-camif", "camif"), 336 ALIAS(HCLK_CAMIF, "s3c-camif", "camif"),
337 ALIAS(HCLK_LCD, "s3c-fb", "lcd"), 337 ALIAS(HCLK_LCD, "s3c-fb", "lcd"),
338 ALIAS(PCLK_SPI1, "s3c6410-spi.1", "spi"), 338 ALIAS(PCLK_SPI1, "s3c6410-spi.1", "spi"),
diff --git a/drivers/dma/dmaengine.c b/drivers/dma/dmaengine.c
index ef63b9058f3c..92caad629d99 100644
--- a/drivers/dma/dmaengine.c
+++ b/drivers/dma/dmaengine.c
@@ -540,6 +540,8 @@ EXPORT_SYMBOL_GPL(dma_get_slave_channel);
540 * @mask: capabilities that the channel must satisfy 540 * @mask: capabilities that the channel must satisfy
541 * @fn: optional callback to disposition available channels 541 * @fn: optional callback to disposition available channels
542 * @fn_param: opaque parameter to pass to dma_filter_fn 542 * @fn_param: opaque parameter to pass to dma_filter_fn
543 *
544 * Returns pointer to appropriate DMA channel on success or NULL.
543 */ 545 */
544struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask, 546struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
545 dma_filter_fn fn, void *fn_param) 547 dma_filter_fn fn, void *fn_param)
@@ -591,18 +593,43 @@ EXPORT_SYMBOL_GPL(__dma_request_channel);
591 * dma_request_slave_channel - try to allocate an exclusive slave channel 593 * dma_request_slave_channel - try to allocate an exclusive slave channel
592 * @dev: pointer to client device structure 594 * @dev: pointer to client device structure
593 * @name: slave channel name 595 * @name: slave channel name
596 *
597 * Returns pointer to appropriate DMA channel on success or an error pointer.
594 */ 598 */
595struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name) 599struct dma_chan *dma_request_slave_channel_reason(struct device *dev,
600 const char *name)
596{ 601{
602 struct dma_chan *chan;
603
597 /* If device-tree is present get slave info from here */ 604 /* If device-tree is present get slave info from here */
598 if (dev->of_node) 605 if (dev->of_node)
599 return of_dma_request_slave_channel(dev->of_node, name); 606 return of_dma_request_slave_channel(dev->of_node, name);
600 607
601 /* If device was enumerated by ACPI get slave info from here */ 608 /* If device was enumerated by ACPI get slave info from here */
602 if (ACPI_HANDLE(dev)) 609 if (ACPI_HANDLE(dev)) {
603 return acpi_dma_request_slave_chan_by_name(dev, name); 610 chan = acpi_dma_request_slave_chan_by_name(dev, name);
611 if (chan)
612 return chan;
613 }
604 614
605 return NULL; 615 return ERR_PTR(-ENODEV);
616}
617EXPORT_SYMBOL_GPL(dma_request_slave_channel_reason);
618
619/**
620 * dma_request_slave_channel - try to allocate an exclusive slave channel
621 * @dev: pointer to client device structure
622 * @name: slave channel name
623 *
624 * Returns pointer to appropriate DMA channel on success or NULL.
625 */
626struct dma_chan *dma_request_slave_channel(struct device *dev,
627 const char *name)
628{
629 struct dma_chan *ch = dma_request_slave_channel_reason(dev, name);
630 if (IS_ERR(ch))
631 return NULL;
632 return ch;
606} 633}
607EXPORT_SYMBOL_GPL(dma_request_slave_channel); 634EXPORT_SYMBOL_GPL(dma_request_slave_channel);
608 635
diff --git a/drivers/dma/of-dma.c b/drivers/dma/of-dma.c
index 0b88dd3d05f4..e8fe9dc455f4 100644
--- a/drivers/dma/of-dma.c
+++ b/drivers/dma/of-dma.c
@@ -143,7 +143,7 @@ static int of_dma_match_channel(struct device_node *np, const char *name,
143 * @np: device node to get DMA request from 143 * @np: device node to get DMA request from
144 * @name: name of desired channel 144 * @name: name of desired channel
145 * 145 *
146 * Returns pointer to appropriate dma channel on success or NULL on error. 146 * Returns pointer to appropriate DMA channel on success or an error pointer.
147 */ 147 */
148struct dma_chan *of_dma_request_slave_channel(struct device_node *np, 148struct dma_chan *of_dma_request_slave_channel(struct device_node *np,
149 const char *name) 149 const char *name)
@@ -152,17 +152,18 @@ struct dma_chan *of_dma_request_slave_channel(struct device_node *np,
152 struct of_dma *ofdma; 152 struct of_dma *ofdma;
153 struct dma_chan *chan; 153 struct dma_chan *chan;
154 int count, i; 154 int count, i;
155 int ret_no_channel = -ENODEV;
155 156
156 if (!np || !name) { 157 if (!np || !name) {
157 pr_err("%s: not enough information provided\n", __func__); 158 pr_err("%s: not enough information provided\n", __func__);
158 return NULL; 159 return ERR_PTR(-ENODEV);
159 } 160 }
160 161
161 count = of_property_count_strings(np, "dma-names"); 162 count = of_property_count_strings(np, "dma-names");
162 if (count < 0) { 163 if (count < 0) {
163 pr_err("%s: dma-names property of node '%s' missing or empty\n", 164 pr_err("%s: dma-names property of node '%s' missing or empty\n",
164 __func__, np->full_name); 165 __func__, np->full_name);
165 return NULL; 166 return ERR_PTR(-ENODEV);
166 } 167 }
167 168
168 for (i = 0; i < count; i++) { 169 for (i = 0; i < count; i++) {
@@ -172,10 +173,12 @@ struct dma_chan *of_dma_request_slave_channel(struct device_node *np,
172 mutex_lock(&of_dma_lock); 173 mutex_lock(&of_dma_lock);
173 ofdma = of_dma_find_controller(&dma_spec); 174 ofdma = of_dma_find_controller(&dma_spec);
174 175
175 if (ofdma) 176 if (ofdma) {
176 chan = ofdma->of_dma_xlate(&dma_spec, ofdma); 177 chan = ofdma->of_dma_xlate(&dma_spec, ofdma);
177 else 178 } else {
179 ret_no_channel = -EPROBE_DEFER;
178 chan = NULL; 180 chan = NULL;
181 }
179 182
180 mutex_unlock(&of_dma_lock); 183 mutex_unlock(&of_dma_lock);
181 184
@@ -185,7 +188,7 @@ struct dma_chan *of_dma_request_slave_channel(struct device_node *np,
185 return chan; 188 return chan;
186 } 189 }
187 190
188 return NULL; 191 return ERR_PTR(ret_no_channel);
189} 192}
190 193
191/** 194/**
diff --git a/drivers/dma/pl330.c b/drivers/dma/pl330.c
index 536632f6479c..c90edecee463 100644
--- a/drivers/dma/pl330.c
+++ b/drivers/dma/pl330.c
@@ -2884,6 +2884,7 @@ static int pl330_dma_device_slave_caps(struct dma_chan *dchan,
2884 caps->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); 2884 caps->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
2885 caps->cmd_pause = false; 2885 caps->cmd_pause = false;
2886 caps->cmd_terminate = true; 2886 caps->cmd_terminate = true;
2887 caps->residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
2887 2888
2888 return 0; 2889 return 0;
2889} 2890}
diff --git a/drivers/mfd/twl-core.c b/drivers/mfd/twl-core.c
index 29473c2c95ae..6ef7685a4cf8 100644
--- a/drivers/mfd/twl-core.c
+++ b/drivers/mfd/twl-core.c
@@ -47,6 +47,9 @@
47#include <linux/i2c.h> 47#include <linux/i2c.h>
48#include <linux/i2c/twl.h> 48#include <linux/i2c/twl.h>
49 49
50/* Register descriptions for audio */
51#include <linux/mfd/twl4030-audio.h>
52
50#include "twl-core.h" 53#include "twl-core.h"
51 54
52/* 55/*
@@ -200,6 +203,105 @@ static struct twl_mapping twl4030_map[] = {
200 { 2, TWL5031_BASEADD_INTERRUPTS }, 203 { 2, TWL5031_BASEADD_INTERRUPTS },
201}; 204};
202 205
206static struct reg_default twl4030_49_defaults[] = {
207 /* Audio Registers */
208 { 0x01, 0x00}, /* CODEC_MODE */
209 { 0x02, 0x00}, /* OPTION */
210 /* 0x03 Unused */
211 { 0x04, 0x00}, /* MICBIAS_CTL */
212 { 0x05, 0x00}, /* ANAMICL */
213 { 0x06, 0x00}, /* ANAMICR */
214 { 0x07, 0x00}, /* AVADC_CTL */
215 { 0x08, 0x00}, /* ADCMICSEL */
216 { 0x09, 0x00}, /* DIGMIXING */
217 { 0x0a, 0x0f}, /* ATXL1PGA */
218 { 0x0b, 0x0f}, /* ATXR1PGA */
219 { 0x0c, 0x0f}, /* AVTXL2PGA */
220 { 0x0d, 0x0f}, /* AVTXR2PGA */
221 { 0x0e, 0x00}, /* AUDIO_IF */
222 { 0x0f, 0x00}, /* VOICE_IF */
223 { 0x10, 0x3f}, /* ARXR1PGA */
224 { 0x11, 0x3f}, /* ARXL1PGA */
225 { 0x12, 0x3f}, /* ARXR2PGA */
226 { 0x13, 0x3f}, /* ARXL2PGA */
227 { 0x14, 0x25}, /* VRXPGA */
228 { 0x15, 0x00}, /* VSTPGA */
229 { 0x16, 0x00}, /* VRX2ARXPGA */
230 { 0x17, 0x00}, /* AVDAC_CTL */
231 { 0x18, 0x00}, /* ARX2VTXPGA */
232 { 0x19, 0x32}, /* ARXL1_APGA_CTL*/
233 { 0x1a, 0x32}, /* ARXR1_APGA_CTL*/
234 { 0x1b, 0x32}, /* ARXL2_APGA_CTL*/
235 { 0x1c, 0x32}, /* ARXR2_APGA_CTL*/
236 { 0x1d, 0x00}, /* ATX2ARXPGA */
237 { 0x1e, 0x00}, /* BT_IF */
238 { 0x1f, 0x55}, /* BTPGA */
239 { 0x20, 0x00}, /* BTSTPGA */
240 { 0x21, 0x00}, /* EAR_CTL */
241 { 0x22, 0x00}, /* HS_SEL */
242 { 0x23, 0x00}, /* HS_GAIN_SET */
243 { 0x24, 0x00}, /* HS_POPN_SET */
244 { 0x25, 0x00}, /* PREDL_CTL */
245 { 0x26, 0x00}, /* PREDR_CTL */
246 { 0x27, 0x00}, /* PRECKL_CTL */
247 { 0x28, 0x00}, /* PRECKR_CTL */
248 { 0x29, 0x00}, /* HFL_CTL */
249 { 0x2a, 0x00}, /* HFR_CTL */
250 { 0x2b, 0x05}, /* ALC_CTL */
251 { 0x2c, 0x00}, /* ALC_SET1 */
252 { 0x2d, 0x00}, /* ALC_SET2 */
253 { 0x2e, 0x00}, /* BOOST_CTL */
254 { 0x2f, 0x00}, /* SOFTVOL_CTL */
255 { 0x30, 0x13}, /* DTMF_FREQSEL */
256 { 0x31, 0x00}, /* DTMF_TONEXT1H */
257 { 0x32, 0x00}, /* DTMF_TONEXT1L */
258 { 0x33, 0x00}, /* DTMF_TONEXT2H */
259 { 0x34, 0x00}, /* DTMF_TONEXT2L */
260 { 0x35, 0x79}, /* DTMF_TONOFF */
261 { 0x36, 0x11}, /* DTMF_WANONOFF */
262 { 0x37, 0x00}, /* I2S_RX_SCRAMBLE_H */
263 { 0x38, 0x00}, /* I2S_RX_SCRAMBLE_M */
264 { 0x39, 0x00}, /* I2S_RX_SCRAMBLE_L */
265 { 0x3a, 0x06}, /* APLL_CTL */
266 { 0x3b, 0x00}, /* DTMF_CTL */
267 { 0x3c, 0x44}, /* DTMF_PGA_CTL2 (0x3C) */
268 { 0x3d, 0x69}, /* DTMF_PGA_CTL1 (0x3D) */
269 { 0x3e, 0x00}, /* MISC_SET_1 */
270 { 0x3f, 0x00}, /* PCMBTMUX */
271 /* 0x40 - 0x42 Unused */
272 { 0x43, 0x00}, /* RX_PATH_SEL */
273 { 0x44, 0x32}, /* VDL_APGA_CTL */
274 { 0x45, 0x00}, /* VIBRA_CTL */
275 { 0x46, 0x00}, /* VIBRA_SET */
276 { 0x47, 0x00}, /* VIBRA_PWM_SET */
277 { 0x48, 0x00}, /* ANAMIC_GAIN */
278 { 0x49, 0x00}, /* MISC_SET_2 */
279 /* End of Audio Registers */
280};
281
282static bool twl4030_49_nop_reg(struct device *dev, unsigned int reg)
283{
284 switch (reg) {
285 case 0:
286 case 3:
287 case 40:
288 case 41:
289 case 42:
290 return false;
291 default:
292 return true;
293 }
294}
295
296static const struct regmap_range twl4030_49_volatile_ranges[] = {
297 regmap_reg_range(TWL4030_BASEADD_TEST, 0xff),
298};
299
300static const struct regmap_access_table twl4030_49_volatile_table = {
301 .yes_ranges = twl4030_49_volatile_ranges,
302 .n_yes_ranges = ARRAY_SIZE(twl4030_49_volatile_ranges),
303};
304
203static struct regmap_config twl4030_regmap_config[4] = { 305static struct regmap_config twl4030_regmap_config[4] = {
204 { 306 {
205 /* Address 0x48 */ 307 /* Address 0x48 */
@@ -212,6 +314,15 @@ static struct regmap_config twl4030_regmap_config[4] = {
212 .reg_bits = 8, 314 .reg_bits = 8,
213 .val_bits = 8, 315 .val_bits = 8,
214 .max_register = 0xff, 316 .max_register = 0xff,
317
318 .readable_reg = twl4030_49_nop_reg,
319 .writeable_reg = twl4030_49_nop_reg,
320
321 .volatile_table = &twl4030_49_volatile_table,
322
323 .reg_defaults = twl4030_49_defaults,
324 .num_reg_defaults = ARRAY_SIZE(twl4030_49_defaults),
325 .cache_type = REGCACHE_RBTREE,
215 }, 326 },
216 { 327 {
217 /* Address 0x4a */ 328 /* Address 0x4a */
@@ -302,35 +413,50 @@ unsigned int twl_rev(void)
302EXPORT_SYMBOL(twl_rev); 413EXPORT_SYMBOL(twl_rev);
303 414
304/** 415/**
305 * twl_i2c_write - Writes a n bit register in TWL4030/TWL5030/TWL60X0 416 * twl_get_regmap - Get the regmap associated with the given module
306 * @mod_no: module number 417 * @mod_no: module number
307 * @value: an array of num_bytes+1 containing data to write
308 * @reg: register address (just offset will do)
309 * @num_bytes: number of bytes to transfer
310 * 418 *
311 * Returns the result of operation - 0 is success 419 * Returns the regmap pointer or NULL in case of failure.
312 */ 420 */
313int twl_i2c_write(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes) 421static struct regmap *twl_get_regmap(u8 mod_no)
314{ 422{
315 int ret;
316 int sid; 423 int sid;
317 struct twl_client *twl; 424 struct twl_client *twl;
318 425
319 if (unlikely(!twl_priv || !twl_priv->ready)) { 426 if (unlikely(!twl_priv || !twl_priv->ready)) {
320 pr_err("%s: not initialized\n", DRIVER_NAME); 427 pr_err("%s: not initialized\n", DRIVER_NAME);
321 return -EPERM; 428 return NULL;
322 } 429 }
323 if (unlikely(mod_no >= twl_get_last_module())) { 430 if (unlikely(mod_no >= twl_get_last_module())) {
324 pr_err("%s: invalid module number %d\n", DRIVER_NAME, mod_no); 431 pr_err("%s: invalid module number %d\n", DRIVER_NAME, mod_no);
325 return -EPERM; 432 return NULL;
326 } 433 }
327 434
328 sid = twl_priv->twl_map[mod_no].sid; 435 sid = twl_priv->twl_map[mod_no].sid;
329 twl = &twl_priv->twl_modules[sid]; 436 twl = &twl_priv->twl_modules[sid];
330 437
331 ret = regmap_bulk_write(twl->regmap, 438 return twl->regmap;
332 twl_priv->twl_map[mod_no].base + reg, value, 439}
333 num_bytes); 440
441/**
442 * twl_i2c_write - Writes a n bit register in TWL4030/TWL5030/TWL60X0
443 * @mod_no: module number
444 * @value: an array of num_bytes+1 containing data to write
445 * @reg: register address (just offset will do)
446 * @num_bytes: number of bytes to transfer
447 *
448 * Returns the result of operation - 0 is success
449 */
450int twl_i2c_write(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes)
451{
452 struct regmap *regmap = twl_get_regmap(mod_no);
453 int ret;
454
455 if (!regmap)
456 return -EPERM;
457
458 ret = regmap_bulk_write(regmap, twl_priv->twl_map[mod_no].base + reg,
459 value, num_bytes);
334 460
335 if (ret) 461 if (ret)
336 pr_err("%s: Write failed (mod %d, reg 0x%02x count %d)\n", 462 pr_err("%s: Write failed (mod %d, reg 0x%02x count %d)\n",
@@ -351,25 +477,14 @@ EXPORT_SYMBOL(twl_i2c_write);
351 */ 477 */
352int twl_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes) 478int twl_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes)
353{ 479{
480 struct regmap *regmap = twl_get_regmap(mod_no);
354 int ret; 481 int ret;
355 int sid;
356 struct twl_client *twl;
357 482
358 if (unlikely(!twl_priv || !twl_priv->ready)) { 483 if (!regmap)
359 pr_err("%s: not initialized\n", DRIVER_NAME);
360 return -EPERM;
361 }
362 if (unlikely(mod_no >= twl_get_last_module())) {
363 pr_err("%s: invalid module number %d\n", DRIVER_NAME, mod_no);
364 return -EPERM; 484 return -EPERM;
365 }
366
367 sid = twl_priv->twl_map[mod_no].sid;
368 twl = &twl_priv->twl_modules[sid];
369 485
370 ret = regmap_bulk_read(twl->regmap, 486 ret = regmap_bulk_read(regmap, twl_priv->twl_map[mod_no].base + reg,
371 twl_priv->twl_map[mod_no].base + reg, value, 487 value, num_bytes);
372 num_bytes);
373 488
374 if (ret) 489 if (ret)
375 pr_err("%s: Read failed (mod %d, reg 0x%02x count %d)\n", 490 pr_err("%s: Read failed (mod %d, reg 0x%02x count %d)\n",
@@ -379,6 +494,27 @@ int twl_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes)
379} 494}
380EXPORT_SYMBOL(twl_i2c_read); 495EXPORT_SYMBOL(twl_i2c_read);
381 496
497/**
498 * twl_regcache_bypass - Configure the regcache bypass for the regmap associated
499 * with the module
500 * @mod_no: module number
501 * @enable: Regcache bypass state
502 *
503 * Returns 0 else failure.
504 */
505int twl_set_regcache_bypass(u8 mod_no, bool enable)
506{
507 struct regmap *regmap = twl_get_regmap(mod_no);
508
509 if (!regmap)
510 return -EPERM;
511
512 regcache_cache_bypass(regmap, enable);
513
514 return 0;
515}
516EXPORT_SYMBOL(twl_set_regcache_bypass);
517
382/*----------------------------------------------------------------------*/ 518/*----------------------------------------------------------------------*/
383 519
384/** 520/**
diff --git a/drivers/mfd/twl6040.c b/drivers/mfd/twl6040.c
index 0779d5ab9ab1..51b6df1a7949 100644
--- a/drivers/mfd/twl6040.c
+++ b/drivers/mfd/twl6040.c
@@ -44,6 +44,54 @@
44#define VIBRACTRL_MEMBER(reg) ((reg == TWL6040_REG_VIBCTLL) ? 0 : 1) 44#define VIBRACTRL_MEMBER(reg) ((reg == TWL6040_REG_VIBCTLL) ? 0 : 1)
45#define TWL6040_NUM_SUPPLIES (2) 45#define TWL6040_NUM_SUPPLIES (2)
46 46
47static struct reg_default twl6040_defaults[] = {
48 { 0x01, 0x4B }, /* REG_ASICID (ro) */
49 { 0x02, 0x00 }, /* REG_ASICREV (ro) */
50 { 0x03, 0x00 }, /* REG_INTID */
51 { 0x04, 0x00 }, /* REG_INTMR */
52 { 0x05, 0x00 }, /* REG_NCPCTRL */
53 { 0x06, 0x00 }, /* REG_LDOCTL */
54 { 0x07, 0x60 }, /* REG_HPPLLCTL */
55 { 0x08, 0x00 }, /* REG_LPPLLCTL */
56 { 0x09, 0x4A }, /* REG_LPPLLDIV */
57 { 0x0A, 0x00 }, /* REG_AMICBCTL */
58 { 0x0B, 0x00 }, /* REG_DMICBCTL */
59 { 0x0C, 0x00 }, /* REG_MICLCTL */
60 { 0x0D, 0x00 }, /* REG_MICRCTL */
61 { 0x0E, 0x00 }, /* REG_MICGAIN */
62 { 0x0F, 0x1B }, /* REG_LINEGAIN */
63 { 0x10, 0x00 }, /* REG_HSLCTL */
64 { 0x11, 0x00 }, /* REG_HSRCTL */
65 { 0x12, 0x00 }, /* REG_HSGAIN */
66 { 0x13, 0x00 }, /* REG_EARCTL */
67 { 0x14, 0x00 }, /* REG_HFLCTL */
68 { 0x15, 0x00 }, /* REG_HFLGAIN */
69 { 0x16, 0x00 }, /* REG_HFRCTL */
70 { 0x17, 0x00 }, /* REG_HFRGAIN */
71 { 0x18, 0x00 }, /* REG_VIBCTLL */
72 { 0x19, 0x00 }, /* REG_VIBDATL */
73 { 0x1A, 0x00 }, /* REG_VIBCTLR */
74 { 0x1B, 0x00 }, /* REG_VIBDATR */
75 { 0x1C, 0x00 }, /* REG_HKCTL1 */
76 { 0x1D, 0x00 }, /* REG_HKCTL2 */
77 { 0x1E, 0x00 }, /* REG_GPOCTL */
78 { 0x1F, 0x00 }, /* REG_ALB */
79 { 0x20, 0x00 }, /* REG_DLB */
80 /* 0x28, REG_TRIM1 */
81 /* 0x29, REG_TRIM2 */
82 /* 0x2A, REG_TRIM3 */
83 /* 0x2B, REG_HSOTRIM */
84 /* 0x2C, REG_HFOTRIM */
85 { 0x2D, 0x08 }, /* REG_ACCCTL */
86 { 0x2E, 0x00 }, /* REG_STATUS (ro) */
87};
88
89struct reg_default twl6040_patch[] = {
90 /* Select I2C bus access to dual access registers */
91 { TWL6040_REG_ACCCTL, 0x09 },
92};
93
94
47static bool twl6040_has_vibra(struct device_node *node) 95static bool twl6040_has_vibra(struct device_node *node)
48{ 96{
49#ifdef CONFIG_OF 97#ifdef CONFIG_OF
@@ -238,6 +286,9 @@ int twl6040_power(struct twl6040 *twl6040, int on)
238 if (twl6040->power_count++) 286 if (twl6040->power_count++)
239 goto out; 287 goto out;
240 288
289 /* Allow writes to the chip */
290 regcache_cache_only(twl6040->regmap, false);
291
241 if (gpio_is_valid(twl6040->audpwron)) { 292 if (gpio_is_valid(twl6040->audpwron)) {
242 /* use automatic power-up sequence */ 293 /* use automatic power-up sequence */
243 ret = twl6040_power_up_automatic(twl6040); 294 ret = twl6040_power_up_automatic(twl6040);
@@ -253,6 +304,10 @@ int twl6040_power(struct twl6040 *twl6040, int on)
253 goto out; 304 goto out;
254 } 305 }
255 } 306 }
307
308 /* Sync with the HW */
309 regcache_sync(twl6040->regmap);
310
256 /* Default PLL configuration after power up */ 311 /* Default PLL configuration after power up */
257 twl6040->pll = TWL6040_SYSCLK_SEL_LPPLL; 312 twl6040->pll = TWL6040_SYSCLK_SEL_LPPLL;
258 twl6040->sysclk = 19200000; 313 twl6040->sysclk = 19200000;
@@ -279,6 +334,11 @@ int twl6040_power(struct twl6040 *twl6040, int on)
279 /* use manual power-down sequence */ 334 /* use manual power-down sequence */
280 twl6040_power_down_manual(twl6040); 335 twl6040_power_down_manual(twl6040);
281 } 336 }
337
338 /* Set regmap to cache only and mark it as dirty */
339 regcache_cache_only(twl6040->regmap, true);
340 regcache_mark_dirty(twl6040->regmap);
341
282 twl6040->sysclk = 0; 342 twl6040->sysclk = 0;
283 twl6040->mclk = 0; 343 twl6040->mclk = 0;
284 } 344 }
@@ -490,9 +550,24 @@ static bool twl6040_readable_reg(struct device *dev, unsigned int reg)
490static bool twl6040_volatile_reg(struct device *dev, unsigned int reg) 550static bool twl6040_volatile_reg(struct device *dev, unsigned int reg)
491{ 551{
492 switch (reg) { 552 switch (reg) {
493 case TWL6040_REG_VIBCTLL: 553 case TWL6040_REG_ASICID:
494 case TWL6040_REG_VIBCTLR: 554 case TWL6040_REG_ASICREV:
495 case TWL6040_REG_INTMR: 555 case TWL6040_REG_INTID:
556 case TWL6040_REG_LPPLLCTL:
557 case TWL6040_REG_HPPLLCTL:
558 case TWL6040_REG_STATUS:
559 return true;
560 default:
561 return false;
562 }
563}
564
565static bool twl6040_writeable_reg(struct device *dev, unsigned int reg)
566{
567 switch (reg) {
568 case TWL6040_REG_ASICID:
569 case TWL6040_REG_ASICREV:
570 case TWL6040_REG_STATUS:
496 return false; 571 return false;
497 default: 572 default:
498 return true; 573 return true;
@@ -502,10 +577,15 @@ static bool twl6040_volatile_reg(struct device *dev, unsigned int reg)
502static struct regmap_config twl6040_regmap_config = { 577static struct regmap_config twl6040_regmap_config = {
503 .reg_bits = 8, 578 .reg_bits = 8,
504 .val_bits = 8, 579 .val_bits = 8,
580
581 .reg_defaults = twl6040_defaults,
582 .num_reg_defaults = ARRAY_SIZE(twl6040_defaults),
583
505 .max_register = TWL6040_REG_STATUS, /* 0x2e */ 584 .max_register = TWL6040_REG_STATUS, /* 0x2e */
506 585
507 .readable_reg = twl6040_readable_reg, 586 .readable_reg = twl6040_readable_reg,
508 .volatile_reg = twl6040_volatile_reg, 587 .volatile_reg = twl6040_volatile_reg,
588 .writeable_reg = twl6040_writeable_reg,
509 589
510 .cache_type = REGCACHE_RBTREE, 590 .cache_type = REGCACHE_RBTREE,
511}; 591};
@@ -624,6 +704,8 @@ static int twl6040_probe(struct i2c_client *client,
624 704
625 /* dual-access registers controlled by I2C only */ 705 /* dual-access registers controlled by I2C only */
626 twl6040_set_bits(twl6040, TWL6040_REG_ACCCTL, TWL6040_I2CSEL); 706 twl6040_set_bits(twl6040, TWL6040_REG_ACCCTL, TWL6040_I2CSEL);
707 regmap_register_patch(twl6040->regmap, twl6040_patch,
708 ARRAY_SIZE(twl6040_patch));
627 709
628 /* 710 /*
629 * The main functionality of twl6040 to provide audio on OMAP4+ systems. 711 * The main functionality of twl6040 to provide audio on OMAP4+ systems.
@@ -656,6 +738,10 @@ static int twl6040_probe(struct i2c_client *client,
656 cell->name = "twl6040-gpo"; 738 cell->name = "twl6040-gpo";
657 children++; 739 children++;
658 740
741 /* The chip is powered down so mark regmap to cache only and dirty */
742 regcache_cache_only(twl6040->regmap, true);
743 regcache_mark_dirty(twl6040->regmap);
744
659 ret = mfd_add_devices(&client->dev, -1, twl6040->cells, children, 745 ret = mfd_add_devices(&client->dev, -1, twl6040->cells, children,
660 NULL, 0, NULL); 746 NULL, 0, NULL);
661 if (ret) 747 if (ret)
diff --git a/drivers/mfd/wm5110-tables.c b/drivers/mfd/wm5110-tables.c
index bf8b3b5ad1fe..4a4432eb499c 100644
--- a/drivers/mfd/wm5110-tables.c
+++ b/drivers/mfd/wm5110-tables.c
@@ -14,6 +14,7 @@
14 14
15#include <linux/mfd/arizona/core.h> 15#include <linux/mfd/arizona/core.h>
16#include <linux/mfd/arizona/registers.h> 16#include <linux/mfd/arizona/registers.h>
17#include <linux/device.h>
17 18
18#include "arizona.h" 19#include "arizona.h"
19 20
@@ -524,6 +525,7 @@ static const struct reg_default wm5110_reg_default[] = {
524 { 0x00000300, 0x0000 }, /* R768 - Input Enables */ 525 { 0x00000300, 0x0000 }, /* R768 - Input Enables */
525 { 0x00000308, 0x0000 }, /* R776 - Input Rate */ 526 { 0x00000308, 0x0000 }, /* R776 - Input Rate */
526 { 0x00000309, 0x0022 }, /* R777 - Input Volume Ramp */ 527 { 0x00000309, 0x0022 }, /* R777 - Input Volume Ramp */
528 { 0x0000030C, 0x0002 }, /* R780 - HPF Control */
527 { 0x00000310, 0x2080 }, /* R784 - IN1L Control */ 529 { 0x00000310, 0x2080 }, /* R784 - IN1L Control */
528 { 0x00000311, 0x0180 }, /* R785 - ADC Digital Volume 1L */ 530 { 0x00000311, 0x0180 }, /* R785 - ADC Digital Volume 1L */
529 { 0x00000312, 0x0000 }, /* R786 - DMIC1L Control */ 531 { 0x00000312, 0x0000 }, /* R786 - DMIC1L Control */
@@ -545,6 +547,7 @@ static const struct reg_default wm5110_reg_default[] = {
545 { 0x00000328, 0x2000 }, /* R808 - IN4L Control */ 547 { 0x00000328, 0x2000 }, /* R808 - IN4L Control */
546 { 0x00000329, 0x0180 }, /* R809 - ADC Digital Volume 4L */ 548 { 0x00000329, 0x0180 }, /* R809 - ADC Digital Volume 4L */
547 { 0x0000032A, 0x0000 }, /* R810 - DMIC4L Control */ 549 { 0x0000032A, 0x0000 }, /* R810 - DMIC4L Control */
550 { 0x0000032C, 0x0000 }, /* R812 - IN4R Control */
548 { 0x0000032D, 0x0180 }, /* R813 - ADC Digital Volume 4R */ 551 { 0x0000032D, 0x0180 }, /* R813 - ADC Digital Volume 4R */
549 { 0x0000032E, 0x0000 }, /* R814 - DMIC4R Control */ 552 { 0x0000032E, 0x0000 }, /* R814 - DMIC4R Control */
550 { 0x00000400, 0x0000 }, /* R1024 - Output Enables 1 */ 553 { 0x00000400, 0x0000 }, /* R1024 - Output Enables 1 */
@@ -598,6 +601,7 @@ static const struct reg_default wm5110_reg_default[] = {
598 { 0x0000043D, 0x0180 }, /* R1085 - DAC Digital Volume 6R */ 601 { 0x0000043D, 0x0180 }, /* R1085 - DAC Digital Volume 6R */
599 { 0x0000043E, 0x0080 }, /* R1086 - DAC Volume Limit 6R */ 602 { 0x0000043E, 0x0080 }, /* R1086 - DAC Volume Limit 6R */
600 { 0x0000043F, 0x0800 }, /* R1087 - Noise Gate Select 6R */ 603 { 0x0000043F, 0x0800 }, /* R1087 - Noise Gate Select 6R */
604 { 0x00000440, 0x8FFF }, /* R1088 - DRE Enable */
601 { 0x00000450, 0x0000 }, /* R1104 - DAC AEC Control 1 */ 605 { 0x00000450, 0x0000 }, /* R1104 - DAC AEC Control 1 */
602 { 0x00000458, 0x0000 }, /* R1112 - Noise Gate Control */ 606 { 0x00000458, 0x0000 }, /* R1112 - Noise Gate Control */
603 { 0x00000480, 0x0040 }, /* R1152 - Class W ANC Threshold 1 */ 607 { 0x00000480, 0x0040 }, /* R1152 - Class W ANC Threshold 1 */
@@ -606,6 +610,9 @@ static const struct reg_default wm5110_reg_default[] = {
606 { 0x00000491, 0x0000 }, /* R1169 - PDM SPK1 CTRL 2 */ 610 { 0x00000491, 0x0000 }, /* R1169 - PDM SPK1 CTRL 2 */
607 { 0x00000492, 0x0069 }, /* R1170 - PDM SPK2 CTRL 1 */ 611 { 0x00000492, 0x0069 }, /* R1170 - PDM SPK2 CTRL 1 */
608 { 0x00000493, 0x0000 }, /* R1171 - PDM SPK2 CTRL 2 */ 612 { 0x00000493, 0x0000 }, /* R1171 - PDM SPK2 CTRL 2 */
613 { 0x000004A0, 0x3480 }, /* R1184 - HP1 Short Circuit Ctrl */
614 { 0x000004A1, 0x3480 }, /* R1185 - HP2 Short Circuit Ctrl */
615 { 0x000004A2, 0x3480 }, /* R1186 - HP3 Short Circuit Ctrl */
609 { 0x00000500, 0x000C }, /* R1280 - AIF1 BCLK Ctrl */ 616 { 0x00000500, 0x000C }, /* R1280 - AIF1 BCLK Ctrl */
610 { 0x00000501, 0x0008 }, /* R1281 - AIF1 Tx Pin Ctrl */ 617 { 0x00000501, 0x0008 }, /* R1281 - AIF1 Tx Pin Ctrl */
611 { 0x00000502, 0x0000 }, /* R1282 - AIF1 Rx Pin Ctrl */ 618 { 0x00000502, 0x0000 }, /* R1282 - AIF1 Rx Pin Ctrl */
@@ -882,6 +889,38 @@ static const struct reg_default wm5110_reg_default[] = {
882 { 0x0000074D, 0x0080 }, /* R1869 - AIF2TX2MIX Input 3 Volume */ 889 { 0x0000074D, 0x0080 }, /* R1869 - AIF2TX2MIX Input 3 Volume */
883 { 0x0000074E, 0x0000 }, /* R1870 - AIF2TX2MIX Input 4 Source */ 890 { 0x0000074E, 0x0000 }, /* R1870 - AIF2TX2MIX Input 4 Source */
884 { 0x0000074F, 0x0080 }, /* R1871 - AIF2TX2MIX Input 4 Volume */ 891 { 0x0000074F, 0x0080 }, /* R1871 - AIF2TX2MIX Input 4 Volume */
892 { 0x00000750, 0x0000 }, /* R1872 - AIF2TX3MIX Input 1 Source */
893 { 0x00000751, 0x0080 }, /* R1873 - AIF2TX3MIX Input 1 Volume */
894 { 0x00000752, 0x0000 }, /* R1874 - AIF2TX3MIX Input 2 Source */
895 { 0x00000753, 0x0080 }, /* R1875 - AIF2TX3MIX Input 2 Volume */
896 { 0x00000754, 0x0000 }, /* R1876 - AIF2TX3MIX Input 3 Source */
897 { 0x00000755, 0x0080 }, /* R1877 - AIF2TX3MIX Input 3 Volume */
898 { 0x00000756, 0x0000 }, /* R1878 - AIF2TX3MIX Input 4 Source */
899 { 0x00000757, 0x0080 }, /* R1879 - AIF2TX3MIX Input 4 Volume */
900 { 0x00000758, 0x0000 }, /* R1880 - AIF2TX4MIX Input 1 Source */
901 { 0x00000759, 0x0080 }, /* R1881 - AIF2TX4MIX Input 1 Volume */
902 { 0x0000075A, 0x0000 }, /* R1882 - AIF2TX4MIX Input 2 Source */
903 { 0x0000075B, 0x0080 }, /* R1883 - AIF2TX4MIX Input 2 Volume */
904 { 0x0000075C, 0x0000 }, /* R1884 - AIF2TX4MIX Input 3 Source */
905 { 0x0000075D, 0x0080 }, /* R1885 - AIF2TX4MIX Input 3 Volume */
906 { 0x0000075E, 0x0000 }, /* R1886 - AIF2TX4MIX Input 4 Source */
907 { 0x0000075F, 0x0080 }, /* R1887 - AIF2TX4MIX Input 4 Volume */
908 { 0x00000760, 0x0000 }, /* R1888 - AIF2TX5MIX Input 1 Source */
909 { 0x00000761, 0x0080 }, /* R1889 - AIF2TX5MIX Input 1 Volume */
910 { 0x00000762, 0x0000 }, /* R1890 - AIF2TX5MIX Input 2 Source */
911 { 0x00000763, 0x0080 }, /* R1891 - AIF2TX5MIX Input 2 Volume */
912 { 0x00000764, 0x0000 }, /* R1892 - AIF2TX5MIX Input 3 Source */
913 { 0x00000765, 0x0080 }, /* R1893 - AIF2TX5MIX Input 3 Volume */
914 { 0x00000766, 0x0000 }, /* R1894 - AIF2TX5MIX Input 4 Source */
915 { 0x00000767, 0x0080 }, /* R1895 - AIF2TX5MIX Input 4 Volume */
916 { 0x00000768, 0x0000 }, /* R1896 - AIF2TX6MIX Input 1 Source */
917 { 0x00000769, 0x0080 }, /* R1897 - AIF2TX6MIX Input 1 Volume */
918 { 0x0000076A, 0x0000 }, /* R1898 - AIF2TX6MIX Input 2 Source */
919 { 0x0000076B, 0x0080 }, /* R1899 - AIF2TX6MIX Input 2 Volume */
920 { 0x0000076C, 0x0000 }, /* R1900 - AIF2TX6MIX Input 3 Source */
921 { 0x0000076D, 0x0080 }, /* R1901 - AIF2TX6MIX Input 3 Volume */
922 { 0x0000076E, 0x0000 }, /* R1902 - AIF2TX6MIX Input 4 Source */
923 { 0x0000076F, 0x0080 }, /* R1903 - AIF2TX6MIX Input 4 Volume */
885 { 0x00000780, 0x0000 }, /* R1920 - AIF3TX1MIX Input 1 Source */ 924 { 0x00000780, 0x0000 }, /* R1920 - AIF3TX1MIX Input 1 Source */
886 { 0x00000781, 0x0080 }, /* R1921 - AIF3TX1MIX Input 1 Volume */ 925 { 0x00000781, 0x0080 }, /* R1921 - AIF3TX1MIX Input 1 Volume */
887 { 0x00000782, 0x0000 }, /* R1922 - AIF3TX1MIX Input 2 Source */ 926 { 0x00000782, 0x0000 }, /* R1922 - AIF3TX1MIX Input 2 Source */
@@ -1342,6 +1381,64 @@ static const struct reg_default wm5110_reg_default[] = {
1342 { 0x00001404, 0x0000 }, /* R5124 - DSP4 Status 1 */ 1381 { 0x00001404, 0x0000 }, /* R5124 - DSP4 Status 1 */
1343}; 1382};
1344 1383
1384static bool wm5110_is_rev_b_adsp_memory(unsigned int reg)
1385{
1386 if ((reg >= 0x100000 && reg < 0x103000) ||
1387 (reg >= 0x180000 && reg < 0x181000) ||
1388 (reg >= 0x190000 && reg < 0x192000) ||
1389 (reg >= 0x1a8000 && reg < 0x1a9000) ||
1390 (reg >= 0x200000 && reg < 0x209000) ||
1391 (reg >= 0x280000 && reg < 0x281000) ||
1392 (reg >= 0x290000 && reg < 0x29a000) ||
1393 (reg >= 0x2a8000 && reg < 0x2aa000) ||
1394 (reg >= 0x300000 && reg < 0x30f000) ||
1395 (reg >= 0x380000 && reg < 0x382000) ||
1396 (reg >= 0x390000 && reg < 0x39e000) ||
1397 (reg >= 0x3a8000 && reg < 0x3b6000) ||
1398 (reg >= 0x400000 && reg < 0x403000) ||
1399 (reg >= 0x480000 && reg < 0x481000) ||
1400 (reg >= 0x490000 && reg < 0x492000) ||
1401 (reg >= 0x4a8000 && reg < 0x4a9000))
1402 return true;
1403 else
1404 return false;
1405}
1406
1407static bool wm5110_is_rev_d_adsp_memory(unsigned int reg)
1408{
1409 if ((reg >= 0x100000 && reg < 0x106000) ||
1410 (reg >= 0x180000 && reg < 0x182000) ||
1411 (reg >= 0x190000 && reg < 0x198000) ||
1412 (reg >= 0x1a8000 && reg < 0x1aa000) ||
1413 (reg >= 0x200000 && reg < 0x20f000) ||
1414 (reg >= 0x280000 && reg < 0x282000) ||
1415 (reg >= 0x290000 && reg < 0x29c000) ||
1416 (reg >= 0x2a6000 && reg < 0x2b4000) ||
1417 (reg >= 0x300000 && reg < 0x30f000) ||
1418 (reg >= 0x380000 && reg < 0x382000) ||
1419 (reg >= 0x390000 && reg < 0x3a2000) ||
1420 (reg >= 0x3a6000 && reg < 0x3b4000) ||
1421 (reg >= 0x400000 && reg < 0x406000) ||
1422 (reg >= 0x480000 && reg < 0x482000) ||
1423 (reg >= 0x490000 && reg < 0x498000) ||
1424 (reg >= 0x4a8000 && reg < 0x4aa000))
1425 return true;
1426 else
1427 return false;
1428}
1429
1430static bool wm5110_is_adsp_memory(struct device *dev, unsigned int reg)
1431{
1432 struct arizona *arizona = dev_get_drvdata(dev);
1433
1434 switch (arizona->rev) {
1435 case 0 ... 2:
1436 return wm5110_is_rev_b_adsp_memory(reg);
1437 default:
1438 return wm5110_is_rev_d_adsp_memory(reg);
1439 }
1440}
1441
1345static bool wm5110_readable_register(struct device *dev, unsigned int reg) 1442static bool wm5110_readable_register(struct device *dev, unsigned int reg)
1346{ 1443{
1347 switch (reg) { 1444 switch (reg) {
@@ -1460,6 +1557,7 @@ static bool wm5110_readable_register(struct device *dev, unsigned int reg)
1460 case ARIZONA_INPUT_ENABLES_STATUS: 1557 case ARIZONA_INPUT_ENABLES_STATUS:
1461 case ARIZONA_INPUT_RATE: 1558 case ARIZONA_INPUT_RATE:
1462 case ARIZONA_INPUT_VOLUME_RAMP: 1559 case ARIZONA_INPUT_VOLUME_RAMP:
1560 case ARIZONA_HPF_CONTROL:
1463 case ARIZONA_IN1L_CONTROL: 1561 case ARIZONA_IN1L_CONTROL:
1464 case ARIZONA_ADC_DIGITAL_VOLUME_1L: 1562 case ARIZONA_ADC_DIGITAL_VOLUME_1L:
1465 case ARIZONA_DMIC1L_CONTROL: 1563 case ARIZONA_DMIC1L_CONTROL:
@@ -1481,6 +1579,7 @@ static bool wm5110_readable_register(struct device *dev, unsigned int reg)
1481 case ARIZONA_IN4L_CONTROL: 1579 case ARIZONA_IN4L_CONTROL:
1482 case ARIZONA_ADC_DIGITAL_VOLUME_4L: 1580 case ARIZONA_ADC_DIGITAL_VOLUME_4L:
1483 case ARIZONA_DMIC4L_CONTROL: 1581 case ARIZONA_DMIC4L_CONTROL:
1582 case ARIZONA_IN4R_CONTROL:
1484 case ARIZONA_ADC_DIGITAL_VOLUME_4R: 1583 case ARIZONA_ADC_DIGITAL_VOLUME_4R:
1485 case ARIZONA_DMIC4R_CONTROL: 1584 case ARIZONA_DMIC4R_CONTROL:
1486 case ARIZONA_OUTPUT_ENABLES_1: 1585 case ARIZONA_OUTPUT_ENABLES_1:
@@ -1536,12 +1635,16 @@ static bool wm5110_readable_register(struct device *dev, unsigned int reg)
1536 case ARIZONA_DAC_DIGITAL_VOLUME_6R: 1635 case ARIZONA_DAC_DIGITAL_VOLUME_6R:
1537 case ARIZONA_DAC_VOLUME_LIMIT_6R: 1636 case ARIZONA_DAC_VOLUME_LIMIT_6R:
1538 case ARIZONA_NOISE_GATE_SELECT_6R: 1637 case ARIZONA_NOISE_GATE_SELECT_6R:
1638 case ARIZONA_DRE_ENABLE:
1539 case ARIZONA_DAC_AEC_CONTROL_1: 1639 case ARIZONA_DAC_AEC_CONTROL_1:
1540 case ARIZONA_NOISE_GATE_CONTROL: 1640 case ARIZONA_NOISE_GATE_CONTROL:
1541 case ARIZONA_PDM_SPK1_CTRL_1: 1641 case ARIZONA_PDM_SPK1_CTRL_1:
1542 case ARIZONA_PDM_SPK1_CTRL_2: 1642 case ARIZONA_PDM_SPK1_CTRL_2:
1543 case ARIZONA_PDM_SPK2_CTRL_1: 1643 case ARIZONA_PDM_SPK2_CTRL_1:
1544 case ARIZONA_PDM_SPK2_CTRL_2: 1644 case ARIZONA_PDM_SPK2_CTRL_2:
1645 case ARIZONA_HP1_SHORT_CIRCUIT_CTRL:
1646 case ARIZONA_HP2_SHORT_CIRCUIT_CTRL:
1647 case ARIZONA_HP3_SHORT_CIRCUIT_CTRL:
1545 case ARIZONA_AIF1_BCLK_CTRL: 1648 case ARIZONA_AIF1_BCLK_CTRL:
1546 case ARIZONA_AIF1_TX_PIN_CTRL: 1649 case ARIZONA_AIF1_TX_PIN_CTRL:
1547 case ARIZONA_AIF1_RX_PIN_CTRL: 1650 case ARIZONA_AIF1_RX_PIN_CTRL:
@@ -1820,6 +1923,38 @@ static bool wm5110_readable_register(struct device *dev, unsigned int reg)
1820 case ARIZONA_AIF2TX2MIX_INPUT_3_VOLUME: 1923 case ARIZONA_AIF2TX2MIX_INPUT_3_VOLUME:
1821 case ARIZONA_AIF2TX2MIX_INPUT_4_SOURCE: 1924 case ARIZONA_AIF2TX2MIX_INPUT_4_SOURCE:
1822 case ARIZONA_AIF2TX2MIX_INPUT_4_VOLUME: 1925 case ARIZONA_AIF2TX2MIX_INPUT_4_VOLUME:
1926 case ARIZONA_AIF2TX3MIX_INPUT_1_SOURCE:
1927 case ARIZONA_AIF2TX3MIX_INPUT_1_VOLUME:
1928 case ARIZONA_AIF2TX3MIX_INPUT_2_SOURCE:
1929 case ARIZONA_AIF2TX3MIX_INPUT_2_VOLUME:
1930 case ARIZONA_AIF2TX3MIX_INPUT_3_SOURCE:
1931 case ARIZONA_AIF2TX3MIX_INPUT_3_VOLUME:
1932 case ARIZONA_AIF2TX3MIX_INPUT_4_SOURCE:
1933 case ARIZONA_AIF2TX3MIX_INPUT_4_VOLUME:
1934 case ARIZONA_AIF2TX4MIX_INPUT_1_SOURCE:
1935 case ARIZONA_AIF2TX4MIX_INPUT_1_VOLUME:
1936 case ARIZONA_AIF2TX4MIX_INPUT_2_SOURCE:
1937 case ARIZONA_AIF2TX4MIX_INPUT_2_VOLUME:
1938 case ARIZONA_AIF2TX4MIX_INPUT_3_SOURCE:
1939 case ARIZONA_AIF2TX4MIX_INPUT_3_VOLUME:
1940 case ARIZONA_AIF2TX4MIX_INPUT_4_SOURCE:
1941 case ARIZONA_AIF2TX4MIX_INPUT_4_VOLUME:
1942 case ARIZONA_AIF2TX5MIX_INPUT_1_SOURCE:
1943 case ARIZONA_AIF2TX5MIX_INPUT_1_VOLUME:
1944 case ARIZONA_AIF2TX5MIX_INPUT_2_SOURCE:
1945 case ARIZONA_AIF2TX5MIX_INPUT_2_VOLUME:
1946 case ARIZONA_AIF2TX5MIX_INPUT_3_SOURCE:
1947 case ARIZONA_AIF2TX5MIX_INPUT_3_VOLUME:
1948 case ARIZONA_AIF2TX5MIX_INPUT_4_SOURCE:
1949 case ARIZONA_AIF2TX5MIX_INPUT_4_VOLUME:
1950 case ARIZONA_AIF2TX6MIX_INPUT_1_SOURCE:
1951 case ARIZONA_AIF2TX6MIX_INPUT_1_VOLUME:
1952 case ARIZONA_AIF2TX6MIX_INPUT_2_SOURCE:
1953 case ARIZONA_AIF2TX6MIX_INPUT_2_VOLUME:
1954 case ARIZONA_AIF2TX6MIX_INPUT_3_SOURCE:
1955 case ARIZONA_AIF2TX6MIX_INPUT_3_VOLUME:
1956 case ARIZONA_AIF2TX6MIX_INPUT_4_SOURCE:
1957 case ARIZONA_AIF2TX6MIX_INPUT_4_VOLUME:
1823 case ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE: 1958 case ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE:
1824 case ARIZONA_AIF3TX1MIX_INPUT_1_VOLUME: 1959 case ARIZONA_AIF3TX1MIX_INPUT_1_VOLUME:
1825 case ARIZONA_AIF3TX1MIX_INPUT_2_SOURCE: 1960 case ARIZONA_AIF3TX1MIX_INPUT_2_SOURCE:
@@ -2331,7 +2466,7 @@ static bool wm5110_readable_register(struct device *dev, unsigned int reg)
2331 case ARIZONA_DSP4_SCRATCH_3: 2466 case ARIZONA_DSP4_SCRATCH_3:
2332 return true; 2467 return true;
2333 default: 2468 default:
2334 return false; 2469 return wm5110_is_adsp_memory(dev, reg);
2335 } 2470 }
2336} 2471}
2337 2472
@@ -2407,16 +2542,18 @@ static bool wm5110_volatile_register(struct device *dev, unsigned int reg)
2407 case ARIZONA_DSP4_SCRATCH_3: 2542 case ARIZONA_DSP4_SCRATCH_3:
2408 return true; 2543 return true;
2409 default: 2544 default:
2410 return false; 2545 return wm5110_is_adsp_memory(dev, reg);
2411 } 2546 }
2412} 2547}
2413 2548
2549#define WM5110_MAX_REGISTER 0x4a9fff
2550
2414const struct regmap_config wm5110_spi_regmap = { 2551const struct regmap_config wm5110_spi_regmap = {
2415 .reg_bits = 32, 2552 .reg_bits = 32,
2416 .pad_bits = 16, 2553 .pad_bits = 16,
2417 .val_bits = 16, 2554 .val_bits = 16,
2418 2555
2419 .max_register = ARIZONA_DSP1_STATUS_2, 2556 .max_register = WM5110_MAX_REGISTER,
2420 .readable_reg = wm5110_readable_register, 2557 .readable_reg = wm5110_readable_register,
2421 .volatile_reg = wm5110_volatile_register, 2558 .volatile_reg = wm5110_volatile_register,
2422 2559
@@ -2430,7 +2567,7 @@ const struct regmap_config wm5110_i2c_regmap = {
2430 .reg_bits = 32, 2567 .reg_bits = 32,
2431 .val_bits = 16, 2568 .val_bits = 16,
2432 2569
2433 .max_register = ARIZONA_DSP1_STATUS_2, 2570 .max_register = WM5110_MAX_REGISTER,
2434 .readable_reg = wm5110_readable_register, 2571 .readable_reg = wm5110_readable_register,
2435 .volatile_reg = wm5110_volatile_register, 2572 .volatile_reg = wm5110_volatile_register,
2436 2573
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index eb1f1ef5fa2e..e2dd2fbec5ee 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -395,7 +395,7 @@ config SPI_S3C24XX_FIQ
395config SPI_S3C64XX 395config SPI_S3C64XX
396 tristate "Samsung S3C64XX series type SPI" 396 tristate "Samsung S3C64XX series type SPI"
397 depends on PLAT_SAMSUNG 397 depends on PLAT_SAMSUNG
398 select S3C64XX_DMA if ARCH_S3C64XX 398 select S3C64XX_PL080 if ARCH_S3C64XX
399 help 399 help
400 SPI driver for Samsung S3C64XX and newer SoCs. 400 SPI driver for Samsung S3C64XX and newer SoCs.
401 401
generated by cgit v1.2.2 (git 2.25.0) at 2026-03-05 08:36:49 -0500