diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/net/stmmac/common.h | 50 | ||||
-rw-r--r-- | drivers/net/stmmac/dwmac1000_core.c | 18 | ||||
-rw-r--r-- | drivers/net/stmmac/dwmac1000_dma.c | 8 | ||||
-rw-r--r-- | drivers/net/stmmac/dwmac100_core.c | 20 | ||||
-rw-r--r-- | drivers/net/stmmac/dwmac100_dma.c | 8 | ||||
-rw-r--r-- | drivers/net/stmmac/dwmac_dma.h | 16 | ||||
-rw-r--r-- | drivers/net/stmmac/dwmac_lib.c | 22 | ||||
-rw-r--r-- | drivers/net/stmmac/enh_desc.c | 2 | ||||
-rw-r--r-- | drivers/net/stmmac/norm_desc.c | 2 | ||||
-rw-r--r-- | drivers/net/stmmac/stmmac.h | 3 | ||||
-rw-r--r-- | drivers/net/stmmac/stmmac_ethtool.c | 21 | ||||
-rw-r--r-- | drivers/net/stmmac/stmmac_main.c | 124 | ||||
-rw-r--r-- | drivers/net/stmmac/stmmac_mdio.c | 21 |
13 files changed, 152 insertions, 163 deletions
diff --git a/drivers/net/stmmac/common.h b/drivers/net/stmmac/common.h index 66b9da0260fe..e8cbcb5c206e 100644 --- a/drivers/net/stmmac/common.h +++ b/drivers/net/stmmac/common.h | |||
@@ -167,7 +167,7 @@ struct stmmac_desc_ops { | |||
167 | int (*get_tx_ls) (struct dma_desc *p); | 167 | int (*get_tx_ls) (struct dma_desc *p); |
168 | /* Return the transmit status looking at the TDES1 */ | 168 | /* Return the transmit status looking at the TDES1 */ |
169 | int (*tx_status) (void *data, struct stmmac_extra_stats *x, | 169 | int (*tx_status) (void *data, struct stmmac_extra_stats *x, |
170 | struct dma_desc *p, unsigned long ioaddr); | 170 | struct dma_desc *p, void __iomem *ioaddr); |
171 | /* Get the buffer size from the descriptor */ | 171 | /* Get the buffer size from the descriptor */ |
172 | int (*get_tx_len) (struct dma_desc *p); | 172 | int (*get_tx_len) (struct dma_desc *p); |
173 | /* Handle extra events on specific interrupts hw dependent */ | 173 | /* Handle extra events on specific interrupts hw dependent */ |
@@ -182,44 +182,44 @@ struct stmmac_desc_ops { | |||
182 | 182 | ||
183 | struct stmmac_dma_ops { | 183 | struct stmmac_dma_ops { |
184 | /* DMA core initialization */ | 184 | /* DMA core initialization */ |
185 | int (*init) (unsigned long ioaddr, int pbl, u32 dma_tx, u32 dma_rx); | 185 | int (*init) (void __iomem *ioaddr, int pbl, u32 dma_tx, u32 dma_rx); |
186 | /* Dump DMA registers */ | 186 | /* Dump DMA registers */ |
187 | void (*dump_regs) (unsigned long ioaddr); | 187 | void (*dump_regs) (void __iomem *ioaddr); |
188 | /* Set tx/rx threshold in the csr6 register | 188 | /* Set tx/rx threshold in the csr6 register |
189 | * An invalid value enables the store-and-forward mode */ | 189 | * An invalid value enables the store-and-forward mode */ |
190 | void (*dma_mode) (unsigned long ioaddr, int txmode, int rxmode); | 190 | void (*dma_mode) (void __iomem *ioaddr, int txmode, int rxmode); |
191 | /* To track extra statistic (if supported) */ | 191 | /* To track extra statistic (if supported) */ |
192 | void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x, | 192 | void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x, |
193 | unsigned long ioaddr); | 193 | void __iomem *ioaddr); |
194 | void (*enable_dma_transmission) (unsigned long ioaddr); | 194 | void (*enable_dma_transmission) (void __iomem *ioaddr); |
195 | void (*enable_dma_irq) (unsigned long ioaddr); | 195 | void (*enable_dma_irq) (void __iomem *ioaddr); |
196 | void (*disable_dma_irq) (unsigned long ioaddr); | 196 | void (*disable_dma_irq) (void __iomem *ioaddr); |
197 | void (*start_tx) (unsigned long ioaddr); | 197 | void (*start_tx) (void __iomem *ioaddr); |
198 | void (*stop_tx) (unsigned long ioaddr); | 198 | void (*stop_tx) (void __iomem *ioaddr); |
199 | void (*start_rx) (unsigned long ioaddr); | 199 | void (*start_rx) (void __iomem *ioaddr); |
200 | void (*stop_rx) (unsigned long ioaddr); | 200 | void (*stop_rx) (void __iomem *ioaddr); |
201 | int (*dma_interrupt) (unsigned long ioaddr, | 201 | int (*dma_interrupt) (void __iomem *ioaddr, |
202 | struct stmmac_extra_stats *x); | 202 | struct stmmac_extra_stats *x); |
203 | }; | 203 | }; |
204 | 204 | ||
205 | struct stmmac_ops { | 205 | struct stmmac_ops { |
206 | /* MAC core initialization */ | 206 | /* MAC core initialization */ |
207 | void (*core_init) (unsigned long ioaddr) ____cacheline_aligned; | 207 | void (*core_init) (void __iomem *ioaddr) ____cacheline_aligned; |
208 | /* Dump MAC registers */ | 208 | /* Dump MAC registers */ |
209 | void (*dump_regs) (unsigned long ioaddr); | 209 | void (*dump_regs) (void __iomem *ioaddr); |
210 | /* Handle extra events on specific interrupts hw dependent */ | 210 | /* Handle extra events on specific interrupts hw dependent */ |
211 | void (*host_irq_status) (unsigned long ioaddr); | 211 | void (*host_irq_status) (void __iomem *ioaddr); |
212 | /* Multicast filter setting */ | 212 | /* Multicast filter setting */ |
213 | void (*set_filter) (struct net_device *dev); | 213 | void (*set_filter) (struct net_device *dev); |
214 | /* Flow control setting */ | 214 | /* Flow control setting */ |
215 | void (*flow_ctrl) (unsigned long ioaddr, unsigned int duplex, | 215 | void (*flow_ctrl) (void __iomem *ioaddr, unsigned int duplex, |
216 | unsigned int fc, unsigned int pause_time); | 216 | unsigned int fc, unsigned int pause_time); |
217 | /* Set power management mode (e.g. magic frame) */ | 217 | /* Set power management mode (e.g. magic frame) */ |
218 | void (*pmt) (unsigned long ioaddr, unsigned long mode); | 218 | void (*pmt) (void __iomem *ioaddr, unsigned long mode); |
219 | /* Set/Get Unicast MAC addresses */ | 219 | /* Set/Get Unicast MAC addresses */ |
220 | void (*set_umac_addr) (unsigned long ioaddr, unsigned char *addr, | 220 | void (*set_umac_addr) (void __iomem *ioaddr, unsigned char *addr, |
221 | unsigned int reg_n); | 221 | unsigned int reg_n); |
222 | void (*get_umac_addr) (unsigned long ioaddr, unsigned char *addr, | 222 | void (*get_umac_addr) (void __iomem *ioaddr, unsigned char *addr, |
223 | unsigned int reg_n); | 223 | unsigned int reg_n); |
224 | }; | 224 | }; |
225 | 225 | ||
@@ -243,11 +243,11 @@ struct mac_device_info { | |||
243 | struct mac_link link; | 243 | struct mac_link link; |
244 | }; | 244 | }; |
245 | 245 | ||
246 | struct mac_device_info *dwmac1000_setup(unsigned long addr); | 246 | struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr); |
247 | struct mac_device_info *dwmac100_setup(unsigned long addr); | 247 | struct mac_device_info *dwmac100_setup(void __iomem *ioaddr); |
248 | 248 | ||
249 | extern void stmmac_set_mac_addr(unsigned long ioaddr, u8 addr[6], | 249 | extern void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6], |
250 | unsigned int high, unsigned int low); | 250 | unsigned int high, unsigned int low); |
251 | extern void stmmac_get_mac_addr(unsigned long ioaddr, unsigned char *addr, | 251 | extern void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr, |
252 | unsigned int high, unsigned int low); | 252 | unsigned int high, unsigned int low); |
253 | extern void dwmac_dma_flush_tx_fifo(unsigned long ioaddr); | 253 | extern void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr); |
diff --git a/drivers/net/stmmac/dwmac1000_core.c b/drivers/net/stmmac/dwmac1000_core.c index 2b2f5c8caf1c..8bbfc0f48dea 100644 --- a/drivers/net/stmmac/dwmac1000_core.c +++ b/drivers/net/stmmac/dwmac1000_core.c | |||
@@ -30,7 +30,7 @@ | |||
30 | #include <linux/slab.h> | 30 | #include <linux/slab.h> |
31 | #include "dwmac1000.h" | 31 | #include "dwmac1000.h" |
32 | 32 | ||
33 | static void dwmac1000_core_init(unsigned long ioaddr) | 33 | static void dwmac1000_core_init(void __iomem *ioaddr) |
34 | { | 34 | { |
35 | u32 value = readl(ioaddr + GMAC_CONTROL); | 35 | u32 value = readl(ioaddr + GMAC_CONTROL); |
36 | value |= GMAC_CORE_INIT; | 36 | value |= GMAC_CORE_INIT; |
@@ -50,7 +50,7 @@ static void dwmac1000_core_init(unsigned long ioaddr) | |||
50 | #endif | 50 | #endif |
51 | } | 51 | } |
52 | 52 | ||
53 | static void dwmac1000_dump_regs(unsigned long ioaddr) | 53 | static void dwmac1000_dump_regs(void __iomem *ioaddr) |
54 | { | 54 | { |
55 | int i; | 55 | int i; |
56 | pr_info("\tDWMAC1000 regs (base addr = 0x%8x)\n", (unsigned int)ioaddr); | 56 | pr_info("\tDWMAC1000 regs (base addr = 0x%8x)\n", (unsigned int)ioaddr); |
@@ -62,14 +62,14 @@ static void dwmac1000_dump_regs(unsigned long ioaddr) | |||
62 | } | 62 | } |
63 | } | 63 | } |
64 | 64 | ||
65 | static void dwmac1000_set_umac_addr(unsigned long ioaddr, unsigned char *addr, | 65 | static void dwmac1000_set_umac_addr(void __iomem *ioaddr, unsigned char *addr, |
66 | unsigned int reg_n) | 66 | unsigned int reg_n) |
67 | { | 67 | { |
68 | stmmac_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n), | 68 | stmmac_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n), |
69 | GMAC_ADDR_LOW(reg_n)); | 69 | GMAC_ADDR_LOW(reg_n)); |
70 | } | 70 | } |
71 | 71 | ||
72 | static void dwmac1000_get_umac_addr(unsigned long ioaddr, unsigned char *addr, | 72 | static void dwmac1000_get_umac_addr(void __iomem *ioaddr, unsigned char *addr, |
73 | unsigned int reg_n) | 73 | unsigned int reg_n) |
74 | { | 74 | { |
75 | stmmac_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n), | 75 | stmmac_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n), |
@@ -78,7 +78,7 @@ static void dwmac1000_get_umac_addr(unsigned long ioaddr, unsigned char *addr, | |||
78 | 78 | ||
79 | static void dwmac1000_set_filter(struct net_device *dev) | 79 | static void dwmac1000_set_filter(struct net_device *dev) |
80 | { | 80 | { |
81 | unsigned long ioaddr = dev->base_addr; | 81 | void __iomem *ioaddr = (void __iomem *) dev->base_addr; |
82 | unsigned int value = 0; | 82 | unsigned int value = 0; |
83 | 83 | ||
84 | CHIP_DBG(KERN_INFO "%s: # mcasts %d, # unicast %d\n", | 84 | CHIP_DBG(KERN_INFO "%s: # mcasts %d, # unicast %d\n", |
@@ -139,7 +139,7 @@ static void dwmac1000_set_filter(struct net_device *dev) | |||
139 | readl(ioaddr + GMAC_HASH_HIGH), readl(ioaddr + GMAC_HASH_LOW)); | 139 | readl(ioaddr + GMAC_HASH_HIGH), readl(ioaddr + GMAC_HASH_LOW)); |
140 | } | 140 | } |
141 | 141 | ||
142 | static void dwmac1000_flow_ctrl(unsigned long ioaddr, unsigned int duplex, | 142 | static void dwmac1000_flow_ctrl(void __iomem *ioaddr, unsigned int duplex, |
143 | unsigned int fc, unsigned int pause_time) | 143 | unsigned int fc, unsigned int pause_time) |
144 | { | 144 | { |
145 | unsigned int flow = 0; | 145 | unsigned int flow = 0; |
@@ -162,7 +162,7 @@ static void dwmac1000_flow_ctrl(unsigned long ioaddr, unsigned int duplex, | |||
162 | writel(flow, ioaddr + GMAC_FLOW_CTRL); | 162 | writel(flow, ioaddr + GMAC_FLOW_CTRL); |
163 | } | 163 | } |
164 | 164 | ||
165 | static void dwmac1000_pmt(unsigned long ioaddr, unsigned long mode) | 165 | static void dwmac1000_pmt(void __iomem *ioaddr, unsigned long mode) |
166 | { | 166 | { |
167 | unsigned int pmt = 0; | 167 | unsigned int pmt = 0; |
168 | 168 | ||
@@ -178,7 +178,7 @@ static void dwmac1000_pmt(unsigned long ioaddr, unsigned long mode) | |||
178 | } | 178 | } |
179 | 179 | ||
180 | 180 | ||
181 | static void dwmac1000_irq_status(unsigned long ioaddr) | 181 | static void dwmac1000_irq_status(void __iomem *ioaddr) |
182 | { | 182 | { |
183 | u32 intr_status = readl(ioaddr + GMAC_INT_STATUS); | 183 | u32 intr_status = readl(ioaddr + GMAC_INT_STATUS); |
184 | 184 | ||
@@ -211,7 +211,7 @@ struct stmmac_ops dwmac1000_ops = { | |||
211 | .get_umac_addr = dwmac1000_get_umac_addr, | 211 | .get_umac_addr = dwmac1000_get_umac_addr, |
212 | }; | 212 | }; |
213 | 213 | ||
214 | struct mac_device_info *dwmac1000_setup(unsigned long ioaddr) | 214 | struct mac_device_info *dwmac1000_setup(void __iomem *ioaddr) |
215 | { | 215 | { |
216 | struct mac_device_info *mac; | 216 | struct mac_device_info *mac; |
217 | u32 uid = readl(ioaddr + GMAC_VERSION); | 217 | u32 uid = readl(ioaddr + GMAC_VERSION); |
diff --git a/drivers/net/stmmac/dwmac1000_dma.c b/drivers/net/stmmac/dwmac1000_dma.c index 415805057cb0..2ef5a56370e9 100644 --- a/drivers/net/stmmac/dwmac1000_dma.c +++ b/drivers/net/stmmac/dwmac1000_dma.c | |||
@@ -29,7 +29,7 @@ | |||
29 | #include "dwmac1000.h" | 29 | #include "dwmac1000.h" |
30 | #include "dwmac_dma.h" | 30 | #include "dwmac_dma.h" |
31 | 31 | ||
32 | static int dwmac1000_dma_init(unsigned long ioaddr, int pbl, u32 dma_tx, | 32 | static int dwmac1000_dma_init(void __iomem *ioaddr, int pbl, u32 dma_tx, |
33 | u32 dma_rx) | 33 | u32 dma_rx) |
34 | { | 34 | { |
35 | u32 value = readl(ioaddr + DMA_BUS_MODE); | 35 | u32 value = readl(ioaddr + DMA_BUS_MODE); |
@@ -58,7 +58,7 @@ static int dwmac1000_dma_init(unsigned long ioaddr, int pbl, u32 dma_tx, | |||
58 | return 0; | 58 | return 0; |
59 | } | 59 | } |
60 | 60 | ||
61 | static void dwmac1000_dma_operation_mode(unsigned long ioaddr, int txmode, | 61 | static void dwmac1000_dma_operation_mode(void __iomem *ioaddr, int txmode, |
62 | int rxmode) | 62 | int rxmode) |
63 | { | 63 | { |
64 | u32 csr6 = readl(ioaddr + DMA_CONTROL); | 64 | u32 csr6 = readl(ioaddr + DMA_CONTROL); |
@@ -111,12 +111,12 @@ static void dwmac1000_dma_operation_mode(unsigned long ioaddr, int txmode, | |||
111 | 111 | ||
112 | /* Not yet implemented --- no RMON module */ | 112 | /* Not yet implemented --- no RMON module */ |
113 | static void dwmac1000_dma_diagnostic_fr(void *data, | 113 | static void dwmac1000_dma_diagnostic_fr(void *data, |
114 | struct stmmac_extra_stats *x, unsigned long ioaddr) | 114 | struct stmmac_extra_stats *x, void __iomem *ioaddr) |
115 | { | 115 | { |
116 | return; | 116 | return; |
117 | } | 117 | } |
118 | 118 | ||
119 | static void dwmac1000_dump_dma_regs(unsigned long ioaddr) | 119 | static void dwmac1000_dump_dma_regs(void __iomem *ioaddr) |
120 | { | 120 | { |
121 | int i; | 121 | int i; |
122 | pr_info(" DMA registers\n"); | 122 | pr_info(" DMA registers\n"); |
diff --git a/drivers/net/stmmac/dwmac100_core.c b/drivers/net/stmmac/dwmac100_core.c index 2fb165fa2ba0..135a8082816e 100644 --- a/drivers/net/stmmac/dwmac100_core.c +++ b/drivers/net/stmmac/dwmac100_core.c | |||
@@ -31,7 +31,7 @@ | |||
31 | #include <linux/crc32.h> | 31 | #include <linux/crc32.h> |
32 | #include "dwmac100.h" | 32 | #include "dwmac100.h" |
33 | 33 | ||
34 | static void dwmac100_core_init(unsigned long ioaddr) | 34 | static void dwmac100_core_init(void __iomem *ioaddr) |
35 | { | 35 | { |
36 | u32 value = readl(ioaddr + MAC_CONTROL); | 36 | u32 value = readl(ioaddr + MAC_CONTROL); |
37 | 37 | ||
@@ -42,12 +42,12 @@ static void dwmac100_core_init(unsigned long ioaddr) | |||
42 | #endif | 42 | #endif |
43 | } | 43 | } |
44 | 44 | ||
45 | static void dwmac100_dump_mac_regs(unsigned long ioaddr) | 45 | static void dwmac100_dump_mac_regs(void __iomem *ioaddr) |
46 | { | 46 | { |
47 | pr_info("\t----------------------------------------------\n" | 47 | pr_info("\t----------------------------------------------\n" |
48 | "\t DWMAC 100 CSR (base addr = 0x%8x)\n" | 48 | "\t DWMAC 100 CSR (base addr = 0x%8x)\n" |
49 | "\t----------------------------------------------\n", | 49 | "\t----------------------------------------------\n", |
50 | (unsigned int)ioaddr); | 50 | (unsigned int) ioaddr); |
51 | pr_info("\tcontrol reg (offset 0x%x): 0x%08x\n", MAC_CONTROL, | 51 | pr_info("\tcontrol reg (offset 0x%x): 0x%08x\n", MAC_CONTROL, |
52 | readl(ioaddr + MAC_CONTROL)); | 52 | readl(ioaddr + MAC_CONTROL)); |
53 | pr_info("\taddr HI (offset 0x%x): 0x%08x\n ", MAC_ADDR_HIGH, | 53 | pr_info("\taddr HI (offset 0x%x): 0x%08x\n ", MAC_ADDR_HIGH, |
@@ -77,18 +77,18 @@ static void dwmac100_dump_mac_regs(unsigned long ioaddr) | |||
77 | MMC_LOW_INTR_MASK, readl(ioaddr + MMC_LOW_INTR_MASK)); | 77 | MMC_LOW_INTR_MASK, readl(ioaddr + MMC_LOW_INTR_MASK)); |
78 | } | 78 | } |
79 | 79 | ||
80 | static void dwmac100_irq_status(unsigned long ioaddr) | 80 | static void dwmac100_irq_status(void __iomem *ioaddr) |
81 | { | 81 | { |
82 | return; | 82 | return; |
83 | } | 83 | } |
84 | 84 | ||
85 | static void dwmac100_set_umac_addr(unsigned long ioaddr, unsigned char *addr, | 85 | static void dwmac100_set_umac_addr(void __iomem *ioaddr, unsigned char *addr, |
86 | unsigned int reg_n) | 86 | unsigned int reg_n) |
87 | { | 87 | { |
88 | stmmac_set_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW); | 88 | stmmac_set_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW); |
89 | } | 89 | } |
90 | 90 | ||
91 | static void dwmac100_get_umac_addr(unsigned long ioaddr, unsigned char *addr, | 91 | static void dwmac100_get_umac_addr(void __iomem *ioaddr, unsigned char *addr, |
92 | unsigned int reg_n) | 92 | unsigned int reg_n) |
93 | { | 93 | { |
94 | stmmac_get_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW); | 94 | stmmac_get_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW); |
@@ -96,7 +96,7 @@ static void dwmac100_get_umac_addr(unsigned long ioaddr, unsigned char *addr, | |||
96 | 96 | ||
97 | static void dwmac100_set_filter(struct net_device *dev) | 97 | static void dwmac100_set_filter(struct net_device *dev) |
98 | { | 98 | { |
99 | unsigned long ioaddr = dev->base_addr; | 99 | void __iomem *ioaddr = (void __iomem *) dev->base_addr; |
100 | u32 value = readl(ioaddr + MAC_CONTROL); | 100 | u32 value = readl(ioaddr + MAC_CONTROL); |
101 | 101 | ||
102 | if (dev->flags & IFF_PROMISC) { | 102 | if (dev->flags & IFF_PROMISC) { |
@@ -145,7 +145,7 @@ static void dwmac100_set_filter(struct net_device *dev) | |||
145 | readl(ioaddr + MAC_HASH_HIGH), readl(ioaddr + MAC_HASH_LOW)); | 145 | readl(ioaddr + MAC_HASH_HIGH), readl(ioaddr + MAC_HASH_LOW)); |
146 | } | 146 | } |
147 | 147 | ||
148 | static void dwmac100_flow_ctrl(unsigned long ioaddr, unsigned int duplex, | 148 | static void dwmac100_flow_ctrl(void __iomem *ioaddr, unsigned int duplex, |
149 | unsigned int fc, unsigned int pause_time) | 149 | unsigned int fc, unsigned int pause_time) |
150 | { | 150 | { |
151 | unsigned int flow = MAC_FLOW_CTRL_ENABLE; | 151 | unsigned int flow = MAC_FLOW_CTRL_ENABLE; |
@@ -158,7 +158,7 @@ static void dwmac100_flow_ctrl(unsigned long ioaddr, unsigned int duplex, | |||
158 | /* No PMT module supported for this Ethernet Controller. | 158 | /* No PMT module supported for this Ethernet Controller. |
159 | * Tested on ST platforms only. | 159 | * Tested on ST platforms only. |
160 | */ | 160 | */ |
161 | static void dwmac100_pmt(unsigned long ioaddr, unsigned long mode) | 161 | static void dwmac100_pmt(void __iomem *ioaddr, unsigned long mode) |
162 | { | 162 | { |
163 | return; | 163 | return; |
164 | } | 164 | } |
@@ -174,7 +174,7 @@ struct stmmac_ops dwmac100_ops = { | |||
174 | .get_umac_addr = dwmac100_get_umac_addr, | 174 | .get_umac_addr = dwmac100_get_umac_addr, |
175 | }; | 175 | }; |
176 | 176 | ||
177 | struct mac_device_info *dwmac100_setup(unsigned long ioaddr) | 177 | struct mac_device_info *dwmac100_setup(void __iomem *ioaddr) |
178 | { | 178 | { |
179 | struct mac_device_info *mac; | 179 | struct mac_device_info *mac; |
180 | 180 | ||
diff --git a/drivers/net/stmmac/dwmac100_dma.c b/drivers/net/stmmac/dwmac100_dma.c index 2fece7b72727..c7279d2b946b 100644 --- a/drivers/net/stmmac/dwmac100_dma.c +++ b/drivers/net/stmmac/dwmac100_dma.c | |||
@@ -31,7 +31,7 @@ | |||
31 | #include "dwmac100.h" | 31 | #include "dwmac100.h" |
32 | #include "dwmac_dma.h" | 32 | #include "dwmac_dma.h" |
33 | 33 | ||
34 | static int dwmac100_dma_init(unsigned long ioaddr, int pbl, u32 dma_tx, | 34 | static int dwmac100_dma_init(void __iomem *ioaddr, int pbl, u32 dma_tx, |
35 | u32 dma_rx) | 35 | u32 dma_rx) |
36 | { | 36 | { |
37 | u32 value = readl(ioaddr + DMA_BUS_MODE); | 37 | u32 value = readl(ioaddr + DMA_BUS_MODE); |
@@ -58,7 +58,7 @@ static int dwmac100_dma_init(unsigned long ioaddr, int pbl, u32 dma_tx, | |||
58 | /* Store and Forward capability is not used at all.. | 58 | /* Store and Forward capability is not used at all.. |
59 | * The transmit threshold can be programmed by | 59 | * The transmit threshold can be programmed by |
60 | * setting the TTC bits in the DMA control register.*/ | 60 | * setting the TTC bits in the DMA control register.*/ |
61 | static void dwmac100_dma_operation_mode(unsigned long ioaddr, int txmode, | 61 | static void dwmac100_dma_operation_mode(void __iomem *ioaddr, int txmode, |
62 | int rxmode) | 62 | int rxmode) |
63 | { | 63 | { |
64 | u32 csr6 = readl(ioaddr + DMA_CONTROL); | 64 | u32 csr6 = readl(ioaddr + DMA_CONTROL); |
@@ -73,7 +73,7 @@ static void dwmac100_dma_operation_mode(unsigned long ioaddr, int txmode, | |||
73 | writel(csr6, ioaddr + DMA_CONTROL); | 73 | writel(csr6, ioaddr + DMA_CONTROL); |
74 | } | 74 | } |
75 | 75 | ||
76 | static void dwmac100_dump_dma_regs(unsigned long ioaddr) | 76 | static void dwmac100_dump_dma_regs(void __iomem *ioaddr) |
77 | { | 77 | { |
78 | int i; | 78 | int i; |
79 | 79 | ||
@@ -91,7 +91,7 @@ static void dwmac100_dump_dma_regs(unsigned long ioaddr) | |||
91 | /* DMA controller has two counters to track the number of | 91 | /* DMA controller has two counters to track the number of |
92 | * the receive missed frames. */ | 92 | * the receive missed frames. */ |
93 | static void dwmac100_dma_diagnostic_fr(void *data, struct stmmac_extra_stats *x, | 93 | static void dwmac100_dma_diagnostic_fr(void *data, struct stmmac_extra_stats *x, |
94 | unsigned long ioaddr) | 94 | void __iomem *ioaddr) |
95 | { | 95 | { |
96 | struct net_device_stats *stats = (struct net_device_stats *)data; | 96 | struct net_device_stats *stats = (struct net_device_stats *)data; |
97 | u32 csr8 = readl(ioaddr + DMA_MISSED_FRAME_CTR); | 97 | u32 csr8 = readl(ioaddr + DMA_MISSED_FRAME_CTR); |
diff --git a/drivers/net/stmmac/dwmac_dma.h b/drivers/net/stmmac/dwmac_dma.h index 7b815a1b7b8c..da3f5ccf83d3 100644 --- a/drivers/net/stmmac/dwmac_dma.h +++ b/drivers/net/stmmac/dwmac_dma.h | |||
@@ -97,12 +97,12 @@ | |||
97 | #define DMA_STATUS_TI 0x00000001 /* Transmit Interrupt */ | 97 | #define DMA_STATUS_TI 0x00000001 /* Transmit Interrupt */ |
98 | #define DMA_CONTROL_FTF 0x00100000 /* Flush transmit FIFO */ | 98 | #define DMA_CONTROL_FTF 0x00100000 /* Flush transmit FIFO */ |
99 | 99 | ||
100 | extern void dwmac_enable_dma_transmission(unsigned long ioaddr); | 100 | extern void dwmac_enable_dma_transmission(void __iomem *ioaddr); |
101 | extern void dwmac_enable_dma_irq(unsigned long ioaddr); | 101 | extern void dwmac_enable_dma_irq(void __iomem *ioaddr); |
102 | extern void dwmac_disable_dma_irq(unsigned long ioaddr); | 102 | extern void dwmac_disable_dma_irq(void __iomem *ioaddr); |
103 | extern void dwmac_dma_start_tx(unsigned long ioaddr); | 103 | extern void dwmac_dma_start_tx(void __iomem *ioaddr); |
104 | extern void dwmac_dma_stop_tx(unsigned long ioaddr); | 104 | extern void dwmac_dma_stop_tx(void __iomem *ioaddr); |
105 | extern void dwmac_dma_start_rx(unsigned long ioaddr); | 105 | extern void dwmac_dma_start_rx(void __iomem *ioaddr); |
106 | extern void dwmac_dma_stop_rx(unsigned long ioaddr); | 106 | extern void dwmac_dma_stop_rx(void __iomem *ioaddr); |
107 | extern int dwmac_dma_interrupt(unsigned long ioaddr, | 107 | extern int dwmac_dma_interrupt(void __iomem *ioaddr, |
108 | struct stmmac_extra_stats *x); | 108 | struct stmmac_extra_stats *x); |
diff --git a/drivers/net/stmmac/dwmac_lib.c b/drivers/net/stmmac/dwmac_lib.c index a85415216ef4..d65fab1ba790 100644 --- a/drivers/net/stmmac/dwmac_lib.c +++ b/drivers/net/stmmac/dwmac_lib.c | |||
@@ -32,43 +32,43 @@ | |||
32 | #endif | 32 | #endif |
33 | 33 | ||
34 | /* CSR1 enables the transmit DMA to check for new descriptor */ | 34 | /* CSR1 enables the transmit DMA to check for new descriptor */ |
35 | void dwmac_enable_dma_transmission(unsigned long ioaddr) | 35 | void dwmac_enable_dma_transmission(void __iomem *ioaddr) |
36 | { | 36 | { |
37 | writel(1, ioaddr + DMA_XMT_POLL_DEMAND); | 37 | writel(1, ioaddr + DMA_XMT_POLL_DEMAND); |
38 | } | 38 | } |
39 | 39 | ||
40 | void dwmac_enable_dma_irq(unsigned long ioaddr) | 40 | void dwmac_enable_dma_irq(void __iomem *ioaddr) |
41 | { | 41 | { |
42 | writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA); | 42 | writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA); |
43 | } | 43 | } |
44 | 44 | ||
45 | void dwmac_disable_dma_irq(unsigned long ioaddr) | 45 | void dwmac_disable_dma_irq(void __iomem *ioaddr) |
46 | { | 46 | { |
47 | writel(0, ioaddr + DMA_INTR_ENA); | 47 | writel(0, ioaddr + DMA_INTR_ENA); |
48 | } | 48 | } |
49 | 49 | ||
50 | void dwmac_dma_start_tx(unsigned long ioaddr) | 50 | void dwmac_dma_start_tx(void __iomem *ioaddr) |
51 | { | 51 | { |
52 | u32 value = readl(ioaddr + DMA_CONTROL); | 52 | u32 value = readl(ioaddr + DMA_CONTROL); |
53 | value |= DMA_CONTROL_ST; | 53 | value |= DMA_CONTROL_ST; |
54 | writel(value, ioaddr + DMA_CONTROL); | 54 | writel(value, ioaddr + DMA_CONTROL); |
55 | } | 55 | } |
56 | 56 | ||
57 | void dwmac_dma_stop_tx(unsigned long ioaddr) | 57 | void dwmac_dma_stop_tx(void __iomem *ioaddr) |
58 | { | 58 | { |
59 | u32 value = readl(ioaddr + DMA_CONTROL); | 59 | u32 value = readl(ioaddr + DMA_CONTROL); |
60 | value &= ~DMA_CONTROL_ST; | 60 | value &= ~DMA_CONTROL_ST; |
61 | writel(value, ioaddr + DMA_CONTROL); | 61 | writel(value, ioaddr + DMA_CONTROL); |
62 | } | 62 | } |
63 | 63 | ||
64 | void dwmac_dma_start_rx(unsigned long ioaddr) | 64 | void dwmac_dma_start_rx(void __iomem *ioaddr) |
65 | { | 65 | { |
66 | u32 value = readl(ioaddr + DMA_CONTROL); | 66 | u32 value = readl(ioaddr + DMA_CONTROL); |
67 | value |= DMA_CONTROL_SR; | 67 | value |= DMA_CONTROL_SR; |
68 | writel(value, ioaddr + DMA_CONTROL); | 68 | writel(value, ioaddr + DMA_CONTROL); |
69 | } | 69 | } |
70 | 70 | ||
71 | void dwmac_dma_stop_rx(unsigned long ioaddr) | 71 | void dwmac_dma_stop_rx(void __iomem *ioaddr) |
72 | { | 72 | { |
73 | u32 value = readl(ioaddr + DMA_CONTROL); | 73 | u32 value = readl(ioaddr + DMA_CONTROL); |
74 | value &= ~DMA_CONTROL_SR; | 74 | value &= ~DMA_CONTROL_SR; |
@@ -145,7 +145,7 @@ static void show_rx_process_state(unsigned int status) | |||
145 | } | 145 | } |
146 | #endif | 146 | #endif |
147 | 147 | ||
148 | int dwmac_dma_interrupt(unsigned long ioaddr, | 148 | int dwmac_dma_interrupt(void __iomem *ioaddr, |
149 | struct stmmac_extra_stats *x) | 149 | struct stmmac_extra_stats *x) |
150 | { | 150 | { |
151 | int ret = 0; | 151 | int ret = 0; |
@@ -219,7 +219,7 @@ int dwmac_dma_interrupt(unsigned long ioaddr, | |||
219 | return ret; | 219 | return ret; |
220 | } | 220 | } |
221 | 221 | ||
222 | void dwmac_dma_flush_tx_fifo(unsigned long ioaddr) | 222 | void dwmac_dma_flush_tx_fifo(void __iomem *ioaddr) |
223 | { | 223 | { |
224 | u32 csr6 = readl(ioaddr + DMA_CONTROL); | 224 | u32 csr6 = readl(ioaddr + DMA_CONTROL); |
225 | writel((csr6 | DMA_CONTROL_FTF), ioaddr + DMA_CONTROL); | 225 | writel((csr6 | DMA_CONTROL_FTF), ioaddr + DMA_CONTROL); |
@@ -227,7 +227,7 @@ void dwmac_dma_flush_tx_fifo(unsigned long ioaddr) | |||
227 | do {} while ((readl(ioaddr + DMA_CONTROL) & DMA_CONTROL_FTF)); | 227 | do {} while ((readl(ioaddr + DMA_CONTROL) & DMA_CONTROL_FTF)); |
228 | } | 228 | } |
229 | 229 | ||
230 | void stmmac_set_mac_addr(unsigned long ioaddr, u8 addr[6], | 230 | void stmmac_set_mac_addr(void __iomem *ioaddr, u8 addr[6], |
231 | unsigned int high, unsigned int low) | 231 | unsigned int high, unsigned int low) |
232 | { | 232 | { |
233 | unsigned long data; | 233 | unsigned long data; |
@@ -238,7 +238,7 @@ void stmmac_set_mac_addr(unsigned long ioaddr, u8 addr[6], | |||
238 | writel(data, ioaddr + low); | 238 | writel(data, ioaddr + low); |
239 | } | 239 | } |
240 | 240 | ||
241 | void stmmac_get_mac_addr(unsigned long ioaddr, unsigned char *addr, | 241 | void stmmac_get_mac_addr(void __iomem *ioaddr, unsigned char *addr, |
242 | unsigned int high, unsigned int low) | 242 | unsigned int high, unsigned int low) |
243 | { | 243 | { |
244 | unsigned int hi_addr, lo_addr; | 244 | unsigned int hi_addr, lo_addr; |
diff --git a/drivers/net/stmmac/enh_desc.c b/drivers/net/stmmac/enh_desc.c index f612f986a7e1..77ff88c3958b 100644 --- a/drivers/net/stmmac/enh_desc.c +++ b/drivers/net/stmmac/enh_desc.c | |||
@@ -25,7 +25,7 @@ | |||
25 | #include "common.h" | 25 | #include "common.h" |
26 | 26 | ||
27 | static int enh_desc_get_tx_status(void *data, struct stmmac_extra_stats *x, | 27 | static int enh_desc_get_tx_status(void *data, struct stmmac_extra_stats *x, |
28 | struct dma_desc *p, unsigned long ioaddr) | 28 | struct dma_desc *p, void __iomem *ioaddr) |
29 | { | 29 | { |
30 | int ret = 0; | 30 | int ret = 0; |
31 | struct net_device_stats *stats = (struct net_device_stats *)data; | 31 | struct net_device_stats *stats = (struct net_device_stats *)data; |
diff --git a/drivers/net/stmmac/norm_desc.c b/drivers/net/stmmac/norm_desc.c index 31ad53643792..51f4440ab98b 100644 --- a/drivers/net/stmmac/norm_desc.c +++ b/drivers/net/stmmac/norm_desc.c | |||
@@ -25,7 +25,7 @@ | |||
25 | #include "common.h" | 25 | #include "common.h" |
26 | 26 | ||
27 | static int ndesc_get_tx_status(void *data, struct stmmac_extra_stats *x, | 27 | static int ndesc_get_tx_status(void *data, struct stmmac_extra_stats *x, |
28 | struct dma_desc *p, unsigned long ioaddr) | 28 | struct dma_desc *p, void __iomem *ioaddr) |
29 | { | 29 | { |
30 | int ret = 0; | 30 | int ret = 0; |
31 | struct net_device_stats *stats = (struct net_device_stats *)data; | 31 | struct net_device_stats *stats = (struct net_device_stats *)data; |
diff --git a/drivers/net/stmmac/stmmac.h b/drivers/net/stmmac/stmmac.h index ebebc644b1b8..cca53dbac361 100644 --- a/drivers/net/stmmac/stmmac.h +++ b/drivers/net/stmmac/stmmac.h | |||
@@ -54,6 +54,7 @@ struct stmmac_priv { | |||
54 | unsigned int dma_buf_sz; | 54 | unsigned int dma_buf_sz; |
55 | struct device *device; | 55 | struct device *device; |
56 | struct mac_device_info *hw; | 56 | struct mac_device_info *hw; |
57 | void __iomem *ioaddr; | ||
57 | 58 | ||
58 | struct stmmac_extra_stats xstats; | 59 | struct stmmac_extra_stats xstats; |
59 | struct napi_struct napi; | 60 | struct napi_struct napi; |
@@ -65,7 +66,7 @@ struct stmmac_priv { | |||
65 | int phy_mask; | 66 | int phy_mask; |
66 | int (*phy_reset) (void *priv); | 67 | int (*phy_reset) (void *priv); |
67 | void (*fix_mac_speed) (void *priv, unsigned int speed); | 68 | void (*fix_mac_speed) (void *priv, unsigned int speed); |
68 | void (*bus_setup)(unsigned long ioaddr); | 69 | void (*bus_setup)(void __iomem *ioaddr); |
69 | void *bsp_priv; | 70 | void *bsp_priv; |
70 | 71 | ||
71 | int phy_irq; | 72 | int phy_irq; |
diff --git a/drivers/net/stmmac/stmmac_ethtool.c b/drivers/net/stmmac/stmmac_ethtool.c index f080509923f0..63b68e61afce 100644 --- a/drivers/net/stmmac/stmmac_ethtool.c +++ b/drivers/net/stmmac/stmmac_ethtool.c | |||
@@ -177,21 +177,21 @@ void stmmac_ethtool_gregs(struct net_device *dev, | |||
177 | if (!priv->is_gmac) { | 177 | if (!priv->is_gmac) { |
178 | /* MAC registers */ | 178 | /* MAC registers */ |
179 | for (i = 0; i < 12; i++) | 179 | for (i = 0; i < 12; i++) |
180 | reg_space[i] = readl(dev->base_addr + (i * 4)); | 180 | reg_space[i] = readl(priv->ioaddr + (i * 4)); |
181 | /* DMA registers */ | 181 | /* DMA registers */ |
182 | for (i = 0; i < 9; i++) | 182 | for (i = 0; i < 9; i++) |
183 | reg_space[i + 12] = | 183 | reg_space[i + 12] = |
184 | readl(dev->base_addr + (DMA_BUS_MODE + (i * 4))); | 184 | readl(priv->ioaddr + (DMA_BUS_MODE + (i * 4))); |
185 | reg_space[22] = readl(dev->base_addr + DMA_CUR_TX_BUF_ADDR); | 185 | reg_space[22] = readl(priv->ioaddr + DMA_CUR_TX_BUF_ADDR); |
186 | reg_space[23] = readl(dev->base_addr + DMA_CUR_RX_BUF_ADDR); | 186 | reg_space[23] = readl(priv->ioaddr + DMA_CUR_RX_BUF_ADDR); |
187 | } else { | 187 | } else { |
188 | /* MAC registers */ | 188 | /* MAC registers */ |
189 | for (i = 0; i < 55; i++) | 189 | for (i = 0; i < 55; i++) |
190 | reg_space[i] = readl(dev->base_addr + (i * 4)); | 190 | reg_space[i] = readl(priv->ioaddr + (i * 4)); |
191 | /* DMA registers */ | 191 | /* DMA registers */ |
192 | for (i = 0; i < 22; i++) | 192 | for (i = 0; i < 22; i++) |
193 | reg_space[i + 55] = | 193 | reg_space[i + 55] = |
194 | readl(dev->base_addr + (DMA_BUS_MODE + (i * 4))); | 194 | readl(priv->ioaddr + (DMA_BUS_MODE + (i * 4))); |
195 | } | 195 | } |
196 | } | 196 | } |
197 | 197 | ||
@@ -263,11 +263,9 @@ stmmac_set_pauseparam(struct net_device *netdev, | |||
263 | cmd.phy_address = phy->addr; | 263 | cmd.phy_address = phy->addr; |
264 | ret = phy_ethtool_sset(phy, &cmd); | 264 | ret = phy_ethtool_sset(phy, &cmd); |
265 | } | 265 | } |
266 | } else { | 266 | } else |
267 | unsigned long ioaddr = netdev->base_addr; | 267 | priv->hw->mac->flow_ctrl(priv->ioaddr, phy->duplex, |
268 | priv->hw->mac->flow_ctrl(ioaddr, phy->duplex, | ||
269 | priv->flow_ctrl, priv->pause); | 268 | priv->flow_ctrl, priv->pause); |
270 | } | ||
271 | spin_unlock(&priv->lock); | 269 | spin_unlock(&priv->lock); |
272 | return ret; | 270 | return ret; |
273 | } | 271 | } |
@@ -276,12 +274,11 @@ static void stmmac_get_ethtool_stats(struct net_device *dev, | |||
276 | struct ethtool_stats *dummy, u64 *data) | 274 | struct ethtool_stats *dummy, u64 *data) |
277 | { | 275 | { |
278 | struct stmmac_priv *priv = netdev_priv(dev); | 276 | struct stmmac_priv *priv = netdev_priv(dev); |
279 | unsigned long ioaddr = dev->base_addr; | ||
280 | int i; | 277 | int i; |
281 | 278 | ||
282 | /* Update HW stats if supported */ | 279 | /* Update HW stats if supported */ |
283 | priv->hw->dma->dma_diagnostic_fr(&dev->stats, (void *) &priv->xstats, | 280 | priv->hw->dma->dma_diagnostic_fr(&dev->stats, (void *) &priv->xstats, |
284 | ioaddr); | 281 | priv->ioaddr); |
285 | 282 | ||
286 | for (i = 0; i < STMMAC_STATS_LEN; i++) { | 283 | for (i = 0; i < STMMAC_STATS_LEN; i++) { |
287 | char *p = (char *)priv + stmmac_gstrings_stats[i].stat_offset; | 284 | char *p = (char *)priv + stmmac_gstrings_stats[i].stat_offset; |
diff --git a/drivers/net/stmmac/stmmac_main.c b/drivers/net/stmmac/stmmac_main.c index 86b6c69c068c..c59c1061252a 100644 --- a/drivers/net/stmmac/stmmac_main.c +++ b/drivers/net/stmmac/stmmac_main.c | |||
@@ -202,7 +202,6 @@ static void stmmac_adjust_link(struct net_device *dev) | |||
202 | { | 202 | { |
203 | struct stmmac_priv *priv = netdev_priv(dev); | 203 | struct stmmac_priv *priv = netdev_priv(dev); |
204 | struct phy_device *phydev = priv->phydev; | 204 | struct phy_device *phydev = priv->phydev; |
205 | unsigned long ioaddr = dev->base_addr; | ||
206 | unsigned long flags; | 205 | unsigned long flags; |
207 | int new_state = 0; | 206 | int new_state = 0; |
208 | unsigned int fc = priv->flow_ctrl, pause_time = priv->pause; | 207 | unsigned int fc = priv->flow_ctrl, pause_time = priv->pause; |
@@ -215,7 +214,7 @@ static void stmmac_adjust_link(struct net_device *dev) | |||
215 | 214 | ||
216 | spin_lock_irqsave(&priv->lock, flags); | 215 | spin_lock_irqsave(&priv->lock, flags); |
217 | if (phydev->link) { | 216 | if (phydev->link) { |
218 | u32 ctrl = readl(ioaddr + MAC_CTRL_REG); | 217 | u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG); |
219 | 218 | ||
220 | /* Now we make sure that we can be in full duplex mode. | 219 | /* Now we make sure that we can be in full duplex mode. |
221 | * If not, we operate in half-duplex mode. */ | 220 | * If not, we operate in half-duplex mode. */ |
@@ -229,7 +228,7 @@ static void stmmac_adjust_link(struct net_device *dev) | |||
229 | } | 228 | } |
230 | /* Flow Control operation */ | 229 | /* Flow Control operation */ |
231 | if (phydev->pause) | 230 | if (phydev->pause) |
232 | priv->hw->mac->flow_ctrl(ioaddr, phydev->duplex, | 231 | priv->hw->mac->flow_ctrl(priv->ioaddr, phydev->duplex, |
233 | fc, pause_time); | 232 | fc, pause_time); |
234 | 233 | ||
235 | if (phydev->speed != priv->speed) { | 234 | if (phydev->speed != priv->speed) { |
@@ -268,7 +267,7 @@ static void stmmac_adjust_link(struct net_device *dev) | |||
268 | priv->speed = phydev->speed; | 267 | priv->speed = phydev->speed; |
269 | } | 268 | } |
270 | 269 | ||
271 | writel(ctrl, ioaddr + MAC_CTRL_REG); | 270 | writel(ctrl, priv->ioaddr + MAC_CTRL_REG); |
272 | 271 | ||
273 | if (!priv->oldlink) { | 272 | if (!priv->oldlink) { |
274 | new_state = 1; | 273 | new_state = 1; |
@@ -345,7 +344,7 @@ static int stmmac_init_phy(struct net_device *dev) | |||
345 | return 0; | 344 | return 0; |
346 | } | 345 | } |
347 | 346 | ||
348 | static inline void stmmac_mac_enable_rx(unsigned long ioaddr) | 347 | static inline void stmmac_mac_enable_rx(void __iomem *ioaddr) |
349 | { | 348 | { |
350 | u32 value = readl(ioaddr + MAC_CTRL_REG); | 349 | u32 value = readl(ioaddr + MAC_CTRL_REG); |
351 | value |= MAC_RNABLE_RX; | 350 | value |= MAC_RNABLE_RX; |
@@ -353,7 +352,7 @@ static inline void stmmac_mac_enable_rx(unsigned long ioaddr) | |||
353 | writel(value, ioaddr + MAC_CTRL_REG); | 352 | writel(value, ioaddr + MAC_CTRL_REG); |
354 | } | 353 | } |
355 | 354 | ||
356 | static inline void stmmac_mac_enable_tx(unsigned long ioaddr) | 355 | static inline void stmmac_mac_enable_tx(void __iomem *ioaddr) |
357 | { | 356 | { |
358 | u32 value = readl(ioaddr + MAC_CTRL_REG); | 357 | u32 value = readl(ioaddr + MAC_CTRL_REG); |
359 | value |= MAC_ENABLE_TX; | 358 | value |= MAC_ENABLE_TX; |
@@ -361,14 +360,14 @@ static inline void stmmac_mac_enable_tx(unsigned long ioaddr) | |||
361 | writel(value, ioaddr + MAC_CTRL_REG); | 360 | writel(value, ioaddr + MAC_CTRL_REG); |
362 | } | 361 | } |
363 | 362 | ||
364 | static inline void stmmac_mac_disable_rx(unsigned long ioaddr) | 363 | static inline void stmmac_mac_disable_rx(void __iomem *ioaddr) |
365 | { | 364 | { |
366 | u32 value = readl(ioaddr + MAC_CTRL_REG); | 365 | u32 value = readl(ioaddr + MAC_CTRL_REG); |
367 | value &= ~MAC_RNABLE_RX; | 366 | value &= ~MAC_RNABLE_RX; |
368 | writel(value, ioaddr + MAC_CTRL_REG); | 367 | writel(value, ioaddr + MAC_CTRL_REG); |
369 | } | 368 | } |
370 | 369 | ||
371 | static inline void stmmac_mac_disable_tx(unsigned long ioaddr) | 370 | static inline void stmmac_mac_disable_tx(void __iomem *ioaddr) |
372 | { | 371 | { |
373 | u32 value = readl(ioaddr + MAC_CTRL_REG); | 372 | u32 value = readl(ioaddr + MAC_CTRL_REG); |
374 | value &= ~MAC_ENABLE_TX; | 373 | value &= ~MAC_ENABLE_TX; |
@@ -577,17 +576,17 @@ static void stmmac_dma_operation_mode(struct stmmac_priv *priv) | |||
577 | { | 576 | { |
578 | if (!priv->is_gmac) { | 577 | if (!priv->is_gmac) { |
579 | /* MAC 10/100 */ | 578 | /* MAC 10/100 */ |
580 | priv->hw->dma->dma_mode(priv->dev->base_addr, tc, 0); | 579 | priv->hw->dma->dma_mode(priv->ioaddr, tc, 0); |
581 | priv->tx_coe = NO_HW_CSUM; | 580 | priv->tx_coe = NO_HW_CSUM; |
582 | } else { | 581 | } else { |
583 | if ((priv->dev->mtu <= ETH_DATA_LEN) && (tx_coe)) { | 582 | if ((priv->dev->mtu <= ETH_DATA_LEN) && (tx_coe)) { |
584 | priv->hw->dma->dma_mode(priv->dev->base_addr, | 583 | priv->hw->dma->dma_mode(priv->ioaddr, |
585 | SF_DMA_MODE, SF_DMA_MODE); | 584 | SF_DMA_MODE, SF_DMA_MODE); |
586 | tc = SF_DMA_MODE; | 585 | tc = SF_DMA_MODE; |
587 | priv->tx_coe = HW_CSUM; | 586 | priv->tx_coe = HW_CSUM; |
588 | } else { | 587 | } else { |
589 | /* Checksum computation is performed in software. */ | 588 | /* Checksum computation is performed in software. */ |
590 | priv->hw->dma->dma_mode(priv->dev->base_addr, tc, | 589 | priv->hw->dma->dma_mode(priv->ioaddr, tc, |
591 | SF_DMA_MODE); | 590 | SF_DMA_MODE); |
592 | priv->tx_coe = NO_HW_CSUM; | 591 | priv->tx_coe = NO_HW_CSUM; |
593 | } | 592 | } |
@@ -603,7 +602,6 @@ static void stmmac_dma_operation_mode(struct stmmac_priv *priv) | |||
603 | static void stmmac_tx(struct stmmac_priv *priv) | 602 | static void stmmac_tx(struct stmmac_priv *priv) |
604 | { | 603 | { |
605 | unsigned int txsize = priv->dma_tx_size; | 604 | unsigned int txsize = priv->dma_tx_size; |
606 | unsigned long ioaddr = priv->dev->base_addr; | ||
607 | 605 | ||
608 | while (priv->dirty_tx != priv->cur_tx) { | 606 | while (priv->dirty_tx != priv->cur_tx) { |
609 | int last; | 607 | int last; |
@@ -621,7 +619,7 @@ static void stmmac_tx(struct stmmac_priv *priv) | |||
621 | int tx_error = | 619 | int tx_error = |
622 | priv->hw->desc->tx_status(&priv->dev->stats, | 620 | priv->hw->desc->tx_status(&priv->dev->stats, |
623 | &priv->xstats, p, | 621 | &priv->xstats, p, |
624 | ioaddr); | 622 | priv->ioaddr); |
625 | if (likely(tx_error == 0)) { | 623 | if (likely(tx_error == 0)) { |
626 | priv->dev->stats.tx_packets++; | 624 | priv->dev->stats.tx_packets++; |
627 | priv->xstats.tx_pkt_n++; | 625 | priv->xstats.tx_pkt_n++; |
@@ -677,7 +675,7 @@ static inline void stmmac_enable_irq(struct stmmac_priv *priv) | |||
677 | priv->tm->timer_start(tmrate); | 675 | priv->tm->timer_start(tmrate); |
678 | else | 676 | else |
679 | #endif | 677 | #endif |
680 | priv->hw->dma->enable_dma_irq(priv->dev->base_addr); | 678 | priv->hw->dma->enable_dma_irq(priv->ioaddr); |
681 | } | 679 | } |
682 | 680 | ||
683 | static inline void stmmac_disable_irq(struct stmmac_priv *priv) | 681 | static inline void stmmac_disable_irq(struct stmmac_priv *priv) |
@@ -687,7 +685,7 @@ static inline void stmmac_disable_irq(struct stmmac_priv *priv) | |||
687 | priv->tm->timer_stop(); | 685 | priv->tm->timer_stop(); |
688 | else | 686 | else |
689 | #endif | 687 | #endif |
690 | priv->hw->dma->disable_dma_irq(priv->dev->base_addr); | 688 | priv->hw->dma->disable_dma_irq(priv->ioaddr); |
691 | } | 689 | } |
692 | 690 | ||
693 | static int stmmac_has_work(struct stmmac_priv *priv) | 691 | static int stmmac_has_work(struct stmmac_priv *priv) |
@@ -742,14 +740,15 @@ static void stmmac_no_timer_stopped(void) | |||
742 | */ | 740 | */ |
743 | static void stmmac_tx_err(struct stmmac_priv *priv) | 741 | static void stmmac_tx_err(struct stmmac_priv *priv) |
744 | { | 742 | { |
743 | |||
745 | netif_stop_queue(priv->dev); | 744 | netif_stop_queue(priv->dev); |
746 | 745 | ||
747 | priv->hw->dma->stop_tx(priv->dev->base_addr); | 746 | priv->hw->dma->stop_tx(priv->ioaddr); |
748 | dma_free_tx_skbufs(priv); | 747 | dma_free_tx_skbufs(priv); |
749 | priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size); | 748 | priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size); |
750 | priv->dirty_tx = 0; | 749 | priv->dirty_tx = 0; |
751 | priv->cur_tx = 0; | 750 | priv->cur_tx = 0; |
752 | priv->hw->dma->start_tx(priv->dev->base_addr); | 751 | priv->hw->dma->start_tx(priv->ioaddr); |
753 | 752 | ||
754 | priv->dev->stats.tx_errors++; | 753 | priv->dev->stats.tx_errors++; |
755 | netif_wake_queue(priv->dev); | 754 | netif_wake_queue(priv->dev); |
@@ -758,11 +757,9 @@ static void stmmac_tx_err(struct stmmac_priv *priv) | |||
758 | 757 | ||
759 | static void stmmac_dma_interrupt(struct stmmac_priv *priv) | 758 | static void stmmac_dma_interrupt(struct stmmac_priv *priv) |
760 | { | 759 | { |
761 | unsigned long ioaddr = priv->dev->base_addr; | ||
762 | int status; | 760 | int status; |
763 | 761 | ||
764 | status = priv->hw->dma->dma_interrupt(priv->dev->base_addr, | 762 | status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats); |
765 | &priv->xstats); | ||
766 | if (likely(status == handle_tx_rx)) | 763 | if (likely(status == handle_tx_rx)) |
767 | _stmmac_schedule(priv); | 764 | _stmmac_schedule(priv); |
768 | 765 | ||
@@ -770,7 +767,7 @@ static void stmmac_dma_interrupt(struct stmmac_priv *priv) | |||
770 | /* Try to bump up the dma threshold on this failure */ | 767 | /* Try to bump up the dma threshold on this failure */ |
771 | if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) { | 768 | if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) { |
772 | tc += 64; | 769 | tc += 64; |
773 | priv->hw->dma->dma_mode(ioaddr, tc, SF_DMA_MODE); | 770 | priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE); |
774 | priv->xstats.threshold = tc; | 771 | priv->xstats.threshold = tc; |
775 | } | 772 | } |
776 | stmmac_tx_err(priv); | 773 | stmmac_tx_err(priv); |
@@ -790,7 +787,6 @@ static void stmmac_dma_interrupt(struct stmmac_priv *priv) | |||
790 | static int stmmac_open(struct net_device *dev) | 787 | static int stmmac_open(struct net_device *dev) |
791 | { | 788 | { |
792 | struct stmmac_priv *priv = netdev_priv(dev); | 789 | struct stmmac_priv *priv = netdev_priv(dev); |
793 | unsigned long ioaddr = dev->base_addr; | ||
794 | int ret; | 790 | int ret; |
795 | 791 | ||
796 | /* Check that the MAC address is valid. If its not, refuse | 792 | /* Check that the MAC address is valid. If its not, refuse |
@@ -846,7 +842,8 @@ static int stmmac_open(struct net_device *dev) | |||
846 | init_dma_desc_rings(dev); | 842 | init_dma_desc_rings(dev); |
847 | 843 | ||
848 | /* DMA initialization and SW reset */ | 844 | /* DMA initialization and SW reset */ |
849 | if (unlikely(priv->hw->dma->init(ioaddr, priv->pbl, priv->dma_tx_phy, | 845 | if (unlikely(priv->hw->dma->init(priv->ioaddr, priv->pbl, |
846 | priv->dma_tx_phy, | ||
850 | priv->dma_rx_phy) < 0)) { | 847 | priv->dma_rx_phy) < 0)) { |
851 | 848 | ||
852 | pr_err("%s: DMA initialization failed\n", __func__); | 849 | pr_err("%s: DMA initialization failed\n", __func__); |
@@ -854,22 +851,22 @@ static int stmmac_open(struct net_device *dev) | |||
854 | } | 851 | } |
855 | 852 | ||
856 | /* Copy the MAC addr into the HW */ | 853 | /* Copy the MAC addr into the HW */ |
857 | priv->hw->mac->set_umac_addr(ioaddr, dev->dev_addr, 0); | 854 | priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0); |
858 | /* If required, perform hw setup of the bus. */ | 855 | /* If required, perform hw setup of the bus. */ |
859 | if (priv->bus_setup) | 856 | if (priv->bus_setup) |
860 | priv->bus_setup(ioaddr); | 857 | priv->bus_setup(priv->ioaddr); |
861 | /* Initialize the MAC Core */ | 858 | /* Initialize the MAC Core */ |
862 | priv->hw->mac->core_init(ioaddr); | 859 | priv->hw->mac->core_init(priv->ioaddr); |
863 | 860 | ||
864 | priv->shutdown = 0; | 861 | priv->shutdown = 0; |
865 | 862 | ||
866 | /* Initialise the MMC (if present) to disable all interrupts. */ | 863 | /* Initialise the MMC (if present) to disable all interrupts. */ |
867 | writel(0xffffffff, ioaddr + MMC_HIGH_INTR_MASK); | 864 | writel(0xffffffff, priv->ioaddr + MMC_HIGH_INTR_MASK); |
868 | writel(0xffffffff, ioaddr + MMC_LOW_INTR_MASK); | 865 | writel(0xffffffff, priv->ioaddr + MMC_LOW_INTR_MASK); |
869 | 866 | ||
870 | /* Enable the MAC Rx/Tx */ | 867 | /* Enable the MAC Rx/Tx */ |
871 | stmmac_mac_enable_rx(ioaddr); | 868 | stmmac_mac_enable_rx(priv->ioaddr); |
872 | stmmac_mac_enable_tx(ioaddr); | 869 | stmmac_mac_enable_tx(priv->ioaddr); |
873 | 870 | ||
874 | /* Set the HW DMA mode and the COE */ | 871 | /* Set the HW DMA mode and the COE */ |
875 | stmmac_dma_operation_mode(priv); | 872 | stmmac_dma_operation_mode(priv); |
@@ -880,16 +877,16 @@ static int stmmac_open(struct net_device *dev) | |||
880 | 877 | ||
881 | /* Start the ball rolling... */ | 878 | /* Start the ball rolling... */ |
882 | DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name); | 879 | DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name); |
883 | priv->hw->dma->start_tx(ioaddr); | 880 | priv->hw->dma->start_tx(priv->ioaddr); |
884 | priv->hw->dma->start_rx(ioaddr); | 881 | priv->hw->dma->start_rx(priv->ioaddr); |
885 | 882 | ||
886 | #ifdef CONFIG_STMMAC_TIMER | 883 | #ifdef CONFIG_STMMAC_TIMER |
887 | priv->tm->timer_start(tmrate); | 884 | priv->tm->timer_start(tmrate); |
888 | #endif | 885 | #endif |
889 | /* Dump DMA/MAC registers */ | 886 | /* Dump DMA/MAC registers */ |
890 | if (netif_msg_hw(priv)) { | 887 | if (netif_msg_hw(priv)) { |
891 | priv->hw->mac->dump_regs(ioaddr); | 888 | priv->hw->mac->dump_regs(priv->ioaddr); |
892 | priv->hw->dma->dump_regs(ioaddr); | 889 | priv->hw->dma->dump_regs(priv->ioaddr); |
893 | } | 890 | } |
894 | 891 | ||
895 | if (priv->phydev) | 892 | if (priv->phydev) |
@@ -933,15 +930,15 @@ static int stmmac_release(struct net_device *dev) | |||
933 | free_irq(dev->irq, dev); | 930 | free_irq(dev->irq, dev); |
934 | 931 | ||
935 | /* Stop TX/RX DMA and clear the descriptors */ | 932 | /* Stop TX/RX DMA and clear the descriptors */ |
936 | priv->hw->dma->stop_tx(dev->base_addr); | 933 | priv->hw->dma->stop_tx(priv->ioaddr); |
937 | priv->hw->dma->stop_rx(dev->base_addr); | 934 | priv->hw->dma->stop_rx(priv->ioaddr); |
938 | 935 | ||
939 | /* Release and free the Rx/Tx resources */ | 936 | /* Release and free the Rx/Tx resources */ |
940 | free_dma_desc_resources(priv); | 937 | free_dma_desc_resources(priv); |
941 | 938 | ||
942 | /* Disable the MAC core */ | 939 | /* Disable the MAC core */ |
943 | stmmac_mac_disable_tx(dev->base_addr); | 940 | stmmac_mac_disable_tx(priv->ioaddr); |
944 | stmmac_mac_disable_rx(dev->base_addr); | 941 | stmmac_mac_disable_rx(priv->ioaddr); |
945 | 942 | ||
946 | netif_carrier_off(dev); | 943 | netif_carrier_off(dev); |
947 | 944 | ||
@@ -1143,7 +1140,7 @@ static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) | |||
1143 | 1140 | ||
1144 | dev->stats.tx_bytes += skb->len; | 1141 | dev->stats.tx_bytes += skb->len; |
1145 | 1142 | ||
1146 | priv->hw->dma->enable_dma_transmission(dev->base_addr); | 1143 | priv->hw->dma->enable_dma_transmission(priv->ioaddr); |
1147 | 1144 | ||
1148 | return NETDEV_TX_OK; | 1145 | return NETDEV_TX_OK; |
1149 | } | 1146 | } |
@@ -1408,11 +1405,9 @@ static irqreturn_t stmmac_interrupt(int irq, void *dev_id) | |||
1408 | return IRQ_NONE; | 1405 | return IRQ_NONE; |
1409 | } | 1406 | } |
1410 | 1407 | ||
1411 | if (priv->is_gmac) { | 1408 | if (priv->is_gmac) |
1412 | unsigned long ioaddr = dev->base_addr; | ||
1413 | /* To handle GMAC own interrupts */ | 1409 | /* To handle GMAC own interrupts */ |
1414 | priv->hw->mac->host_irq_status(ioaddr); | 1410 | priv->hw->mac->host_irq_status((void __iomem *) dev->base_addr); |
1415 | } | ||
1416 | 1411 | ||
1417 | stmmac_dma_interrupt(priv); | 1412 | stmmac_dma_interrupt(priv); |
1418 | 1413 | ||
@@ -1525,7 +1520,8 @@ static int stmmac_probe(struct net_device *dev) | |||
1525 | netif_napi_add(dev, &priv->napi, stmmac_poll, 64); | 1520 | netif_napi_add(dev, &priv->napi, stmmac_poll, 64); |
1526 | 1521 | ||
1527 | /* Get the MAC address */ | 1522 | /* Get the MAC address */ |
1528 | priv->hw->mac->get_umac_addr(dev->base_addr, dev->dev_addr, 0); | 1523 | priv->hw->mac->get_umac_addr((void __iomem *) dev->base_addr, |
1524 | dev->dev_addr, 0); | ||
1529 | 1525 | ||
1530 | if (!is_valid_ether_addr(dev->dev_addr)) | 1526 | if (!is_valid_ether_addr(dev->dev_addr)) |
1531 | pr_warning("\tno valid MAC address;" | 1527 | pr_warning("\tno valid MAC address;" |
@@ -1555,14 +1551,13 @@ static int stmmac_probe(struct net_device *dev) | |||
1555 | static int stmmac_mac_device_setup(struct net_device *dev) | 1551 | static int stmmac_mac_device_setup(struct net_device *dev) |
1556 | { | 1552 | { |
1557 | struct stmmac_priv *priv = netdev_priv(dev); | 1553 | struct stmmac_priv *priv = netdev_priv(dev); |
1558 | unsigned long ioaddr = dev->base_addr; | ||
1559 | 1554 | ||
1560 | struct mac_device_info *device; | 1555 | struct mac_device_info *device; |
1561 | 1556 | ||
1562 | if (priv->is_gmac) | 1557 | if (priv->is_gmac) |
1563 | device = dwmac1000_setup(ioaddr); | 1558 | device = dwmac1000_setup(priv->ioaddr); |
1564 | else | 1559 | else |
1565 | device = dwmac100_setup(ioaddr); | 1560 | device = dwmac100_setup(priv->ioaddr); |
1566 | 1561 | ||
1567 | if (!device) | 1562 | if (!device) |
1568 | return -ENOMEM; | 1563 | return -ENOMEM; |
@@ -1656,7 +1651,7 @@ static int stmmac_dvr_probe(struct platform_device *pdev) | |||
1656 | { | 1651 | { |
1657 | int ret = 0; | 1652 | int ret = 0; |
1658 | struct resource *res; | 1653 | struct resource *res; |
1659 | unsigned int *addr = NULL; | 1654 | void __iomem *addr = NULL; |
1660 | struct net_device *ndev = NULL; | 1655 | struct net_device *ndev = NULL; |
1661 | struct stmmac_priv *priv; | 1656 | struct stmmac_priv *priv; |
1662 | struct plat_stmmacenet_data *plat_dat; | 1657 | struct plat_stmmacenet_data *plat_dat; |
@@ -1711,6 +1706,7 @@ static int stmmac_dvr_probe(struct platform_device *pdev) | |||
1711 | priv->pbl = plat_dat->pbl; /* TLI */ | 1706 | priv->pbl = plat_dat->pbl; /* TLI */ |
1712 | priv->is_gmac = plat_dat->has_gmac; /* GMAC is on board */ | 1707 | priv->is_gmac = plat_dat->has_gmac; /* GMAC is on board */ |
1713 | priv->enh_desc = plat_dat->enh_desc; | 1708 | priv->enh_desc = plat_dat->enh_desc; |
1709 | priv->ioaddr = addr; | ||
1714 | 1710 | ||
1715 | platform_set_drvdata(pdev, ndev); | 1711 | platform_set_drvdata(pdev, ndev); |
1716 | 1712 | ||
@@ -1782,11 +1778,11 @@ static int stmmac_dvr_remove(struct platform_device *pdev) | |||
1782 | 1778 | ||
1783 | pr_info("%s:\n\tremoving driver", __func__); | 1779 | pr_info("%s:\n\tremoving driver", __func__); |
1784 | 1780 | ||
1785 | priv->hw->dma->stop_rx(ndev->base_addr); | 1781 | priv->hw->dma->stop_rx(priv->ioaddr); |
1786 | priv->hw->dma->stop_tx(ndev->base_addr); | 1782 | priv->hw->dma->stop_tx(priv->ioaddr); |
1787 | 1783 | ||
1788 | stmmac_mac_disable_rx(ndev->base_addr); | 1784 | stmmac_mac_disable_rx(priv->ioaddr); |
1789 | stmmac_mac_disable_tx(ndev->base_addr); | 1785 | stmmac_mac_disable_tx(priv->ioaddr); |
1790 | 1786 | ||
1791 | netif_carrier_off(ndev); | 1787 | netif_carrier_off(ndev); |
1792 | 1788 | ||
@@ -1795,7 +1791,7 @@ static int stmmac_dvr_remove(struct platform_device *pdev) | |||
1795 | platform_set_drvdata(pdev, NULL); | 1791 | platform_set_drvdata(pdev, NULL); |
1796 | unregister_netdev(ndev); | 1792 | unregister_netdev(ndev); |
1797 | 1793 | ||
1798 | iounmap((void *)ndev->base_addr); | 1794 | iounmap((void *)priv->ioaddr); |
1799 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | 1795 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1800 | release_mem_region(res->start, resource_size(res)); | 1796 | release_mem_region(res->start, resource_size(res)); |
1801 | 1797 | ||
@@ -1830,22 +1826,21 @@ static int stmmac_suspend(struct platform_device *pdev, pm_message_t state) | |||
1830 | napi_disable(&priv->napi); | 1826 | napi_disable(&priv->napi); |
1831 | 1827 | ||
1832 | /* Stop TX/RX DMA */ | 1828 | /* Stop TX/RX DMA */ |
1833 | priv->hw->dma->stop_tx(dev->base_addr); | 1829 | priv->hw->dma->stop_tx(priv->ioaddr); |
1834 | priv->hw->dma->stop_rx(dev->base_addr); | 1830 | priv->hw->dma->stop_rx(priv->ioaddr); |
1835 | /* Clear the Rx/Tx descriptors */ | 1831 | /* Clear the Rx/Tx descriptors */ |
1836 | priv->hw->desc->init_rx_desc(priv->dma_rx, priv->dma_rx_size, | 1832 | priv->hw->desc->init_rx_desc(priv->dma_rx, priv->dma_rx_size, |
1837 | dis_ic); | 1833 | dis_ic); |
1838 | priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size); | 1834 | priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size); |
1839 | 1835 | ||
1840 | stmmac_mac_disable_tx(dev->base_addr); | 1836 | stmmac_mac_disable_tx(priv->ioaddr); |
1841 | 1837 | ||
1842 | if (device_may_wakeup(&(pdev->dev))) { | 1838 | if (device_may_wakeup(&(pdev->dev))) { |
1843 | /* Enable Power down mode by programming the PMT regs */ | 1839 | /* Enable Power down mode by programming the PMT regs */ |
1844 | if (priv->wolenabled == PMT_SUPPORTED) | 1840 | if (priv->wolenabled == PMT_SUPPORTED) |
1845 | priv->hw->mac->pmt(dev->base_addr, | 1841 | priv->hw->mac->pmt(priv->ioaddr, priv->wolopts); |
1846 | priv->wolopts); | ||
1847 | } else { | 1842 | } else { |
1848 | stmmac_mac_disable_rx(dev->base_addr); | 1843 | stmmac_mac_disable_rx(priv->ioaddr); |
1849 | } | 1844 | } |
1850 | } else { | 1845 | } else { |
1851 | priv->shutdown = 1; | 1846 | priv->shutdown = 1; |
@@ -1863,7 +1858,6 @@ static int stmmac_resume(struct platform_device *pdev) | |||
1863 | { | 1858 | { |
1864 | struct net_device *dev = platform_get_drvdata(pdev); | 1859 | struct net_device *dev = platform_get_drvdata(pdev); |
1865 | struct stmmac_priv *priv = netdev_priv(dev); | 1860 | struct stmmac_priv *priv = netdev_priv(dev); |
1866 | unsigned long ioaddr = dev->base_addr; | ||
1867 | 1861 | ||
1868 | if (!netif_running(dev)) | 1862 | if (!netif_running(dev)) |
1869 | return 0; | 1863 | return 0; |
@@ -1884,15 +1878,15 @@ static int stmmac_resume(struct platform_device *pdev) | |||
1884 | * from another devices (e.g. serial console). */ | 1878 | * from another devices (e.g. serial console). */ |
1885 | if (device_may_wakeup(&(pdev->dev))) | 1879 | if (device_may_wakeup(&(pdev->dev))) |
1886 | if (priv->wolenabled == PMT_SUPPORTED) | 1880 | if (priv->wolenabled == PMT_SUPPORTED) |
1887 | priv->hw->mac->pmt(dev->base_addr, 0); | 1881 | priv->hw->mac->pmt(priv->ioaddr, 0); |
1888 | 1882 | ||
1889 | netif_device_attach(dev); | 1883 | netif_device_attach(dev); |
1890 | 1884 | ||
1891 | /* Enable the MAC and DMA */ | 1885 | /* Enable the MAC and DMA */ |
1892 | stmmac_mac_enable_rx(ioaddr); | 1886 | stmmac_mac_enable_rx(priv->ioaddr); |
1893 | stmmac_mac_enable_tx(ioaddr); | 1887 | stmmac_mac_enable_tx(priv->ioaddr); |
1894 | priv->hw->dma->start_tx(ioaddr); | 1888 | priv->hw->dma->start_tx(priv->ioaddr); |
1895 | priv->hw->dma->start_rx(ioaddr); | 1889 | priv->hw->dma->start_rx(priv->ioaddr); |
1896 | 1890 | ||
1897 | #ifdef CONFIG_STMMAC_TIMER | 1891 | #ifdef CONFIG_STMMAC_TIMER |
1898 | priv->tm->timer_start(tmrate); | 1892 | priv->tm->timer_start(tmrate); |
diff --git a/drivers/net/stmmac/stmmac_mdio.c b/drivers/net/stmmac/stmmac_mdio.c index 40b2c7929719..03dea1401571 100644 --- a/drivers/net/stmmac/stmmac_mdio.c +++ b/drivers/net/stmmac/stmmac_mdio.c | |||
@@ -47,7 +47,6 @@ static int stmmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg) | |||
47 | { | 47 | { |
48 | struct net_device *ndev = bus->priv; | 48 | struct net_device *ndev = bus->priv; |
49 | struct stmmac_priv *priv = netdev_priv(ndev); | 49 | struct stmmac_priv *priv = netdev_priv(ndev); |
50 | unsigned long ioaddr = ndev->base_addr; | ||
51 | unsigned int mii_address = priv->hw->mii.addr; | 50 | unsigned int mii_address = priv->hw->mii.addr; |
52 | unsigned int mii_data = priv->hw->mii.data; | 51 | unsigned int mii_data = priv->hw->mii.data; |
53 | 52 | ||
@@ -56,12 +55,12 @@ static int stmmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg) | |||
56 | ((phyreg << 6) & (0x000007C0))); | 55 | ((phyreg << 6) & (0x000007C0))); |
57 | regValue |= MII_BUSY; /* in case of GMAC */ | 56 | regValue |= MII_BUSY; /* in case of GMAC */ |
58 | 57 | ||
59 | do {} while (((readl(ioaddr + mii_address)) & MII_BUSY) == 1); | 58 | do {} while (((readl(priv->ioaddr + mii_address)) & MII_BUSY) == 1); |
60 | writel(regValue, ioaddr + mii_address); | 59 | writel(regValue, priv->ioaddr + mii_address); |
61 | do {} while (((readl(ioaddr + mii_address)) & MII_BUSY) == 1); | 60 | do {} while (((readl(priv->ioaddr + mii_address)) & MII_BUSY) == 1); |
62 | 61 | ||
63 | /* Read the data from the MII data register */ | 62 | /* Read the data from the MII data register */ |
64 | data = (int)readl(ioaddr + mii_data); | 63 | data = (int)readl(priv->ioaddr + mii_data); |
65 | 64 | ||
66 | return data; | 65 | return data; |
67 | } | 66 | } |
@@ -79,7 +78,6 @@ static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg, | |||
79 | { | 78 | { |
80 | struct net_device *ndev = bus->priv; | 79 | struct net_device *ndev = bus->priv; |
81 | struct stmmac_priv *priv = netdev_priv(ndev); | 80 | struct stmmac_priv *priv = netdev_priv(ndev); |
82 | unsigned long ioaddr = ndev->base_addr; | ||
83 | unsigned int mii_address = priv->hw->mii.addr; | 81 | unsigned int mii_address = priv->hw->mii.addr; |
84 | unsigned int mii_data = priv->hw->mii.data; | 82 | unsigned int mii_data = priv->hw->mii.data; |
85 | 83 | ||
@@ -90,14 +88,14 @@ static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg, | |||
90 | value |= MII_BUSY; | 88 | value |= MII_BUSY; |
91 | 89 | ||
92 | /* Wait until any existing MII operation is complete */ | 90 | /* Wait until any existing MII operation is complete */ |
93 | do {} while (((readl(ioaddr + mii_address)) & MII_BUSY) == 1); | 91 | do {} while (((readl(priv->ioaddr + mii_address)) & MII_BUSY) == 1); |
94 | 92 | ||
95 | /* Set the MII address register to write */ | 93 | /* Set the MII address register to write */ |
96 | writel(phydata, ioaddr + mii_data); | 94 | writel(phydata, priv->ioaddr + mii_data); |
97 | writel(value, ioaddr + mii_address); | 95 | writel(value, priv->ioaddr + mii_address); |
98 | 96 | ||
99 | /* Wait until any existing MII operation is complete */ | 97 | /* Wait until any existing MII operation is complete */ |
100 | do {} while (((readl(ioaddr + mii_address)) & MII_BUSY) == 1); | 98 | do {} while (((readl(priv->ioaddr + mii_address)) & MII_BUSY) == 1); |
101 | 99 | ||
102 | return 0; | 100 | return 0; |
103 | } | 101 | } |
@@ -111,7 +109,6 @@ static int stmmac_mdio_reset(struct mii_bus *bus) | |||
111 | { | 109 | { |
112 | struct net_device *ndev = bus->priv; | 110 | struct net_device *ndev = bus->priv; |
113 | struct stmmac_priv *priv = netdev_priv(ndev); | 111 | struct stmmac_priv *priv = netdev_priv(ndev); |
114 | unsigned long ioaddr = ndev->base_addr; | ||
115 | unsigned int mii_address = priv->hw->mii.addr; | 112 | unsigned int mii_address = priv->hw->mii.addr; |
116 | 113 | ||
117 | if (priv->phy_reset) { | 114 | if (priv->phy_reset) { |
@@ -123,7 +120,7 @@ static int stmmac_mdio_reset(struct mii_bus *bus) | |||
123 | * It doesn't complete its reset until at least one clock cycle | 120 | * It doesn't complete its reset until at least one clock cycle |
124 | * on MDC, so perform a dummy mdio read. | 121 | * on MDC, so perform a dummy mdio read. |
125 | */ | 122 | */ |
126 | writel(0, ioaddr + mii_address); | 123 | writel(0, priv->ioaddr + mii_address); |
127 | 124 | ||
128 | return 0; | 125 | return 0; |
129 | } | 126 | } |