14 files changed, 98 insertions, 20 deletions

diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c
index 5bf825dfaa09..8d74de82456e 100644
--- a/drivers/gpu/drm/radeon/atombios_dp.c
+++ b/drivers/gpu/drm/radeon/atombios_dp.c
@@ -178,6 +178,13 @@ radeon_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
         switch (msg->request & ~DP_AUX_I2C_MOT) {
         case DP_AUX_NATIVE_WRITE:
         case DP_AUX_I2C_WRITE:
+                /* The atom implementation only supports writes with a max payload of
+                 * 12 bytes since it uses 4 bits for the total count (header + payload)
+                 * in the parameter space.  The atom interface supports 16 byte
+                 * payloads for reads. The hw itself supports up to 16 bytes of payload.
+                 */
+                if (WARN_ON_ONCE(msg->size > 12))
+                        return -E2BIG;
                 /* tx_size needs to be 4 even for bare address packets since the atom
                  * table needs the info in tx_buf[3].
                  */
diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c b/drivers/gpu/drm/radeon/atombios_encoders.c
index 7c9df1eac065..7fe7b749e182 100644
--- a/drivers/gpu/drm/radeon/atombios_encoders.c
+++ b/drivers/gpu/drm/radeon/atombios_encoders.c
@@ -731,7 +731,9 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
                 dig_connector = radeon_connector->con_priv;
                 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
                     (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
-                        if (radeon_audio != 0 && ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
+                        if (radeon_audio != 0 &&
+                            drm_detect_monitor_audio(radeon_connector_edid(connector)) &&
+                            ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
                                 return ATOM_ENCODER_MODE_DP_AUDIO;
                         return ATOM_ENCODER_MODE_DP;
                 } else if (radeon_audio != 0) {
@@ -747,7 +749,9 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
                 }
                 break;
         case DRM_MODE_CONNECTOR_eDP:
-                if (radeon_audio != 0 && ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
+                if (radeon_audio != 0 &&
+                    drm_detect_monitor_audio(radeon_connector_edid(connector)) &&
+                    ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
                         return ATOM_ENCODER_MODE_DP_AUDIO;
                 return ATOM_ENCODER_MODE_DP;
         case DRM_MODE_CONNECTOR_DVIA:
@@ -1720,8 +1724,10 @@ radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
         }
 
         encoder_mode = atombios_get_encoder_mode(encoder);
-        if (radeon_audio != 0 &&
-                (encoder_mode == ATOM_ENCODER_MODE_HDMI || ENCODER_MODE_IS_DP(encoder_mode)))
+        if (connector && (radeon_audio != 0) &&
+            ((encoder_mode == ATOM_ENCODER_MODE_HDMI) ||
+             (ENCODER_MODE_IS_DP(encoder_mode) &&
+              drm_detect_monitor_audio(radeon_connector_edid(connector)))))
                 radeon_audio_dpms(encoder, mode);
 }
 
@@ -2136,6 +2142,7 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
         struct drm_device *dev = encoder->dev;
         struct radeon_device *rdev = dev->dev_private;
         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+        struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
         int encoder_mode;
 
         radeon_encoder->pixel_clock = adjusted_mode->clock;
@@ -2164,8 +2171,10 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
                 /* handled in dpms */
                 encoder_mode = atombios_get_encoder_mode(encoder);
-                if (radeon_audio != 0 &&
-                        (encoder_mode == ATOM_ENCODER_MODE_HDMI || ENCODER_MODE_IS_DP(encoder_mode)))
+                if (connector && (radeon_audio != 0) &&
+                    ((encoder_mode == ATOM_ENCODER_MODE_HDMI) ||
+                     (ENCODER_MODE_IS_DP(encoder_mode) &&
+                      drm_detect_monitor_audio(radeon_connector_edid(connector)))))
                         radeon_audio_mode_set(encoder, adjusted_mode);
                 break;
         case ENCODER_OBJECT_ID_INTERNAL_DDI:
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index e6a4ba236c70..0c993da9c8fb 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -3613,6 +3613,8 @@ static void cik_gpu_init(struct radeon_device *rdev)
         }
 
         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
+        WREG32(SRBM_INT_CNTL, 0x1);
+        WREG32(SRBM_INT_ACK, 0x1);
 
         WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
 
@@ -7230,6 +7232,8 @@ static void cik_disable_interrupt_state(struct radeon_device *rdev)
         WREG32(CP_ME2_PIPE3_INT_CNTL, 0);
         /* grbm */
         WREG32(GRBM_INT_CNTL, 0);
+        /* SRBM */
+        WREG32(SRBM_INT_CNTL, 0);
         /* vline/vblank, etc. */
         WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
         WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
@@ -8046,6 +8050,10 @@ restart_ih:
                                 break;
                         }
                         break;
+                case 96:
+                        DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR));
+                        WREG32(SRBM_INT_ACK, 0x1);
+                        break;
                 case 124: /* UVD */
                         DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data);
                         radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);
diff --git a/drivers/gpu/drm/radeon/cikd.h b/drivers/gpu/drm/radeon/cikd.h
index 03003f8a6de6..c648e1996dab 100644
--- a/drivers/gpu/drm/radeon/cikd.h
+++ b/drivers/gpu/drm/radeon/cikd.h
@@ -482,6 +482,10 @@
 #define         SOFT_RESET_ORB                          (1 << 23)
 #define         SOFT_RESET_VCE                          (1 << 24)
 
+#define SRBM_READ_ERROR                                 0xE98
+#define SRBM_INT_CNTL                                   0xEA0
+#define SRBM_INT_ACK                                    0xEA8
+
 #define VM_L2_CNTL                                      0x1400
 #define         ENABLE_L2_CACHE                                 (1 << 0)
 #define         ENABLE_L2_FRAGMENT_PROCESSING                   (1 << 1)
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 78600f534c80..4c0e24b3bb90 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -3253,6 +3253,8 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
         }
 
         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
+        WREG32(SRBM_INT_CNTL, 0x1);
+        WREG32(SRBM_INT_ACK, 0x1);
 
         evergreen_fix_pci_max_read_req_size(rdev);
 
@@ -4324,6 +4326,7 @@ void evergreen_disable_interrupt_state(struct radeon_device *rdev)
         tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
         WREG32(DMA_CNTL, tmp);
         WREG32(GRBM_INT_CNTL, 0);
+        WREG32(SRBM_INT_CNTL, 0);
         WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
         WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
         if (rdev->num_crtc >= 4) {
@@ -5066,6 +5069,10 @@ restart_ih:
                                 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
                                 break;
                         }
+                case 96:
+                        DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR));
+                        WREG32(SRBM_INT_ACK, 0x1);
+                        break;
                 case 124: /* UVD */
                         DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data);
                         radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index ee83d2a88750..a8d1d5240fcb 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -1191,6 +1191,10 @@
 #define         SOFT_RESET_REGBB                        (1 << 22)
 #define         SOFT_RESET_ORB                          (1 << 23)
 
+#define SRBM_READ_ERROR                                 0xE98
+#define SRBM_INT_CNTL                                   0xEA0
+#define SRBM_INT_ACK                                    0xEA8
+
 /* display watermarks */
 #define DC_LB_MEMORY_SPLIT                                0x6b0c
 #define PRIORITY_A_CNT                                    0x6b18
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 24242a7f0ac3..dab00812abaa 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -962,6 +962,8 @@ static void cayman_gpu_init(struct radeon_device *rdev)
         }
 
         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
+        WREG32(SRBM_INT_CNTL, 0x1);
+        WREG32(SRBM_INT_ACK, 0x1);
 
         evergreen_fix_pci_max_read_req_size(rdev);
 
@@ -1086,12 +1088,12 @@ static void cayman_gpu_init(struct radeon_device *rdev)
 
         if ((rdev->config.cayman.max_backends_per_se == 1) &&
             (rdev->flags & RADEON_IS_IGP)) {
-                if ((disabled_rb_mask & 3) == 1) {
-                        /* RB0 disabled, RB1 enabled */
-                        tmp = 0x11111111;
-                } else {
+                if ((disabled_rb_mask & 3) == 2) {
                         /* RB1 disabled, RB0 enabled */
                         tmp = 0x00000000;
+                } else {
+                        /* RB0 disabled, RB1 enabled */
+                        tmp = 0x11111111;
                 }
         } else {
                 tmp = gb_addr_config & NUM_PIPES_MASK;
diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h
index ad7125486894..6b44580440d0 100644
--- a/drivers/gpu/drm/radeon/nid.h
+++ b/drivers/gpu/drm/radeon/nid.h
@@ -82,6 +82,10 @@
 #define         SOFT_RESET_REGBB                        (1 << 22)
 #define         SOFT_RESET_ORB                          (1 << 23)
 
+#define SRBM_READ_ERROR                                 0xE98
+#define SRBM_INT_CNTL                                   0xEA0
+#define SRBM_INT_ACK                                    0xEA8
+
 #define SRBM_STATUS2                                    0x0EC4
 #define         DMA_BUSY                                (1 << 5)
 #define         DMA1_BUSY                               (1 << 6)
diff --git a/drivers/gpu/drm/radeon/r600_dpm.c b/drivers/gpu/drm/radeon/r600_dpm.c
index 843b65f46ece..fa2154493cf1 100644
--- a/drivers/gpu/drm/radeon/r600_dpm.c
+++ b/drivers/gpu/drm/radeon/r600_dpm.c
@@ -188,7 +188,7 @@ u32 r600_dpm_get_vrefresh(struct radeon_device *rdev)
                 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
                         radeon_crtc = to_radeon_crtc(crtc);
                         if (crtc->enabled && radeon_crtc->enabled && radeon_crtc->hw_mode.clock) {
-                                vrefresh = radeon_crtc->hw_mode.vrefresh;
+                                vrefresh = drm_mode_vrefresh(&radeon_crtc->hw_mode);
                                 break;
                         }
                 }
diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c
index c830863bc98a..a579ed379f20 100644
--- a/drivers/gpu/drm/radeon/radeon_cs.c
+++ b/drivers/gpu/drm/radeon/radeon_cs.c
@@ -715,6 +715,7 @@ int radeon_cs_packet_parse(struct radeon_cs_parser *p,
         struct radeon_cs_chunk *ib_chunk = p->chunk_ib;
         struct radeon_device *rdev = p->rdev;
         uint32_t header;
+        int ret = 0, i;
 
         if (idx >= ib_chunk->length_dw) {
                 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
@@ -743,14 +744,25 @@ int radeon_cs_packet_parse(struct radeon_cs_parser *p,
                 break;
         default:
                 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
-                return -EINVAL;
+                ret = -EINVAL;
+                goto dump_ib;
         }
         if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
                 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
                           pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
-                return -EINVAL;
+                ret = -EINVAL;
+                goto dump_ib;
         }
         return 0;
+
+dump_ib:
+        for (i = 0; i < ib_chunk->length_dw; i++) {
+                if (i == idx)
+                        printk("\t0x%08x <---\n", radeon_get_ib_value(p, i));
+                else
+                        printk("\t0x%08x\n", radeon_get_ib_value(p, i));
+        }
+        return ret;
 }
 
 /**
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
index 6b670b0bc47b..3a297037cc17 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -179,9 +179,12 @@ static void radeon_encoder_add_backlight(struct radeon_encoder *radeon_encoder,
                     (rdev->pdev->subsystem_vendor == 0x1734) &&
                     (rdev->pdev->subsystem_device == 0x1107))
                         use_bl = false;
+/* Older PPC macs use on-GPU backlight controller */
+#ifndef CONFIG_PPC_PMAC
                 /* disable native backlight control on older asics */
                 else if (rdev->family < CHIP_R600)
                         use_bl = false;
+#endif
                 else
                         use_bl = true;
         }
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
index 9f758d39420d..33cf4108386d 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -852,6 +852,12 @@ static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
                         single_display = false;
         }
 
+        /* 120hz tends to be problematic even if they are under the
+         * vblank limit.
+         */
+        if (single_display && (r600_dpm_get_vrefresh(rdev) >= 120))
+                single_display = false;
+
         /* certain older asics have a separare 3D performance state,
          * so try that first if the user selected performance
          */
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 73107fe9e46f..bcf516a8a2f1 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -3162,6 +3162,8 @@ static void si_gpu_init(struct radeon_device *rdev)
         }
 
         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
+        WREG32(SRBM_INT_CNTL, 1);
+        WREG32(SRBM_INT_ACK, 1);
 
         evergreen_fix_pci_max_read_req_size(rdev);
 
@@ -4699,12 +4701,6 @@ int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
                 switch (pkt.type) {
                 case RADEON_PACKET_TYPE0:
                         dev_err(rdev->dev, "Packet0 not allowed!\n");
-                        for (i = 0; i < ib->length_dw; i++) {
-                                if (i == idx)
-                                        printk("\t0x%08x <---\n", ib->ptr[i]);
-                                else
-                                        printk("\t0x%08x\n", ib->ptr[i]);
-                        }
                         ret = -EINVAL;
                         break;
                 case RADEON_PACKET_TYPE2:
@@ -4736,8 +4732,15 @@ int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
                         ret = -EINVAL;
                         break;
                 }
-                if (ret)
+                if (ret) {
+                        for (i = 0; i < ib->length_dw; i++) {
+                                if (i == idx)
+                                        printk("\t0x%08x <---\n", ib->ptr[i]);
+                                else
+                                        printk("\t0x%08x\n", ib->ptr[i]);
+                        }
                         break;
+                }
         } while (idx < ib->length_dw);
 
         return ret;
@@ -5910,6 +5913,7 @@ static void si_disable_interrupt_state(struct radeon_device *rdev)
         tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
         WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp);
         WREG32(GRBM_INT_CNTL, 0);
+        WREG32(SRBM_INT_CNTL, 0);
         if (rdev->num_crtc >= 2) {
                 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
                 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
@@ -6609,6 +6613,10 @@ restart_ih:
                                 break;
                         }
                         break;
+                case 96:
+                        DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR));
+                        WREG32(SRBM_INT_ACK, 0x1);
+                        break;
                 case 124: /* UVD */
                         DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data);
                         radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);
diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h
index cbd91d226f3c..c27118cab16a 100644
--- a/drivers/gpu/drm/radeon/sid.h
+++ b/drivers/gpu/drm/radeon/sid.h
@@ -358,6 +358,10 @@
 #define CC_SYS_RB_BACKEND_DISABLE                       0xe80
 #define GC_USER_SYS_RB_BACKEND_DISABLE                  0xe84
 
+#define SRBM_READ_ERROR                                 0xE98
+#define SRBM_INT_CNTL                                   0xEA0
+#define SRBM_INT_ACK                                    0xEA8
+
 #define SRBM_STATUS2                                    0x0EC4
 #define         DMA_BUSY                                (1 << 5)
 #define         DMA1_BUSY                               (1 << 6)