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-rw-r--r--drivers/i2c/Kconfig10
-rw-r--r--drivers/i2c/Makefile1
-rw-r--r--drivers/i2c/busses/Kconfig20
-rw-r--r--drivers/i2c/busses/Makefile2
-rw-r--r--drivers/i2c/busses/i2c-at91.c127
-rw-r--r--drivers/i2c/busses/i2c-davinci.c24
-rw-r--r--drivers/i2c/busses/i2c-exynos5.c4
-rw-r--r--drivers/i2c/busses/i2c-i801.c57
-rw-r--r--drivers/i2c/busses/i2c-img-scb.c1412
-rw-r--r--drivers/i2c/busses/i2c-imx.c354
-rw-r--r--drivers/i2c/busses/i2c-meson.c492
-rw-r--r--drivers/i2c/busses/i2c-mpc.c18
-rw-r--r--drivers/i2c/busses/i2c-mxs.c2
-rw-r--r--drivers/i2c/busses/i2c-omap.c133
-rw-r--r--drivers/i2c/busses/i2c-pxa.c19
-rw-r--r--drivers/i2c/busses/i2c-rcar.c124
-rw-r--r--drivers/i2c/busses/i2c-rk3x.c251
-rw-r--r--drivers/i2c/busses/i2c-s3c2410.c29
-rw-r--r--drivers/i2c/busses/i2c-sh_mobile.c244
-rw-r--r--drivers/i2c/busses/i2c-xiic.c58
-rw-r--r--drivers/i2c/i2c-core.c64
-rw-r--r--drivers/i2c/i2c-mux.c12
-rw-r--r--drivers/i2c/i2c-slave-eeprom.c170
-rw-r--r--drivers/misc/eeprom/at24.c35
-rw-r--r--drivers/of/irq.c1
25 files changed, 3486 insertions, 177 deletions
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index b51a402752c4..8c9e619f3026 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -110,6 +110,16 @@ config I2C_STUB
110 110
111 If you don't know what to do here, definitely say N. 111 If you don't know what to do here, definitely say N.
112 112
113config I2C_SLAVE
114 bool "I2C slave support"
115
116if I2C_SLAVE
117
118config I2C_SLAVE_EEPROM
119 tristate "I2C eeprom slave driver"
120
121endif
122
113config I2C_DEBUG_CORE 123config I2C_DEBUG_CORE
114 bool "I2C Core debugging messages" 124 bool "I2C Core debugging messages"
115 help 125 help
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 1722f50f2473..45095b3d16a9 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -9,6 +9,7 @@ obj-$(CONFIG_I2C_CHARDEV) += i2c-dev.o
9obj-$(CONFIG_I2C_MUX) += i2c-mux.o 9obj-$(CONFIG_I2C_MUX) += i2c-mux.o
10obj-y += algos/ busses/ muxes/ 10obj-y += algos/ busses/ muxes/
11obj-$(CONFIG_I2C_STUB) += i2c-stub.o 11obj-$(CONFIG_I2C_STUB) += i2c-stub.o
12obj-$(CONFIG_I2C_SLAVE_EEPROM) += i2c-slave-eeprom.o
12 13
13ccflags-$(CONFIG_I2C_DEBUG_CORE) := -DDEBUG 14ccflags-$(CONFIG_I2C_DEBUG_CORE) := -DDEBUG
14CFLAGS_i2c-core.o := -Wno-deprecated-declarations 15CFLAGS_i2c-core.o := -Wno-deprecated-declarations
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index b4d135cc2f39..c1351d9fb35b 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -123,6 +123,7 @@ config I2C_I801
123 Wildcat Point-LP (PCH) 123 Wildcat Point-LP (PCH)
124 BayTrail (SOC) 124 BayTrail (SOC)
125 Sunrise Point-H (PCH) 125 Sunrise Point-H (PCH)
126 Sunrise Point-LP (PCH)
126 127
127 This driver can also be built as a module. If so, the module 128 This driver can also be built as a module. If so, the module
128 will be called i2c-i801. 129 will be called i2c-i801.
@@ -523,6 +524,16 @@ config I2C_IBM_IIC
523 This driver can also be built as a module. If so, the module 524 This driver can also be built as a module. If so, the module
524 will be called i2c-ibm_iic. 525 will be called i2c-ibm_iic.
525 526
527config I2C_IMG
528 tristate "Imagination Technologies I2C SCB Controller"
529 depends on MIPS || METAG || COMPILE_TEST
530 help
531 Say Y here if you want to use the IMG I2C SCB controller,
532 available on the TZ1090 and other IMG SoCs.
533
534 This driver can also be built as a module. If so, the module
535 will be called i2c-img-scb.
536
526config I2C_IMX 537config I2C_IMX
527 tristate "IMX I2C interface" 538 tristate "IMX I2C interface"
528 depends on ARCH_MXC 539 depends on ARCH_MXC
@@ -553,6 +564,13 @@ config I2C_KEMPLD
553 This driver can also be built as a module. If so, the module 564 This driver can also be built as a module. If so, the module
554 will be called i2c-kempld. 565 will be called i2c-kempld.
555 566
567config I2C_MESON
568 tristate "Amlogic Meson I2C controller"
569 depends on ARCH_MESON
570 help
571 If you say yes to this option, support will be included for the
572 I2C interface on the Amlogic Meson family of SoCs.
573
556config I2C_MPC 574config I2C_MPC
557 tristate "MPC107/824x/85xx/512x/52xx/83xx/86xx" 575 tristate "MPC107/824x/85xx/512x/52xx/83xx/86xx"
558 depends on PPC 576 depends on PPC
@@ -702,7 +720,7 @@ config I2C_RIIC
702 720
703config I2C_RK3X 721config I2C_RK3X
704 tristate "Rockchip RK3xxx I2C adapter" 722 tristate "Rockchip RK3xxx I2C adapter"
705 depends on OF 723 depends on OF && COMMON_CLK
706 help 724 help
707 Say Y here to include support for the I2C adapter in Rockchip RK3xxx 725 Say Y here to include support for the I2C adapter in Rockchip RK3xxx
708 SoCs. 726 SoCs.
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index cdac7f15eab5..5e6c8223719e 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -50,9 +50,11 @@ obj-$(CONFIG_I2C_GPIO) += i2c-gpio.o
50obj-$(CONFIG_I2C_HIGHLANDER) += i2c-highlander.o 50obj-$(CONFIG_I2C_HIGHLANDER) += i2c-highlander.o
51obj-$(CONFIG_I2C_HIX5HD2) += i2c-hix5hd2.o 51obj-$(CONFIG_I2C_HIX5HD2) += i2c-hix5hd2.o
52obj-$(CONFIG_I2C_IBM_IIC) += i2c-ibm_iic.o 52obj-$(CONFIG_I2C_IBM_IIC) += i2c-ibm_iic.o
53obj-$(CONFIG_I2C_IMG) += i2c-img-scb.o
53obj-$(CONFIG_I2C_IMX) += i2c-imx.o 54obj-$(CONFIG_I2C_IMX) += i2c-imx.o
54obj-$(CONFIG_I2C_IOP3XX) += i2c-iop3xx.o 55obj-$(CONFIG_I2C_IOP3XX) += i2c-iop3xx.o
55obj-$(CONFIG_I2C_KEMPLD) += i2c-kempld.o 56obj-$(CONFIG_I2C_KEMPLD) += i2c-kempld.o
57obj-$(CONFIG_I2C_MESON) += i2c-meson.o
56obj-$(CONFIG_I2C_MPC) += i2c-mpc.o 58obj-$(CONFIG_I2C_MPC) += i2c-mpc.o
57obj-$(CONFIG_I2C_MV64XXX) += i2c-mv64xxx.o 59obj-$(CONFIG_I2C_MV64XXX) += i2c-mv64xxx.o
58obj-$(CONFIG_I2C_MXS) += i2c-mxs.o 60obj-$(CONFIG_I2C_MXS) += i2c-mxs.o
diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c
index e05a672db3e5..87e2f142ae6c 100644
--- a/drivers/i2c/busses/i2c-at91.c
+++ b/drivers/i2c/busses/i2c-at91.c
@@ -31,10 +31,13 @@
31#include <linux/platform_device.h> 31#include <linux/platform_device.h>
32#include <linux/slab.h> 32#include <linux/slab.h>
33#include <linux/platform_data/dma-atmel.h> 33#include <linux/platform_data/dma-atmel.h>
34#include <linux/pm_runtime.h>
35#include <linux/pinctrl/consumer.h>
34 36
35#define DEFAULT_TWI_CLK_HZ 100000 /* max 400 Kbits/s */ 37#define DEFAULT_TWI_CLK_HZ 100000 /* max 400 Kbits/s */
36#define AT91_I2C_TIMEOUT msecs_to_jiffies(100) /* transfer timeout */ 38#define AT91_I2C_TIMEOUT msecs_to_jiffies(100) /* transfer timeout */
37#define AT91_I2C_DMA_THRESHOLD 8 /* enable DMA if transfer size is bigger than this threshold */ 39#define AT91_I2C_DMA_THRESHOLD 8 /* enable DMA if transfer size is bigger than this threshold */
40#define AUTOSUSPEND_TIMEOUT 2000
38 41
39/* AT91 TWI register definitions */ 42/* AT91 TWI register definitions */
40#define AT91_TWI_CR 0x0000 /* Control Register */ 43#define AT91_TWI_CR 0x0000 /* Control Register */
@@ -72,7 +75,6 @@ struct at91_twi_pdata {
72 unsigned clk_max_div; 75 unsigned clk_max_div;
73 unsigned clk_offset; 76 unsigned clk_offset;
74 bool has_unre_flag; 77 bool has_unre_flag;
75 bool has_dma_support;
76 struct at_dma_slave dma_slave; 78 struct at_dma_slave dma_slave;
77}; 79};
78 80
@@ -481,6 +483,10 @@ static int at91_twi_xfer(struct i2c_adapter *adap, struct i2c_msg *msg, int num)
481 483
482 dev_dbg(&adap->dev, "at91_xfer: processing %d messages:\n", num); 484 dev_dbg(&adap->dev, "at91_xfer: processing %d messages:\n", num);
483 485
486 ret = pm_runtime_get_sync(dev->dev);
487 if (ret < 0)
488 goto out;
489
484 /* 490 /*
485 * The hardware can handle at most two messages concatenated by a 491 * The hardware can handle at most two messages concatenated by a
486 * repeated start via it's internal address feature. 492 * repeated start via it's internal address feature.
@@ -488,18 +494,21 @@ static int at91_twi_xfer(struct i2c_adapter *adap, struct i2c_msg *msg, int num)
488 if (num > 2) { 494 if (num > 2) {
489 dev_err(dev->dev, 495 dev_err(dev->dev,
490 "cannot handle more than two concatenated messages.\n"); 496 "cannot handle more than two concatenated messages.\n");
491 return 0; 497 ret = 0;
498 goto out;
492 } else if (num == 2) { 499 } else if (num == 2) {
493 int internal_address = 0; 500 int internal_address = 0;
494 int i; 501 int i;
495 502
496 if (msg->flags & I2C_M_RD) { 503 if (msg->flags & I2C_M_RD) {
497 dev_err(dev->dev, "first transfer must be write.\n"); 504 dev_err(dev->dev, "first transfer must be write.\n");
498 return -EINVAL; 505 ret = -EINVAL;
506 goto out;
499 } 507 }
500 if (msg->len > 3) { 508 if (msg->len > 3) {
501 dev_err(dev->dev, "first message size must be <= 3.\n"); 509 dev_err(dev->dev, "first message size must be <= 3.\n");
502 return -EINVAL; 510 ret = -EINVAL;
511 goto out;
503 } 512 }
504 513
505 /* 1st msg is put into the internal address, start with 2nd */ 514 /* 1st msg is put into the internal address, start with 2nd */
@@ -523,7 +532,12 @@ static int at91_twi_xfer(struct i2c_adapter *adap, struct i2c_msg *msg, int num)
523 532
524 ret = at91_do_twi_transfer(dev); 533 ret = at91_do_twi_transfer(dev);
525 534
526 return (ret < 0) ? ret : num; 535 ret = (ret < 0) ? ret : num;
536out:
537 pm_runtime_mark_last_busy(dev->dev);
538 pm_runtime_put_autosuspend(dev->dev);
539
540 return ret;
527} 541}
528 542
529static u32 at91_twi_func(struct i2c_adapter *adapter) 543static u32 at91_twi_func(struct i2c_adapter *adapter)
@@ -541,35 +555,30 @@ static struct at91_twi_pdata at91rm9200_config = {
541 .clk_max_div = 5, 555 .clk_max_div = 5,
542 .clk_offset = 3, 556 .clk_offset = 3,
543 .has_unre_flag = true, 557 .has_unre_flag = true,
544 .has_dma_support = false,
545}; 558};
546 559
547static struct at91_twi_pdata at91sam9261_config = { 560static struct at91_twi_pdata at91sam9261_config = {
548 .clk_max_div = 5, 561 .clk_max_div = 5,
549 .clk_offset = 4, 562 .clk_offset = 4,
550 .has_unre_flag = false, 563 .has_unre_flag = false,
551 .has_dma_support = false,
552}; 564};
553 565
554static struct at91_twi_pdata at91sam9260_config = { 566static struct at91_twi_pdata at91sam9260_config = {
555 .clk_max_div = 7, 567 .clk_max_div = 7,
556 .clk_offset = 4, 568 .clk_offset = 4,
557 .has_unre_flag = false, 569 .has_unre_flag = false,
558 .has_dma_support = false,
559}; 570};
560 571
561static struct at91_twi_pdata at91sam9g20_config = { 572static struct at91_twi_pdata at91sam9g20_config = {
562 .clk_max_div = 7, 573 .clk_max_div = 7,
563 .clk_offset = 4, 574 .clk_offset = 4,
564 .has_unre_flag = false, 575 .has_unre_flag = false,
565 .has_dma_support = false,
566}; 576};
567 577
568static struct at91_twi_pdata at91sam9g10_config = { 578static struct at91_twi_pdata at91sam9g10_config = {
569 .clk_max_div = 7, 579 .clk_max_div = 7,
570 .clk_offset = 4, 580 .clk_offset = 4,
571 .has_unre_flag = false, 581 .has_unre_flag = false,
572 .has_dma_support = false,
573}; 582};
574 583
575static const struct platform_device_id at91_twi_devtypes[] = { 584static const struct platform_device_id at91_twi_devtypes[] = {
@@ -598,7 +607,6 @@ static struct at91_twi_pdata at91sam9x5_config = {
598 .clk_max_div = 7, 607 .clk_max_div = 7,
599 .clk_offset = 4, 608 .clk_offset = 4,
600 .has_unre_flag = false, 609 .has_unre_flag = false,
601 .has_dma_support = true,
602}; 610};
603 611
604static const struct of_device_id atmel_twi_dt_ids[] = { 612static const struct of_device_id atmel_twi_dt_ids[] = {
@@ -627,30 +635,11 @@ static const struct of_device_id atmel_twi_dt_ids[] = {
627MODULE_DEVICE_TABLE(of, atmel_twi_dt_ids); 635MODULE_DEVICE_TABLE(of, atmel_twi_dt_ids);
628#endif 636#endif
629 637
630static bool filter(struct dma_chan *chan, void *pdata)
631{
632 struct at91_twi_pdata *sl_pdata = pdata;
633 struct at_dma_slave *sl;
634
635 if (!sl_pdata)
636 return false;
637
638 sl = &sl_pdata->dma_slave;
639 if (sl && (sl->dma_dev == chan->device->dev)) {
640 chan->private = sl;
641 return true;
642 } else {
643 return false;
644 }
645}
646
647static int at91_twi_configure_dma(struct at91_twi_dev *dev, u32 phy_addr) 638static int at91_twi_configure_dma(struct at91_twi_dev *dev, u32 phy_addr)
648{ 639{
649 int ret = 0; 640 int ret = 0;
650 struct at91_twi_pdata *pdata = dev->pdata;
651 struct dma_slave_config slave_config; 641 struct dma_slave_config slave_config;
652 struct at91_twi_dma *dma = &dev->dma; 642 struct at91_twi_dma *dma = &dev->dma;
653 dma_cap_mask_t mask;
654 643
655 memset(&slave_config, 0, sizeof(slave_config)); 644 memset(&slave_config, 0, sizeof(slave_config));
656 slave_config.src_addr = (dma_addr_t)phy_addr + AT91_TWI_RHR; 645 slave_config.src_addr = (dma_addr_t)phy_addr + AT91_TWI_RHR;
@@ -661,22 +650,17 @@ static int at91_twi_configure_dma(struct at91_twi_dev *dev, u32 phy_addr)
661 slave_config.dst_maxburst = 1; 650 slave_config.dst_maxburst = 1;
662 slave_config.device_fc = false; 651 slave_config.device_fc = false;
663 652
664 dma_cap_zero(mask); 653 dma->chan_tx = dma_request_slave_channel_reason(dev->dev, "tx");
665 dma_cap_set(DMA_SLAVE, mask); 654 if (IS_ERR(dma->chan_tx)) {
666 655 ret = PTR_ERR(dma->chan_tx);
667 dma->chan_tx = dma_request_slave_channel_compat(mask, filter, pdata, 656 dma->chan_tx = NULL;
668 dev->dev, "tx");
669 if (!dma->chan_tx) {
670 dev_err(dev->dev, "can't get a DMA channel for tx\n");
671 ret = -EBUSY;
672 goto error; 657 goto error;
673 } 658 }
674 659
675 dma->chan_rx = dma_request_slave_channel_compat(mask, filter, pdata, 660 dma->chan_rx = dma_request_slave_channel_reason(dev->dev, "rx");
676 dev->dev, "rx"); 661 if (IS_ERR(dma->chan_rx)) {
677 if (!dma->chan_rx) { 662 ret = PTR_ERR(dma->chan_rx);
678 dev_err(dev->dev, "can't get a DMA channel for rx\n"); 663 dma->chan_rx = NULL;
679 ret = -EBUSY;
680 goto error; 664 goto error;
681 } 665 }
682 666
@@ -697,6 +681,7 @@ static int at91_twi_configure_dma(struct at91_twi_dev *dev, u32 phy_addr)
697 sg_init_table(&dma->sg, 1); 681 sg_init_table(&dma->sg, 1);
698 dma->buf_mapped = false; 682 dma->buf_mapped = false;
699 dma->xfer_in_progress = false; 683 dma->xfer_in_progress = false;
684 dev->use_dma = true;
700 685
701 dev_info(dev->dev, "using %s (tx) and %s (rx) for DMA transfers\n", 686 dev_info(dev->dev, "using %s (tx) and %s (rx) for DMA transfers\n",
702 dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx)); 687 dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx));
@@ -704,7 +689,8 @@ static int at91_twi_configure_dma(struct at91_twi_dev *dev, u32 phy_addr)
704 return ret; 689 return ret;
705 690
706error: 691error:
707 dev_info(dev->dev, "can't use DMA\n"); 692 if (ret != -EPROBE_DEFER)
693 dev_info(dev->dev, "can't use DMA, error %d\n", ret);
708 if (dma->chan_rx) 694 if (dma->chan_rx)
709 dma_release_channel(dma->chan_rx); 695 dma_release_channel(dma->chan_rx);
710 if (dma->chan_tx) 696 if (dma->chan_tx)
@@ -772,9 +758,10 @@ static int at91_twi_probe(struct platform_device *pdev)
772 } 758 }
773 clk_prepare_enable(dev->clk); 759 clk_prepare_enable(dev->clk);
774 760
775 if (dev->pdata->has_dma_support) { 761 if (dev->dev->of_node) {
776 if (at91_twi_configure_dma(dev, phy_addr) == 0) 762 rc = at91_twi_configure_dma(dev, phy_addr);
777 dev->use_dma = true; 763 if (rc == -EPROBE_DEFER)
764 return rc;
778 } 765 }
779 766
780 rc = of_property_read_u32(dev->dev->of_node, "clock-frequency", 767 rc = of_property_read_u32(dev->dev->of_node, "clock-frequency",
@@ -795,11 +782,20 @@ static int at91_twi_probe(struct platform_device *pdev)
795 dev->adapter.timeout = AT91_I2C_TIMEOUT; 782 dev->adapter.timeout = AT91_I2C_TIMEOUT;
796 dev->adapter.dev.of_node = pdev->dev.of_node; 783 dev->adapter.dev.of_node = pdev->dev.of_node;
797 784
785 pm_runtime_set_autosuspend_delay(dev->dev, AUTOSUSPEND_TIMEOUT);
786 pm_runtime_use_autosuspend(dev->dev);
787 pm_runtime_set_active(dev->dev);
788 pm_runtime_enable(dev->dev);
789
798 rc = i2c_add_numbered_adapter(&dev->adapter); 790 rc = i2c_add_numbered_adapter(&dev->adapter);
799 if (rc) { 791 if (rc) {
800 dev_err(dev->dev, "Adapter %s registration failed\n", 792 dev_err(dev->dev, "Adapter %s registration failed\n",
801 dev->adapter.name); 793 dev->adapter.name);
802 clk_disable_unprepare(dev->clk); 794 clk_disable_unprepare(dev->clk);
795
796 pm_runtime_disable(dev->dev);
797 pm_runtime_set_suspended(dev->dev);
798
803 return rc; 799 return rc;
804 } 800 }
805 801
@@ -814,6 +810,9 @@ static int at91_twi_remove(struct platform_device *pdev)
814 i2c_del_adapter(&dev->adapter); 810 i2c_del_adapter(&dev->adapter);
815 clk_disable_unprepare(dev->clk); 811 clk_disable_unprepare(dev->clk);
816 812
813 pm_runtime_disable(dev->dev);
814 pm_runtime_set_suspended(dev->dev);
815
817 return 0; 816 return 0;
818} 817}
819 818
@@ -823,7 +822,9 @@ static int at91_twi_runtime_suspend(struct device *dev)
823{ 822{
824 struct at91_twi_dev *twi_dev = dev_get_drvdata(dev); 823 struct at91_twi_dev *twi_dev = dev_get_drvdata(dev);
825 824
826 clk_disable(twi_dev->clk); 825 clk_disable_unprepare(twi_dev->clk);
826
827 pinctrl_pm_select_sleep_state(dev);
827 828
828 return 0; 829 return 0;
829} 830}
@@ -832,10 +833,38 @@ static int at91_twi_runtime_resume(struct device *dev)
832{ 833{
833 struct at91_twi_dev *twi_dev = dev_get_drvdata(dev); 834 struct at91_twi_dev *twi_dev = dev_get_drvdata(dev);
834 835
835 return clk_enable(twi_dev->clk); 836 pinctrl_pm_select_default_state(dev);
837
838 return clk_prepare_enable(twi_dev->clk);
839}
840
841static int at91_twi_suspend_noirq(struct device *dev)
842{
843 if (!pm_runtime_status_suspended(dev))
844 at91_twi_runtime_suspend(dev);
845
846 return 0;
847}
848
849static int at91_twi_resume_noirq(struct device *dev)
850{
851 int ret;
852
853 if (!pm_runtime_status_suspended(dev)) {
854 ret = at91_twi_runtime_resume(dev);
855 if (ret)
856 return ret;
857 }
858
859 pm_runtime_mark_last_busy(dev);
860 pm_request_autosuspend(dev);
861
862 return 0;
836} 863}
837 864
838static const struct dev_pm_ops at91_twi_pm = { 865static const struct dev_pm_ops at91_twi_pm = {
866 .suspend_noirq = at91_twi_suspend_noirq,
867 .resume_noirq = at91_twi_resume_noirq,
839 .runtime_suspend = at91_twi_runtime_suspend, 868 .runtime_suspend = at91_twi_runtime_suspend,
840 .runtime_resume = at91_twi_runtime_resume, 869 .runtime_resume = at91_twi_runtime_resume,
841}; 870};
diff --git a/drivers/i2c/busses/i2c-davinci.c b/drivers/i2c/busses/i2c-davinci.c
index 01f0cd87a4a5..0aa1054711af 100644
--- a/drivers/i2c/busses/i2c-davinci.c
+++ b/drivers/i2c/busses/i2c-davinci.c
@@ -368,8 +368,7 @@ i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop)
368 flag |= DAVINCI_I2C_MDR_STP; 368 flag |= DAVINCI_I2C_MDR_STP;
369 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag); 369 davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
370 370
371 r = wait_for_completion_interruptible_timeout(&dev->cmd_complete, 371 r = wait_for_completion_timeout(&dev->cmd_complete, dev->adapter.timeout);
372 dev->adapter.timeout);
373 if (r == 0) { 372 if (r == 0) {
374 dev_err(dev->dev, "controller timed out\n"); 373 dev_err(dev->dev, "controller timed out\n");
375 davinci_i2c_recover_bus(dev); 374 davinci_i2c_recover_bus(dev);
@@ -380,7 +379,6 @@ i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop)
380 if (dev->buf_len) { 379 if (dev->buf_len) {
381 /* This should be 0 if all bytes were transferred 380 /* This should be 0 if all bytes were transferred
382 * or dev->cmd_err denotes an error. 381 * or dev->cmd_err denotes an error.
383 * A signal may have aborted the transfer.
384 */ 382 */
385 if (r >= 0) { 383 if (r >= 0) {
386 dev_err(dev->dev, "abnormal termination buf_len=%i\n", 384 dev_err(dev->dev, "abnormal termination buf_len=%i\n",
@@ -634,13 +632,17 @@ static int davinci_i2c_probe(struct platform_device *pdev)
634{ 632{
635 struct davinci_i2c_dev *dev; 633 struct davinci_i2c_dev *dev;
636 struct i2c_adapter *adap; 634 struct i2c_adapter *adap;
637 struct resource *mem, *irq; 635 struct resource *mem;
638 int r; 636 int r, irq;
639 637
640 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 638 irq = platform_get_irq(pdev, 0);
641 if (!irq) { 639 if (irq <= 0) {
642 dev_err(&pdev->dev, "no irq resource?\n"); 640 if (!irq)
643 return -ENODEV; 641 irq = -ENXIO;
642 if (irq != -EPROBE_DEFER)
643 dev_err(&pdev->dev,
644 "can't get irq resource ret=%d\n", irq);
645 return irq;
644 } 646 }
645 647
646 dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_i2c_dev), 648 dev = devm_kzalloc(&pdev->dev, sizeof(struct davinci_i2c_dev),
@@ -655,7 +657,7 @@ static int davinci_i2c_probe(struct platform_device *pdev)
655 init_completion(&dev->xfr_complete); 657 init_completion(&dev->xfr_complete);
656#endif 658#endif
657 dev->dev = &pdev->dev; 659 dev->dev = &pdev->dev;
658 dev->irq = irq->start; 660 dev->irq = irq;
659 dev->pdata = dev_get_platdata(&pdev->dev); 661 dev->pdata = dev_get_platdata(&pdev->dev);
660 platform_set_drvdata(pdev, dev); 662 platform_set_drvdata(pdev, dev);
661 663
diff --git a/drivers/i2c/busses/i2c-exynos5.c b/drivers/i2c/busses/i2c-exynos5.c
index 81e6263cd7da..271533d564ec 100644
--- a/drivers/i2c/busses/i2c-exynos5.c
+++ b/drivers/i2c/busses/i2c-exynos5.c
@@ -457,7 +457,7 @@ static irqreturn_t exynos5_i2c_irq(int irqno, void *dev_id)
457 goto stop; 457 goto stop;
458 } else if (int_status & HSI2C_INT_TIMEOUT) { 458 } else if (int_status & HSI2C_INT_TIMEOUT) {
459 dev_dbg(i2c->dev, "Accessing device timed out\n"); 459 dev_dbg(i2c->dev, "Accessing device timed out\n");
460 i2c->state = -EAGAIN; 460 i2c->state = -ETIMEDOUT;
461 goto stop; 461 goto stop;
462 } 462 }
463 } else if (int_status & HSI2C_INT_I2C) { 463 } else if (int_status & HSI2C_INT_I2C) {
@@ -476,7 +476,7 @@ static irqreturn_t exynos5_i2c_irq(int irqno, void *dev_id)
476 goto stop; 476 goto stop;
477 } else if (trans_status & HSI2C_TIMEOUT_AUTO) { 477 } else if (trans_status & HSI2C_TIMEOUT_AUTO) {
478 dev_dbg(i2c->dev, "Accessing device timed out\n"); 478 dev_dbg(i2c->dev, "Accessing device timed out\n");
479 i2c->state = -EAGAIN; 479 i2c->state = -ETIMEDOUT;
480 goto stop; 480 goto stop;
481 } else if (trans_status & HSI2C_TRANS_DONE) { 481 } else if (trans_status & HSI2C_TRANS_DONE) {
482 i2c->trans_done = 1; 482 i2c->trans_done = 1;
diff --git a/drivers/i2c/busses/i2c-i801.c b/drivers/i2c/busses/i2c-i801.c
index 6ab4f1cb21f3..8fafb254e42a 100644
--- a/drivers/i2c/busses/i2c-i801.c
+++ b/drivers/i2c/busses/i2c-i801.c
@@ -2,7 +2,7 @@
2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>, 2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
3 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker 3 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
4 <mdsxyz123@yahoo.com> 4 <mdsxyz123@yahoo.com>
5 Copyright (C) 2007 - 2012 Jean Delvare <jdelvare@suse.de> 5 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de>
6 Copyright (C) 2010 Intel Corporation, 6 Copyright (C) 2010 Intel Corporation,
7 David Woodhouse <dwmw2@infradead.org> 7 David Woodhouse <dwmw2@infradead.org>
8 8
@@ -59,6 +59,7 @@
59 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes 59 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes
60 * BayTrail (SOC) 0x0f12 32 hard yes yes yes 60 * BayTrail (SOC) 0x0f12 32 hard yes yes yes
61 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes 61 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes
62 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes
62 * 63 *
63 * Features supported by this driver: 64 * Features supported by this driver:
64 * Software PEC no 65 * Software PEC no
@@ -109,12 +110,16 @@
109 110
110/* PCI Address Constants */ 111/* PCI Address Constants */
111#define SMBBAR 4 112#define SMBBAR 4
113#define SMBPCICTL 0x004
112#define SMBPCISTS 0x006 114#define SMBPCISTS 0x006
113#define SMBHSTCFG 0x040 115#define SMBHSTCFG 0x040
114 116
115/* Host status bits for SMBPCISTS */ 117/* Host status bits for SMBPCISTS */
116#define SMBPCISTS_INTS 0x08 118#define SMBPCISTS_INTS 0x08
117 119
120/* Control bits for SMBPCICTL */
121#define SMBPCICTL_INTDIS 0x0400
122
118/* Host configuration bits for SMBHSTCFG */ 123/* Host configuration bits for SMBHSTCFG */
119#define SMBHSTCFG_HST_EN 1 124#define SMBHSTCFG_HST_EN 1
120#define SMBHSTCFG_SMB_SMI_EN 2 125#define SMBHSTCFG_SMB_SMI_EN 2
@@ -182,6 +187,7 @@
182#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22 187#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22
183#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2 188#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2
184#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123 189#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123
190#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23
185 191
186struct i801_mux_config { 192struct i801_mux_config {
187 char *gpio_chip; 193 char *gpio_chip;
@@ -371,6 +377,7 @@ static int i801_transaction(struct i801_priv *priv, int xact)
371{ 377{
372 int status; 378 int status;
373 int result; 379 int result;
380 const struct i2c_adapter *adap = &priv->adapter;
374 381
375 result = i801_check_pre(priv); 382 result = i801_check_pre(priv);
376 if (result < 0) 383 if (result < 0)
@@ -379,7 +386,14 @@ static int i801_transaction(struct i801_priv *priv, int xact)
379 if (priv->features & FEATURE_IRQ) { 386 if (priv->features & FEATURE_IRQ) {
380 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START, 387 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
381 SMBHSTCNT(priv)); 388 SMBHSTCNT(priv));
382 wait_event(priv->waitq, (status = priv->status)); 389 result = wait_event_timeout(priv->waitq,
390 (status = priv->status),
391 adap->timeout);
392 if (!result) {
393 status = -ETIMEDOUT;
394 dev_warn(&priv->pci_dev->dev,
395 "Timeout waiting for interrupt!\n");
396 }
383 priv->status = 0; 397 priv->status = 0;
384 return i801_check_post(priv, status); 398 return i801_check_post(priv, status);
385 } 399 }
@@ -493,9 +507,6 @@ static irqreturn_t i801_isr(int irq, void *dev_id)
493 return IRQ_NONE; 507 return IRQ_NONE;
494 508
495 status = inb_p(SMBHSTSTS(priv)); 509 status = inb_p(SMBHSTSTS(priv));
496 if (status != 0x42)
497 dev_dbg(&priv->pci_dev->dev, "irq: status = %02x\n", status);
498
499 if (status & SMBHSTSTS_BYTE_DONE) 510 if (status & SMBHSTSTS_BYTE_DONE)
500 i801_isr_byte_done(priv); 511 i801_isr_byte_done(priv);
501 512
@@ -527,6 +538,7 @@ static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
527 int smbcmd; 538 int smbcmd;
528 int status; 539 int status;
529 int result; 540 int result;
541 const struct i2c_adapter *adap = &priv->adapter;
530 542
531 result = i801_check_pre(priv); 543 result = i801_check_pre(priv);
532 if (result < 0) 544 if (result < 0)
@@ -555,7 +567,14 @@ static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
555 priv->data = &data->block[1]; 567 priv->data = &data->block[1];
556 568
557 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv)); 569 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
558 wait_event(priv->waitq, (status = priv->status)); 570 result = wait_event_timeout(priv->waitq,
571 (status = priv->status),
572 adap->timeout);
573 if (!result) {
574 status = -ETIMEDOUT;
575 dev_warn(&priv->pci_dev->dev,
576 "Timeout waiting for interrupt!\n");
577 }
559 priv->status = 0; 578 priv->status = 0;
560 return i801_check_post(priv, status); 579 return i801_check_post(priv, status);
561 } 580 }
@@ -829,6 +848,7 @@ static const struct pci_device_id i801_ids[] = {
829 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) }, 848 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
830 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) }, 849 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) },
831 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) }, 850 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) },
851 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) },
832 { 0, } 852 { 0, }
833}; 853};
834 854
@@ -1212,6 +1232,25 @@ static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1212 outb_p(inb_p(SMBAUXCTL(priv)) & 1232 outb_p(inb_p(SMBAUXCTL(priv)) &
1213 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); 1233 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1214 1234
1235 /* Default timeout in interrupt mode: 200 ms */
1236 priv->adapter.timeout = HZ / 5;
1237
1238 if (priv->features & FEATURE_IRQ) {
1239 u16 pcictl, pcists;
1240
1241 /* Complain if an interrupt is already pending */
1242 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
1243 if (pcists & SMBPCISTS_INTS)
1244 dev_warn(&dev->dev, "An interrupt is pending!\n");
1245
1246 /* Check if interrupts have been disabled */
1247 pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl);
1248 if (pcictl & SMBPCICTL_INTDIS) {
1249 dev_info(&dev->dev, "Interrupts are disabled\n");
1250 priv->features &= ~FEATURE_IRQ;
1251 }
1252 }
1253
1215 if (priv->features & FEATURE_IRQ) { 1254 if (priv->features & FEATURE_IRQ) {
1216 init_waitqueue_head(&priv->waitq); 1255 init_waitqueue_head(&priv->waitq);
1217 1256
@@ -1220,10 +1259,11 @@ static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1220 if (err) { 1259 if (err) {
1221 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n", 1260 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1222 dev->irq, err); 1261 dev->irq, err);
1223 goto exit_release; 1262 priv->features &= ~FEATURE_IRQ;
1224 } 1263 }
1225 dev_info(&dev->dev, "SMBus using PCI Interrupt\n");
1226 } 1264 }
1265 dev_info(&dev->dev, "SMBus using %s\n",
1266 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1227 1267
1228 /* set up the sysfs linkage to our parent device */ 1268 /* set up the sysfs linkage to our parent device */
1229 priv->adapter.dev.parent = &dev->dev; 1269 priv->adapter.dev.parent = &dev->dev;
@@ -1250,7 +1290,6 @@ static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1250exit_free_irq: 1290exit_free_irq:
1251 if (priv->features & FEATURE_IRQ) 1291 if (priv->features & FEATURE_IRQ)
1252 free_irq(dev->irq, priv); 1292 free_irq(dev->irq, priv);
1253exit_release:
1254 pci_release_region(dev, SMBBAR); 1293 pci_release_region(dev, SMBBAR);
1255exit: 1294exit:
1256 kfree(priv); 1295 kfree(priv);
diff --git a/drivers/i2c/busses/i2c-img-scb.c b/drivers/i2c/busses/i2c-img-scb.c
new file mode 100644
index 000000000000..0fcc1694c607
--- /dev/null
+++ b/drivers/i2c/busses/i2c-img-scb.c
@@ -0,0 +1,1412 @@
1/*
2 * I2C adapter for the IMG Serial Control Bus (SCB) IP block.
3 *
4 * Copyright (C) 2009, 2010, 2012, 2014 Imagination Technologies Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * There are three ways that this I2C controller can be driven:
11 *
12 * - Raw control of the SDA and SCK signals.
13 *
14 * This corresponds to MODE_RAW, which takes control of the signals
15 * directly for a certain number of clock cycles (the INT_TIMING
16 * interrupt can be used for timing).
17 *
18 * - Atomic commands. A low level I2C symbol (such as generate
19 * start/stop/ack/nack bit, generate byte, receive byte, and receive
20 * ACK) is given to the hardware, with detection of completion by bits
21 * in the LINESTAT register.
22 *
23 * This mode of operation is used by MODE_ATOMIC, which uses an I2C
24 * state machine in the interrupt handler to compose/react to I2C
25 * transactions using atomic mode commands, and also by MODE_SEQUENCE,
26 * which emits a simple fixed sequence of atomic mode commands.
27 *
28 * Due to software control, the use of atomic commands usually results
29 * in suboptimal use of the bus, with gaps between the I2C symbols while
30 * the driver decides what to do next.
31 *
32 * - Automatic mode. A bus address, and whether to read/write is
33 * specified, and the hardware takes care of the I2C state machine,
34 * using a FIFO to send/receive bytes of data to an I2C slave. The
35 * driver just has to keep the FIFO drained or filled in response to the
36 * appropriate FIFO interrupts.
37 *
38 * This corresponds to MODE_AUTOMATIC, which manages the FIFOs and deals
39 * with control of repeated start bits between I2C messages.
40 *
41 * Use of automatic mode and the FIFO can make much more efficient use
42 * of the bus compared to individual atomic commands, with potentially
43 * no wasted time between I2C symbols or I2C messages.
44 *
45 * In most cases MODE_AUTOMATIC is used, however if any of the messages in
46 * a transaction are zero byte writes (e.g. used by i2cdetect for probing
47 * the bus), MODE_ATOMIC must be used since automatic mode is normally
48 * started by the writing of data into the FIFO.
49 *
50 * The other modes are used in specific circumstances where MODE_ATOMIC and
51 * MODE_AUTOMATIC aren't appropriate. MODE_RAW is used to implement a bus
52 * recovery routine. MODE_SEQUENCE is used to reset the bus and make sure
53 * it is in a sane state.
54 *
55 * Notice that the driver implements a timer-based timeout mechanism.
56 * The reason for this mechanism is to reduce the number of interrupts
57 * received in automatic mode.
58 *
59 * The driver would get a slave event and transaction done interrupts for
60 * each atomic mode command that gets completed. However, these events are
61 * not needed in automatic mode, becase those atomic mode commands are
62 * managed automatically by the hardware.
63 *
64 * In practice, normal I2C transactions will be complete well before you
65 * get the timer interrupt, as the timer is re-scheduled during FIFO
66 * maintenance and disabled after the transaction is complete.
67 *
68 * In this way normal automatic mode operation isn't impacted by
69 * unnecessary interrupts, but the exceptional abort condition can still be
70 * detected (with a slight delay).
71 */
72
73#include <linux/bitops.h>
74#include <linux/clk.h>
75#include <linux/completion.h>
76#include <linux/err.h>
77#include <linux/i2c.h>
78#include <linux/init.h>
79#include <linux/interrupt.h>
80#include <linux/io.h>
81#include <linux/kernel.h>
82#include <linux/module.h>
83#include <linux/of_platform.h>
84#include <linux/platform_device.h>
85#include <linux/slab.h>
86#include <linux/timer.h>
87
88/* Register offsets */
89
90#define SCB_STATUS_REG 0x00
91#define SCB_OVERRIDE_REG 0x04
92#define SCB_READ_ADDR_REG 0x08
93#define SCB_READ_COUNT_REG 0x0c
94#define SCB_WRITE_ADDR_REG 0x10
95#define SCB_READ_DATA_REG 0x14
96#define SCB_WRITE_DATA_REG 0x18
97#define SCB_FIFO_STATUS_REG 0x1c
98#define SCB_CONTROL_SOFT_RESET 0x1f
99#define SCB_CLK_SET_REG 0x3c
100#define SCB_INT_STATUS_REG 0x40
101#define SCB_INT_CLEAR_REG 0x44
102#define SCB_INT_MASK_REG 0x48
103#define SCB_CONTROL_REG 0x4c
104#define SCB_TIME_TPL_REG 0x50
105#define SCB_TIME_TPH_REG 0x54
106#define SCB_TIME_TP2S_REG 0x58
107#define SCB_TIME_TBI_REG 0x60
108#define SCB_TIME_TSL_REG 0x64
109#define SCB_TIME_TDL_REG 0x68
110#define SCB_TIME_TSDL_REG 0x6c
111#define SCB_TIME_TSDH_REG 0x70
112#define SCB_READ_XADDR_REG 0x74
113#define SCB_WRITE_XADDR_REG 0x78
114#define SCB_WRITE_COUNT_REG 0x7c
115#define SCB_CORE_REV_REG 0x80
116#define SCB_TIME_TCKH_REG 0x84
117#define SCB_TIME_TCKL_REG 0x88
118#define SCB_FIFO_FLUSH_REG 0x8c
119#define SCB_READ_FIFO_REG 0x94
120#define SCB_CLEAR_REG 0x98
121
122/* SCB_CONTROL_REG bits */
123
124#define SCB_CONTROL_CLK_ENABLE 0x1e0
125#define SCB_CONTROL_TRANSACTION_HALT 0x200
126
127#define FIFO_READ_FULL BIT(0)
128#define FIFO_READ_EMPTY BIT(1)
129#define FIFO_WRITE_FULL BIT(2)
130#define FIFO_WRITE_EMPTY BIT(3)
131
132/* SCB_CLK_SET_REG bits */
133#define SCB_FILT_DISABLE BIT(31)
134#define SCB_FILT_BYPASS BIT(30)
135#define SCB_FILT_INC_MASK 0x7f
136#define SCB_FILT_INC_SHIFT 16
137#define SCB_INC_MASK 0x7f
138#define SCB_INC_SHIFT 8
139
140/* SCB_INT_*_REG bits */
141
142#define INT_BUS_INACTIVE BIT(0)
143#define INT_UNEXPECTED_START BIT(1)
144#define INT_SCLK_LOW_TIMEOUT BIT(2)
145#define INT_SDAT_LOW_TIMEOUT BIT(3)
146#define INT_WRITE_ACK_ERR BIT(4)
147#define INT_ADDR_ACK_ERR BIT(5)
148#define INT_FIFO_FULL BIT(9)
149#define INT_FIFO_FILLING BIT(10)
150#define INT_FIFO_EMPTY BIT(11)
151#define INT_FIFO_EMPTYING BIT(12)
152#define INT_TRANSACTION_DONE BIT(15)
153#define INT_SLAVE_EVENT BIT(16)
154#define INT_TIMING BIT(18)
155
156#define INT_FIFO_FULL_FILLING (INT_FIFO_FULL | INT_FIFO_FILLING)
157#define INT_FIFO_EMPTY_EMPTYING (INT_FIFO_EMPTY | INT_FIFO_EMPTYING)
158
159/* Level interrupts need clearing after handling instead of before */
160#define INT_LEVEL 0x01e00
161
162/* Don't allow any interrupts while the clock may be off */
163#define INT_ENABLE_MASK_INACTIVE 0x00000
164
165/* Interrupt masks for the different driver modes */
166
167#define INT_ENABLE_MASK_RAW INT_TIMING
168
169#define INT_ENABLE_MASK_ATOMIC (INT_TRANSACTION_DONE | \
170 INT_SLAVE_EVENT | \
171 INT_ADDR_ACK_ERR | \
172 INT_WRITE_ACK_ERR)
173
174#define INT_ENABLE_MASK_AUTOMATIC (INT_SCLK_LOW_TIMEOUT | \
175 INT_ADDR_ACK_ERR | \
176 INT_WRITE_ACK_ERR | \
177 INT_FIFO_FULL | \
178 INT_FIFO_FILLING | \
179 INT_FIFO_EMPTY | \
180 INT_FIFO_EMPTYING)
181
182#define INT_ENABLE_MASK_WAITSTOP (INT_SLAVE_EVENT | \
183 INT_ADDR_ACK_ERR | \
184 INT_WRITE_ACK_ERR)
185
186/* SCB_STATUS_REG fields */
187
188#define LINESTAT_SCLK_LINE_STATUS BIT(0)
189#define LINESTAT_SCLK_EN BIT(1)
190#define LINESTAT_SDAT_LINE_STATUS BIT(2)
191#define LINESTAT_SDAT_EN BIT(3)
192#define LINESTAT_DET_START_STATUS BIT(4)
193#define LINESTAT_DET_STOP_STATUS BIT(5)
194#define LINESTAT_DET_ACK_STATUS BIT(6)
195#define LINESTAT_DET_NACK_STATUS BIT(7)
196#define LINESTAT_BUS_IDLE BIT(8)
197#define LINESTAT_T_DONE_STATUS BIT(9)
198#define LINESTAT_SCLK_OUT_STATUS BIT(10)
199#define LINESTAT_SDAT_OUT_STATUS BIT(11)
200#define LINESTAT_GEN_LINE_MASK_STATUS BIT(12)
201#define LINESTAT_START_BIT_DET BIT(13)
202#define LINESTAT_STOP_BIT_DET BIT(14)
203#define LINESTAT_ACK_DET BIT(15)
204#define LINESTAT_NACK_DET BIT(16)
205#define LINESTAT_INPUT_HELD_V BIT(17)
206#define LINESTAT_ABORT_DET BIT(18)
207#define LINESTAT_ACK_OR_NACK_DET (LINESTAT_ACK_DET | LINESTAT_NACK_DET)
208#define LINESTAT_INPUT_DATA 0xff000000
209#define LINESTAT_INPUT_DATA_SHIFT 24
210
211#define LINESTAT_CLEAR_SHIFT 13
212#define LINESTAT_LATCHED (0x3f << LINESTAT_CLEAR_SHIFT)
213
214/* SCB_OVERRIDE_REG fields */
215
216#define OVERRIDE_SCLK_OVR BIT(0)
217#define OVERRIDE_SCLKEN_OVR BIT(1)
218#define OVERRIDE_SDAT_OVR BIT(2)
219#define OVERRIDE_SDATEN_OVR BIT(3)
220#define OVERRIDE_MASTER BIT(9)
221#define OVERRIDE_LINE_OVR_EN BIT(10)
222#define OVERRIDE_DIRECT BIT(11)
223#define OVERRIDE_CMD_SHIFT 4
224#define OVERRIDE_CMD_MASK 0x1f
225#define OVERRIDE_DATA_SHIFT 24
226
227#define OVERRIDE_SCLK_DOWN (OVERRIDE_LINE_OVR_EN | \
228 OVERRIDE_SCLKEN_OVR)
229#define OVERRIDE_SCLK_UP (OVERRIDE_LINE_OVR_EN | \
230 OVERRIDE_SCLKEN_OVR | \
231 OVERRIDE_SCLK_OVR)
232#define OVERRIDE_SDAT_DOWN (OVERRIDE_LINE_OVR_EN | \
233 OVERRIDE_SDATEN_OVR)
234#define OVERRIDE_SDAT_UP (OVERRIDE_LINE_OVR_EN | \
235 OVERRIDE_SDATEN_OVR | \
236 OVERRIDE_SDAT_OVR)
237
238/* OVERRIDE_CMD values */
239
240#define CMD_PAUSE 0x00
241#define CMD_GEN_DATA 0x01
242#define CMD_GEN_START 0x02
243#define CMD_GEN_STOP 0x03
244#define CMD_GEN_ACK 0x04
245#define CMD_GEN_NACK 0x05
246#define CMD_RET_DATA 0x08
247#define CMD_RET_ACK 0x09
248
249/* Fixed timing values */
250
251#define TIMEOUT_TBI 0x0
252#define TIMEOUT_TSL 0xffff
253#define TIMEOUT_TDL 0x0
254
255/* Transaction timeout */
256
257#define IMG_I2C_TIMEOUT (msecs_to_jiffies(1000))
258
259/*
260 * Worst incs are 1 (innacurate) and 16*256 (irregular).
261 * So a sensible inc is the logarithmic mean: 64 (2^6), which is
262 * in the middle of the valid range (0-127).
263 */
264#define SCB_OPT_INC 64
265
266/* Setup the clock enable filtering for 25 ns */
267#define SCB_FILT_GLITCH 25
268
269/*
270 * Bits to return from interrupt handler functions for different modes.
271 * This delays completion until we've finished with the registers, so that the
272 * function waiting for completion can safely disable the clock to save power.
273 */
274#define ISR_COMPLETE_M BIT(31)
275#define ISR_FATAL_M BIT(30)
276#define ISR_WAITSTOP BIT(29)
277#define ISR_STATUS_M 0x0000ffff /* contains +ve errno */
278#define ISR_COMPLETE(err) (ISR_COMPLETE_M | (ISR_STATUS_M & (err)))
279#define ISR_FATAL(err) (ISR_COMPLETE(err) | ISR_FATAL_M)
280
281#define REL_SOC_IP_SCB_2_2_1 0x00020201
282
283enum img_i2c_mode {
284 MODE_INACTIVE,
285 MODE_RAW,
286 MODE_ATOMIC,
287 MODE_AUTOMATIC,
288 MODE_SEQUENCE,
289 MODE_FATAL,
290 MODE_WAITSTOP,
291 MODE_SUSPEND,
292};
293
294/* Timing parameters for i2c modes (in ns) */
295struct img_i2c_timings {
296 const char *name;
297 unsigned int max_bitrate;
298 unsigned int tckh, tckl, tsdh, tsdl;
299 unsigned int tp2s, tpl, tph;
300};
301
302/* The timings array must be ordered from slower to faster */
303static struct img_i2c_timings timings[] = {
304 /* Standard mode */
305 {
306 .name = "standard",
307 .max_bitrate = 100000,
308 .tckh = 4000,
309 .tckl = 4700,
310 .tsdh = 4700,
311 .tsdl = 8700,
312 .tp2s = 4700,
313 .tpl = 4700,
314 .tph = 4000,
315 },
316 /* Fast mode */
317 {
318 .name = "fast",
319 .max_bitrate = 400000,
320 .tckh = 600,
321 .tckl = 1300,
322 .tsdh = 600,
323 .tsdl = 1200,
324 .tp2s = 1300,
325 .tpl = 600,
326 .tph = 600,
327 },
328};
329
330/* Reset dance */
331static u8 img_i2c_reset_seq[] = { CMD_GEN_START,
332 CMD_GEN_DATA, 0xff,
333 CMD_RET_ACK,
334 CMD_GEN_START,
335 CMD_GEN_STOP,
336 0 };
337/* Just issue a stop (after an abort condition) */
338static u8 img_i2c_stop_seq[] = { CMD_GEN_STOP,
339 0 };
340
341/* We're interested in different interrupts depending on the mode */
342static unsigned int img_i2c_int_enable_by_mode[] = {
343 [MODE_INACTIVE] = INT_ENABLE_MASK_INACTIVE,
344 [MODE_RAW] = INT_ENABLE_MASK_RAW,
345 [MODE_ATOMIC] = INT_ENABLE_MASK_ATOMIC,
346 [MODE_AUTOMATIC] = INT_ENABLE_MASK_AUTOMATIC,
347 [MODE_SEQUENCE] = INT_ENABLE_MASK_ATOMIC,
348 [MODE_FATAL] = 0,
349 [MODE_WAITSTOP] = INT_ENABLE_MASK_WAITSTOP,
350 [MODE_SUSPEND] = 0,
351};
352
353/* Atomic command names */
354static const char * const img_i2c_atomic_cmd_names[] = {
355 [CMD_PAUSE] = "PAUSE",
356 [CMD_GEN_DATA] = "GEN_DATA",
357 [CMD_GEN_START] = "GEN_START",
358 [CMD_GEN_STOP] = "GEN_STOP",
359 [CMD_GEN_ACK] = "GEN_ACK",
360 [CMD_GEN_NACK] = "GEN_NACK",
361 [CMD_RET_DATA] = "RET_DATA",
362 [CMD_RET_ACK] = "RET_ACK",
363};
364
365struct img_i2c {
366 struct i2c_adapter adap;
367
368 void __iomem *base;
369
370 /*
371 * The scb core clock is used to get the input frequency, and to disable
372 * it after every set of transactions to save some power.
373 */
374 struct clk *scb_clk, *sys_clk;
375 unsigned int bitrate;
376 bool need_wr_rd_fence;
377
378 /* state */
379 struct completion msg_complete;
380 spinlock_t lock; /* lock before doing anything with the state */
381 struct i2c_msg msg;
382
383 /* After the last transaction, wait for a stop bit */
384 bool last_msg;
385 int msg_status;
386
387 enum img_i2c_mode mode;
388 u32 int_enable; /* depends on mode */
389 u32 line_status; /* line status over command */
390
391 /*
392 * To avoid slave event interrupts in automatic mode, use a timer to
393 * poll the abort condition if we don't get an interrupt for too long.
394 */
395 struct timer_list check_timer;
396 bool t_halt;
397
398 /* atomic mode state */
399 bool at_t_done;
400 bool at_slave_event;
401 int at_cur_cmd;
402 u8 at_cur_data;
403
404 /* Sequence: either reset or stop. See img_i2c_sequence. */
405 u8 *seq;
406
407 /* raw mode */
408 unsigned int raw_timeout;
409};
410
411static void img_i2c_writel(struct img_i2c *i2c, u32 offset, u32 value)
412{
413 writel(value, i2c->base + offset);
414}
415
416static u32 img_i2c_readl(struct img_i2c *i2c, u32 offset)
417{
418 return readl(i2c->base + offset);
419}
420
421/*
422 * The code to read from the master read fifo, and write to the master
423 * write fifo, checks a bit in an SCB register before every byte to
424 * ensure that the fifo is not full (write fifo) or empty (read fifo).
425 * Due to clock domain crossing inside the SCB block the updated value
426 * of this bit is only visible after 2 cycles.
427 *
428 * The scb_wr_rd_fence() function does 2 dummy writes (to the read-only
429 * revision register), and it's called after reading from or writing to the
430 * fifos to ensure that subsequent reads of the fifo status bits do not read
431 * stale values.
432 */
433static void img_i2c_wr_rd_fence(struct img_i2c *i2c)
434{
435 if (i2c->need_wr_rd_fence) {
436 img_i2c_writel(i2c, SCB_CORE_REV_REG, 0);
437 img_i2c_writel(i2c, SCB_CORE_REV_REG, 0);
438 }
439}
440
441static void img_i2c_switch_mode(struct img_i2c *i2c, enum img_i2c_mode mode)
442{
443 i2c->mode = mode;
444 i2c->int_enable = img_i2c_int_enable_by_mode[mode];
445 i2c->line_status = 0;
446}
447
448static void img_i2c_raw_op(struct img_i2c *i2c)
449{
450 i2c->raw_timeout = 0;
451 img_i2c_writel(i2c, SCB_OVERRIDE_REG,
452 OVERRIDE_SCLKEN_OVR |
453 OVERRIDE_SDATEN_OVR |
454 OVERRIDE_MASTER |
455 OVERRIDE_LINE_OVR_EN |
456 OVERRIDE_DIRECT |
457 ((i2c->at_cur_cmd & OVERRIDE_CMD_MASK) << OVERRIDE_CMD_SHIFT) |
458 (i2c->at_cur_data << OVERRIDE_DATA_SHIFT));
459}
460
461static const char *img_i2c_atomic_op_name(unsigned int cmd)
462{
463 if (unlikely(cmd >= ARRAY_SIZE(img_i2c_atomic_cmd_names)))
464 return "UNKNOWN";
465 return img_i2c_atomic_cmd_names[cmd];
466}
467
468/* Send a single atomic mode command to the hardware */
469static void img_i2c_atomic_op(struct img_i2c *i2c, int cmd, u8 data)
470{
471 i2c->at_cur_cmd = cmd;
472 i2c->at_cur_data = data;
473
474 /* work around lack of data setup time when generating data */
475 if (cmd == CMD_GEN_DATA && i2c->mode == MODE_ATOMIC) {
476 u32 line_status = img_i2c_readl(i2c, SCB_STATUS_REG);
477
478 if (line_status & LINESTAT_SDAT_LINE_STATUS && !(data & 0x80)) {
479 /* hold the data line down for a moment */
480 img_i2c_switch_mode(i2c, MODE_RAW);
481 img_i2c_raw_op(i2c);
482 return;
483 }
484 }
485
486 dev_dbg(i2c->adap.dev.parent,
487 "atomic cmd=%s (%d) data=%#x\n",
488 img_i2c_atomic_op_name(cmd), cmd, data);
489 i2c->at_t_done = (cmd == CMD_RET_DATA || cmd == CMD_RET_ACK);
490 i2c->at_slave_event = false;
491 i2c->line_status = 0;
492
493 img_i2c_writel(i2c, SCB_OVERRIDE_REG,
494 ((cmd & OVERRIDE_CMD_MASK) << OVERRIDE_CMD_SHIFT) |
495 OVERRIDE_MASTER |
496 OVERRIDE_DIRECT |
497 (data << OVERRIDE_DATA_SHIFT));
498}
499
500/* Start a transaction in atomic mode */
501static void img_i2c_atomic_start(struct img_i2c *i2c)
502{
503 img_i2c_switch_mode(i2c, MODE_ATOMIC);
504 img_i2c_writel(i2c, SCB_INT_MASK_REG, i2c->int_enable);
505 img_i2c_atomic_op(i2c, CMD_GEN_START, 0x00);
506}
507
508static void img_i2c_soft_reset(struct img_i2c *i2c)
509{
510 i2c->t_halt = false;
511 img_i2c_writel(i2c, SCB_CONTROL_REG, 0);
512 img_i2c_writel(i2c, SCB_CONTROL_REG,
513 SCB_CONTROL_CLK_ENABLE | SCB_CONTROL_SOFT_RESET);
514}
515
516/* enable or release transaction halt for control of repeated starts */
517static void img_i2c_transaction_halt(struct img_i2c *i2c, bool t_halt)
518{
519 u32 val;
520
521 if (i2c->t_halt == t_halt)
522 return;
523 i2c->t_halt = t_halt;
524 val = img_i2c_readl(i2c, SCB_CONTROL_REG);
525 if (t_halt)
526 val |= SCB_CONTROL_TRANSACTION_HALT;
527 else
528 val &= ~SCB_CONTROL_TRANSACTION_HALT;
529 img_i2c_writel(i2c, SCB_CONTROL_REG, val);
530}
531
532/* Drain data from the FIFO into the buffer (automatic mode) */
533static void img_i2c_read_fifo(struct img_i2c *i2c)
534{
535 while (i2c->msg.len) {
536 u32 fifo_status;
537 u8 data;
538
539 fifo_status = img_i2c_readl(i2c, SCB_FIFO_STATUS_REG);
540 if (fifo_status & FIFO_READ_EMPTY)
541 break;
542
543 data = img_i2c_readl(i2c, SCB_READ_DATA_REG);
544 *i2c->msg.buf = data;
545
546 img_i2c_writel(i2c, SCB_READ_FIFO_REG, 0xff);
547 img_i2c_wr_rd_fence(i2c);
548 i2c->msg.len--;
549 i2c->msg.buf++;
550 }
551}
552
553/* Fill the FIFO with data from the buffer (automatic mode) */
554static void img_i2c_write_fifo(struct img_i2c *i2c)
555{
556 while (i2c->msg.len) {
557 u32 fifo_status;
558
559 fifo_status = img_i2c_readl(i2c, SCB_FIFO_STATUS_REG);
560 if (fifo_status & FIFO_WRITE_FULL)
561 break;
562
563 img_i2c_writel(i2c, SCB_WRITE_DATA_REG, *i2c->msg.buf);
564 img_i2c_wr_rd_fence(i2c);
565 i2c->msg.len--;
566 i2c->msg.buf++;
567 }
568
569 /* Disable fifo emptying interrupt if nothing more to write */
570 if (!i2c->msg.len)
571 i2c->int_enable &= ~INT_FIFO_EMPTYING;
572}
573
574/* Start a read transaction in automatic mode */
575static void img_i2c_read(struct img_i2c *i2c)
576{
577 img_i2c_switch_mode(i2c, MODE_AUTOMATIC);
578 if (!i2c->last_msg)
579 i2c->int_enable |= INT_SLAVE_EVENT;
580
581 img_i2c_writel(i2c, SCB_INT_MASK_REG, i2c->int_enable);
582 img_i2c_writel(i2c, SCB_READ_ADDR_REG, i2c->msg.addr);
583 img_i2c_writel(i2c, SCB_READ_COUNT_REG, i2c->msg.len);
584
585 img_i2c_transaction_halt(i2c, false);
586 mod_timer(&i2c->check_timer, jiffies + msecs_to_jiffies(1));
587}
588
589/* Start a write transaction in automatic mode */
590static void img_i2c_write(struct img_i2c *i2c)
591{
592 img_i2c_switch_mode(i2c, MODE_AUTOMATIC);
593 if (!i2c->last_msg)
594 i2c->int_enable |= INT_SLAVE_EVENT;
595
596 img_i2c_writel(i2c, SCB_WRITE_ADDR_REG, i2c->msg.addr);
597 img_i2c_writel(i2c, SCB_WRITE_COUNT_REG, i2c->msg.len);
598
599 img_i2c_transaction_halt(i2c, false);
600 mod_timer(&i2c->check_timer, jiffies + msecs_to_jiffies(1));
601 img_i2c_write_fifo(i2c);
602
603 /* img_i2c_write_fifo() may modify int_enable */
604 img_i2c_writel(i2c, SCB_INT_MASK_REG, i2c->int_enable);
605}
606
607/*
608 * Indicate that the transaction is complete. This is called from the
609 * ISR to wake up the waiting thread, after which the ISR must not
610 * access any more SCB registers.
611 */
612static void img_i2c_complete_transaction(struct img_i2c *i2c, int status)
613{
614 img_i2c_switch_mode(i2c, MODE_INACTIVE);
615 if (status) {
616 i2c->msg_status = status;
617 img_i2c_transaction_halt(i2c, false);
618 }
619 complete(&i2c->msg_complete);
620}
621
622static unsigned int img_i2c_raw_atomic_delay_handler(struct img_i2c *i2c,
623 u32 int_status, u32 line_status)
624{
625 /* Stay in raw mode for this, so we don't just loop infinitely */
626 img_i2c_atomic_op(i2c, i2c->at_cur_cmd, i2c->at_cur_data);
627 img_i2c_switch_mode(i2c, MODE_ATOMIC);
628 return 0;
629}
630
631static unsigned int img_i2c_raw(struct img_i2c *i2c, u32 int_status,
632 u32 line_status)
633{
634 if (int_status & INT_TIMING) {
635 if (i2c->raw_timeout == 0)
636 return img_i2c_raw_atomic_delay_handler(i2c,
637 int_status, line_status);
638 --i2c->raw_timeout;
639 }
640 return 0;
641}
642
643static unsigned int img_i2c_sequence(struct img_i2c *i2c, u32 int_status)
644{
645 static const unsigned int continue_bits[] = {
646 [CMD_GEN_START] = LINESTAT_START_BIT_DET,
647 [CMD_GEN_DATA] = LINESTAT_INPUT_HELD_V,
648 [CMD_RET_ACK] = LINESTAT_ACK_DET | LINESTAT_NACK_DET,
649 [CMD_RET_DATA] = LINESTAT_INPUT_HELD_V,
650 [CMD_GEN_STOP] = LINESTAT_STOP_BIT_DET,
651 };
652 int next_cmd = -1;
653 u8 next_data = 0x00;
654
655 if (int_status & INT_SLAVE_EVENT)
656 i2c->at_slave_event = true;
657 if (int_status & INT_TRANSACTION_DONE)
658 i2c->at_t_done = true;
659
660 if (!i2c->at_slave_event || !i2c->at_t_done)
661 return 0;
662
663 /* wait if no continue bits are set */
664 if (i2c->at_cur_cmd >= 0 &&
665 i2c->at_cur_cmd < ARRAY_SIZE(continue_bits)) {
666 unsigned int cont_bits = continue_bits[i2c->at_cur_cmd];
667
668 if (cont_bits) {
669 cont_bits |= LINESTAT_ABORT_DET;
670 if (!(i2c->line_status & cont_bits))
671 return 0;
672 }
673 }
674
675 /* follow the sequence of commands in i2c->seq */
676 next_cmd = *i2c->seq;
677 /* stop on a nil */
678 if (!next_cmd) {
679 img_i2c_writel(i2c, SCB_OVERRIDE_REG, 0);
680 return ISR_COMPLETE(0);
681 }
682 /* when generating data, the next byte is the data */
683 if (next_cmd == CMD_GEN_DATA) {
684 ++i2c->seq;
685 next_data = *i2c->seq;
686 }
687 ++i2c->seq;
688 img_i2c_atomic_op(i2c, next_cmd, next_data);
689
690 return 0;
691}
692
693static void img_i2c_reset_start(struct img_i2c *i2c)
694{
695 /* Initiate the magic dance */
696 img_i2c_switch_mode(i2c, MODE_SEQUENCE);
697 img_i2c_writel(i2c, SCB_INT_MASK_REG, i2c->int_enable);
698 i2c->seq = img_i2c_reset_seq;
699 i2c->at_slave_event = true;
700 i2c->at_t_done = true;
701 i2c->at_cur_cmd = -1;
702
703 /* img_i2c_reset_seq isn't empty so the following won't fail */
704 img_i2c_sequence(i2c, 0);
705}
706
707static void img_i2c_stop_start(struct img_i2c *i2c)
708{
709 /* Initiate a stop bit sequence */
710 img_i2c_switch_mode(i2c, MODE_SEQUENCE);
711 img_i2c_writel(i2c, SCB_INT_MASK_REG, i2c->int_enable);
712 i2c->seq = img_i2c_stop_seq;
713 i2c->at_slave_event = true;
714 i2c->at_t_done = true;
715 i2c->at_cur_cmd = -1;
716
717 /* img_i2c_stop_seq isn't empty so the following won't fail */
718 img_i2c_sequence(i2c, 0);
719}
720
721static unsigned int img_i2c_atomic(struct img_i2c *i2c,
722 u32 int_status,
723 u32 line_status)
724{
725 int next_cmd = -1;
726 u8 next_data = 0x00;
727
728 if (int_status & INT_SLAVE_EVENT)
729 i2c->at_slave_event = true;
730 if (int_status & INT_TRANSACTION_DONE)
731 i2c->at_t_done = true;
732
733 if (!i2c->at_slave_event || !i2c->at_t_done)
734 goto next_atomic_cmd;
735 if (i2c->line_status & LINESTAT_ABORT_DET) {
736 dev_dbg(i2c->adap.dev.parent, "abort condition detected\n");
737 next_cmd = CMD_GEN_STOP;
738 i2c->msg_status = -EIO;
739 goto next_atomic_cmd;
740 }
741
742 /* i2c->at_cur_cmd may have completed */
743 switch (i2c->at_cur_cmd) {
744 case CMD_GEN_START:
745 next_cmd = CMD_GEN_DATA;
746 next_data = (i2c->msg.addr << 1);
747 if (i2c->msg.flags & I2C_M_RD)
748 next_data |= 0x1;
749 break;
750 case CMD_GEN_DATA:
751 if (i2c->line_status & LINESTAT_INPUT_HELD_V)
752 next_cmd = CMD_RET_ACK;
753 break;
754 case CMD_RET_ACK:
755 if (i2c->line_status & LINESTAT_ACK_DET) {
756 if (i2c->msg.len == 0) {
757 next_cmd = CMD_GEN_STOP;
758 } else if (i2c->msg.flags & I2C_M_RD) {
759 next_cmd = CMD_RET_DATA;
760 } else {
761 next_cmd = CMD_GEN_DATA;
762 next_data = *i2c->msg.buf;
763 --i2c->msg.len;
764 ++i2c->msg.buf;
765 }
766 } else if (i2c->line_status & LINESTAT_NACK_DET) {
767 i2c->msg_status = -EIO;
768 next_cmd = CMD_GEN_STOP;
769 }
770 break;
771 case CMD_RET_DATA:
772 if (i2c->line_status & LINESTAT_INPUT_HELD_V) {
773 *i2c->msg.buf = (i2c->line_status &
774 LINESTAT_INPUT_DATA)
775 >> LINESTAT_INPUT_DATA_SHIFT;
776 --i2c->msg.len;
777 ++i2c->msg.buf;
778 if (i2c->msg.len)
779 next_cmd = CMD_GEN_ACK;
780 else
781 next_cmd = CMD_GEN_NACK;
782 }
783 break;
784 case CMD_GEN_ACK:
785 if (i2c->line_status & LINESTAT_ACK_DET) {
786 next_cmd = CMD_RET_DATA;
787 } else {
788 i2c->msg_status = -EIO;
789 next_cmd = CMD_GEN_STOP;
790 }
791 break;
792 case CMD_GEN_NACK:
793 next_cmd = CMD_GEN_STOP;
794 break;
795 case CMD_GEN_STOP:
796 img_i2c_writel(i2c, SCB_OVERRIDE_REG, 0);
797 return ISR_COMPLETE(0);
798 default:
799 dev_err(i2c->adap.dev.parent, "bad atomic command %d\n",
800 i2c->at_cur_cmd);
801 i2c->msg_status = -EIO;
802 next_cmd = CMD_GEN_STOP;
803 break;
804 }
805
806next_atomic_cmd:
807 if (next_cmd != -1) {
808 /* don't actually stop unless we're the last transaction */
809 if (next_cmd == CMD_GEN_STOP && !i2c->msg_status &&
810 !i2c->last_msg)
811 return ISR_COMPLETE(0);
812 img_i2c_atomic_op(i2c, next_cmd, next_data);
813 }
814 return 0;
815}
816
817/*
818 * Timer function to check if something has gone wrong in automatic mode (so we
819 * don't have to handle so many interrupts just to catch an exception).
820 */
821static void img_i2c_check_timer(unsigned long arg)
822{
823 struct img_i2c *i2c = (struct img_i2c *)arg;
824 unsigned long flags;
825 unsigned int line_status;
826
827 spin_lock_irqsave(&i2c->lock, flags);
828 line_status = img_i2c_readl(i2c, SCB_STATUS_REG);
829
830 /* check for an abort condition */
831 if (line_status & LINESTAT_ABORT_DET) {
832 dev_dbg(i2c->adap.dev.parent,
833 "abort condition detected by check timer\n");
834 /* enable slave event interrupt mask to trigger irq */
835 img_i2c_writel(i2c, SCB_INT_MASK_REG,
836 i2c->int_enable | INT_SLAVE_EVENT);
837 }
838
839 spin_unlock_irqrestore(&i2c->lock, flags);
840}
841
842static unsigned int img_i2c_auto(struct img_i2c *i2c,
843 unsigned int int_status,
844 unsigned int line_status)
845{
846 if (int_status & (INT_WRITE_ACK_ERR | INT_ADDR_ACK_ERR))
847 return ISR_COMPLETE(EIO);
848
849 if (line_status & LINESTAT_ABORT_DET) {
850 dev_dbg(i2c->adap.dev.parent, "abort condition detected\n");
851 /* empty the read fifo */
852 if ((i2c->msg.flags & I2C_M_RD) &&
853 (int_status & INT_FIFO_FULL_FILLING))
854 img_i2c_read_fifo(i2c);
855 /* use atomic mode and try to force a stop bit */
856 i2c->msg_status = -EIO;
857 img_i2c_stop_start(i2c);
858 return 0;
859 }
860
861 /* Enable transaction halt on start bit */
862 if (!i2c->last_msg && i2c->line_status & LINESTAT_START_BIT_DET) {
863 img_i2c_transaction_halt(i2c, true);
864 /* we're no longer interested in the slave event */
865 i2c->int_enable &= ~INT_SLAVE_EVENT;
866 }
867
868 mod_timer(&i2c->check_timer, jiffies + msecs_to_jiffies(1));
869
870 if (i2c->msg.flags & I2C_M_RD) {
871 if (int_status & INT_FIFO_FULL_FILLING) {
872 img_i2c_read_fifo(i2c);
873 if (i2c->msg.len == 0)
874 return ISR_WAITSTOP;
875 }
876 } else {
877 if (int_status & INT_FIFO_EMPTY_EMPTYING) {
878 /*
879 * The write fifo empty indicates that we're in the
880 * last byte so it's safe to start a new write
881 * transaction without losing any bytes from the
882 * previous one.
883 * see 2.3.7 Repeated Start Transactions.
884 */
885 if ((int_status & INT_FIFO_EMPTY) &&
886 i2c->msg.len == 0)
887 return ISR_WAITSTOP;
888 img_i2c_write_fifo(i2c);
889 }
890 }
891
892 return 0;
893}
894
895static irqreturn_t img_i2c_isr(int irq, void *dev_id)
896{
897 struct img_i2c *i2c = (struct img_i2c *)dev_id;
898 u32 int_status, line_status;
899 /* We handle transaction completion AFTER accessing registers */
900 unsigned int hret;
901
902 /* Read interrupt status register. */
903 int_status = img_i2c_readl(i2c, SCB_INT_STATUS_REG);
904 /* Clear detected interrupts. */
905 img_i2c_writel(i2c, SCB_INT_CLEAR_REG, int_status);
906
907 /*
908 * Read line status and clear it until it actually is clear. We have
909 * to be careful not to lose any line status bits that get latched.
910 */
911 line_status = img_i2c_readl(i2c, SCB_STATUS_REG);
912 if (line_status & LINESTAT_LATCHED) {
913 img_i2c_writel(i2c, SCB_CLEAR_REG,
914 (line_status & LINESTAT_LATCHED)
915 >> LINESTAT_CLEAR_SHIFT);
916 img_i2c_wr_rd_fence(i2c);
917 }
918
919 spin_lock(&i2c->lock);
920
921 /* Keep track of line status bits received */
922 i2c->line_status &= ~LINESTAT_INPUT_DATA;
923 i2c->line_status |= line_status;
924
925 /*
926 * Certain interrupts indicate that sclk low timeout is not
927 * a problem. If any of these are set, just continue.
928 */
929 if ((int_status & INT_SCLK_LOW_TIMEOUT) &&
930 !(int_status & (INT_SLAVE_EVENT |
931 INT_FIFO_EMPTY |
932 INT_FIFO_FULL))) {
933 dev_crit(i2c->adap.dev.parent,
934 "fatal: clock low timeout occurred %s addr 0x%02x\n",
935 (i2c->msg.flags & I2C_M_RD) ? "reading" : "writing",
936 i2c->msg.addr);
937 hret = ISR_FATAL(EIO);
938 goto out;
939 }
940
941 if (i2c->mode == MODE_ATOMIC)
942 hret = img_i2c_atomic(i2c, int_status, line_status);
943 else if (i2c->mode == MODE_AUTOMATIC)
944 hret = img_i2c_auto(i2c, int_status, line_status);
945 else if (i2c->mode == MODE_SEQUENCE)
946 hret = img_i2c_sequence(i2c, int_status);
947 else if (i2c->mode == MODE_WAITSTOP && (int_status & INT_SLAVE_EVENT) &&
948 (line_status & LINESTAT_STOP_BIT_DET))
949 hret = ISR_COMPLETE(0);
950 else if (i2c->mode == MODE_RAW)
951 hret = img_i2c_raw(i2c, int_status, line_status);
952 else
953 hret = 0;
954
955 /* Clear detected level interrupts. */
956 img_i2c_writel(i2c, SCB_INT_CLEAR_REG, int_status & INT_LEVEL);
957
958out:
959 if (hret & ISR_WAITSTOP) {
960 /*
961 * Only wait for stop on last message.
962 * Also we may already have detected the stop bit.
963 */
964 if (!i2c->last_msg || i2c->line_status & LINESTAT_STOP_BIT_DET)
965 hret = ISR_COMPLETE(0);
966 else
967 img_i2c_switch_mode(i2c, MODE_WAITSTOP);
968 }
969
970 /* now we've finished using regs, handle transaction completion */
971 if (hret & ISR_COMPLETE_M) {
972 int status = -(hret & ISR_STATUS_M);
973
974 img_i2c_complete_transaction(i2c, status);
975 if (hret & ISR_FATAL_M)
976 img_i2c_switch_mode(i2c, MODE_FATAL);
977 }
978
979 /* Enable interrupts (int_enable may be altered by changing mode) */
980 img_i2c_writel(i2c, SCB_INT_MASK_REG, i2c->int_enable);
981
982 spin_unlock(&i2c->lock);
983
984 return IRQ_HANDLED;
985}
986
987/* Force a bus reset sequence and wait for it to complete */
988static int img_i2c_reset_bus(struct img_i2c *i2c)
989{
990 unsigned long flags;
991 int ret;
992
993 spin_lock_irqsave(&i2c->lock, flags);
994 reinit_completion(&i2c->msg_complete);
995 img_i2c_reset_start(i2c);
996 spin_unlock_irqrestore(&i2c->lock, flags);
997
998 ret = wait_for_completion_timeout(&i2c->msg_complete, IMG_I2C_TIMEOUT);
999 if (ret == 0)
1000 return -ETIMEDOUT;
1001 return 0;
1002}
1003
1004static int img_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
1005 int num)
1006{
1007 struct img_i2c *i2c = i2c_get_adapdata(adap);
1008 bool atomic = false;
1009 int i, ret;
1010
1011 if (i2c->mode == MODE_SUSPEND) {
1012 WARN(1, "refusing to service transaction in suspended state\n");
1013 return -EIO;
1014 }
1015
1016 if (i2c->mode == MODE_FATAL)
1017 return -EIO;
1018
1019 for (i = 0; i < num; i++) {
1020 if (likely(msgs[i].len))
1021 continue;
1022 /*
1023 * 0 byte reads are not possible because the slave could try
1024 * and pull the data line low, preventing a stop bit.
1025 */
1026 if (unlikely(msgs[i].flags & I2C_M_RD))
1027 return -EIO;
1028 /*
1029 * 0 byte writes are possible and used for probing, but we
1030 * cannot do them in automatic mode, so use atomic mode
1031 * instead.
1032 */
1033 atomic = true;
1034 }
1035
1036 ret = clk_prepare_enable(i2c->scb_clk);
1037 if (ret)
1038 return ret;
1039
1040 for (i = 0; i < num; i++) {
1041 struct i2c_msg *msg = &msgs[i];
1042 unsigned long flags;
1043
1044 spin_lock_irqsave(&i2c->lock, flags);
1045
1046 /*
1047 * Make a copy of the message struct. We mustn't modify the
1048 * original or we'll confuse drivers and i2c-dev.
1049 */
1050 i2c->msg = *msg;
1051 i2c->msg_status = 0;
1052
1053 /*
1054 * After the last message we must have waited for a stop bit.
1055 * Not waiting can cause problems when the clock is disabled
1056 * before the stop bit is sent, and the linux I2C interface
1057 * requires separate transfers not to joined with repeated
1058 * start.
1059 */
1060 i2c->last_msg = (i == num - 1);
1061 reinit_completion(&i2c->msg_complete);
1062
1063 if (atomic)
1064 img_i2c_atomic_start(i2c);
1065 else if (msg->flags & I2C_M_RD)
1066 img_i2c_read(i2c);
1067 else
1068 img_i2c_write(i2c);
1069 spin_unlock_irqrestore(&i2c->lock, flags);
1070
1071 ret = wait_for_completion_timeout(&i2c->msg_complete,
1072 IMG_I2C_TIMEOUT);
1073 del_timer_sync(&i2c->check_timer);
1074
1075 if (ret == 0) {
1076 dev_err(adap->dev.parent, "i2c transfer timed out\n");
1077 i2c->msg_status = -ETIMEDOUT;
1078 break;
1079 }
1080
1081 if (i2c->msg_status)
1082 break;
1083 }
1084
1085 clk_disable_unprepare(i2c->scb_clk);
1086
1087 return i2c->msg_status ? i2c->msg_status : num;
1088}
1089
1090static u32 img_i2c_func(struct i2c_adapter *adap)
1091{
1092 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
1093}
1094
1095static const struct i2c_algorithm img_i2c_algo = {
1096 .master_xfer = img_i2c_xfer,
1097 .functionality = img_i2c_func,
1098};
1099
1100static int img_i2c_init(struct img_i2c *i2c)
1101{
1102 unsigned int clk_khz, bitrate_khz, clk_period, tckh, tckl, tsdh;
1103 unsigned int i, ret, data, prescale, inc, int_bitrate, filt;
1104 struct img_i2c_timings timing;
1105 u32 rev;
1106
1107 ret = clk_prepare_enable(i2c->scb_clk);
1108 if (ret)
1109 return ret;
1110
1111 rev = img_i2c_readl(i2c, SCB_CORE_REV_REG);
1112 if ((rev & 0x00ffffff) < 0x00020200) {
1113 dev_info(i2c->adap.dev.parent,
1114 "Unknown hardware revision (%d.%d.%d.%d)\n",
1115 (rev >> 24) & 0xff, (rev >> 16) & 0xff,
1116 (rev >> 8) & 0xff, rev & 0xff);
1117 clk_disable_unprepare(i2c->scb_clk);
1118 return -EINVAL;
1119 }
1120
1121 if (rev == REL_SOC_IP_SCB_2_2_1) {
1122 i2c->need_wr_rd_fence = true;
1123 dev_info(i2c->adap.dev.parent, "fence quirk enabled");
1124 }
1125
1126 bitrate_khz = i2c->bitrate / 1000;
1127 clk_khz = clk_get_rate(i2c->scb_clk) / 1000;
1128
1129 /* Determine what mode we're in from the bitrate */
1130 timing = timings[0];
1131 for (i = 0; i < ARRAY_SIZE(timings); i++) {
1132 if (i2c->bitrate <= timings[i].max_bitrate) {
1133 timing = timings[i];
1134 break;
1135 }
1136 }
1137
1138 /* Find the prescale that would give us that inc (approx delay = 0) */
1139 prescale = SCB_OPT_INC * clk_khz / (256 * 16 * bitrate_khz);
1140 prescale = clamp_t(unsigned int, prescale, 1, 8);
1141 clk_khz /= prescale;
1142
1143 /* Setup the clock increment value */
1144 inc = (256 * 16 * bitrate_khz) / clk_khz;
1145
1146 /*
1147 * The clock generation logic allows to filter glitches on the bus.
1148 * This filter is able to remove bus glitches shorter than 50ns.
1149 * If the clock enable rate is greater than 20 MHz, no filtering
1150 * is required, so we need to disable it.
1151 * If it's between the 20-40 MHz range, there's no need to divide
1152 * the clock to get a filter.
1153 */
1154 if (clk_khz < 20000) {
1155 filt = SCB_FILT_DISABLE;
1156 } else if (clk_khz < 40000) {
1157 filt = SCB_FILT_BYPASS;
1158 } else {
1159 /* Calculate filter clock */
1160 filt = (64000 / ((clk_khz / 1000) * SCB_FILT_GLITCH));
1161
1162 /* Scale up if needed */
1163 if (64000 % ((clk_khz / 1000) * SCB_FILT_GLITCH))
1164 inc++;
1165
1166 if (filt > SCB_FILT_INC_MASK)
1167 filt = SCB_FILT_INC_MASK;
1168
1169 filt = (filt & SCB_FILT_INC_MASK) << SCB_FILT_INC_SHIFT;
1170 }
1171 data = filt | ((inc & SCB_INC_MASK) << SCB_INC_SHIFT) | (prescale - 1);
1172 img_i2c_writel(i2c, SCB_CLK_SET_REG, data);
1173
1174 /* Obtain the clock period of the fx16 clock in ns */
1175 clk_period = (256 * 1000000) / (clk_khz * inc);
1176
1177 /* Calculate the bitrate in terms of internal clock pulses */
1178 int_bitrate = 1000000 / (bitrate_khz * clk_period);
1179 if ((1000000 % (bitrate_khz * clk_period)) >=
1180 ((bitrate_khz * clk_period) / 2))
1181 int_bitrate++;
1182
1183 /* Setup TCKH value */
1184 tckh = timing.tckh / clk_period;
1185 if (timing.tckh % clk_period)
1186 tckh++;
1187
1188 if (tckh > 0)
1189 data = tckh - 1;
1190 else
1191 data = 0;
1192
1193 img_i2c_writel(i2c, SCB_TIME_TCKH_REG, data);
1194
1195 /* Setup TCKL value */
1196 tckl = int_bitrate - tckh;
1197
1198 if (tckl > 0)
1199 data = tckl - 1;
1200 else
1201 data = 0;
1202
1203 img_i2c_writel(i2c, SCB_TIME_TCKL_REG, data);
1204
1205 /* Setup TSDH value */
1206 tsdh = timing.tsdh / clk_period;
1207 if (timing.tsdh % clk_period)
1208 tsdh++;
1209
1210 if (tsdh > 1)
1211 data = tsdh - 1;
1212 else
1213 data = 0x01;
1214 img_i2c_writel(i2c, SCB_TIME_TSDH_REG, data);
1215
1216 /* This value is used later */
1217 tsdh = data;
1218
1219 /* Setup TPL value */
1220 data = timing.tpl / clk_period;
1221 if (data > 0)
1222 --data;
1223 img_i2c_writel(i2c, SCB_TIME_TPL_REG, data);
1224
1225 /* Setup TPH value */
1226 data = timing.tph / clk_period;
1227 if (data > 0)
1228 --data;
1229 img_i2c_writel(i2c, SCB_TIME_TPH_REG, data);
1230
1231 /* Setup TSDL value to TPL + TSDH + 2 */
1232 img_i2c_writel(i2c, SCB_TIME_TSDL_REG, data + tsdh + 2);
1233
1234 /* Setup TP2S value */
1235 data = timing.tp2s / clk_period;
1236 if (data > 0)
1237 --data;
1238 img_i2c_writel(i2c, SCB_TIME_TP2S_REG, data);
1239
1240 img_i2c_writel(i2c, SCB_TIME_TBI_REG, TIMEOUT_TBI);
1241 img_i2c_writel(i2c, SCB_TIME_TSL_REG, TIMEOUT_TSL);
1242 img_i2c_writel(i2c, SCB_TIME_TDL_REG, TIMEOUT_TDL);
1243
1244 /* Take module out of soft reset and enable clocks */
1245 img_i2c_soft_reset(i2c);
1246
1247 /* Disable all interrupts */
1248 img_i2c_writel(i2c, SCB_INT_MASK_REG, 0);
1249
1250 /* Clear all interrupts */
1251 img_i2c_writel(i2c, SCB_INT_CLEAR_REG, ~0);
1252
1253 /* Clear the scb_line_status events */
1254 img_i2c_writel(i2c, SCB_CLEAR_REG, ~0);
1255
1256 /* Enable interrupts */
1257 img_i2c_writel(i2c, SCB_INT_MASK_REG, i2c->int_enable);
1258
1259 /* Perform a synchronous sequence to reset the bus */
1260 ret = img_i2c_reset_bus(i2c);
1261
1262 clk_disable_unprepare(i2c->scb_clk);
1263
1264 return ret;
1265}
1266
1267static int img_i2c_probe(struct platform_device *pdev)
1268{
1269 struct device_node *node = pdev->dev.of_node;
1270 struct img_i2c *i2c;
1271 struct resource *res;
1272 int irq, ret;
1273 u32 val;
1274
1275 i2c = devm_kzalloc(&pdev->dev, sizeof(struct img_i2c), GFP_KERNEL);
1276 if (!i2c)
1277 return -ENOMEM;
1278
1279 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1280 i2c->base = devm_ioremap_resource(&pdev->dev, res);
1281 if (IS_ERR(i2c->base))
1282 return PTR_ERR(i2c->base);
1283
1284 irq = platform_get_irq(pdev, 0);
1285 if (irq < 0) {
1286 dev_err(&pdev->dev, "can't get irq number\n");
1287 return irq;
1288 }
1289
1290 i2c->sys_clk = devm_clk_get(&pdev->dev, "sys");
1291 if (IS_ERR(i2c->sys_clk)) {
1292 dev_err(&pdev->dev, "can't get system clock\n");
1293 return PTR_ERR(i2c->sys_clk);
1294 }
1295
1296 i2c->scb_clk = devm_clk_get(&pdev->dev, "scb");
1297 if (IS_ERR(i2c->scb_clk)) {
1298 dev_err(&pdev->dev, "can't get core clock\n");
1299 return PTR_ERR(i2c->scb_clk);
1300 }
1301
1302 ret = devm_request_irq(&pdev->dev, irq, img_i2c_isr, 0,
1303 pdev->name, i2c);
1304 if (ret) {
1305 dev_err(&pdev->dev, "can't request irq %d\n", irq);
1306 return ret;
1307 }
1308
1309 /* Set up the exception check timer */
1310 init_timer(&i2c->check_timer);
1311 i2c->check_timer.function = img_i2c_check_timer;
1312 i2c->check_timer.data = (unsigned long)i2c;
1313
1314 i2c->bitrate = timings[0].max_bitrate;
1315 if (!of_property_read_u32(node, "clock-frequency", &val))
1316 i2c->bitrate = val;
1317
1318 i2c_set_adapdata(&i2c->adap, i2c);
1319 i2c->adap.dev.parent = &pdev->dev;
1320 i2c->adap.dev.of_node = node;
1321 i2c->adap.owner = THIS_MODULE;
1322 i2c->adap.algo = &img_i2c_algo;
1323 i2c->adap.retries = 5;
1324 i2c->adap.nr = pdev->id;
1325 snprintf(i2c->adap.name, sizeof(i2c->adap.name), "IMG SCB I2C");
1326
1327 img_i2c_switch_mode(i2c, MODE_INACTIVE);
1328 spin_lock_init(&i2c->lock);
1329 init_completion(&i2c->msg_complete);
1330
1331 platform_set_drvdata(pdev, i2c);
1332
1333 ret = clk_prepare_enable(i2c->sys_clk);
1334 if (ret)
1335 return ret;
1336
1337 ret = img_i2c_init(i2c);
1338 if (ret)
1339 goto disable_clk;
1340
1341 ret = i2c_add_numbered_adapter(&i2c->adap);
1342 if (ret < 0) {
1343 dev_err(&pdev->dev, "failed to add adapter\n");
1344 goto disable_clk;
1345 }
1346
1347 return 0;
1348
1349disable_clk:
1350 clk_disable_unprepare(i2c->sys_clk);
1351 return ret;
1352}
1353
1354static int img_i2c_remove(struct platform_device *dev)
1355{
1356 struct img_i2c *i2c = platform_get_drvdata(dev);
1357
1358 i2c_del_adapter(&i2c->adap);
1359 clk_disable_unprepare(i2c->sys_clk);
1360
1361 return 0;
1362}
1363
1364#ifdef CONFIG_PM_SLEEP
1365static int img_i2c_suspend(struct device *dev)
1366{
1367 struct img_i2c *i2c = dev_get_drvdata(dev);
1368
1369 img_i2c_switch_mode(i2c, MODE_SUSPEND);
1370
1371 clk_disable_unprepare(i2c->sys_clk);
1372
1373 return 0;
1374}
1375
1376static int img_i2c_resume(struct device *dev)
1377{
1378 struct img_i2c *i2c = dev_get_drvdata(dev);
1379 int ret;
1380
1381 ret = clk_prepare_enable(i2c->sys_clk);
1382 if (ret)
1383 return ret;
1384
1385 img_i2c_init(i2c);
1386
1387 return 0;
1388}
1389#endif /* CONFIG_PM_SLEEP */
1390
1391static SIMPLE_DEV_PM_OPS(img_i2c_pm, img_i2c_suspend, img_i2c_resume);
1392
1393static const struct of_device_id img_scb_i2c_match[] = {
1394 { .compatible = "img,scb-i2c" },
1395 { }
1396};
1397MODULE_DEVICE_TABLE(of, img_scb_i2c_match);
1398
1399static struct platform_driver img_scb_i2c_driver = {
1400 .driver = {
1401 .name = "img-i2c-scb",
1402 .of_match_table = img_scb_i2c_match,
1403 .pm = &img_i2c_pm,
1404 },
1405 .probe = img_i2c_probe,
1406 .remove = img_i2c_remove,
1407};
1408module_platform_driver(img_scb_i2c_driver);
1409
1410MODULE_AUTHOR("James Hogan <james.hogan@imgtec.com>");
1411MODULE_DESCRIPTION("IMG host I2C driver");
1412MODULE_LICENSE("GPL v2");
diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c
index e9fb7cf78612..aab1f4bb9e30 100644
--- a/drivers/i2c/busses/i2c-imx.c
+++ b/drivers/i2c/busses/i2c-imx.c
@@ -32,22 +32,27 @@
32/** Includes ******************************************************************* 32/** Includes *******************************************************************
33*******************************************************************************/ 33*******************************************************************************/
34 34
35#include <linux/init.h> 35#include <linux/clk.h>
36#include <linux/kernel.h> 36#include <linux/completion.h>
37#include <linux/module.h>
38#include <linux/errno.h>
39#include <linux/err.h>
40#include <linux/interrupt.h>
41#include <linux/delay.h> 37#include <linux/delay.h>
38#include <linux/dma-mapping.h>
39#include <linux/dmaengine.h>
40#include <linux/dmapool.h>
41#include <linux/err.h>
42#include <linux/errno.h>
42#include <linux/i2c.h> 43#include <linux/i2c.h>
44#include <linux/init.h>
45#include <linux/interrupt.h>
43#include <linux/io.h> 46#include <linux/io.h>
44#include <linux/sched.h> 47#include <linux/kernel.h>
45#include <linux/platform_device.h> 48#include <linux/module.h>
46#include <linux/clk.h>
47#include <linux/slab.h>
48#include <linux/of.h> 49#include <linux/of.h>
49#include <linux/of_device.h> 50#include <linux/of_device.h>
51#include <linux/of_dma.h>
50#include <linux/platform_data/i2c-imx.h> 52#include <linux/platform_data/i2c-imx.h>
53#include <linux/platform_device.h>
54#include <linux/sched.h>
55#include <linux/slab.h>
51 56
52/** Defines ******************************************************************** 57/** Defines ********************************************************************
53*******************************************************************************/ 58*******************************************************************************/
@@ -58,6 +63,15 @@
58/* Default value */ 63/* Default value */
59#define IMX_I2C_BIT_RATE 100000 /* 100kHz */ 64#define IMX_I2C_BIT_RATE 100000 /* 100kHz */
60 65
66/*
67 * Enable DMA if transfer byte size is bigger than this threshold.
68 * As the hardware request, it must bigger than 4 bytes.\
69 * I have set '16' here, maybe it's not the best but I think it's
70 * the appropriate.
71 */
72#define DMA_THRESHOLD 16
73#define DMA_TIMEOUT 1000
74
61/* IMX I2C registers: 75/* IMX I2C registers:
62 * the I2C register offset is different between SoCs, 76 * the I2C register offset is different between SoCs,
63 * to provid support for all these chips, split the 77 * to provid support for all these chips, split the
@@ -83,6 +97,7 @@
83#define I2SR_IBB 0x20 97#define I2SR_IBB 0x20
84#define I2SR_IAAS 0x40 98#define I2SR_IAAS 0x40
85#define I2SR_ICF 0x80 99#define I2SR_ICF 0x80
100#define I2CR_DMAEN 0x02
86#define I2CR_RSTA 0x04 101#define I2CR_RSTA 0x04
87#define I2CR_TXAK 0x08 102#define I2CR_TXAK 0x08
88#define I2CR_MTX 0x10 103#define I2CR_MTX 0x10
@@ -169,6 +184,17 @@ struct imx_i2c_hwdata {
169 unsigned i2cr_ien_opcode; 184 unsigned i2cr_ien_opcode;
170}; 185};
171 186
187struct imx_i2c_dma {
188 struct dma_chan *chan_tx;
189 struct dma_chan *chan_rx;
190 struct dma_chan *chan_using;
191 struct completion cmd_complete;
192 dma_addr_t dma_buf;
193 unsigned int dma_len;
194 enum dma_transfer_direction dma_transfer_dir;
195 enum dma_data_direction dma_data_dir;
196};
197
172struct imx_i2c_struct { 198struct imx_i2c_struct {
173 struct i2c_adapter adapter; 199 struct i2c_adapter adapter;
174 struct clk *clk; 200 struct clk *clk;
@@ -181,6 +207,8 @@ struct imx_i2c_struct {
181 unsigned int cur_clk; 207 unsigned int cur_clk;
182 unsigned int bitrate; 208 unsigned int bitrate;
183 const struct imx_i2c_hwdata *hwdata; 209 const struct imx_i2c_hwdata *hwdata;
210
211 struct imx_i2c_dma *dma;
184}; 212};
185 213
186static const struct imx_i2c_hwdata imx1_i2c_hwdata = { 214static const struct imx_i2c_hwdata imx1_i2c_hwdata = {
@@ -251,6 +279,138 @@ static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx,
251 return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift)); 279 return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift));
252} 280}
253 281
282/* Functions for DMA support */
283static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx,
284 dma_addr_t phy_addr)
285{
286 struct imx_i2c_dma *dma;
287 struct dma_slave_config dma_sconfig;
288 struct device *dev = &i2c_imx->adapter.dev;
289 int ret;
290
291 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
292 if (!dma)
293 return;
294
295 dma->chan_tx = dma_request_slave_channel(dev, "tx");
296 if (!dma->chan_tx) {
297 dev_dbg(dev, "can't request DMA tx channel\n");
298 ret = -ENODEV;
299 goto fail_al;
300 }
301
302 dma_sconfig.dst_addr = phy_addr +
303 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift);
304 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
305 dma_sconfig.dst_maxburst = 1;
306 dma_sconfig.direction = DMA_MEM_TO_DEV;
307 ret = dmaengine_slave_config(dma->chan_tx, &dma_sconfig);
308 if (ret < 0) {
309 dev_dbg(dev, "can't configure tx channel\n");
310 goto fail_tx;
311 }
312
313 dma->chan_rx = dma_request_slave_channel(dev, "rx");
314 if (!dma->chan_rx) {
315 dev_dbg(dev, "can't request DMA rx channel\n");
316 ret = -ENODEV;
317 goto fail_tx;
318 }
319
320 dma_sconfig.src_addr = phy_addr +
321 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift);
322 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
323 dma_sconfig.src_maxburst = 1;
324 dma_sconfig.direction = DMA_DEV_TO_MEM;
325 ret = dmaengine_slave_config(dma->chan_rx, &dma_sconfig);
326 if (ret < 0) {
327 dev_dbg(dev, "can't configure rx channel\n");
328 goto fail_rx;
329 }
330
331 i2c_imx->dma = dma;
332 init_completion(&dma->cmd_complete);
333 dev_info(dev, "using %s (tx) and %s (rx) for DMA transfers\n",
334 dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx));
335
336 return;
337
338fail_rx:
339 dma_release_channel(dma->chan_rx);
340fail_tx:
341 dma_release_channel(dma->chan_tx);
342fail_al:
343 devm_kfree(dev, dma);
344 dev_info(dev, "can't use DMA\n");
345}
346
347static void i2c_imx_dma_callback(void *arg)
348{
349 struct imx_i2c_struct *i2c_imx = (struct imx_i2c_struct *)arg;
350 struct imx_i2c_dma *dma = i2c_imx->dma;
351
352 dma_unmap_single(dma->chan_using->device->dev, dma->dma_buf,
353 dma->dma_len, dma->dma_data_dir);
354 complete(&dma->cmd_complete);
355}
356
357static int i2c_imx_dma_xfer(struct imx_i2c_struct *i2c_imx,
358 struct i2c_msg *msgs)
359{
360 struct imx_i2c_dma *dma = i2c_imx->dma;
361 struct dma_async_tx_descriptor *txdesc;
362 struct device *dev = &i2c_imx->adapter.dev;
363 struct device *chan_dev = dma->chan_using->device->dev;
364
365 dma->dma_buf = dma_map_single(chan_dev, msgs->buf,
366 dma->dma_len, dma->dma_data_dir);
367 if (dma_mapping_error(chan_dev, dma->dma_buf)) {
368 dev_err(dev, "DMA mapping failed\n");
369 goto err_map;
370 }
371
372 txdesc = dmaengine_prep_slave_single(dma->chan_using, dma->dma_buf,
373 dma->dma_len, dma->dma_transfer_dir,
374 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
375 if (!txdesc) {
376 dev_err(dev, "Not able to get desc for DMA xfer\n");
377 goto err_desc;
378 }
379
380 txdesc->callback = i2c_imx_dma_callback;
381 txdesc->callback_param = i2c_imx;
382 if (dma_submit_error(dmaengine_submit(txdesc))) {
383 dev_err(dev, "DMA submit failed\n");
384 goto err_submit;
385 }
386
387 dma_async_issue_pending(dma->chan_using);
388 return 0;
389
390err_submit:
391err_desc:
392 dma_unmap_single(chan_dev, dma->dma_buf,
393 dma->dma_len, dma->dma_data_dir);
394err_map:
395 return -EINVAL;
396}
397
398static void i2c_imx_dma_free(struct imx_i2c_struct *i2c_imx)
399{
400 struct imx_i2c_dma *dma = i2c_imx->dma;
401
402 dma->dma_buf = 0;
403 dma->dma_len = 0;
404
405 dma_release_channel(dma->chan_tx);
406 dma->chan_tx = NULL;
407
408 dma_release_channel(dma->chan_rx);
409 dma->chan_rx = NULL;
410
411 dma->chan_using = NULL;
412}
413
254/** Functions for IMX I2C adapter driver *************************************** 414/** Functions for IMX I2C adapter driver ***************************************
255*******************************************************************************/ 415*******************************************************************************/
256 416
@@ -382,6 +542,7 @@ static int i2c_imx_start(struct imx_i2c_struct *i2c_imx)
382 i2c_imx->stopped = 0; 542 i2c_imx->stopped = 0;
383 543
384 temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK; 544 temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK;
545 temp &= ~I2CR_DMAEN;
385 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 546 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
386 return result; 547 return result;
387} 548}
@@ -395,6 +556,8 @@ static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx)
395 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 556 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
396 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 557 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
397 temp &= ~(I2CR_MSTA | I2CR_MTX); 558 temp &= ~(I2CR_MSTA | I2CR_MTX);
559 if (i2c_imx->dma)
560 temp &= ~I2CR_DMAEN;
398 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 561 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
399 } 562 }
400 if (is_imx1_i2c(i2c_imx)) { 563 if (is_imx1_i2c(i2c_imx)) {
@@ -435,6 +598,155 @@ static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
435 return IRQ_NONE; 598 return IRQ_NONE;
436} 599}
437 600
601static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx,
602 struct i2c_msg *msgs)
603{
604 int result;
605 unsigned int temp = 0;
606 unsigned long orig_jiffies = jiffies;
607 struct imx_i2c_dma *dma = i2c_imx->dma;
608 struct device *dev = &i2c_imx->adapter.dev;
609
610 dma->chan_using = dma->chan_tx;
611 dma->dma_transfer_dir = DMA_MEM_TO_DEV;
612 dma->dma_data_dir = DMA_TO_DEVICE;
613 dma->dma_len = msgs->len - 1;
614 result = i2c_imx_dma_xfer(i2c_imx, msgs);
615 if (result)
616 return result;
617
618 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
619 temp |= I2CR_DMAEN;
620 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
621
622 /*
623 * Write slave address.
624 * The first byte must be transmitted by the CPU.
625 */
626 imx_i2c_write_reg(msgs->addr << 1, i2c_imx, IMX_I2C_I2DR);
627 reinit_completion(&i2c_imx->dma->cmd_complete);
628 result = wait_for_completion_timeout(
629 &i2c_imx->dma->cmd_complete,
630 msecs_to_jiffies(DMA_TIMEOUT));
631 if (result <= 0) {
632 dmaengine_terminate_all(dma->chan_using);
633 return result ?: -ETIMEDOUT;
634 }
635
636 /* Waiting for transfer complete. */
637 while (1) {
638 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
639 if (temp & I2SR_ICF)
640 break;
641 if (time_after(jiffies, orig_jiffies +
642 msecs_to_jiffies(DMA_TIMEOUT))) {
643 dev_dbg(dev, "<%s> Timeout\n", __func__);
644 return -ETIMEDOUT;
645 }
646 schedule();
647 }
648
649 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
650 temp &= ~I2CR_DMAEN;
651 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
652
653 /* The last data byte must be transferred by the CPU. */
654 imx_i2c_write_reg(msgs->buf[msgs->len-1],
655 i2c_imx, IMX_I2C_I2DR);
656 result = i2c_imx_trx_complete(i2c_imx);
657 if (result)
658 return result;
659
660 return i2c_imx_acked(i2c_imx);
661}
662
663static int i2c_imx_dma_read(struct imx_i2c_struct *i2c_imx,
664 struct i2c_msg *msgs, bool is_lastmsg)
665{
666 int result;
667 unsigned int temp;
668 unsigned long orig_jiffies = jiffies;
669 struct imx_i2c_dma *dma = i2c_imx->dma;
670 struct device *dev = &i2c_imx->adapter.dev;
671
672 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
673 temp |= I2CR_DMAEN;
674 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
675
676 dma->chan_using = dma->chan_rx;
677 dma->dma_transfer_dir = DMA_DEV_TO_MEM;
678 dma->dma_data_dir = DMA_FROM_DEVICE;
679 /* The last two data bytes must be transferred by the CPU. */
680 dma->dma_len = msgs->len - 2;
681 result = i2c_imx_dma_xfer(i2c_imx, msgs);
682 if (result)
683 return result;
684
685 reinit_completion(&i2c_imx->dma->cmd_complete);
686 result = wait_for_completion_timeout(
687 &i2c_imx->dma->cmd_complete,
688 msecs_to_jiffies(DMA_TIMEOUT));
689 if (result <= 0) {
690 dmaengine_terminate_all(dma->chan_using);
691 return result ?: -ETIMEDOUT;
692 }
693
694 /* waiting for transfer complete. */
695 while (1) {
696 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
697 if (temp & I2SR_ICF)
698 break;
699 if (time_after(jiffies, orig_jiffies +
700 msecs_to_jiffies(DMA_TIMEOUT))) {
701 dev_dbg(dev, "<%s> Timeout\n", __func__);
702 return -ETIMEDOUT;
703 }
704 schedule();
705 }
706
707 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
708 temp &= ~I2CR_DMAEN;
709 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
710
711 /* read n-1 byte data */
712 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
713 temp |= I2CR_TXAK;
714 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
715
716 msgs->buf[msgs->len-2] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
717 /* read n byte data */
718 result = i2c_imx_trx_complete(i2c_imx);
719 if (result)
720 return result;
721
722 if (is_lastmsg) {
723 /*
724 * It must generate STOP before read I2DR to prevent
725 * controller from generating another clock cycle
726 */
727 dev_dbg(dev, "<%s> clear MSTA\n", __func__);
728 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
729 temp &= ~(I2CR_MSTA | I2CR_MTX);
730 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
731 i2c_imx_bus_busy(i2c_imx, 0);
732 i2c_imx->stopped = 1;
733 } else {
734 /*
735 * For i2c master receiver repeat restart operation like:
736 * read -> repeat MSTA -> read/write
737 * The controller must set MTX before read the last byte in
738 * the first read operation, otherwise the first read cost
739 * one extra clock cycle.
740 */
741 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
742 temp |= I2CR_MTX;
743 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
744 }
745 msgs->buf[msgs->len-1] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR);
746
747 return 0;
748}
749
438static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs) 750static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
439{ 751{
440 int i, result; 752 int i, result;
@@ -504,6 +816,9 @@ static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs, bo
504 816
505 dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__); 817 dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__);
506 818
819 if (i2c_imx->dma && msgs->len >= DMA_THRESHOLD && !block_data)
820 return i2c_imx_dma_read(i2c_imx, msgs, is_lastmsg);
821
507 /* read data */ 822 /* read data */
508 for (i = 0; i < msgs->len; i++) { 823 for (i = 0; i < msgs->len; i++) {
509 u8 len = 0; 824 u8 len = 0;
@@ -618,8 +933,12 @@ static int i2c_imx_xfer(struct i2c_adapter *adapter,
618#endif 933#endif
619 if (msgs[i].flags & I2C_M_RD) 934 if (msgs[i].flags & I2C_M_RD)
620 result = i2c_imx_read(i2c_imx, &msgs[i], is_lastmsg); 935 result = i2c_imx_read(i2c_imx, &msgs[i], is_lastmsg);
621 else 936 else {
622 result = i2c_imx_write(i2c_imx, &msgs[i]); 937 if (i2c_imx->dma && msgs[i].len >= DMA_THRESHOLD)
938 result = i2c_imx_dma_write(i2c_imx, &msgs[i]);
939 else
940 result = i2c_imx_write(i2c_imx, &msgs[i]);
941 }
623 if (result) 942 if (result)
624 goto fail0; 943 goto fail0;
625 } 944 }
@@ -654,6 +973,7 @@ static int i2c_imx_probe(struct platform_device *pdev)
654 struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev); 973 struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev);
655 void __iomem *base; 974 void __iomem *base;
656 int irq, ret; 975 int irq, ret;
976 dma_addr_t phy_addr;
657 977
658 dev_dbg(&pdev->dev, "<%s>\n", __func__); 978 dev_dbg(&pdev->dev, "<%s>\n", __func__);
659 979
@@ -668,8 +988,8 @@ static int i2c_imx_probe(struct platform_device *pdev)
668 if (IS_ERR(base)) 988 if (IS_ERR(base))
669 return PTR_ERR(base); 989 return PTR_ERR(base);
670 990
671 i2c_imx = devm_kzalloc(&pdev->dev, sizeof(struct imx_i2c_struct), 991 phy_addr = (dma_addr_t)res->start;
672 GFP_KERNEL); 992 i2c_imx = devm_kzalloc(&pdev->dev, sizeof(*i2c_imx), GFP_KERNEL);
673 if (!i2c_imx) 993 if (!i2c_imx)
674 return -ENOMEM; 994 return -ENOMEM;
675 995
@@ -743,6 +1063,9 @@ static int i2c_imx_probe(struct platform_device *pdev)
743 i2c_imx->adapter.name); 1063 i2c_imx->adapter.name);
744 dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n"); 1064 dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");
745 1065
1066 /* Init DMA config if support*/
1067 i2c_imx_dma_request(i2c_imx, phy_addr);
1068
746 return 0; /* Return OK */ 1069 return 0; /* Return OK */
747 1070
748clk_disable: 1071clk_disable:
@@ -758,6 +1081,9 @@ static int i2c_imx_remove(struct platform_device *pdev)
758 dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n"); 1081 dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n");
759 i2c_del_adapter(&i2c_imx->adapter); 1082 i2c_del_adapter(&i2c_imx->adapter);
760 1083
1084 if (i2c_imx->dma)
1085 i2c_imx_dma_free(i2c_imx);
1086
761 /* setup chip registers to defaults */ 1087 /* setup chip registers to defaults */
762 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR); 1088 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR);
763 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR); 1089 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR);
diff --git a/drivers/i2c/busses/i2c-meson.c b/drivers/i2c/busses/i2c-meson.c
new file mode 100644
index 000000000000..5e176adca8e8
--- /dev/null
+++ b/drivers/i2c/busses/i2c-meson.c
@@ -0,0 +1,492 @@
1/*
2 * I2C bus driver for Amlogic Meson SoCs
3 *
4 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/clk.h>
12#include <linux/completion.h>
13#include <linux/i2c.h>
14#include <linux/interrupt.h>
15#include <linux/io.h>
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/of.h>
19#include <linux/platform_device.h>
20#include <linux/types.h>
21
22/* Meson I2C register map */
23#define REG_CTRL 0x00
24#define REG_SLAVE_ADDR 0x04
25#define REG_TOK_LIST0 0x08
26#define REG_TOK_LIST1 0x0c
27#define REG_TOK_WDATA0 0x10
28#define REG_TOK_WDATA1 0x14
29#define REG_TOK_RDATA0 0x18
30#define REG_TOK_RDATA1 0x1c
31
32/* Control register fields */
33#define REG_CTRL_START BIT(0)
34#define REG_CTRL_ACK_IGNORE BIT(1)
35#define REG_CTRL_STATUS BIT(2)
36#define REG_CTRL_ERROR BIT(3)
37#define REG_CTRL_CLKDIV_SHIFT 12
38#define REG_CTRL_CLKDIV_MASK ((BIT(10) - 1) << REG_CTRL_CLKDIV_SHIFT)
39
40#define I2C_TIMEOUT_MS 500
41#define DEFAULT_FREQ 100000
42
43enum {
44 TOKEN_END = 0,
45 TOKEN_START,
46 TOKEN_SLAVE_ADDR_WRITE,
47 TOKEN_SLAVE_ADDR_READ,
48 TOKEN_DATA,
49 TOKEN_DATA_LAST,
50 TOKEN_STOP,
51};
52
53enum {
54 STATE_IDLE,
55 STATE_READ,
56 STATE_WRITE,
57 STATE_STOP,
58};
59
60/**
61 * struct meson_i2c - Meson I2C device private data
62 *
63 * @adap: I2C adapter instance
64 * @dev: Pointer to device structure
65 * @regs: Base address of the device memory mapped registers
66 * @clk: Pointer to clock structure
67 * @irq: IRQ number
68 * @msg: Pointer to the current I2C message
69 * @state: Current state in the driver state machine
70 * @last: Flag set for the last message in the transfer
71 * @count: Number of bytes to be sent/received in current transfer
72 * @pos: Current position in the send/receive buffer
73 * @error: Flag set when an error is received
74 * @lock: To avoid race conditions between irq handler and xfer code
75 * @done: Completion used to wait for transfer termination
76 * @frequency: Operating frequency of I2C bus clock
77 * @tokens: Sequence of tokens to be written to the device
78 * @num_tokens: Number of tokens
79 */
80struct meson_i2c {
81 struct i2c_adapter adap;
82 struct device *dev;
83 void __iomem *regs;
84 struct clk *clk;
85 int irq;
86
87 struct i2c_msg *msg;
88 int state;
89 bool last;
90 int count;
91 int pos;
92 int error;
93
94 spinlock_t lock;
95 struct completion done;
96 unsigned int frequency;
97 u32 tokens[2];
98 int num_tokens;
99};
100
101static void meson_i2c_set_mask(struct meson_i2c *i2c, int reg, u32 mask,
102 u32 val)
103{
104 u32 data;
105
106 data = readl(i2c->regs + reg);
107 data &= ~mask;
108 data |= val & mask;
109 writel(data, i2c->regs + reg);
110}
111
112static void meson_i2c_reset_tokens(struct meson_i2c *i2c)
113{
114 i2c->tokens[0] = 0;
115 i2c->tokens[1] = 0;
116 i2c->num_tokens = 0;
117}
118
119static void meson_i2c_add_token(struct meson_i2c *i2c, int token)
120{
121 if (i2c->num_tokens < 8)
122 i2c->tokens[0] |= (token & 0xf) << (i2c->num_tokens * 4);
123 else
124 i2c->tokens[1] |= (token & 0xf) << ((i2c->num_tokens % 8) * 4);
125
126 i2c->num_tokens++;
127}
128
129static void meson_i2c_write_tokens(struct meson_i2c *i2c)
130{
131 writel(i2c->tokens[0], i2c->regs + REG_TOK_LIST0);
132 writel(i2c->tokens[1], i2c->regs + REG_TOK_LIST1);
133}
134
135static void meson_i2c_set_clk_div(struct meson_i2c *i2c)
136{
137 unsigned long clk_rate = clk_get_rate(i2c->clk);
138 unsigned int div;
139
140 div = DIV_ROUND_UP(clk_rate, i2c->frequency * 4);
141 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_CLKDIV_MASK,
142 div << REG_CTRL_CLKDIV_SHIFT);
143
144 dev_dbg(i2c->dev, "%s: clk %lu, freq %u, div %u\n", __func__,
145 clk_rate, i2c->frequency, div);
146}
147
148static void meson_i2c_get_data(struct meson_i2c *i2c, char *buf, int len)
149{
150 u32 rdata0, rdata1;
151 int i;
152
153 rdata0 = readl(i2c->regs + REG_TOK_RDATA0);
154 rdata1 = readl(i2c->regs + REG_TOK_RDATA1);
155
156 dev_dbg(i2c->dev, "%s: data %08x %08x len %d\n", __func__,
157 rdata0, rdata1, len);
158
159 for (i = 0; i < min_t(int, 4, len); i++)
160 *buf++ = (rdata0 >> i * 8) & 0xff;
161
162 for (i = 4; i < min_t(int, 8, len); i++)
163 *buf++ = (rdata1 >> (i - 4) * 8) & 0xff;
164}
165
166static void meson_i2c_put_data(struct meson_i2c *i2c, char *buf, int len)
167{
168 u32 wdata0 = 0, wdata1 = 0;
169 int i;
170
171 for (i = 0; i < min_t(int, 4, len); i++)
172 wdata0 |= *buf++ << (i * 8);
173
174 for (i = 4; i < min_t(int, 8, len); i++)
175 wdata1 |= *buf++ << ((i - 4) * 8);
176
177 writel(wdata0, i2c->regs + REG_TOK_WDATA0);
178 writel(wdata0, i2c->regs + REG_TOK_WDATA1);
179
180 dev_dbg(i2c->dev, "%s: data %08x %08x len %d\n", __func__,
181 wdata0, wdata1, len);
182}
183
184static void meson_i2c_prepare_xfer(struct meson_i2c *i2c)
185{
186 bool write = !(i2c->msg->flags & I2C_M_RD);
187 int i;
188
189 i2c->count = min_t(int, i2c->msg->len - i2c->pos, 8);
190
191 for (i = 0; i < i2c->count - 1; i++)
192 meson_i2c_add_token(i2c, TOKEN_DATA);
193
194 if (i2c->count) {
195 if (write || i2c->pos + i2c->count < i2c->msg->len)
196 meson_i2c_add_token(i2c, TOKEN_DATA);
197 else
198 meson_i2c_add_token(i2c, TOKEN_DATA_LAST);
199 }
200
201 if (write)
202 meson_i2c_put_data(i2c, i2c->msg->buf + i2c->pos, i2c->count);
203}
204
205static void meson_i2c_stop(struct meson_i2c *i2c)
206{
207 dev_dbg(i2c->dev, "%s: last %d\n", __func__, i2c->last);
208
209 if (i2c->last) {
210 i2c->state = STATE_STOP;
211 meson_i2c_add_token(i2c, TOKEN_STOP);
212 } else {
213 i2c->state = STATE_IDLE;
214 complete_all(&i2c->done);
215 }
216}
217
218static irqreturn_t meson_i2c_irq(int irqno, void *dev_id)
219{
220 struct meson_i2c *i2c = dev_id;
221 unsigned int ctrl;
222
223 spin_lock(&i2c->lock);
224
225 meson_i2c_reset_tokens(i2c);
226 ctrl = readl(i2c->regs + REG_CTRL);
227
228 dev_dbg(i2c->dev, "irq: state %d, pos %d, count %d, ctrl %08x\n",
229 i2c->state, i2c->pos, i2c->count, ctrl);
230
231 if (ctrl & REG_CTRL_ERROR && i2c->state != STATE_IDLE) {
232 /*
233 * The bit is set when the IGNORE_NAK bit is cleared
234 * and the device didn't respond. In this case, the
235 * I2C controller automatically generates a STOP
236 * condition.
237 */
238 dev_dbg(i2c->dev, "error bit set\n");
239 i2c->error = -ENXIO;
240 i2c->state = STATE_IDLE;
241 complete_all(&i2c->done);
242 goto out;
243 }
244
245 switch (i2c->state) {
246 case STATE_READ:
247 if (i2c->count > 0) {
248 meson_i2c_get_data(i2c, i2c->msg->buf + i2c->pos,
249 i2c->count);
250 i2c->pos += i2c->count;
251 }
252
253 if (i2c->pos >= i2c->msg->len) {
254 meson_i2c_stop(i2c);
255 break;
256 }
257
258 meson_i2c_prepare_xfer(i2c);
259 break;
260 case STATE_WRITE:
261 i2c->pos += i2c->count;
262
263 if (i2c->pos >= i2c->msg->len) {
264 meson_i2c_stop(i2c);
265 break;
266 }
267
268 meson_i2c_prepare_xfer(i2c);
269 break;
270 case STATE_STOP:
271 i2c->state = STATE_IDLE;
272 complete_all(&i2c->done);
273 break;
274 case STATE_IDLE:
275 break;
276 }
277
278out:
279 if (i2c->state != STATE_IDLE) {
280 /* Restart the processing */
281 meson_i2c_write_tokens(i2c);
282 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, 0);
283 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START,
284 REG_CTRL_START);
285 }
286
287 spin_unlock(&i2c->lock);
288
289 return IRQ_HANDLED;
290}
291
292static void meson_i2c_do_start(struct meson_i2c *i2c, struct i2c_msg *msg)
293{
294 int token;
295
296 token = (msg->flags & I2C_M_RD) ? TOKEN_SLAVE_ADDR_READ :
297 TOKEN_SLAVE_ADDR_WRITE;
298
299 writel(msg->addr << 1, i2c->regs + REG_SLAVE_ADDR);
300 meson_i2c_add_token(i2c, TOKEN_START);
301 meson_i2c_add_token(i2c, token);
302}
303
304static int meson_i2c_xfer_msg(struct meson_i2c *i2c, struct i2c_msg *msg,
305 int last)
306{
307 unsigned long time_left, flags;
308 int ret = 0;
309
310 i2c->msg = msg;
311 i2c->last = last;
312 i2c->pos = 0;
313 i2c->count = 0;
314 i2c->error = 0;
315
316 meson_i2c_reset_tokens(i2c);
317
318 flags = (msg->flags & I2C_M_IGNORE_NAK) ? REG_CTRL_ACK_IGNORE : 0;
319 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_ACK_IGNORE, flags);
320
321 if (!(msg->flags & I2C_M_NOSTART))
322 meson_i2c_do_start(i2c, msg);
323
324 i2c->state = (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE;
325 meson_i2c_prepare_xfer(i2c);
326 meson_i2c_write_tokens(i2c);
327 reinit_completion(&i2c->done);
328
329 /* Start the transfer */
330 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, REG_CTRL_START);
331
332 time_left = msecs_to_jiffies(I2C_TIMEOUT_MS);
333 time_left = wait_for_completion_timeout(&i2c->done, time_left);
334
335 /*
336 * Protect access to i2c struct and registers from interrupt
337 * handlers triggered by a transfer terminated after the
338 * timeout period
339 */
340 spin_lock_irqsave(&i2c->lock, flags);
341
342 /* Abort any active operation */
343 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, 0);
344
345 if (!time_left) {
346 i2c->state = STATE_IDLE;
347 ret = -ETIMEDOUT;
348 }
349
350 if (i2c->error)
351 ret = i2c->error;
352
353 spin_unlock_irqrestore(&i2c->lock, flags);
354
355 return ret;
356}
357
358static int meson_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
359 int num)
360{
361 struct meson_i2c *i2c = adap->algo_data;
362 int i, ret = 0, count = 0;
363
364 clk_enable(i2c->clk);
365 meson_i2c_set_clk_div(i2c);
366
367 for (i = 0; i < num; i++) {
368 ret = meson_i2c_xfer_msg(i2c, msgs + i, i == num - 1);
369 if (ret)
370 break;
371 count++;
372 }
373
374 clk_disable(i2c->clk);
375
376 return ret ? ret : count;
377}
378
379static u32 meson_i2c_func(struct i2c_adapter *adap)
380{
381 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
382}
383
384static const struct i2c_algorithm meson_i2c_algorithm = {
385 .master_xfer = meson_i2c_xfer,
386 .functionality = meson_i2c_func,
387};
388
389static int meson_i2c_probe(struct platform_device *pdev)
390{
391 struct device_node *np = pdev->dev.of_node;
392 struct meson_i2c *i2c;
393 struct resource *mem;
394 int ret = 0;
395
396 i2c = devm_kzalloc(&pdev->dev, sizeof(struct meson_i2c), GFP_KERNEL);
397 if (!i2c)
398 return -ENOMEM;
399
400 if (of_property_read_u32(pdev->dev.of_node, "clock-frequency",
401 &i2c->frequency))
402 i2c->frequency = DEFAULT_FREQ;
403
404 i2c->dev = &pdev->dev;
405 platform_set_drvdata(pdev, i2c);
406
407 spin_lock_init(&i2c->lock);
408 init_completion(&i2c->done);
409
410 i2c->clk = devm_clk_get(&pdev->dev, NULL);
411 if (IS_ERR(i2c->clk)) {
412 dev_err(&pdev->dev, "can't get device clock\n");
413 return PTR_ERR(i2c->clk);
414 }
415
416 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
417 i2c->regs = devm_ioremap_resource(&pdev->dev, mem);
418 if (IS_ERR(i2c->regs))
419 return PTR_ERR(i2c->regs);
420
421 i2c->irq = platform_get_irq(pdev, 0);
422 if (i2c->irq < 0) {
423 dev_err(&pdev->dev, "can't find IRQ\n");
424 return i2c->irq;
425 }
426
427 ret = devm_request_irq(&pdev->dev, i2c->irq, meson_i2c_irq,
428 0, dev_name(&pdev->dev), i2c);
429 if (ret < 0) {
430 dev_err(&pdev->dev, "can't request IRQ\n");
431 return ret;
432 }
433
434 ret = clk_prepare(i2c->clk);
435 if (ret < 0) {
436 dev_err(&pdev->dev, "can't prepare clock\n");
437 return ret;
438 }
439
440 strlcpy(i2c->adap.name, "Meson I2C adapter",
441 sizeof(i2c->adap.name));
442 i2c->adap.owner = THIS_MODULE;
443 i2c->adap.algo = &meson_i2c_algorithm;
444 i2c->adap.dev.parent = &pdev->dev;
445 i2c->adap.dev.of_node = np;
446 i2c->adap.algo_data = i2c;
447
448 /*
449 * A transfer is triggered when START bit changes from 0 to 1.
450 * Ensure that the bit is set to 0 after probe
451 */
452 meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, 0);
453
454 ret = i2c_add_adapter(&i2c->adap);
455 if (ret < 0) {
456 dev_err(&pdev->dev, "can't register adapter\n");
457 clk_unprepare(i2c->clk);
458 return ret;
459 }
460
461 return 0;
462}
463
464static int meson_i2c_remove(struct platform_device *pdev)
465{
466 struct meson_i2c *i2c = platform_get_drvdata(pdev);
467
468 i2c_del_adapter(&i2c->adap);
469 clk_unprepare(i2c->clk);
470
471 return 0;
472}
473
474static const struct of_device_id meson_i2c_match[] = {
475 { .compatible = "amlogic,meson6-i2c" },
476 { },
477};
478
479static struct platform_driver meson_i2c_driver = {
480 .probe = meson_i2c_probe,
481 .remove = meson_i2c_remove,
482 .driver = {
483 .name = "meson-i2c",
484 .of_match_table = meson_i2c_match,
485 },
486};
487
488module_platform_driver(meson_i2c_driver);
489
490MODULE_DESCRIPTION("Amlogic Meson I2C Bus driver");
491MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
492MODULE_LICENSE("GPL v2");
diff --git a/drivers/i2c/busses/i2c-mpc.c b/drivers/i2c/busses/i2c-mpc.c
index 0edf630b099a..4c5d7d92b9fe 100644
--- a/drivers/i2c/busses/i2c-mpc.c
+++ b/drivers/i2c/busses/i2c-mpc.c
@@ -124,7 +124,7 @@ static void mpc_i2c_fixup(struct mpc_i2c *i2c)
124static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing) 124static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing)
125{ 125{
126 unsigned long orig_jiffies = jiffies; 126 unsigned long orig_jiffies = jiffies;
127 u32 x; 127 u32 cmd_err;
128 int result = 0; 128 int result = 0;
129 129
130 if (!i2c->irq) { 130 if (!i2c->irq) {
@@ -133,11 +133,11 @@ static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing)
133 if (time_after(jiffies, orig_jiffies + timeout)) { 133 if (time_after(jiffies, orig_jiffies + timeout)) {
134 dev_dbg(i2c->dev, "timeout\n"); 134 dev_dbg(i2c->dev, "timeout\n");
135 writeccr(i2c, 0); 135 writeccr(i2c, 0);
136 result = -EIO; 136 result = -ETIMEDOUT;
137 break; 137 break;
138 } 138 }
139 } 139 }
140 x = readb(i2c->base + MPC_I2C_SR); 140 cmd_err = readb(i2c->base + MPC_I2C_SR);
141 writeb(0, i2c->base + MPC_I2C_SR); 141 writeb(0, i2c->base + MPC_I2C_SR);
142 } else { 142 } else {
143 /* Interrupt mode */ 143 /* Interrupt mode */
@@ -150,28 +150,28 @@ static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing)
150 result = -ETIMEDOUT; 150 result = -ETIMEDOUT;
151 } 151 }
152 152
153 x = i2c->interrupt; 153 cmd_err = i2c->interrupt;
154 i2c->interrupt = 0; 154 i2c->interrupt = 0;
155 } 155 }
156 156
157 if (result < 0) 157 if (result < 0)
158 return result; 158 return result;
159 159
160 if (!(x & CSR_MCF)) { 160 if (!(cmd_err & CSR_MCF)) {
161 dev_dbg(i2c->dev, "unfinished\n"); 161 dev_dbg(i2c->dev, "unfinished\n");
162 return -EIO; 162 return -EIO;
163 } 163 }
164 164
165 if (x & CSR_MAL) { 165 if (cmd_err & CSR_MAL) {
166 dev_dbg(i2c->dev, "MAL\n"); 166 dev_dbg(i2c->dev, "MAL\n");
167 return -EIO; 167 return -EAGAIN;
168 } 168 }
169 169
170 if (writing && (x & CSR_RXAK)) { 170 if (writing && (cmd_err & CSR_RXAK)) {
171 dev_dbg(i2c->dev, "No RXAK\n"); 171 dev_dbg(i2c->dev, "No RXAK\n");
172 /* generate stop */ 172 /* generate stop */
173 writeccr(i2c, CCR_MEN); 173 writeccr(i2c, CCR_MEN);
174 return -EIO; 174 return -ENXIO;
175 } 175 }
176 return 0; 176 return 0;
177} 177}
diff --git a/drivers/i2c/busses/i2c-mxs.c b/drivers/i2c/busses/i2c-mxs.c
index 07e1be6f8992..3e7893aa97ef 100644
--- a/drivers/i2c/busses/i2c-mxs.c
+++ b/drivers/i2c/busses/i2c-mxs.c
@@ -811,7 +811,7 @@ static int mxs_i2c_probe(struct platform_device *pdev)
811 struct resource *res; 811 struct resource *res;
812 int err, irq; 812 int err, irq;
813 813
814 i2c = devm_kzalloc(dev, sizeof(struct mxs_i2c_dev), GFP_KERNEL); 814 i2c = devm_kzalloc(dev, sizeof(*i2c), GFP_KERNEL);
815 if (!i2c) 815 if (!i2c)
816 return -ENOMEM; 816 return -ENOMEM;
817 817
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 0e650a0d0ad0..984fede623ea 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -54,6 +54,9 @@
54/* timeout for pm runtime autosuspend */ 54/* timeout for pm runtime autosuspend */
55#define OMAP_I2C_PM_TIMEOUT 1000 /* ms */ 55#define OMAP_I2C_PM_TIMEOUT 1000 /* ms */
56 56
57/* timeout for making decision on bus free status */
58#define OMAP_I2C_BUS_FREE_TIMEOUT (msecs_to_jiffies(10))
59
57/* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */ 60/* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
58enum { 61enum {
59 OMAP_I2C_REV_REG = 0, 62 OMAP_I2C_REV_REG = 0,
@@ -98,7 +101,7 @@ enum {
98#define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */ 101#define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
99#define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ 102#define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
100#define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */ 103#define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */
101#define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */ 104#define OMAP_I2C_STAT_BF (1 << 8) /* Bus Free */
102#define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ 105#define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
103#define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */ 106#define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */
104#define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */ 107#define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */
@@ -146,16 +149,20 @@ enum {
146#define OMAP_I2C_SCLH_HSSCLH 8 149#define OMAP_I2C_SCLH_HSSCLH 8
147 150
148/* I2C System Test Register (OMAP_I2C_SYSTEST): */ 151/* I2C System Test Register (OMAP_I2C_SYSTEST): */
149#ifdef DEBUG
150#define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ 152#define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
151#define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */ 153#define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */
152#define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */ 154#define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
153#define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */ 155#define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
156/* Functional mode */
157#define OMAP_I2C_SYSTEST_SCL_I_FUNC (1 << 8) /* SCL line input value */
158#define OMAP_I2C_SYSTEST_SCL_O_FUNC (1 << 7) /* SCL line output value */
159#define OMAP_I2C_SYSTEST_SDA_I_FUNC (1 << 6) /* SDA line input value */
160#define OMAP_I2C_SYSTEST_SDA_O_FUNC (1 << 5) /* SDA line output value */
161/* SDA/SCL IO mode */
154#define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */ 162#define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */
155#define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */ 163#define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */
156#define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */ 164#define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */
157#define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */ 165#define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
158#endif
159 166
160/* OCP_SYSSTATUS bit definitions */ 167/* OCP_SYSSTATUS bit definitions */
161#define SYSS_RESETDONE_MASK (1 << 0) 168#define SYSS_RESETDONE_MASK (1 << 0)
@@ -202,6 +209,9 @@ struct omap_i2c_dev {
202 */ 209 */
203 u32 rev; 210 u32 rev;
204 unsigned b_hw:1; /* bad h/w fixes */ 211 unsigned b_hw:1; /* bad h/w fixes */
212 unsigned bb_valid:1; /* true when BB-bit reflects
213 * the I2C bus state
214 */
205 unsigned receiver:1; /* true when we're in receiver mode */ 215 unsigned receiver:1; /* true when we're in receiver mode */
206 u16 iestate; /* Saved interrupt register */ 216 u16 iestate; /* Saved interrupt register */
207 u16 pscstate; 217 u16 pscstate;
@@ -290,6 +300,12 @@ static void __omap_i2c_init(struct omap_i2c_dev *dev)
290 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); 300 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
291 301
292 /* 302 /*
303 * NOTE: right after setting CON_EN, STAT_BB could be 0 while the
304 * bus is busy. It will be changed to 1 on the next IP FCLK clock.
305 * udelay(1) will be enough to fix that.
306 */
307
308 /*
293 * Don't write to this register if the IE state is 0 as it can 309 * Don't write to this register if the IE state is 0 as it can
294 * cause deadlock. 310 * cause deadlock.
295 */ 311 */
@@ -328,7 +344,12 @@ static int omap_i2c_reset(struct omap_i2c_dev *dev)
328 /* SYSC register is cleared by the reset; rewrite it */ 344 /* SYSC register is cleared by the reset; rewrite it */
329 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, sysc); 345 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, sysc);
330 346
347 if (dev->rev > OMAP_I2C_REV_ON_3430_3530) {
348 /* Schedule I2C-bus monitoring on the next transfer */
349 dev->bb_valid = 0;
350 }
331 } 351 }
352
332 return 0; 353 return 0;
333} 354}
334 355
@@ -441,6 +462,11 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
441 dev->scllstate = scll; 462 dev->scllstate = scll;
442 dev->sclhstate = sclh; 463 dev->sclhstate = sclh;
443 464
465 if (dev->rev <= OMAP_I2C_REV_ON_3430_3530) {
466 /* Not implemented */
467 dev->bb_valid = 1;
468 }
469
444 __omap_i2c_init(dev); 470 __omap_i2c_init(dev);
445 471
446 return 0; 472 return 0;
@@ -465,6 +491,91 @@ static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
465 return 0; 491 return 0;
466} 492}
467 493
494/*
495 * Wait while BB-bit doesn't reflect the I2C bus state
496 *
497 * In a multimaster environment, after IP software reset, BB-bit value doesn't
498 * correspond to the current bus state. It may happen what BB-bit will be 0,
499 * while the bus is busy due to another I2C master activity.
500 * Here are BB-bit values after reset:
501 * SDA SCL BB NOTES
502 * 0 0 0 1, 2
503 * 1 0 0 1, 2
504 * 0 1 1
505 * 1 1 0 3
506 * Later, if IP detect SDA=0 and SCL=1 (ACK) or SDA 1->0 while SCL=1 (START)
507 * combinations on the bus, it set BB-bit to 1.
508 * If IP detect SDA 0->1 while SCL=1 (STOP) combination on the bus,
509 * it set BB-bit to 0 and BF to 1.
510 * BB and BF bits correctly tracks the bus state while IP is suspended
511 * BB bit became valid on the next FCLK clock after CON_EN bit set
512 *
513 * NOTES:
514 * 1. Any transfer started when BB=0 and bus is busy wouldn't be
515 * completed by IP and results in controller timeout.
516 * 2. Any transfer started when BB=0 and SCL=0 results in IP
517 * starting to drive SDA low. In that case IP corrupt data
518 * on the bus.
519 * 3. Any transfer started in the middle of another master's transfer
520 * results in unpredictable results and data corruption
521 */
522static int omap_i2c_wait_for_bb_valid(struct omap_i2c_dev *dev)
523{
524 unsigned long bus_free_timeout = 0;
525 unsigned long timeout;
526 int bus_free = 0;
527 u16 stat, systest;
528
529 if (dev->bb_valid)
530 return 0;
531
532 timeout = jiffies + OMAP_I2C_TIMEOUT;
533 while (1) {
534 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
535 /*
536 * We will see BB or BF event in a case IP had detected any
537 * activity on the I2C bus. Now IP correctly tracks the bus
538 * state. BB-bit value is valid.
539 */
540 if (stat & (OMAP_I2C_STAT_BB | OMAP_I2C_STAT_BF))
541 break;
542
543 /*
544 * Otherwise, we must look signals on the bus to make
545 * the right decision.
546 */
547 systest = omap_i2c_read_reg(dev, OMAP_I2C_SYSTEST_REG);
548 if ((systest & OMAP_I2C_SYSTEST_SCL_I_FUNC) &&
549 (systest & OMAP_I2C_SYSTEST_SDA_I_FUNC)) {
550 if (!bus_free) {
551 bus_free_timeout = jiffies +
552 OMAP_I2C_BUS_FREE_TIMEOUT;
553 bus_free = 1;
554 }
555
556 /*
557 * SDA and SCL lines was high for 10 ms without bus
558 * activity detected. The bus is free. Consider
559 * BB-bit value is valid.
560 */
561 if (time_after(jiffies, bus_free_timeout))
562 break;
563 } else {
564 bus_free = 0;
565 }
566
567 if (time_after(jiffies, timeout)) {
568 dev_warn(dev->dev, "timeout waiting for bus ready\n");
569 return -ETIMEDOUT;
570 }
571
572 msleep(1);
573 }
574
575 dev->bb_valid = 1;
576 return 0;
577}
578
468static void omap_i2c_resize_fifo(struct omap_i2c_dev *dev, u8 size, bool is_rx) 579static void omap_i2c_resize_fifo(struct omap_i2c_dev *dev, u8 size, bool is_rx)
469{ 580{
470 u16 buf; 581 u16 buf;
@@ -557,7 +668,11 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
557 668
558 if (!dev->b_hw && stop) 669 if (!dev->b_hw && stop)
559 w |= OMAP_I2C_CON_STP; 670 w |= OMAP_I2C_CON_STP;
560 671 /*
672 * NOTE: STAT_BB bit could became 1 here if another master occupy
673 * the bus. IP successfully complete transfer when the bus will be
674 * free again (BB reset to 0).
675 */
561 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w); 676 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
562 677
563 /* 678 /*
@@ -600,13 +715,15 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
600 return 0; 715 return 0;
601 716
602 /* We have an error */ 717 /* We have an error */
603 if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR | 718 if (dev->cmd_err & (OMAP_I2C_STAT_ROVR | OMAP_I2C_STAT_XUDF)) {
604 OMAP_I2C_STAT_XUDF)) {
605 omap_i2c_reset(dev); 719 omap_i2c_reset(dev);
606 __omap_i2c_init(dev); 720 __omap_i2c_init(dev);
607 return -EIO; 721 return -EIO;
608 } 722 }
609 723
724 if (dev->cmd_err & OMAP_I2C_STAT_AL)
725 return -EAGAIN;
726
610 if (dev->cmd_err & OMAP_I2C_STAT_NACK) { 727 if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
611 if (msg->flags & I2C_M_IGNORE_NAK) 728 if (msg->flags & I2C_M_IGNORE_NAK)
612 return 0; 729 return 0;
@@ -635,6 +752,10 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
635 if (r < 0) 752 if (r < 0)
636 goto out; 753 goto out;
637 754
755 r = omap_i2c_wait_for_bb_valid(dev);
756 if (r < 0)
757 goto out;
758
638 r = omap_i2c_wait_for_bb(dev); 759 r = omap_i2c_wait_for_bb(dev);
639 if (r < 0) 760 if (r < 0)
640 goto out; 761 goto out;
diff --git a/drivers/i2c/busses/i2c-pxa.c b/drivers/i2c/busses/i2c-pxa.c
index be671f7a0e06..f80df8f84609 100644
--- a/drivers/i2c/busses/i2c-pxa.c
+++ b/drivers/i2c/busses/i2c-pxa.c
@@ -885,7 +885,9 @@ static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr)
885 return; /* ignore */ 885 return; /* ignore */
886 } 886 }
887 887
888 if (isr & ISR_BED) { 888 if ((isr & ISR_BED) &&
889 (!((i2c->msg->flags & I2C_M_IGNORE_NAK) &&
890 (isr & ISR_ACKNAK)))) {
889 int ret = BUS_ERROR; 891 int ret = BUS_ERROR;
890 892
891 /* 893 /*
@@ -919,12 +921,14 @@ static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr)
919 icr |= ICR_ALDIE | ICR_TB; 921 icr |= ICR_ALDIE | ICR_TB;
920 922
921 /* 923 /*
922 * If this is the last byte of the last message, send 924 * If this is the last byte of the last message or last byte
923 * a STOP. 925 * of any message with I2C_M_STOP (e.g. SCCB), send a STOP.
924 */ 926 */
925 if (i2c->msg_ptr == i2c->msg->len && 927 if ((i2c->msg_ptr == i2c->msg->len) &&
926 i2c->msg_idx == i2c->msg_num - 1) 928 ((i2c->msg->flags & I2C_M_STOP) ||
927 icr |= ICR_STOP; 929 (i2c->msg_idx == i2c->msg_num - 1)))
930 icr |= ICR_STOP;
931
928 } else if (i2c->msg_idx < i2c->msg_num - 1) { 932 } else if (i2c->msg_idx < i2c->msg_num - 1) {
929 /* 933 /*
930 * Next segment of the message. 934 * Next segment of the message.
@@ -1071,7 +1075,8 @@ static int i2c_pxa_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num
1071 1075
1072static u32 i2c_pxa_functionality(struct i2c_adapter *adap) 1076static u32 i2c_pxa_functionality(struct i2c_adapter *adap)
1073{ 1077{
1074 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 1078 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
1079 I2C_FUNC_PROTOCOL_MANGLING | I2C_FUNC_NOSTART;
1075} 1080}
1076 1081
1077static const struct i2c_algorithm i2c_pxa_algorithm = { 1082static const struct i2c_algorithm i2c_pxa_algorithm = {
diff --git a/drivers/i2c/busses/i2c-rcar.c b/drivers/i2c/busses/i2c-rcar.c
index d826e82dd997..835057741aa6 100644
--- a/drivers/i2c/busses/i2c-rcar.c
+++ b/drivers/i2c/busses/i2c-rcar.c
@@ -48,6 +48,12 @@
48#define ICMAR 0x20 /* master address */ 48#define ICMAR 0x20 /* master address */
49#define ICRXTX 0x24 /* data port */ 49#define ICRXTX 0x24 /* data port */
50 50
51/* ICSCR */
52#define SDBS (1 << 3) /* slave data buffer select */
53#define SIE (1 << 2) /* slave interface enable */
54#define GCAE (1 << 1) /* general call address enable */
55#define FNA (1 << 0) /* forced non acknowledgment */
56
51/* ICMCR */ 57/* ICMCR */
52#define MDBS (1 << 7) /* non-fifo mode switch */ 58#define MDBS (1 << 7) /* non-fifo mode switch */
53#define FSCL (1 << 6) /* override SCL pin */ 59#define FSCL (1 << 6) /* override SCL pin */
@@ -58,6 +64,15 @@
58#define FSB (1 << 1) /* force stop bit */ 64#define FSB (1 << 1) /* force stop bit */
59#define ESG (1 << 0) /* en startbit gen */ 65#define ESG (1 << 0) /* en startbit gen */
60 66
67/* ICSSR (also for ICSIER) */
68#define GCAR (1 << 6) /* general call received */
69#define STM (1 << 5) /* slave transmit mode */
70#define SSR (1 << 4) /* stop received */
71#define SDE (1 << 3) /* slave data empty */
72#define SDT (1 << 2) /* slave data transmitted */
73#define SDR (1 << 1) /* slave data received */
74#define SAR (1 << 0) /* slave addr received */
75
61/* ICMSR (also for ICMIE) */ 76/* ICMSR (also for ICMIE) */
62#define MNR (1 << 6) /* nack received */ 77#define MNR (1 << 6) /* nack received */
63#define MAL (1 << 5) /* arbitration lost */ 78#define MAL (1 << 5) /* arbitration lost */
@@ -103,6 +118,7 @@ struct rcar_i2c_priv {
103 u32 icccr; 118 u32 icccr;
104 u32 flags; 119 u32 flags;
105 enum rcar_i2c_type devtype; 120 enum rcar_i2c_type devtype;
121 struct i2c_client *slave;
106}; 122};
107 123
108#define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent) 124#define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent)
@@ -126,15 +142,6 @@ static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg)
126 142
127static void rcar_i2c_init(struct rcar_i2c_priv *priv) 143static void rcar_i2c_init(struct rcar_i2c_priv *priv)
128{ 144{
129 /*
130 * reset slave mode.
131 * slave mode is not used on this driver
132 */
133 rcar_i2c_write(priv, ICSIER, 0);
134 rcar_i2c_write(priv, ICSAR, 0);
135 rcar_i2c_write(priv, ICSCR, 0);
136 rcar_i2c_write(priv, ICSSR, 0);
137
138 /* reset master mode */ 145 /* reset master mode */
139 rcar_i2c_write(priv, ICMIER, 0); 146 rcar_i2c_write(priv, ICMIER, 0);
140 rcar_i2c_write(priv, ICMCR, 0); 147 rcar_i2c_write(priv, ICMCR, 0);
@@ -360,6 +367,63 @@ static int rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr)
360 return 0; 367 return 0;
361} 368}
362 369
370static bool rcar_i2c_slave_irq(struct rcar_i2c_priv *priv)
371{
372 u32 ssr_raw, ssr_filtered;
373 u8 value;
374
375 ssr_raw = rcar_i2c_read(priv, ICSSR) & 0xff;
376 ssr_filtered = ssr_raw & rcar_i2c_read(priv, ICSIER);
377
378 if (!ssr_filtered)
379 return false;
380
381 /* address detected */
382 if (ssr_filtered & SAR) {
383 /* read or write request */
384 if (ssr_raw & STM) {
385 i2c_slave_event(priv->slave, I2C_SLAVE_REQ_READ_START, &value);
386 rcar_i2c_write(priv, ICRXTX, value);
387 rcar_i2c_write(priv, ICSIER, SDE | SSR | SAR);
388 } else {
389 i2c_slave_event(priv->slave, I2C_SLAVE_REQ_WRITE_START, &value);
390 rcar_i2c_read(priv, ICRXTX); /* dummy read */
391 rcar_i2c_write(priv, ICSIER, SDR | SSR | SAR);
392 }
393
394 rcar_i2c_write(priv, ICSSR, ~SAR & 0xff);
395 }
396
397 /* master sent stop */
398 if (ssr_filtered & SSR) {
399 i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value);
400 rcar_i2c_write(priv, ICSIER, SAR | SSR);
401 rcar_i2c_write(priv, ICSSR, ~SSR & 0xff);
402 }
403
404 /* master wants to write to us */
405 if (ssr_filtered & SDR) {
406 int ret;
407
408 value = rcar_i2c_read(priv, ICRXTX);
409 ret = i2c_slave_event(priv->slave, I2C_SLAVE_REQ_WRITE_END, &value);
410 /* Send NACK in case of error */
411 rcar_i2c_write(priv, ICSCR, SIE | SDBS | (ret < 0 ? FNA : 0));
412 i2c_slave_event(priv->slave, I2C_SLAVE_REQ_WRITE_START, &value);
413 rcar_i2c_write(priv, ICSSR, ~SDR & 0xff);
414 }
415
416 /* master wants to read from us */
417 if (ssr_filtered & SDE) {
418 i2c_slave_event(priv->slave, I2C_SLAVE_REQ_READ_END, &value);
419 i2c_slave_event(priv->slave, I2C_SLAVE_REQ_READ_START, &value);
420 rcar_i2c_write(priv, ICRXTX, value);
421 rcar_i2c_write(priv, ICSSR, ~SDE & 0xff);
422 }
423
424 return true;
425}
426
363static irqreturn_t rcar_i2c_irq(int irq, void *ptr) 427static irqreturn_t rcar_i2c_irq(int irq, void *ptr)
364{ 428{
365 struct rcar_i2c_priv *priv = ptr; 429 struct rcar_i2c_priv *priv = ptr;
@@ -369,6 +433,9 @@ static irqreturn_t rcar_i2c_irq(int irq, void *ptr)
369 /*-------------- spin lock -----------------*/ 433 /*-------------- spin lock -----------------*/
370 spin_lock(&priv->lock); 434 spin_lock(&priv->lock);
371 435
436 if (rcar_i2c_slave_irq(priv))
437 goto exit;
438
372 msr = rcar_i2c_read(priv, ICMSR); 439 msr = rcar_i2c_read(priv, ICMSR);
373 440
374 /* Only handle interrupts that are currently enabled */ 441 /* Only handle interrupts that are currently enabled */
@@ -499,6 +566,43 @@ out:
499 return ret; 566 return ret;
500} 567}
501 568
569static int rcar_reg_slave(struct i2c_client *slave)
570{
571 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter);
572
573 if (priv->slave)
574 return -EBUSY;
575
576 if (slave->flags & I2C_CLIENT_TEN)
577 return -EAFNOSUPPORT;
578
579 pm_runtime_forbid(rcar_i2c_priv_to_dev(priv));
580
581 priv->slave = slave;
582 rcar_i2c_write(priv, ICSAR, slave->addr);
583 rcar_i2c_write(priv, ICSSR, 0);
584 rcar_i2c_write(priv, ICSIER, SAR | SSR);
585 rcar_i2c_write(priv, ICSCR, SIE | SDBS);
586
587 return 0;
588}
589
590static int rcar_unreg_slave(struct i2c_client *slave)
591{
592 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter);
593
594 WARN_ON(!priv->slave);
595
596 rcar_i2c_write(priv, ICSIER, 0);
597 rcar_i2c_write(priv, ICSCR, 0);
598
599 priv->slave = NULL;
600
601 pm_runtime_allow(rcar_i2c_priv_to_dev(priv));
602
603 return 0;
604}
605
502static u32 rcar_i2c_func(struct i2c_adapter *adap) 606static u32 rcar_i2c_func(struct i2c_adapter *adap)
503{ 607{
504 /* This HW can't do SMBUS_QUICK and NOSTART */ 608 /* This HW can't do SMBUS_QUICK and NOSTART */
@@ -508,6 +612,8 @@ static u32 rcar_i2c_func(struct i2c_adapter *adap)
508static const struct i2c_algorithm rcar_i2c_algo = { 612static const struct i2c_algorithm rcar_i2c_algo = {
509 .master_xfer = rcar_i2c_master_xfer, 613 .master_xfer = rcar_i2c_master_xfer,
510 .functionality = rcar_i2c_func, 614 .functionality = rcar_i2c_func,
615 .reg_slave = rcar_reg_slave,
616 .unreg_slave = rcar_unreg_slave,
511}; 617};
512 618
513static const struct of_device_id rcar_i2c_dt_ids[] = { 619static const struct of_device_id rcar_i2c_dt_ids[] = {
diff --git a/drivers/i2c/busses/i2c-rk3x.c b/drivers/i2c/busses/i2c-rk3x.c
index f486d0eac4d0..0ee5802f36d3 100644
--- a/drivers/i2c/busses/i2c-rk3x.c
+++ b/drivers/i2c/busses/i2c-rk3x.c
@@ -24,6 +24,7 @@
24#include <linux/wait.h> 24#include <linux/wait.h>
25#include <linux/mfd/syscon.h> 25#include <linux/mfd/syscon.h>
26#include <linux/regmap.h> 26#include <linux/regmap.h>
27#include <linux/math64.h>
27 28
28 29
29/* Register Map */ 30/* Register Map */
@@ -97,6 +98,7 @@ struct rk3x_i2c {
97 /* Hardware resources */ 98 /* Hardware resources */
98 void __iomem *regs; 99 void __iomem *regs;
99 struct clk *clk; 100 struct clk *clk;
101 struct notifier_block clk_rate_nb;
100 102
101 /* Settings */ 103 /* Settings */
102 unsigned int scl_frequency; 104 unsigned int scl_frequency;
@@ -428,18 +430,231 @@ out:
428 return IRQ_HANDLED; 430 return IRQ_HANDLED;
429} 431}
430 432
431static void rk3x_i2c_set_scl_rate(struct rk3x_i2c *i2c, unsigned long scl_rate) 433/**
434 * Calculate divider values for desired SCL frequency
435 *
436 * @clk_rate: I2C input clock rate
437 * @scl_rate: Desired SCL rate
438 * @div_low: Divider output for low
439 * @div_high: Divider output for high
440 *
441 * Returns: 0 on success, -EINVAL if the goal SCL rate is too slow. In that case
442 * a best-effort divider value is returned in divs. If the target rate is
443 * too high, we silently use the highest possible rate.
444 */
445static int rk3x_i2c_calc_divs(unsigned long clk_rate, unsigned long scl_rate,
446 unsigned long *div_low, unsigned long *div_high)
432{ 447{
433 unsigned long i2c_rate = clk_get_rate(i2c->clk); 448 unsigned long min_low_ns, min_high_ns;
434 unsigned int div; 449 unsigned long max_data_hold_ns;
450 unsigned long data_hold_buffer_ns;
451 unsigned long max_low_ns, min_total_ns;
452
453 unsigned long clk_rate_khz, scl_rate_khz;
454
455 unsigned long min_low_div, min_high_div;
456 unsigned long max_low_div;
457
458 unsigned long min_div_for_hold, min_total_div;
459 unsigned long extra_div, extra_low_div, ideal_low_div;
460
461 int ret = 0;
462
463 /* Only support standard-mode and fast-mode */
464 if (WARN_ON(scl_rate > 400000))
465 scl_rate = 400000;
466
467 /* prevent scl_rate_khz from becoming 0 */
468 if (WARN_ON(scl_rate < 1000))
469 scl_rate = 1000;
470
471 /*
472 * min_low_ns: The minimum number of ns we need to hold low
473 * to meet i2c spec
474 * min_high_ns: The minimum number of ns we need to hold high
475 * to meet i2c spec
476 * max_low_ns: The maximum number of ns we can hold low
477 * to meet i2c spec
478 *
479 * Note: max_low_ns should be (max data hold time * 2 - buffer)
480 * This is because the i2c host on Rockchip holds the data line
481 * for half the low time.
482 */
483 if (scl_rate <= 100000) {
484 min_low_ns = 4700;
485 min_high_ns = 4000;
486 max_data_hold_ns = 3450;
487 data_hold_buffer_ns = 50;
488 } else {
489 min_low_ns = 1300;
490 min_high_ns = 600;
491 max_data_hold_ns = 900;
492 data_hold_buffer_ns = 50;
493 }
494 max_low_ns = max_data_hold_ns * 2 - data_hold_buffer_ns;
495 min_total_ns = min_low_ns + min_high_ns;
496
497 /* Adjust to avoid overflow */
498 clk_rate_khz = DIV_ROUND_UP(clk_rate, 1000);
499 scl_rate_khz = scl_rate / 1000;
500
501 /*
502 * We need the total div to be >= this number
503 * so we don't clock too fast.
504 */
505 min_total_div = DIV_ROUND_UP(clk_rate_khz, scl_rate_khz * 8);
506
507 /* These are the min dividers needed for min hold times. */
508 min_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns, 8 * 1000000);
509 min_high_div = DIV_ROUND_UP(clk_rate_khz * min_high_ns, 8 * 1000000);
510 min_div_for_hold = (min_low_div + min_high_div);
511
512 /*
513 * This is the maximum divider so we don't go over the max.
514 * We don't round up here (we round down) since this is a max.
515 */
516 max_low_div = clk_rate_khz * max_low_ns / (8 * 1000000);
517
518 if (min_low_div > max_low_div) {
519 WARN_ONCE(true,
520 "Conflicting, min_low_div %lu, max_low_div %lu\n",
521 min_low_div, max_low_div);
522 max_low_div = min_low_div;
523 }
524
525 if (min_div_for_hold > min_total_div) {
526 /*
527 * Time needed to meet hold requirements is important.
528 * Just use that.
529 */
530 *div_low = min_low_div;
531 *div_high = min_high_div;
532 } else {
533 /*
534 * We've got to distribute some time among the low and high
535 * so we don't run too fast.
536 */
537 extra_div = min_total_div - min_div_for_hold;
538
539 /*
540 * We'll try to split things up perfectly evenly,
541 * biasing slightly towards having a higher div
542 * for low (spend more time low).
543 */
544 ideal_low_div = DIV_ROUND_UP(clk_rate_khz * min_low_ns,
545 scl_rate_khz * 8 * min_total_ns);
546
547 /* Don't allow it to go over the max */
548 if (ideal_low_div > max_low_div)
549 ideal_low_div = max_low_div;
550
551 /*
552 * Handle when the ideal low div is going to take up
553 * more than we have.
554 */
555 if (ideal_low_div > min_low_div + extra_div)
556 ideal_low_div = min_low_div + extra_div;
435 557
436 /* set DIV = DIVH = DIVL 558 /* Give low the "ideal" and give high whatever extra is left */
437 * SCL rate = (clk rate) / (8 * (DIVH + 1 + DIVL + 1)) 559 extra_low_div = ideal_low_div - min_low_div;
438 * = (clk rate) / (16 * (DIV + 1)) 560 *div_low = ideal_low_div;
561 *div_high = min_high_div + (extra_div - extra_low_div);
562 }
563
564 /*
565 * Adjust to the fact that the hardware has an implicit "+1".
566 * NOTE: Above calculations always produce div_low > 0 and div_high > 0.
439 */ 567 */
440 div = DIV_ROUND_UP(i2c_rate, scl_rate * 16) - 1; 568 *div_low = *div_low - 1;
569 *div_high = *div_high - 1;
570
571 /* Maximum divider supported by hw is 0xffff */
572 if (*div_low > 0xffff) {
573 *div_low = 0xffff;
574 ret = -EINVAL;
575 }
576
577 if (*div_high > 0xffff) {
578 *div_high = 0xffff;
579 ret = -EINVAL;
580 }
581
582 return ret;
583}
584
585static void rk3x_i2c_adapt_div(struct rk3x_i2c *i2c, unsigned long clk_rate)
586{
587 unsigned long div_low, div_high;
588 u64 t_low_ns, t_high_ns;
589 int ret;
590
591 ret = rk3x_i2c_calc_divs(clk_rate, i2c->scl_frequency, &div_low,
592 &div_high);
593
594 WARN_ONCE(ret != 0, "Could not reach SCL freq %u", i2c->scl_frequency);
595
596 clk_enable(i2c->clk);
597 i2c_writel(i2c, (div_high << 16) | (div_low & 0xffff), REG_CLKDIV);
598 clk_disable(i2c->clk);
441 599
442 i2c_writel(i2c, (div << 16) | (div & 0xffff), REG_CLKDIV); 600 t_low_ns = div_u64(((u64)div_low + 1) * 8 * 1000000000, clk_rate);
601 t_high_ns = div_u64(((u64)div_high + 1) * 8 * 1000000000, clk_rate);
602 dev_dbg(i2c->dev,
603 "CLK %lukhz, Req %uns, Act low %lluns high %lluns\n",
604 clk_rate / 1000,
605 1000000000 / i2c->scl_frequency,
606 t_low_ns, t_high_ns);
607}
608
609/**
610 * rk3x_i2c_clk_notifier_cb - Clock rate change callback
611 * @nb: Pointer to notifier block
612 * @event: Notification reason
613 * @data: Pointer to notification data object
614 *
615 * The callback checks whether a valid bus frequency can be generated after the
616 * change. If so, the change is acknowledged, otherwise the change is aborted.
617 * New dividers are written to the HW in the pre- or post change notification
618 * depending on the scaling direction.
619 *
620 * Code adapted from i2c-cadence.c.
621 *
622 * Return: NOTIFY_STOP if the rate change should be aborted, NOTIFY_OK
623 * to acknowedge the change, NOTIFY_DONE if the notification is
624 * considered irrelevant.
625 */
626static int rk3x_i2c_clk_notifier_cb(struct notifier_block *nb, unsigned long
627 event, void *data)
628{
629 struct clk_notifier_data *ndata = data;
630 struct rk3x_i2c *i2c = container_of(nb, struct rk3x_i2c, clk_rate_nb);
631 unsigned long div_low, div_high;
632
633 switch (event) {
634 case PRE_RATE_CHANGE:
635 if (rk3x_i2c_calc_divs(ndata->new_rate, i2c->scl_frequency,
636 &div_low, &div_high) != 0) {
637 return NOTIFY_STOP;
638 }
639
640 /* scale up */
641 if (ndata->new_rate > ndata->old_rate)
642 rk3x_i2c_adapt_div(i2c, ndata->new_rate);
643
644 return NOTIFY_OK;
645 case POST_RATE_CHANGE:
646 /* scale down */
647 if (ndata->new_rate < ndata->old_rate)
648 rk3x_i2c_adapt_div(i2c, ndata->new_rate);
649 return NOTIFY_OK;
650 case ABORT_RATE_CHANGE:
651 /* scale up */
652 if (ndata->new_rate > ndata->old_rate)
653 rk3x_i2c_adapt_div(i2c, ndata->old_rate);
654 return NOTIFY_OK;
655 default:
656 return NOTIFY_DONE;
657 }
443} 658}
444 659
445/** 660/**
@@ -536,9 +751,6 @@ static int rk3x_i2c_xfer(struct i2c_adapter *adap,
536 751
537 clk_enable(i2c->clk); 752 clk_enable(i2c->clk);
538 753
539 /* The clock rate might have changed, so setup the divider again */
540 rk3x_i2c_set_scl_rate(i2c, i2c->scl_frequency);
541
542 i2c->is_last_msg = false; 754 i2c->is_last_msg = false;
543 755
544 /* 756 /*
@@ -624,6 +836,7 @@ static int rk3x_i2c_probe(struct platform_device *pdev)
624 int bus_nr; 836 int bus_nr;
625 u32 value; 837 u32 value;
626 int irq; 838 int irq;
839 unsigned long clk_rate;
627 840
628 i2c = devm_kzalloc(&pdev->dev, sizeof(struct rk3x_i2c), GFP_KERNEL); 841 i2c = devm_kzalloc(&pdev->dev, sizeof(struct rk3x_i2c), GFP_KERNEL);
629 if (!i2c) 842 if (!i2c)
@@ -724,16 +937,28 @@ static int rk3x_i2c_probe(struct platform_device *pdev)
724 return ret; 937 return ret;
725 } 938 }
726 939
940 i2c->clk_rate_nb.notifier_call = rk3x_i2c_clk_notifier_cb;
941 ret = clk_notifier_register(i2c->clk, &i2c->clk_rate_nb);
942 if (ret != 0) {
943 dev_err(&pdev->dev, "Unable to register clock notifier\n");
944 goto err_clk;
945 }
946
947 clk_rate = clk_get_rate(i2c->clk);
948 rk3x_i2c_adapt_div(i2c, clk_rate);
949
727 ret = i2c_add_adapter(&i2c->adap); 950 ret = i2c_add_adapter(&i2c->adap);
728 if (ret < 0) { 951 if (ret < 0) {
729 dev_err(&pdev->dev, "Could not register adapter\n"); 952 dev_err(&pdev->dev, "Could not register adapter\n");
730 goto err_clk; 953 goto err_clk_notifier;
731 } 954 }
732 955
733 dev_info(&pdev->dev, "Initialized RK3xxx I2C bus at %p\n", i2c->regs); 956 dev_info(&pdev->dev, "Initialized RK3xxx I2C bus at %p\n", i2c->regs);
734 957
735 return 0; 958 return 0;
736 959
960err_clk_notifier:
961 clk_notifier_unregister(i2c->clk, &i2c->clk_rate_nb);
737err_clk: 962err_clk:
738 clk_unprepare(i2c->clk); 963 clk_unprepare(i2c->clk);
739 return ret; 964 return ret;
@@ -744,6 +969,8 @@ static int rk3x_i2c_remove(struct platform_device *pdev)
744 struct rk3x_i2c *i2c = platform_get_drvdata(pdev); 969 struct rk3x_i2c *i2c = platform_get_drvdata(pdev);
745 970
746 i2c_del_adapter(&i2c->adap); 971 i2c_del_adapter(&i2c->adap);
972
973 clk_notifier_unregister(i2c->clk, &i2c->clk_rate_nb);
747 clk_unprepare(i2c->clk); 974 clk_unprepare(i2c->clk);
748 975
749 return 0; 976 return 0;
diff --git a/drivers/i2c/busses/i2c-s3c2410.c b/drivers/i2c/busses/i2c-s3c2410.c
index 65244774bfa3..09a6bace457e 100644
--- a/drivers/i2c/busses/i2c-s3c2410.c
+++ b/drivers/i2c/busses/i2c-s3c2410.c
@@ -35,6 +35,8 @@
35#include <linux/of.h> 35#include <linux/of.h>
36#include <linux/of_gpio.h> 36#include <linux/of_gpio.h>
37#include <linux/pinctrl/consumer.h> 37#include <linux/pinctrl/consumer.h>
38#include <linux/mfd/syscon.h>
39#include <linux/regmap.h>
38 40
39#include <asm/irq.h> 41#include <asm/irq.h>
40 42
@@ -87,6 +89,9 @@
87/* Max time to wait for bus to become idle after a xfer (in us) */ 89/* Max time to wait for bus to become idle after a xfer (in us) */
88#define S3C2410_IDLE_TIMEOUT 5000 90#define S3C2410_IDLE_TIMEOUT 5000
89 91
92/* Exynos5 Sysreg offset */
93#define EXYNOS5_SYS_I2C_CFG 0x0234
94
90/* i2c controller state */ 95/* i2c controller state */
91enum s3c24xx_i2c_state { 96enum s3c24xx_i2c_state {
92 STATE_IDLE, 97 STATE_IDLE,
@@ -123,6 +128,8 @@ struct s3c24xx_i2c {
123#if defined(CONFIG_ARM_S3C24XX_CPUFREQ) 128#if defined(CONFIG_ARM_S3C24XX_CPUFREQ)
124 struct notifier_block freq_transition; 129 struct notifier_block freq_transition;
125#endif 130#endif
131 struct regmap *sysreg;
132 unsigned int sys_i2c_cfg;
126}; 133};
127 134
128static struct platform_device_id s3c24xx_driver_ids[] = { 135static struct platform_device_id s3c24xx_driver_ids[] = {
@@ -1071,6 +1078,7 @@ static void
1071s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c) 1078s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c)
1072{ 1079{
1073 struct s3c2410_platform_i2c *pdata = i2c->pdata; 1080 struct s3c2410_platform_i2c *pdata = i2c->pdata;
1081 int id;
1074 1082
1075 if (!np) 1083 if (!np)
1076 return; 1084 return;
@@ -1080,6 +1088,21 @@ s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c)
1080 of_property_read_u32(np, "samsung,i2c-slave-addr", &pdata->slave_addr); 1088 of_property_read_u32(np, "samsung,i2c-slave-addr", &pdata->slave_addr);
1081 of_property_read_u32(np, "samsung,i2c-max-bus-freq", 1089 of_property_read_u32(np, "samsung,i2c-max-bus-freq",
1082 (u32 *)&pdata->frequency); 1090 (u32 *)&pdata->frequency);
1091 /*
1092 * Exynos5's legacy i2c controller and new high speed i2c
1093 * controller have muxed interrupt sources. By default the
1094 * interrupts for 4-channel HS-I2C controller are enabled.
1095 * If nodes for first four channels of legacy i2c controller
1096 * are available then re-configure the interrupts via the
1097 * system register.
1098 */
1099 id = of_alias_get_id(np, "i2c");
1100 i2c->sysreg = syscon_regmap_lookup_by_phandle(np,
1101 "samsung,sysreg-phandle");
1102 if (IS_ERR(i2c->sysreg))
1103 return;
1104
1105 regmap_update_bits(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, BIT(id), 0);
1083} 1106}
1084#else 1107#else
1085static void 1108static void
@@ -1260,6 +1283,9 @@ static int s3c24xx_i2c_suspend_noirq(struct device *dev)
1260 1283
1261 i2c->suspended = 1; 1284 i2c->suspended = 1;
1262 1285
1286 if (!IS_ERR(i2c->sysreg))
1287 regmap_read(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, &i2c->sys_i2c_cfg);
1288
1263 return 0; 1289 return 0;
1264} 1290}
1265 1291
@@ -1268,6 +1294,9 @@ static int s3c24xx_i2c_resume_noirq(struct device *dev)
1268 struct platform_device *pdev = to_platform_device(dev); 1294 struct platform_device *pdev = to_platform_device(dev);
1269 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev); 1295 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
1270 1296
1297 if (!IS_ERR(i2c->sysreg))
1298 regmap_write(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, i2c->sys_i2c_cfg);
1299
1271 clk_prepare_enable(i2c->clk); 1300 clk_prepare_enable(i2c->clk);
1272 s3c24xx_i2c_init(i2c); 1301 s3c24xx_i2c_init(i2c);
1273 clk_disable_unprepare(i2c->clk); 1302 clk_disable_unprepare(i2c->clk);
diff --git a/drivers/i2c/busses/i2c-sh_mobile.c b/drivers/i2c/busses/i2c-sh_mobile.c
index 4855188747c9..421e00418ef1 100644
--- a/drivers/i2c/busses/i2c-sh_mobile.c
+++ b/drivers/i2c/busses/i2c-sh_mobile.c
@@ -1,6 +1,8 @@
1/* 1/*
2 * SuperH Mobile I2C Controller 2 * SuperH Mobile I2C Controller
3 * 3 *
4 * Copyright (C) 2014 Wolfram Sang <wsa@sang-engineering.com>
5 *
4 * Copyright (C) 2008 Magnus Damm 6 * Copyright (C) 2008 Magnus Damm
5 * 7 *
6 * Portions of the code based on out-of-tree driver i2c-sh7343.c 8 * Portions of the code based on out-of-tree driver i2c-sh7343.c
@@ -16,20 +18,22 @@
16 * GNU General Public License for more details. 18 * GNU General Public License for more details.
17 */ 19 */
18 20
21#include <linux/clk.h>
22#include <linux/delay.h>
23#include <linux/dmaengine.h>
24#include <linux/dma-mapping.h>
25#include <linux/err.h>
26#include <linux/i2c.h>
27#include <linux/i2c/i2c-sh_mobile.h>
28#include <linux/init.h>
29#include <linux/interrupt.h>
30#include <linux/io.h>
19#include <linux/kernel.h> 31#include <linux/kernel.h>
20#include <linux/module.h> 32#include <linux/module.h>
21#include <linux/init.h> 33#include <linux/of_device.h>
22#include <linux/delay.h>
23#include <linux/platform_device.h> 34#include <linux/platform_device.h>
24#include <linux/interrupt.h>
25#include <linux/i2c.h>
26#include <linux/err.h>
27#include <linux/pm_runtime.h> 35#include <linux/pm_runtime.h>
28#include <linux/clk.h>
29#include <linux/io.h>
30#include <linux/slab.h> 36#include <linux/slab.h>
31#include <linux/of_device.h>
32#include <linux/i2c/i2c-sh_mobile.h>
33 37
34/* Transmit operation: */ 38/* Transmit operation: */
35/* */ 39/* */
@@ -110,6 +114,7 @@ enum sh_mobile_i2c_op {
110 OP_TX_FIRST, 114 OP_TX_FIRST,
111 OP_TX, 115 OP_TX,
112 OP_TX_STOP, 116 OP_TX_STOP,
117 OP_TX_STOP_DATA,
113 OP_TX_TO_RX, 118 OP_TX_TO_RX,
114 OP_RX, 119 OP_RX,
115 OP_RX_STOP, 120 OP_RX_STOP,
@@ -134,6 +139,11 @@ struct sh_mobile_i2c_data {
134 int pos; 139 int pos;
135 int sr; 140 int sr;
136 bool send_stop; 141 bool send_stop;
142
143 struct dma_chan *dma_tx;
144 struct dma_chan *dma_rx;
145 struct scatterlist sg;
146 enum dma_data_direction dma_direction;
137}; 147};
138 148
139struct sh_mobile_dt_config { 149struct sh_mobile_dt_config {
@@ -171,6 +181,8 @@ struct sh_mobile_dt_config {
171 181
172#define ICIC_ICCLB8 0x80 182#define ICIC_ICCLB8 0x80
173#define ICIC_ICCHB8 0x40 183#define ICIC_ICCHB8 0x40
184#define ICIC_TDMAE 0x20
185#define ICIC_RDMAE 0x10
174#define ICIC_ALE 0x08 186#define ICIC_ALE 0x08
175#define ICIC_TACKE 0x04 187#define ICIC_TACKE 0x04
176#define ICIC_WAITE 0x02 188#define ICIC_WAITE 0x02
@@ -277,6 +289,7 @@ static int sh_mobile_i2c_init(struct sh_mobile_i2c_data *pd)
277 else 289 else
278 pd->icic &= ~ICIC_ICCHB8; 290 pd->icic &= ~ICIC_ICCHB8;
279 291
292 dev_dbg(pd->dev, "timing values: L/H=0x%x/0x%x\n", pd->iccl, pd->icch);
280 return 0; 293 return 0;
281} 294}
282 295
@@ -332,8 +345,10 @@ static unsigned char i2c_op(struct sh_mobile_i2c_data *pd,
332 case OP_TX: /* write data */ 345 case OP_TX: /* write data */
333 iic_wr(pd, ICDR, data); 346 iic_wr(pd, ICDR, data);
334 break; 347 break;
335 case OP_TX_STOP: /* write data and issue a stop afterwards */ 348 case OP_TX_STOP_DATA: /* write data and issue a stop afterwards */
336 iic_wr(pd, ICDR, data); 349 iic_wr(pd, ICDR, data);
350 /* fallthrough */
351 case OP_TX_STOP: /* issue a stop */
337 iic_wr(pd, ICCR, pd->send_stop ? ICCR_ICE | ICCR_TRS 352 iic_wr(pd, ICCR, pd->send_stop ? ICCR_ICE | ICCR_TRS
338 : ICCR_ICE | ICCR_TRS | ICCR_BBSY); 353 : ICCR_ICE | ICCR_TRS | ICCR_BBSY);
339 break; 354 break;
@@ -389,13 +404,17 @@ static int sh_mobile_i2c_isr_tx(struct sh_mobile_i2c_data *pd)
389{ 404{
390 unsigned char data; 405 unsigned char data;
391 406
392 if (pd->pos == pd->msg->len) 407 if (pd->pos == pd->msg->len) {
408 /* Send stop if we haven't yet (DMA case) */
409 if (pd->send_stop && (iic_rd(pd, ICCR) & ICCR_BBSY))
410 i2c_op(pd, OP_TX_STOP, 0);
393 return 1; 411 return 1;
412 }
394 413
395 sh_mobile_i2c_get_data(pd, &data); 414 sh_mobile_i2c_get_data(pd, &data);
396 415
397 if (sh_mobile_i2c_is_last_byte(pd)) 416 if (sh_mobile_i2c_is_last_byte(pd))
398 i2c_op(pd, OP_TX_STOP, data); 417 i2c_op(pd, OP_TX_STOP_DATA, data);
399 else if (sh_mobile_i2c_is_first_byte(pd)) 418 else if (sh_mobile_i2c_is_first_byte(pd))
400 i2c_op(pd, OP_TX_FIRST, data); 419 i2c_op(pd, OP_TX_FIRST, data);
401 else 420 else
@@ -447,10 +466,9 @@ static int sh_mobile_i2c_isr_rx(struct sh_mobile_i2c_data *pd)
447 466
448static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id) 467static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
449{ 468{
450 struct platform_device *dev = dev_id; 469 struct sh_mobile_i2c_data *pd = dev_id;
451 struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev);
452 unsigned char sr; 470 unsigned char sr;
453 int wakeup; 471 int wakeup = 0;
454 472
455 sr = iic_rd(pd, ICSR); 473 sr = iic_rd(pd, ICSR);
456 pd->sr |= sr; /* remember state */ 474 pd->sr |= sr; /* remember state */
@@ -459,15 +477,21 @@ static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
459 (pd->msg->flags & I2C_M_RD) ? "read" : "write", 477 (pd->msg->flags & I2C_M_RD) ? "read" : "write",
460 pd->pos, pd->msg->len); 478 pd->pos, pd->msg->len);
461 479
462 if (sr & (ICSR_AL | ICSR_TACK)) { 480 /* Kick off TxDMA after preface was done */
481 if (pd->dma_direction == DMA_TO_DEVICE && pd->pos == 0)
482 iic_set_clr(pd, ICIC, ICIC_TDMAE, 0);
483 else if (sr & (ICSR_AL | ICSR_TACK))
463 /* don't interrupt transaction - continue to issue stop */ 484 /* don't interrupt transaction - continue to issue stop */
464 iic_wr(pd, ICSR, sr & ~(ICSR_AL | ICSR_TACK)); 485 iic_wr(pd, ICSR, sr & ~(ICSR_AL | ICSR_TACK));
465 wakeup = 0; 486 else if (pd->msg->flags & I2C_M_RD)
466 } else if (pd->msg->flags & I2C_M_RD)
467 wakeup = sh_mobile_i2c_isr_rx(pd); 487 wakeup = sh_mobile_i2c_isr_rx(pd);
468 else 488 else
469 wakeup = sh_mobile_i2c_isr_tx(pd); 489 wakeup = sh_mobile_i2c_isr_tx(pd);
470 490
491 /* Kick off RxDMA after preface was done */
492 if (pd->dma_direction == DMA_FROM_DEVICE && pd->pos == 1)
493 iic_set_clr(pd, ICIC, ICIC_RDMAE, 0);
494
471 if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */ 495 if (sr & ICSR_WAIT) /* TODO: add delay here to support slow acks */
472 iic_wr(pd, ICSR, sr & ~ICSR_WAIT); 496 iic_wr(pd, ICSR, sr & ~ICSR_WAIT);
473 497
@@ -482,6 +506,84 @@ static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
482 return IRQ_HANDLED; 506 return IRQ_HANDLED;
483} 507}
484 508
509static void sh_mobile_i2c_dma_unmap(struct sh_mobile_i2c_data *pd)
510{
511 struct dma_chan *chan = pd->dma_direction == DMA_FROM_DEVICE
512 ? pd->dma_rx : pd->dma_tx;
513
514 dma_unmap_single(chan->device->dev, sg_dma_address(&pd->sg),
515 pd->msg->len, pd->dma_direction);
516
517 pd->dma_direction = DMA_NONE;
518}
519
520static void sh_mobile_i2c_cleanup_dma(struct sh_mobile_i2c_data *pd)
521{
522 if (pd->dma_direction == DMA_NONE)
523 return;
524 else if (pd->dma_direction == DMA_FROM_DEVICE)
525 dmaengine_terminate_all(pd->dma_rx);
526 else if (pd->dma_direction == DMA_TO_DEVICE)
527 dmaengine_terminate_all(pd->dma_tx);
528
529 sh_mobile_i2c_dma_unmap(pd);
530}
531
532static void sh_mobile_i2c_dma_callback(void *data)
533{
534 struct sh_mobile_i2c_data *pd = data;
535
536 sh_mobile_i2c_dma_unmap(pd);
537 pd->pos = pd->msg->len;
538
539 iic_set_clr(pd, ICIC, 0, ICIC_TDMAE | ICIC_RDMAE);
540}
541
542static void sh_mobile_i2c_xfer_dma(struct sh_mobile_i2c_data *pd)
543{
544 bool read = pd->msg->flags & I2C_M_RD;
545 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
546 struct dma_chan *chan = read ? pd->dma_rx : pd->dma_tx;
547 struct dma_async_tx_descriptor *txdesc;
548 dma_addr_t dma_addr;
549 dma_cookie_t cookie;
550
551 if (!chan)
552 return;
553
554 dma_addr = dma_map_single(chan->device->dev, pd->msg->buf, pd->msg->len, dir);
555 if (dma_mapping_error(pd->dev, dma_addr)) {
556 dev_dbg(pd->dev, "dma map failed, using PIO\n");
557 return;
558 }
559
560 sg_dma_len(&pd->sg) = pd->msg->len;
561 sg_dma_address(&pd->sg) = dma_addr;
562
563 pd->dma_direction = dir;
564
565 txdesc = dmaengine_prep_slave_sg(chan, &pd->sg, 1,
566 read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV,
567 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
568 if (!txdesc) {
569 dev_dbg(pd->dev, "dma prep slave sg failed, using PIO\n");
570 sh_mobile_i2c_cleanup_dma(pd);
571 return;
572 }
573
574 txdesc->callback = sh_mobile_i2c_dma_callback;
575 txdesc->callback_param = pd;
576
577 cookie = dmaengine_submit(txdesc);
578 if (dma_submit_error(cookie)) {
579 dev_dbg(pd->dev, "submitting dma failed, using PIO\n");
580 sh_mobile_i2c_cleanup_dma(pd);
581 return;
582 }
583
584 dma_async_issue_pending(chan);
585}
586
485static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg, 587static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg,
486 bool do_init) 588 bool do_init)
487{ 589{
@@ -506,6 +608,9 @@ static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg,
506 pd->pos = -1; 608 pd->pos = -1;
507 pd->sr = 0; 609 pd->sr = 0;
508 610
611 if (pd->msg->len > 8)
612 sh_mobile_i2c_xfer_dma(pd);
613
509 /* Enable all interrupts to begin with */ 614 /* Enable all interrupts to begin with */
510 iic_wr(pd, ICIC, ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE); 615 iic_wr(pd, ICIC, ICIC_DTEE | ICIC_WAITE | ICIC_ALE | ICIC_TACKE);
511 return 0; 616 return 0;
@@ -589,6 +694,9 @@ static int sh_mobile_i2c_xfer(struct i2c_adapter *adapter,
589 5 * HZ); 694 5 * HZ);
590 if (!k) { 695 if (!k) {
591 dev_err(pd->dev, "Transfer request timed out\n"); 696 dev_err(pd->dev, "Transfer request timed out\n");
697 if (pd->dma_direction != DMA_NONE)
698 sh_mobile_i2c_cleanup_dma(pd);
699
592 err = -ETIMEDOUT; 700 err = -ETIMEDOUT;
593 break; 701 break;
594 } 702 }
@@ -622,22 +730,77 @@ static const struct sh_mobile_dt_config default_dt_config = {
622 .clks_per_count = 1, 730 .clks_per_count = 1,
623}; 731};
624 732
625static const struct sh_mobile_dt_config rcar_gen2_dt_config = { 733static const struct sh_mobile_dt_config fast_clock_dt_config = {
626 .clks_per_count = 2, 734 .clks_per_count = 2,
627}; 735};
628 736
629static const struct of_device_id sh_mobile_i2c_dt_ids[] = { 737static const struct of_device_id sh_mobile_i2c_dt_ids[] = {
630 { .compatible = "renesas,rmobile-iic", .data = &default_dt_config }, 738 { .compatible = "renesas,rmobile-iic", .data = &default_dt_config },
631 { .compatible = "renesas,iic-r8a7790", .data = &rcar_gen2_dt_config }, 739 { .compatible = "renesas,iic-r8a73a4", .data = &fast_clock_dt_config },
632 { .compatible = "renesas,iic-r8a7791", .data = &rcar_gen2_dt_config }, 740 { .compatible = "renesas,iic-r8a7790", .data = &fast_clock_dt_config },
633 { .compatible = "renesas,iic-r8a7792", .data = &rcar_gen2_dt_config }, 741 { .compatible = "renesas,iic-r8a7791", .data = &fast_clock_dt_config },
634 { .compatible = "renesas,iic-r8a7793", .data = &rcar_gen2_dt_config }, 742 { .compatible = "renesas,iic-r8a7792", .data = &fast_clock_dt_config },
635 { .compatible = "renesas,iic-r8a7794", .data = &rcar_gen2_dt_config }, 743 { .compatible = "renesas,iic-r8a7793", .data = &fast_clock_dt_config },
744 { .compatible = "renesas,iic-r8a7794", .data = &fast_clock_dt_config },
745 { .compatible = "renesas,iic-sh73a0", .data = &fast_clock_dt_config },
636 {}, 746 {},
637}; 747};
638MODULE_DEVICE_TABLE(of, sh_mobile_i2c_dt_ids); 748MODULE_DEVICE_TABLE(of, sh_mobile_i2c_dt_ids);
639 749
640static int sh_mobile_i2c_hook_irqs(struct platform_device *dev) 750static int sh_mobile_i2c_request_dma_chan(struct device *dev, enum dma_transfer_direction dir,
751 dma_addr_t port_addr, struct dma_chan **chan_ptr)
752{
753 struct dma_chan *chan;
754 struct dma_slave_config cfg;
755 char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx";
756 int ret;
757
758 *chan_ptr = NULL;
759
760 chan = dma_request_slave_channel_reason(dev, chan_name);
761 if (IS_ERR(chan)) {
762 ret = PTR_ERR(chan);
763 dev_dbg(dev, "request_channel failed for %s (%d)\n", chan_name, ret);
764 return ret;
765 }
766
767 memset(&cfg, 0, sizeof(cfg));
768 cfg.direction = dir;
769 if (dir == DMA_MEM_TO_DEV) {
770 cfg.dst_addr = port_addr;
771 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
772 } else {
773 cfg.src_addr = port_addr;
774 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
775 }
776
777 ret = dmaengine_slave_config(chan, &cfg);
778 if (ret) {
779 dev_dbg(dev, "slave_config failed for %s (%d)\n", chan_name, ret);
780 dma_release_channel(chan);
781 return ret;
782 }
783
784 *chan_ptr = chan;
785
786 dev_dbg(dev, "got DMA channel for %s\n", chan_name);
787 return 0;
788}
789
790static void sh_mobile_i2c_release_dma(struct sh_mobile_i2c_data *pd)
791{
792 if (pd->dma_tx) {
793 dma_release_channel(pd->dma_tx);
794 pd->dma_tx = NULL;
795 }
796
797 if (pd->dma_rx) {
798 dma_release_channel(pd->dma_rx);
799 pd->dma_rx = NULL;
800 }
801}
802
803static int sh_mobile_i2c_hook_irqs(struct platform_device *dev, struct sh_mobile_i2c_data *pd)
641{ 804{
642 struct resource *res; 805 struct resource *res;
643 resource_size_t n; 806 resource_size_t n;
@@ -646,7 +809,7 @@ static int sh_mobile_i2c_hook_irqs(struct platform_device *dev)
646 while ((res = platform_get_resource(dev, IORESOURCE_IRQ, k))) { 809 while ((res = platform_get_resource(dev, IORESOURCE_IRQ, k))) {
647 for (n = res->start; n <= res->end; n++) { 810 for (n = res->start; n <= res->end; n++) {
648 ret = devm_request_irq(&dev->dev, n, sh_mobile_i2c_isr, 811 ret = devm_request_irq(&dev->dev, n, sh_mobile_i2c_isr,
649 0, dev_name(&dev->dev), dev); 812 0, dev_name(&dev->dev), pd);
650 if (ret) { 813 if (ret) {
651 dev_err(&dev->dev, "cannot request IRQ %pa\n", &n); 814 dev_err(&dev->dev, "cannot request IRQ %pa\n", &n);
652 return ret; 815 return ret;
@@ -677,7 +840,7 @@ static int sh_mobile_i2c_probe(struct platform_device *dev)
677 return PTR_ERR(pd->clk); 840 return PTR_ERR(pd->clk);
678 } 841 }
679 842
680 ret = sh_mobile_i2c_hook_irqs(dev); 843 ret = sh_mobile_i2c_hook_irqs(dev, pd);
681 if (ret) 844 if (ret)
682 return ret; 845 return ret;
683 846
@@ -723,6 +886,21 @@ static int sh_mobile_i2c_probe(struct platform_device *dev)
723 if (ret) 886 if (ret)
724 return ret; 887 return ret;
725 888
889 /* Init DMA */
890 sg_init_table(&pd->sg, 1);
891 pd->dma_direction = DMA_NONE;
892 ret = sh_mobile_i2c_request_dma_chan(pd->dev, DMA_DEV_TO_MEM,
893 res->start + ICDR, &pd->dma_rx);
894 if (ret == -EPROBE_DEFER)
895 return ret;
896
897 ret = sh_mobile_i2c_request_dma_chan(pd->dev, DMA_MEM_TO_DEV,
898 res->start + ICDR, &pd->dma_tx);
899 if (ret == -EPROBE_DEFER) {
900 sh_mobile_i2c_release_dma(pd);
901 return ret;
902 }
903
726 /* Enable Runtime PM for this device. 904 /* Enable Runtime PM for this device.
727 * 905 *
728 * Also tell the Runtime PM core to ignore children 906 * Also tell the Runtime PM core to ignore children
@@ -754,13 +932,13 @@ static int sh_mobile_i2c_probe(struct platform_device *dev)
754 932
755 ret = i2c_add_numbered_adapter(adap); 933 ret = i2c_add_numbered_adapter(adap);
756 if (ret < 0) { 934 if (ret < 0) {
935 sh_mobile_i2c_release_dma(pd);
757 dev_err(&dev->dev, "cannot add numbered adapter\n"); 936 dev_err(&dev->dev, "cannot add numbered adapter\n");
758 return ret; 937 return ret;
759 } 938 }
760 939
761 dev_info(&dev->dev, 940 dev_info(&dev->dev, "I2C adapter %d, bus speed %lu Hz, DMA=%c\n",
762 "I2C adapter %d with bus speed %lu Hz (L/H=0x%x/0x%x)\n", 941 adap->nr, pd->bus_speed, (pd->dma_rx || pd->dma_tx) ? 'y' : 'n');
763 adap->nr, pd->bus_speed, pd->iccl, pd->icch);
764 942
765 return 0; 943 return 0;
766} 944}
@@ -770,6 +948,7 @@ static int sh_mobile_i2c_remove(struct platform_device *dev)
770 struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev); 948 struct sh_mobile_i2c_data *pd = platform_get_drvdata(dev);
771 949
772 i2c_del_adapter(&pd->adap); 950 i2c_del_adapter(&pd->adap);
951 sh_mobile_i2c_release_dma(pd);
773 pm_runtime_disable(&dev->dev); 952 pm_runtime_disable(&dev->dev);
774 return 0; 953 return 0;
775} 954}
@@ -806,16 +985,15 @@ static int __init sh_mobile_i2c_adap_init(void)
806{ 985{
807 return platform_driver_register(&sh_mobile_i2c_driver); 986 return platform_driver_register(&sh_mobile_i2c_driver);
808} 987}
988subsys_initcall(sh_mobile_i2c_adap_init);
809 989
810static void __exit sh_mobile_i2c_adap_exit(void) 990static void __exit sh_mobile_i2c_adap_exit(void)
811{ 991{
812 platform_driver_unregister(&sh_mobile_i2c_driver); 992 platform_driver_unregister(&sh_mobile_i2c_driver);
813} 993}
814
815subsys_initcall(sh_mobile_i2c_adap_init);
816module_exit(sh_mobile_i2c_adap_exit); 994module_exit(sh_mobile_i2c_adap_exit);
817 995
818MODULE_DESCRIPTION("SuperH Mobile I2C Bus Controller driver"); 996MODULE_DESCRIPTION("SuperH Mobile I2C Bus Controller driver");
819MODULE_AUTHOR("Magnus Damm"); 997MODULE_AUTHOR("Magnus Damm and Wolfram Sang");
820MODULE_LICENSE("GPL v2"); 998MODULE_LICENSE("GPL v2");
821MODULE_ALIAS("platform:i2c-sh_mobile"); 999MODULE_ALIAS("platform:i2c-sh_mobile");
diff --git a/drivers/i2c/busses/i2c-xiic.c b/drivers/i2c/busses/i2c-xiic.c
index cc65ea0b818f..522916a33aa0 100644
--- a/drivers/i2c/busses/i2c-xiic.c
+++ b/drivers/i2c/busses/i2c-xiic.c
@@ -46,6 +46,11 @@ enum xilinx_i2c_state {
46 STATE_START 46 STATE_START
47}; 47};
48 48
49enum xiic_endian {
50 LITTLE,
51 BIG
52};
53
49/** 54/**
50 * struct xiic_i2c - Internal representation of the XIIC I2C bus 55 * struct xiic_i2c - Internal representation of the XIIC I2C bus
51 * @base: Memory base of the HW registers 56 * @base: Memory base of the HW registers
@@ -70,6 +75,7 @@ struct xiic_i2c {
70 enum xilinx_i2c_state state; 75 enum xilinx_i2c_state state;
71 struct i2c_msg *rx_msg; 76 struct i2c_msg *rx_msg;
72 int rx_pos; 77 int rx_pos;
78 enum xiic_endian endianness;
73}; 79};
74 80
75 81
@@ -170,29 +176,58 @@ struct xiic_i2c {
170static void xiic_start_xfer(struct xiic_i2c *i2c); 176static void xiic_start_xfer(struct xiic_i2c *i2c);
171static void __xiic_start_xfer(struct xiic_i2c *i2c); 177static void __xiic_start_xfer(struct xiic_i2c *i2c);
172 178
179/*
180 * For the register read and write functions, a little-endian and big-endian
181 * version are necessary. Endianness is detected during the probe function.
182 * Only the least significant byte [doublet] of the register are ever
183 * accessed. This requires an offset of 3 [2] from the base address for
184 * big-endian systems.
185 */
186
173static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value) 187static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value)
174{ 188{
175 iowrite8(value, i2c->base + reg); 189 if (i2c->endianness == LITTLE)
190 iowrite8(value, i2c->base + reg);
191 else
192 iowrite8(value, i2c->base + reg + 3);
176} 193}
177 194
178static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg) 195static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg)
179{ 196{
180 return ioread8(i2c->base + reg); 197 u8 ret;
198
199 if (i2c->endianness == LITTLE)
200 ret = ioread8(i2c->base + reg);
201 else
202 ret = ioread8(i2c->base + reg + 3);
203 return ret;
181} 204}
182 205
183static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value) 206static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value)
184{ 207{
185 iowrite16(value, i2c->base + reg); 208 if (i2c->endianness == LITTLE)
209 iowrite16(value, i2c->base + reg);
210 else
211 iowrite16be(value, i2c->base + reg + 2);
186} 212}
187 213
188static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value) 214static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value)
189{ 215{
190 iowrite32(value, i2c->base + reg); 216 if (i2c->endianness == LITTLE)
217 iowrite32(value, i2c->base + reg);
218 else
219 iowrite32be(value, i2c->base + reg);
191} 220}
192 221
193static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg) 222static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg)
194{ 223{
195 return ioread32(i2c->base + reg); 224 u32 ret;
225
226 if (i2c->endianness == LITTLE)
227 ret = ioread32(i2c->base + reg);
228 else
229 ret = ioread32be(i2c->base + reg);
230 return ret;
196} 231}
197 232
198static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask) 233static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask)
@@ -692,6 +727,7 @@ static int xiic_i2c_probe(struct platform_device *pdev)
692 struct resource *res; 727 struct resource *res;
693 int ret, irq; 728 int ret, irq;
694 u8 i; 729 u8 i;
730 u32 sr;
695 731
696 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); 732 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
697 if (!i2c) 733 if (!i2c)
@@ -724,6 +760,18 @@ static int xiic_i2c_probe(struct platform_device *pdev)
724 return ret; 760 return ret;
725 } 761 }
726 762
763 /*
764 * Detect endianness
765 * Try to reset the TX FIFO. Then check the EMPTY flag. If it is not
766 * set, assume that the endianness was wrong and swap.
767 */
768 i2c->endianness = LITTLE;
769 xiic_setreg32(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK);
770 /* Reset is cleared in xiic_reinit */
771 sr = xiic_getreg32(i2c, XIIC_SR_REG_OFFSET);
772 if (!(sr & XIIC_SR_TX_FIFO_EMPTY_MASK))
773 i2c->endianness = BIG;
774
727 xiic_reinit(i2c); 775 xiic_reinit(i2c);
728 776
729 /* add i2c adapter to i2c tree */ 777 /* add i2c adapter to i2c tree */
diff --git a/drivers/i2c/i2c-core.c b/drivers/i2c/i2c-core.c
index 229a89e84b0f..39d25a8cb1ad 100644
--- a/drivers/i2c/i2c-core.c
+++ b/drivers/i2c/i2c-core.c
@@ -24,6 +24,7 @@
24 (c) 2013 Wolfram Sang <wsa@the-dreams.de> 24 (c) 2013 Wolfram Sang <wsa@the-dreams.de>
25 I2C ACPI code Copyright (C) 2014 Intel Corp 25 I2C ACPI code Copyright (C) 2014 Intel Corp
26 Author: Lan Tianyu <tianyu.lan@intel.com> 26 Author: Lan Tianyu <tianyu.lan@intel.com>
27 I2C slave support (c) 2014 by Wolfram Sang <wsa@sang-engineering.com>
27 */ 28 */
28 29
29#include <linux/module.h> 30#include <linux/module.h>
@@ -261,7 +262,7 @@ acpi_i2c_space_handler(u32 function, acpi_physical_address command,
261 struct acpi_resource *ares; 262 struct acpi_resource *ares;
262 u32 accessor_type = function >> 16; 263 u32 accessor_type = function >> 16;
263 u8 action = function & ACPI_IO_MASK; 264 u8 action = function & ACPI_IO_MASK;
264 acpi_status ret = AE_OK; 265 acpi_status ret;
265 int status; 266 int status;
266 267
267 ret = acpi_buffer_to_resource(info->connection, info->length, &ares); 268 ret = acpi_buffer_to_resource(info->connection, info->length, &ares);
@@ -628,6 +629,17 @@ static int i2c_device_probe(struct device *dev)
628 if (!client) 629 if (!client)
629 return 0; 630 return 0;
630 631
632 if (!client->irq && dev->of_node) {
633 int irq = of_irq_get(dev->of_node, 0);
634
635 if (irq == -EPROBE_DEFER)
636 return irq;
637 if (irq < 0)
638 irq = 0;
639
640 client->irq = irq;
641 }
642
631 driver = to_i2c_driver(dev->driver); 643 driver = to_i2c_driver(dev->driver);
632 if (!driver->probe || !driver->id_table) 644 if (!driver->probe || !driver->id_table)
633 return -ENODEV; 645 return -ENODEV;
@@ -1401,7 +1413,6 @@ static struct i2c_client *of_i2c_register_device(struct i2c_adapter *adap,
1401 return ERR_PTR(-EINVAL); 1413 return ERR_PTR(-EINVAL);
1402 } 1414 }
1403 1415
1404 info.irq = irq_of_parse_and_map(node, 0);
1405 info.of_node = of_node_get(node); 1416 info.of_node = of_node_get(node);
1406 info.archdata = &dev_ad; 1417 info.archdata = &dev_ad;
1407 1418
@@ -1415,7 +1426,6 @@ static struct i2c_client *of_i2c_register_device(struct i2c_adapter *adap,
1415 dev_err(&adap->dev, "of_i2c: Failure registering %s\n", 1426 dev_err(&adap->dev, "of_i2c: Failure registering %s\n",
1416 node->full_name); 1427 node->full_name);
1417 of_node_put(node); 1428 of_node_put(node);
1418 irq_dispose_mapping(info.irq);
1419 return ERR_PTR(-EINVAL); 1429 return ERR_PTR(-EINVAL);
1420 } 1430 }
1421 return result; 1431 return result;
@@ -2962,6 +2972,54 @@ trace:
2962} 2972}
2963EXPORT_SYMBOL(i2c_smbus_xfer); 2973EXPORT_SYMBOL(i2c_smbus_xfer);
2964 2974
2975int i2c_slave_register(struct i2c_client *client, i2c_slave_cb_t slave_cb)
2976{
2977 int ret;
2978
2979 if (!client || !slave_cb)
2980 return -EINVAL;
2981
2982 if (!(client->flags & I2C_CLIENT_TEN)) {
2983 /* Enforce stricter address checking */
2984 ret = i2c_check_addr_validity(client->addr);
2985 if (ret)
2986 return ret;
2987 }
2988
2989 if (!client->adapter->algo->reg_slave)
2990 return -EOPNOTSUPP;
2991
2992 client->slave_cb = slave_cb;
2993
2994 i2c_lock_adapter(client->adapter);
2995 ret = client->adapter->algo->reg_slave(client);
2996 i2c_unlock_adapter(client->adapter);
2997
2998 if (ret)
2999 client->slave_cb = NULL;
3000
3001 return ret;
3002}
3003EXPORT_SYMBOL_GPL(i2c_slave_register);
3004
3005int i2c_slave_unregister(struct i2c_client *client)
3006{
3007 int ret;
3008
3009 if (!client->adapter->algo->unreg_slave)
3010 return -EOPNOTSUPP;
3011
3012 i2c_lock_adapter(client->adapter);
3013 ret = client->adapter->algo->unreg_slave(client);
3014 i2c_unlock_adapter(client->adapter);
3015
3016 if (ret == 0)
3017 client->slave_cb = NULL;
3018
3019 return ret;
3020}
3021EXPORT_SYMBOL_GPL(i2c_slave_unregister);
3022
2965MODULE_AUTHOR("Simon G. Vogl <simon@tk.uni-linz.ac.at>"); 3023MODULE_AUTHOR("Simon G. Vogl <simon@tk.uni-linz.ac.at>");
2966MODULE_DESCRIPTION("I2C-Bus main module"); 3024MODULE_DESCRIPTION("I2C-Bus main module");
2967MODULE_LICENSE("GPL"); 3025MODULE_LICENSE("GPL");
diff --git a/drivers/i2c/i2c-mux.c b/drivers/i2c/i2c-mux.c
index 2d0847b6be62..593f7ca9adc7 100644
--- a/drivers/i2c/i2c-mux.c
+++ b/drivers/i2c/i2c-mux.c
@@ -110,6 +110,7 @@ struct i2c_adapter *i2c_add_mux_adapter(struct i2c_adapter *parent,
110 void *, u32)) 110 void *, u32))
111{ 111{
112 struct i2c_mux_priv *priv; 112 struct i2c_mux_priv *priv;
113 char symlink_name[20];
113 int ret; 114 int ret;
114 115
115 priv = kzalloc(sizeof(struct i2c_mux_priv), GFP_KERNEL); 116 priv = kzalloc(sizeof(struct i2c_mux_priv), GFP_KERNEL);
@@ -183,6 +184,12 @@ struct i2c_adapter *i2c_add_mux_adapter(struct i2c_adapter *parent,
183 return NULL; 184 return NULL;
184 } 185 }
185 186
187 WARN(sysfs_create_link(&priv->adap.dev.kobj, &mux_dev->kobj, "mux_device"),
188 "can't create symlink to mux device\n");
189
190 snprintf(symlink_name, sizeof(symlink_name), "channel-%u", chan_id);
191 WARN(sysfs_create_link(&mux_dev->kobj, &priv->adap.dev.kobj, symlink_name),
192 "can't create symlink for channel %u\n", chan_id);
186 dev_info(&parent->dev, "Added multiplexed i2c bus %d\n", 193 dev_info(&parent->dev, "Added multiplexed i2c bus %d\n",
187 i2c_adapter_id(&priv->adap)); 194 i2c_adapter_id(&priv->adap));
188 195
@@ -193,7 +200,12 @@ EXPORT_SYMBOL_GPL(i2c_add_mux_adapter);
193void i2c_del_mux_adapter(struct i2c_adapter *adap) 200void i2c_del_mux_adapter(struct i2c_adapter *adap)
194{ 201{
195 struct i2c_mux_priv *priv = adap->algo_data; 202 struct i2c_mux_priv *priv = adap->algo_data;
203 char symlink_name[20];
204
205 snprintf(symlink_name, sizeof(symlink_name), "channel-%u", priv->chan_id);
206 sysfs_remove_link(&adap->dev.parent->kobj, symlink_name);
196 207
208 sysfs_remove_link(&priv->adap.dev.kobj, "mux_device");
197 i2c_del_adapter(adap); 209 i2c_del_adapter(adap);
198 kfree(priv); 210 kfree(priv);
199} 211}
diff --git a/drivers/i2c/i2c-slave-eeprom.c b/drivers/i2c/i2c-slave-eeprom.c
new file mode 100644
index 000000000000..6631400b5f02
--- /dev/null
+++ b/drivers/i2c/i2c-slave-eeprom.c
@@ -0,0 +1,170 @@
1/*
2 * I2C slave mode EEPROM simulator
3 *
4 * Copyright (C) 2014 by Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
5 * Copyright (C) 2014 by Renesas Electronics Corporation
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; version 2 of the License.
10 *
11 * Because most IP blocks can only detect one I2C slave address anyhow, this
12 * driver does not support simulating EEPROM types which take more than one
13 * address. It is prepared to simulate bigger EEPROMs with an internal 16 bit
14 * pointer, yet implementation is deferred until the need actually arises.
15 */
16
17#include <linux/i2c.h>
18#include <linux/init.h>
19#include <linux/module.h>
20#include <linux/of.h>
21#include <linux/slab.h>
22#include <linux/spinlock.h>
23#include <linux/sysfs.h>
24
25struct eeprom_data {
26 struct bin_attribute bin;
27 bool first_write;
28 spinlock_t buffer_lock;
29 u8 buffer_idx;
30 u8 buffer[];
31};
32
33static int i2c_slave_eeprom_slave_cb(struct i2c_client *client,
34 enum i2c_slave_event event, u8 *val)
35{
36 struct eeprom_data *eeprom = i2c_get_clientdata(client);
37
38 switch (event) {
39 case I2C_SLAVE_REQ_WRITE_END:
40 if (eeprom->first_write) {
41 eeprom->buffer_idx = *val;
42 eeprom->first_write = false;
43 } else {
44 spin_lock(&eeprom->buffer_lock);
45 eeprom->buffer[eeprom->buffer_idx++] = *val;
46 spin_unlock(&eeprom->buffer_lock);
47 }
48 break;
49
50 case I2C_SLAVE_REQ_READ_START:
51 spin_lock(&eeprom->buffer_lock);
52 *val = eeprom->buffer[eeprom->buffer_idx];
53 spin_unlock(&eeprom->buffer_lock);
54 break;
55
56 case I2C_SLAVE_REQ_READ_END:
57 eeprom->buffer_idx++;
58 break;
59
60 case I2C_SLAVE_STOP:
61 eeprom->first_write = true;
62 break;
63
64 default:
65 break;
66 }
67
68 return 0;
69}
70
71static ssize_t i2c_slave_eeprom_bin_read(struct file *filp, struct kobject *kobj,
72 struct bin_attribute *attr, char *buf, loff_t off, size_t count)
73{
74 struct eeprom_data *eeprom;
75 unsigned long flags;
76
77 if (off + count >= attr->size)
78 return -EFBIG;
79
80 eeprom = dev_get_drvdata(container_of(kobj, struct device, kobj));
81
82 spin_lock_irqsave(&eeprom->buffer_lock, flags);
83 memcpy(buf, &eeprom->buffer[off], count);
84 spin_unlock_irqrestore(&eeprom->buffer_lock, flags);
85
86 return count;
87}
88
89static ssize_t i2c_slave_eeprom_bin_write(struct file *filp, struct kobject *kobj,
90 struct bin_attribute *attr, char *buf, loff_t off, size_t count)
91{
92 struct eeprom_data *eeprom;
93 unsigned long flags;
94
95 if (off + count >= attr->size)
96 return -EFBIG;
97
98 eeprom = dev_get_drvdata(container_of(kobj, struct device, kobj));
99
100 spin_lock_irqsave(&eeprom->buffer_lock, flags);
101 memcpy(&eeprom->buffer[off], buf, count);
102 spin_unlock_irqrestore(&eeprom->buffer_lock, flags);
103
104 return count;
105}
106
107static int i2c_slave_eeprom_probe(struct i2c_client *client, const struct i2c_device_id *id)
108{
109 struct eeprom_data *eeprom;
110 int ret;
111 unsigned size = id->driver_data;
112
113 eeprom = devm_kzalloc(&client->dev, sizeof(struct eeprom_data) + size, GFP_KERNEL);
114 if (!eeprom)
115 return -ENOMEM;
116
117 eeprom->first_write = true;
118 spin_lock_init(&eeprom->buffer_lock);
119 i2c_set_clientdata(client, eeprom);
120
121 sysfs_bin_attr_init(&eeprom->bin);
122 eeprom->bin.attr.name = "slave-eeprom";
123 eeprom->bin.attr.mode = S_IRUSR | S_IWUSR;
124 eeprom->bin.read = i2c_slave_eeprom_bin_read;
125 eeprom->bin.write = i2c_slave_eeprom_bin_write;
126 eeprom->bin.size = size;
127
128 ret = sysfs_create_bin_file(&client->dev.kobj, &eeprom->bin);
129 if (ret)
130 return ret;
131
132 ret = i2c_slave_register(client, i2c_slave_eeprom_slave_cb);
133 if (ret) {
134 sysfs_remove_bin_file(&client->dev.kobj, &eeprom->bin);
135 return ret;
136 }
137
138 return 0;
139};
140
141static int i2c_slave_eeprom_remove(struct i2c_client *client)
142{
143 struct eeprom_data *eeprom = i2c_get_clientdata(client);
144
145 i2c_slave_unregister(client);
146 sysfs_remove_bin_file(&client->dev.kobj, &eeprom->bin);
147
148 return 0;
149}
150
151static const struct i2c_device_id i2c_slave_eeprom_id[] = {
152 { "slave-24c02", 2048 / 8 },
153 { }
154};
155MODULE_DEVICE_TABLE(i2c, i2c_slave_eeprom_id);
156
157static struct i2c_driver i2c_slave_eeprom_driver = {
158 .driver = {
159 .name = "i2c-slave-eeprom",
160 .owner = THIS_MODULE,
161 },
162 .probe = i2c_slave_eeprom_probe,
163 .remove = i2c_slave_eeprom_remove,
164 .id_table = i2c_slave_eeprom_id,
165};
166module_i2c_driver(i2c_slave_eeprom_driver);
167
168MODULE_AUTHOR("Wolfram Sang <wsa@sang-engineering.com>");
169MODULE_DESCRIPTION("I2C slave mode EEPROM simulator");
170MODULE_LICENSE("GPL v2");
diff --git a/drivers/misc/eeprom/at24.c b/drivers/misc/eeprom/at24.c
index d87f77f790d6..2d3db81be099 100644
--- a/drivers/misc/eeprom/at24.c
+++ b/drivers/misc/eeprom/at24.c
@@ -56,6 +56,7 @@ struct at24_data {
56 struct at24_platform_data chip; 56 struct at24_platform_data chip;
57 struct memory_accessor macc; 57 struct memory_accessor macc;
58 int use_smbus; 58 int use_smbus;
59 int use_smbus_write;
59 60
60 /* 61 /*
61 * Lock protects against activities from other Linux tasks, 62 * Lock protects against activities from other Linux tasks,
@@ -324,7 +325,7 @@ static ssize_t at24_eeprom_write(struct at24_data *at24, const char *buf,
324{ 325{
325 struct i2c_client *client; 326 struct i2c_client *client;
326 struct i2c_msg msg; 327 struct i2c_msg msg;
327 ssize_t status; 328 ssize_t status = 0;
328 unsigned long timeout, write_time; 329 unsigned long timeout, write_time;
329 unsigned next_page; 330 unsigned next_page;
330 331
@@ -365,9 +366,18 @@ static ssize_t at24_eeprom_write(struct at24_data *at24, const char *buf,
365 timeout = jiffies + msecs_to_jiffies(write_timeout); 366 timeout = jiffies + msecs_to_jiffies(write_timeout);
366 do { 367 do {
367 write_time = jiffies; 368 write_time = jiffies;
368 if (at24->use_smbus) { 369 if (at24->use_smbus_write) {
369 status = i2c_smbus_write_i2c_block_data(client, 370 switch (at24->use_smbus_write) {
370 offset, count, buf); 371 case I2C_SMBUS_I2C_BLOCK_DATA:
372 status = i2c_smbus_write_i2c_block_data(client,
373 offset, count, buf);
374 break;
375 case I2C_SMBUS_BYTE_DATA:
376 status = i2c_smbus_write_byte_data(client,
377 offset, buf[0]);
378 break;
379 }
380
371 if (status == 0) 381 if (status == 0)
372 status = count; 382 status = count;
373 } else { 383 } else {
@@ -487,6 +497,7 @@ static int at24_probe(struct i2c_client *client, const struct i2c_device_id *id)
487 struct at24_platform_data chip; 497 struct at24_platform_data chip;
488 bool writable; 498 bool writable;
489 int use_smbus = 0; 499 int use_smbus = 0;
500 int use_smbus_write = 0;
490 struct at24_data *at24; 501 struct at24_data *at24;
491 int err; 502 int err;
492 unsigned i, num_addresses; 503 unsigned i, num_addresses;
@@ -546,6 +557,18 @@ static int at24_probe(struct i2c_client *client, const struct i2c_device_id *id)
546 } 557 }
547 } 558 }
548 559
560 /* Use I2C operations unless we're stuck with SMBus extensions. */
561 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
562 if (i2c_check_functionality(client->adapter,
563 I2C_FUNC_SMBUS_WRITE_I2C_BLOCK)) {
564 use_smbus_write = I2C_SMBUS_I2C_BLOCK_DATA;
565 } else if (i2c_check_functionality(client->adapter,
566 I2C_FUNC_SMBUS_WRITE_BYTE_DATA)) {
567 use_smbus_write = I2C_SMBUS_BYTE_DATA;
568 chip.page_size = 1;
569 }
570 }
571
549 if (chip.flags & AT24_FLAG_TAKE8ADDR) 572 if (chip.flags & AT24_FLAG_TAKE8ADDR)
550 num_addresses = 8; 573 num_addresses = 8;
551 else 574 else
@@ -559,6 +582,7 @@ static int at24_probe(struct i2c_client *client, const struct i2c_device_id *id)
559 582
560 mutex_init(&at24->lock); 583 mutex_init(&at24->lock);
561 at24->use_smbus = use_smbus; 584 at24->use_smbus = use_smbus;
585 at24->use_smbus_write = use_smbus_write;
562 at24->chip = chip; 586 at24->chip = chip;
563 at24->num_addresses = num_addresses; 587 at24->num_addresses = num_addresses;
564 588
@@ -576,8 +600,7 @@ static int at24_probe(struct i2c_client *client, const struct i2c_device_id *id)
576 600
577 writable = !(chip.flags & AT24_FLAG_READONLY); 601 writable = !(chip.flags & AT24_FLAG_READONLY);
578 if (writable) { 602 if (writable) {
579 if (!use_smbus || i2c_check_functionality(client->adapter, 603 if (!use_smbus || use_smbus_write) {
580 I2C_FUNC_SMBUS_WRITE_I2C_BLOCK)) {
581 604
582 unsigned write_max = chip.page_size; 605 unsigned write_max = chip.page_size;
583 606
diff --git a/drivers/of/irq.c b/drivers/of/irq.c
index 1471e0a223a5..0d7765807f49 100644
--- a/drivers/of/irq.c
+++ b/drivers/of/irq.c
@@ -405,6 +405,7 @@ int of_irq_get(struct device_node *dev, int index)
405 405
406 return irq_create_of_mapping(&oirq); 406 return irq_create_of_mapping(&oirq);
407} 407}
408EXPORT_SYMBOL_GPL(of_irq_get);
408 409
409/** 410/**
410 * of_irq_get_byname - Decode a node's IRQ and return it as a Linux irq number 411 * of_irq_get_byname - Decode a node's IRQ and return it as a Linux irq number
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-24 08:21:38 -0400