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-rw-r--r--drivers/gpu/drm/msm/adreno/a2xx.xml.h58
-rw-r--r--drivers/gpu/drm/msm/adreno/a3xx.xml.h296
-rw-r--r--drivers/gpu/drm/msm/adreno/a3xx_gpu.h5
-rw-r--r--drivers/gpu/drm/msm/adreno/adreno_common.xml.h56
-rw-r--r--drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h239
-rw-r--r--drivers/gpu/drm/msm/dsi/dsi.xml.h4
-rw-r--r--drivers/gpu/drm/msm/dsi/mmss_cc.xml.h4
-rw-r--r--drivers/gpu/drm/msm/dsi/sfpb.xml.h4
-rw-r--r--drivers/gpu/drm/msm/hdmi/hdmi.xml.h109
-rw-r--r--drivers/gpu/drm/msm/hdmi/qfprom.xml.h4
-rw-r--r--drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h4
-rw-r--r--drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h6
-rw-r--r--drivers/gpu/drm/msm/mdp/mdp_common.xml.h4
13 files changed, 692 insertions, 101 deletions
diff --git a/drivers/gpu/drm/msm/adreno/a2xx.xml.h b/drivers/gpu/drm/msm/adreno/a2xx.xml.h
index 85d615e7d62f..a8a144b38eaa 100644
--- a/drivers/gpu/drm/msm/adreno/a2xx.xml.h
+++ b/drivers/gpu/drm/msm/adreno/a2xx.xml.h
@@ -10,13 +10,13 @@ git clone https://github.com/freedreno/envytools.git
10The rules-ng-ng source files this header was generated from are: 10The rules-ng-ng source files this header was generated from are:
11- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2013-11-30 14:47:15) 11- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2013-11-30 14:47:15)
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
13- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32814 bytes, from 2013-11-30 15:07:33) 13- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2014-06-02 15:21:30)
14- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 8900 bytes, from 2013-10-22 23:57:49) 14- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 9859 bytes, from 2014-06-02 15:21:30)
15- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 10574 bytes, from 2013-11-13 05:44:45) 15- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14477 bytes, from 2014-05-16 11:51:57)
16- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 53644 bytes, from 2013-11-30 15:07:33) 16- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 58020 bytes, from 2014-06-25 12:57:16)
17- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 8344 bytes, from 2013-11-30 14:49:47) 17- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 26602 bytes, from 2014-06-25 12:57:16)
18 18
19Copyright (C) 2013 by the following authors: 19Copyright (C) 2013-2014 by the following authors:
20- Rob Clark <robdclark@gmail.com> (robclark) 20- Rob Clark <robdclark@gmail.com> (robclark)
21 21
22Permission is hereby granted, free of charge, to any person obtaining 22Permission is hereby granted, free of charge, to any person obtaining
@@ -203,6 +203,15 @@ enum a2xx_rb_copy_sample_select {
203 SAMPLE_0123 = 6, 203 SAMPLE_0123 = 6,
204}; 204};
205 205
206enum a2xx_rb_blend_opcode {
207 BLEND_DST_PLUS_SRC = 0,
208 BLEND_SRC_MINUS_DST = 1,
209 BLEND_MIN_DST_SRC = 2,
210 BLEND_MAX_DST_SRC = 3,
211 BLEND_DST_MINUS_SRC = 4,
212 BLEND_DST_PLUS_SRC_BIAS = 5,
213};
214
206enum adreno_mmu_clnt_beh { 215enum adreno_mmu_clnt_beh {
207 BEH_NEVR = 0, 216 BEH_NEVR = 0,
208 BEH_TRAN_RNG = 1, 217 BEH_TRAN_RNG = 1,
@@ -890,6 +899,39 @@ static inline uint32_t A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS(uint32_t val)
890#define REG_A2XX_VGT_EVENT_INITIATOR 0x000021f9 899#define REG_A2XX_VGT_EVENT_INITIATOR 0x000021f9
891 900
892#define REG_A2XX_VGT_DRAW_INITIATOR 0x000021fc 901#define REG_A2XX_VGT_DRAW_INITIATOR 0x000021fc
902#define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f
903#define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT 0
904static inline uint32_t A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val)
905{
906 return ((val) << A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK;
907}
908#define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK 0x000000c0
909#define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT 6
910static inline uint32_t A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val)
911{
912 return ((val) << A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK;
913}
914#define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK 0x00000600
915#define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT 9
916static inline uint32_t A2XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val)
917{
918 return ((val) << A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT) & A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK;
919}
920#define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK 0x00000800
921#define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT 11
922static inline uint32_t A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val)
923{
924 return ((val) << A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK;
925}
926#define A2XX_VGT_DRAW_INITIATOR_NOT_EOP 0x00001000
927#define A2XX_VGT_DRAW_INITIATOR_SMALL_INDEX 0x00002000
928#define A2XX_VGT_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE 0x00004000
929#define A2XX_VGT_DRAW_INITIATOR_NUM_INDICES__MASK 0xffff0000
930#define A2XX_VGT_DRAW_INITIATOR_NUM_INDICES__SHIFT 16
931static inline uint32_t A2XX_VGT_DRAW_INITIATOR_NUM_INDICES(uint32_t val)
932{
933 return ((val) << A2XX_VGT_DRAW_INITIATOR_NUM_INDICES__SHIFT) & A2XX_VGT_DRAW_INITIATOR_NUM_INDICES__MASK;
934}
893 935
894#define REG_A2XX_VGT_IMMED_DATA 0x000021fd 936#define REG_A2XX_VGT_IMMED_DATA 0x000021fd
895 937
@@ -963,7 +1005,7 @@ static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(enum adreno_rb_blend
963} 1005}
964#define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK 0x000000e0 1006#define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK 0x000000e0
965#define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT 5 1007#define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT 5
966static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(enum adreno_rb_blend_opcode val) 1008static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(enum a2xx_rb_blend_opcode val)
967{ 1009{
968 return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK; 1010 return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK;
969} 1011}
@@ -981,7 +1023,7 @@ static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(enum adreno_rb_blend
981} 1023}
982#define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK 0x00e00000 1024#define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK 0x00e00000
983#define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT 21 1025#define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT 21
984static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(enum adreno_rb_blend_opcode val) 1026static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(enum a2xx_rb_blend_opcode val)
985{ 1027{
986 return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK; 1028 return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK;
987} 1029}
diff --git a/drivers/gpu/drm/msm/adreno/a3xx.xml.h b/drivers/gpu/drm/msm/adreno/a3xx.xml.h
index a7be56163d23..303e8a9e91a5 100644
--- a/drivers/gpu/drm/msm/adreno/a3xx.xml.h
+++ b/drivers/gpu/drm/msm/adreno/a3xx.xml.h
@@ -10,13 +10,13 @@ git clone https://github.com/freedreno/envytools.git
10The rules-ng-ng source files this header was generated from are: 10The rules-ng-ng source files this header was generated from are:
11- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2013-11-30 14:47:15) 11- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2013-11-30 14:47:15)
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
13- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32814 bytes, from 2013-11-30 15:07:33) 13- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2014-06-02 15:21:30)
14- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 8900 bytes, from 2013-10-22 23:57:49) 14- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 9859 bytes, from 2014-06-02 15:21:30)
15- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 10574 bytes, from 2013-11-13 05:44:45) 15- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14477 bytes, from 2014-05-16 11:51:57)
16- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 53644 bytes, from 2013-11-30 15:07:33) 16- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 58020 bytes, from 2014-06-25 12:57:16)
17- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 8344 bytes, from 2013-11-30 14:49:47) 17- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 26602 bytes, from 2014-06-25 12:57:16)
18 18
19Copyright (C) 2013 by the following authors: 19Copyright (C) 2013-2014 by the following authors:
20- Rob Clark <robdclark@gmail.com> (robclark) 20- Rob Clark <robdclark@gmail.com> (robclark)
21 21
22Permission is hereby granted, free of charge, to any person obtaining 22Permission is hereby granted, free of charge, to any person obtaining
@@ -41,31 +41,11 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
41*/ 41*/
42 42
43 43
44enum a3xx_render_mode {
45 RB_RENDERING_PASS = 0,
46 RB_TILING_PASS = 1,
47 RB_RESOLVE_PASS = 2,
48};
49
50enum a3xx_tile_mode { 44enum a3xx_tile_mode {
51 LINEAR = 0, 45 LINEAR = 0,
52 TILE_32X32 = 2, 46 TILE_32X32 = 2,
53}; 47};
54 48
55enum a3xx_threadmode {
56 MULTI = 0,
57 SINGLE = 1,
58};
59
60enum a3xx_instrbuffermode {
61 BUFFER = 1,
62};
63
64enum a3xx_threadsize {
65 TWO_QUADS = 0,
66 FOUR_QUADS = 1,
67};
68
69enum a3xx_state_block_id { 49enum a3xx_state_block_id {
70 HLSQ_BLOCK_ID_TP_TEX = 2, 50 HLSQ_BLOCK_ID_TP_TEX = 2,
71 HLSQ_BLOCK_ID_TP_MIPMAP = 3, 51 HLSQ_BLOCK_ID_TP_MIPMAP = 3,
@@ -169,6 +149,8 @@ enum a3xx_color_fmt {
169 RB_R8G8B8A8_UNORM = 8, 149 RB_R8G8B8A8_UNORM = 8,
170 RB_Z16_UNORM = 12, 150 RB_Z16_UNORM = 12,
171 RB_A8_UNORM = 20, 151 RB_A8_UNORM = 20,
152 RB_R16G16B16A16_FLOAT = 27,
153 RB_R32G32B32A32_FLOAT = 51,
172}; 154};
173 155
174enum a3xx_color_swap { 156enum a3xx_color_swap {
@@ -178,12 +160,6 @@ enum a3xx_color_swap {
178 XYZW = 3, 160 XYZW = 3,
179}; 161};
180 162
181enum a3xx_msaa_samples {
182 MSAA_ONE = 0,
183 MSAA_TWO = 1,
184 MSAA_FOUR = 2,
185};
186
187enum a3xx_sp_perfcounter_select { 163enum a3xx_sp_perfcounter_select {
188 SP_FS_CFLOW_INSTRUCTIONS = 12, 164 SP_FS_CFLOW_INSTRUCTIONS = 12,
189 SP_FS_FULL_ALU_INSTRUCTIONS = 14, 165 SP_FS_FULL_ALU_INSTRUCTIONS = 14,
@@ -191,21 +167,45 @@ enum a3xx_sp_perfcounter_select {
191 SP_ALU_ACTIVE_CYCLES = 29, 167 SP_ALU_ACTIVE_CYCLES = 29,
192}; 168};
193 169
194enum adreno_rb_copy_control_mode { 170enum a3xx_rop_code {
195 RB_COPY_RESOLVE = 1, 171 ROP_CLEAR = 0,
196 RB_COPY_DEPTH_STENCIL = 5, 172 ROP_NOR = 1,
173 ROP_AND_INVERTED = 2,
174 ROP_COPY_INVERTED = 3,
175 ROP_AND_REVERSE = 4,
176 ROP_INVERT = 5,
177 ROP_XOR = 6,
178 ROP_NAND = 7,
179 ROP_AND = 8,
180 ROP_EQUIV = 9,
181 ROP_NOOP = 10,
182 ROP_OR_INVERTED = 11,
183 ROP_COPY = 12,
184 ROP_OR_REVERSE = 13,
185 ROP_OR = 14,
186 ROP_SET = 15,
187};
188
189enum a3xx_rb_blend_opcode {
190 BLEND_DST_PLUS_SRC = 0,
191 BLEND_SRC_MINUS_DST = 1,
192 BLEND_DST_MINUS_SRC = 2,
193 BLEND_MIN_DST_SRC = 3,
194 BLEND_MAX_DST_SRC = 4,
197}; 195};
198 196
199enum a3xx_tex_filter { 197enum a3xx_tex_filter {
200 A3XX_TEX_NEAREST = 0, 198 A3XX_TEX_NEAREST = 0,
201 A3XX_TEX_LINEAR = 1, 199 A3XX_TEX_LINEAR = 1,
200 A3XX_TEX_ANISO = 2,
202}; 201};
203 202
204enum a3xx_tex_clamp { 203enum a3xx_tex_clamp {
205 A3XX_TEX_REPEAT = 0, 204 A3XX_TEX_REPEAT = 0,
206 A3XX_TEX_CLAMP_TO_EDGE = 1, 205 A3XX_TEX_CLAMP_TO_EDGE = 1,
207 A3XX_TEX_MIRROR_REPEAT = 2, 206 A3XX_TEX_MIRROR_REPEAT = 2,
208 A3XX_TEX_CLAMP_NONE = 3, 207 A3XX_TEX_CLAMP_TO_BORDER = 3,
208 A3XX_TEX_MIRROR_CLAMP = 4,
209}; 209};
210 210
211enum a3xx_tex_swiz { 211enum a3xx_tex_swiz {
@@ -316,6 +316,7 @@ enum a3xx_tex_type {
316#define REG_A3XX_RBBM_INT_0_STATUS 0x00000064 316#define REG_A3XX_RBBM_INT_0_STATUS 0x00000064
317 317
318#define REG_A3XX_RBBM_PERFCTR_CTL 0x00000080 318#define REG_A3XX_RBBM_PERFCTR_CTL 0x00000080
319#define A3XX_RBBM_PERFCTR_CTL_ENABLE 0x00000001
319 320
320#define REG_A3XX_RBBM_PERFCTR_LOAD_CMD0 0x00000081 321#define REG_A3XX_RBBM_PERFCTR_LOAD_CMD0 0x00000081
321 322
@@ -549,6 +550,10 @@ static inline uint32_t REG_A3XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000460
549 550
550#define REG_A3XX_CP_AHB_FAULT 0x0000054d 551#define REG_A3XX_CP_AHB_FAULT 0x0000054d
551 552
553#define REG_A3XX_SP_GLOBAL_MEM_SIZE 0x00000e22
554
555#define REG_A3XX_SP_GLOBAL_MEM_ADDR 0x00000e23
556
552#define REG_A3XX_GRAS_CL_CLIP_CNTL 0x00002040 557#define REG_A3XX_GRAS_CL_CLIP_CNTL 0x00002040
553#define A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER 0x00001000 558#define A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER 0x00001000
554#define A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE 0x00010000 559#define A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE 0x00010000
@@ -556,6 +561,9 @@ static inline uint32_t REG_A3XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000460
556#define A3XX_GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE 0x00080000 561#define A3XX_GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE 0x00080000
557#define A3XX_GRAS_CL_CLIP_CNTL_VP_XFORM_DISABLE 0x00100000 562#define A3XX_GRAS_CL_CLIP_CNTL_VP_XFORM_DISABLE 0x00100000
558#define A3XX_GRAS_CL_CLIP_CNTL_PERSP_DIVISION_DISABLE 0x00200000 563#define A3XX_GRAS_CL_CLIP_CNTL_PERSP_DIVISION_DISABLE 0x00200000
564#define A3XX_GRAS_CL_CLIP_CNTL_ZCOORD 0x00800000
565#define A3XX_GRAS_CL_CLIP_CNTL_WCOORD 0x01000000
566#define A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE 0x02000000
559 567
560#define REG_A3XX_GRAS_CL_GB_CLIP_ADJ 0x00002044 568#define REG_A3XX_GRAS_CL_GB_CLIP_ADJ 0x00002044
561#define A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK 0x000003ff 569#define A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK 0x000003ff
@@ -620,8 +628,26 @@ static inline uint32_t A3XX_GRAS_CL_VPORT_ZSCALE(float val)
620} 628}
621 629
622#define REG_A3XX_GRAS_SU_POINT_MINMAX 0x00002068 630#define REG_A3XX_GRAS_SU_POINT_MINMAX 0x00002068
631#define A3XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff
632#define A3XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0
633static inline uint32_t A3XX_GRAS_SU_POINT_MINMAX_MIN(float val)
634{
635 return ((((uint32_t)(val * 8.0))) << A3XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A3XX_GRAS_SU_POINT_MINMAX_MIN__MASK;
636}
637#define A3XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000
638#define A3XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16
639static inline uint32_t A3XX_GRAS_SU_POINT_MINMAX_MAX(float val)
640{
641 return ((((uint32_t)(val * 8.0))) << A3XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A3XX_GRAS_SU_POINT_MINMAX_MAX__MASK;
642}
623 643
624#define REG_A3XX_GRAS_SU_POINT_SIZE 0x00002069 644#define REG_A3XX_GRAS_SU_POINT_SIZE 0x00002069
645#define A3XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff
646#define A3XX_GRAS_SU_POINT_SIZE__SHIFT 0
647static inline uint32_t A3XX_GRAS_SU_POINT_SIZE(float val)
648{
649 return ((((uint32_t)(val * 8.0))) << A3XX_GRAS_SU_POINT_SIZE__SHIFT) & A3XX_GRAS_SU_POINT_SIZE__MASK;
650}
625 651
626#define REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE 0x0000206c 652#define REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE 0x0000206c
627#define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK 0x00ffffff 653#define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK 0x00ffffff
@@ -743,6 +769,7 @@ static inline uint32_t A3XX_RB_MODE_CONTROL_RENDER_MODE(enum a3xx_render_mode va
743#define A3XX_RB_MODE_CONTROL_PACKER_TIMER_ENABLE 0x00010000 769#define A3XX_RB_MODE_CONTROL_PACKER_TIMER_ENABLE 0x00010000
744 770
745#define REG_A3XX_RB_RENDER_CONTROL 0x000020c1 771#define REG_A3XX_RB_RENDER_CONTROL 0x000020c1
772#define A3XX_RB_RENDER_CONTROL_FACENESS 0x00000008
746#define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK 0x00000ff0 773#define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK 0x00000ff0
747#define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT 4 774#define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT 4
748static inline uint32_t A3XX_RB_RENDER_CONTROL_BIN_WIDTH(uint32_t val) 775static inline uint32_t A3XX_RB_RENDER_CONTROL_BIN_WIDTH(uint32_t val)
@@ -751,6 +778,10 @@ static inline uint32_t A3XX_RB_RENDER_CONTROL_BIN_WIDTH(uint32_t val)
751} 778}
752#define A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE 0x00001000 779#define A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE 0x00001000
753#define A3XX_RB_RENDER_CONTROL_ENABLE_GMEM 0x00002000 780#define A3XX_RB_RENDER_CONTROL_ENABLE_GMEM 0x00002000
781#define A3XX_RB_RENDER_CONTROL_XCOORD 0x00004000
782#define A3XX_RB_RENDER_CONTROL_YCOORD 0x00008000
783#define A3XX_RB_RENDER_CONTROL_ZCOORD 0x00010000
784#define A3XX_RB_RENDER_CONTROL_WCOORD 0x00020000
754#define A3XX_RB_RENDER_CONTROL_ALPHA_TEST 0x00400000 785#define A3XX_RB_RENDER_CONTROL_ALPHA_TEST 0x00400000
755#define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK 0x07000000 786#define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK 0x07000000
756#define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT 24 787#define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT 24
@@ -796,7 +827,7 @@ static inline uint32_t REG_A3XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020c4
796#define A3XX_RB_MRT_CONTROL_BLEND2 0x00000020 827#define A3XX_RB_MRT_CONTROL_BLEND2 0x00000020
797#define A3XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000f00 828#define A3XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000f00
798#define A3XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 8 829#define A3XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 8
799static inline uint32_t A3XX_RB_MRT_CONTROL_ROP_CODE(uint32_t val) 830static inline uint32_t A3XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val)
800{ 831{
801 return ((val) << A3XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A3XX_RB_MRT_CONTROL_ROP_CODE__MASK; 832 return ((val) << A3XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A3XX_RB_MRT_CONTROL_ROP_CODE__MASK;
802} 833}
@@ -856,7 +887,7 @@ static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_b
856} 887}
857#define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0 888#define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0
858#define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5 889#define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5
859static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum adreno_rb_blend_opcode val) 890static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
860{ 891{
861 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK; 892 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK;
862} 893}
@@ -874,7 +905,7 @@ static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb
874} 905}
875#define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000 906#define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000
876#define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21 907#define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21
877static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum adreno_rb_blend_opcode val) 908static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
878{ 909{
879 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK; 910 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK;
880} 911}
@@ -957,17 +988,24 @@ static inline uint32_t A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples
957{ 988{
958 return ((val) << A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK; 989 return ((val) << A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK;
959} 990}
991#define A3XX_RB_COPY_CONTROL_DEPTHCLEAR 0x00000008
960#define A3XX_RB_COPY_CONTROL_MODE__MASK 0x00000070 992#define A3XX_RB_COPY_CONTROL_MODE__MASK 0x00000070
961#define A3XX_RB_COPY_CONTROL_MODE__SHIFT 4 993#define A3XX_RB_COPY_CONTROL_MODE__SHIFT 4
962static inline uint32_t A3XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val) 994static inline uint32_t A3XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val)
963{ 995{
964 return ((val) << A3XX_RB_COPY_CONTROL_MODE__SHIFT) & A3XX_RB_COPY_CONTROL_MODE__MASK; 996 return ((val) << A3XX_RB_COPY_CONTROL_MODE__SHIFT) & A3XX_RB_COPY_CONTROL_MODE__MASK;
965} 997}
966#define A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK 0xfffffc00 998#define A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK 0x00000f00
967#define A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 10 999#define A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT 8
1000static inline uint32_t A3XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val)
1001{
1002 return ((val) << A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK;
1003}
1004#define A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK 0xffffc000
1005#define A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 14
968static inline uint32_t A3XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val) 1006static inline uint32_t A3XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val)
969{ 1007{
970 return ((val >> 10) << A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK; 1008 return ((val >> 14) << A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK;
971} 1009}
972 1010
973#define REG_A3XX_RB_COPY_DEST_BASE 0x000020ed 1011#define REG_A3XX_RB_COPY_DEST_BASE 0x000020ed
@@ -1005,6 +1043,12 @@ static inline uint32_t A3XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val)
1005{ 1043{
1006 return ((val) << A3XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A3XX_RB_COPY_DEST_INFO_SWAP__MASK; 1044 return ((val) << A3XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A3XX_RB_COPY_DEST_INFO_SWAP__MASK;
1007} 1045}
1046#define A3XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00
1047#define A3XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10
1048static inline uint32_t A3XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
1049{
1050 return ((val) << A3XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A3XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK;
1051}
1008#define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK 0x0003c000 1052#define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK 0x0003c000
1009#define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT 14 1053#define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT 14
1010static inline uint32_t A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val) 1054static inline uint32_t A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val)
@@ -1019,6 +1063,7 @@ static inline uint32_t A3XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endi
1019} 1063}
1020 1064
1021#define REG_A3XX_RB_DEPTH_CONTROL 0x00002100 1065#define REG_A3XX_RB_DEPTH_CONTROL 0x00002100
1066#define A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z 0x00000001
1022#define A3XX_RB_DEPTH_CONTROL_Z_ENABLE 0x00000002 1067#define A3XX_RB_DEPTH_CONTROL_Z_ENABLE 0x00000002
1023#define A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE 0x00000004 1068#define A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE 0x00000004
1024#define A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00000008 1069#define A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00000008
@@ -1044,7 +1089,7 @@ static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_form
1044#define A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 11 1089#define A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 11
1045static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) 1090static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val)
1046{ 1091{
1047 return ((val >> 10) << A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; 1092 return ((val >> 12) << A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK;
1048} 1093}
1049 1094
1050#define REG_A3XX_RB_DEPTH_PITCH 0x00002103 1095#define REG_A3XX_RB_DEPTH_PITCH 0x00002103
@@ -1172,6 +1217,8 @@ static inline uint32_t A3XX_RB_WINDOW_OFFSET_Y(uint32_t val)
1172} 1217}
1173 1218
1174#define REG_A3XX_RB_SAMPLE_COUNT_CONTROL 0x00002110 1219#define REG_A3XX_RB_SAMPLE_COUNT_CONTROL 0x00002110
1220#define A3XX_RB_SAMPLE_COUNT_CONTROL_RESET 0x00000001
1221#define A3XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002
1175 1222
1176#define REG_A3XX_RB_SAMPLE_COUNT_ADDR 0x00002111 1223#define REG_A3XX_RB_SAMPLE_COUNT_ADDR 0x00002111
1177 1224
@@ -1179,7 +1226,23 @@ static inline uint32_t A3XX_RB_WINDOW_OFFSET_Y(uint32_t val)
1179 1226
1180#define REG_A3XX_RB_Z_CLAMP_MAX 0x00002115 1227#define REG_A3XX_RB_Z_CLAMP_MAX 0x00002115
1181 1228
1229#define REG_A3XX_VGT_BIN_BASE 0x000021e1
1230
1231#define REG_A3XX_VGT_BIN_SIZE 0x000021e2
1232
1182#define REG_A3XX_PC_VSTREAM_CONTROL 0x000021e4 1233#define REG_A3XX_PC_VSTREAM_CONTROL 0x000021e4
1234#define A3XX_PC_VSTREAM_CONTROL_SIZE__MASK 0x003f0000
1235#define A3XX_PC_VSTREAM_CONTROL_SIZE__SHIFT 16
1236static inline uint32_t A3XX_PC_VSTREAM_CONTROL_SIZE(uint32_t val)
1237{
1238 return ((val) << A3XX_PC_VSTREAM_CONTROL_SIZE__SHIFT) & A3XX_PC_VSTREAM_CONTROL_SIZE__MASK;
1239}
1240#define A3XX_PC_VSTREAM_CONTROL_N__MASK 0x07c00000
1241#define A3XX_PC_VSTREAM_CONTROL_N__SHIFT 22
1242static inline uint32_t A3XX_PC_VSTREAM_CONTROL_N(uint32_t val)
1243{
1244 return ((val) << A3XX_PC_VSTREAM_CONTROL_N__SHIFT) & A3XX_PC_VSTREAM_CONTROL_N__MASK;
1245}
1183 1246
1184#define REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL 0x000021ea 1247#define REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL 0x000021ea
1185 1248
@@ -1203,6 +1266,7 @@ static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_
1203 return ((val) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK; 1266 return ((val) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK;
1204} 1267}
1205#define A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000 1268#define A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000
1269#define A3XX_PC_PRIM_VTX_CNTL_PSIZE 0x04000000
1206 1270
1207#define REG_A3XX_PC_RESTART_INDEX 0x000021ed 1271#define REG_A3XX_PC_RESTART_INDEX 0x000021ed
1208 1272
@@ -1232,6 +1296,7 @@ static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize
1232} 1296}
1233#define A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE 0x00000100 1297#define A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE 0x00000100
1234#define A3XX_HLSQ_CONTROL_1_REG_RESERVED1 0x00000200 1298#define A3XX_HLSQ_CONTROL_1_REG_RESERVED1 0x00000200
1299#define A3XX_HLSQ_CONTROL_1_REG_ZWCOORD 0x02000000
1235 1300
1236#define REG_A3XX_HLSQ_CONTROL_2_REG 0x00002202 1301#define REG_A3XX_HLSQ_CONTROL_2_REG 0x00002202
1237#define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK 0xfc000000 1302#define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK 0xfc000000
@@ -1242,6 +1307,12 @@ static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val)
1242} 1307}
1243 1308
1244#define REG_A3XX_HLSQ_CONTROL_3_REG 0x00002203 1309#define REG_A3XX_HLSQ_CONTROL_3_REG 0x00002203
1310#define A3XX_HLSQ_CONTROL_3_REG_REGID__MASK 0x000000ff
1311#define A3XX_HLSQ_CONTROL_3_REG_REGID__SHIFT 0
1312static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val)
1313{
1314 return ((val) << A3XX_HLSQ_CONTROL_3_REG_REGID__SHIFT) & A3XX_HLSQ_CONTROL_3_REG_REGID__MASK;
1315}
1245 1316
1246#define REG_A3XX_HLSQ_VS_CONTROL_REG 0x00002204 1317#define REG_A3XX_HLSQ_VS_CONTROL_REG 0x00002204
1247#define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x00000fff 1318#define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x00000fff
@@ -1312,10 +1383,36 @@ static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(uint32_t val)
1312} 1383}
1313 1384
1314#define REG_A3XX_HLSQ_CL_NDRANGE_0_REG 0x0000220a 1385#define REG_A3XX_HLSQ_CL_NDRANGE_0_REG 0x0000220a
1386#define A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__MASK 0x00000003
1387#define A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__SHIFT 0
1388static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM(uint32_t val)
1389{
1390 return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__MASK;
1391}
1392#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__MASK 0x00000ffc
1393#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__SHIFT 2
1394static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0(uint32_t val)
1395{
1396 return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__MASK;
1397}
1398#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__MASK 0x003ff000
1399#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__SHIFT 12
1400static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1(uint32_t val)
1401{
1402 return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__MASK;
1403}
1404#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__MASK 0xffc00000
1405#define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__SHIFT 22
1406static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2(uint32_t val)
1407{
1408 return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__MASK;
1409}
1410
1411static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK(uint32_t i0) { return 0x0000220b + 0x2*i0; }
1315 1412
1316#define REG_A3XX_HLSQ_CL_NDRANGE_1_REG 0x0000220b 1413static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_SIZE(uint32_t i0) { return 0x0000220b + 0x2*i0; }
1317 1414
1318#define REG_A3XX_HLSQ_CL_NDRANGE_2_REG 0x0000220c 1415static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_OFFSET(uint32_t i0) { return 0x0000220c + 0x2*i0; }
1319 1416
1320#define REG_A3XX_HLSQ_CL_CONTROL_0_REG 0x00002211 1417#define REG_A3XX_HLSQ_CL_CONTROL_0_REG 0x00002211
1321 1418
@@ -1323,7 +1420,9 @@ static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(uint32_t val)
1323 1420
1324#define REG_A3XX_HLSQ_CL_KERNEL_CONST_REG 0x00002214 1421#define REG_A3XX_HLSQ_CL_KERNEL_CONST_REG 0x00002214
1325 1422
1326#define REG_A3XX_HLSQ_CL_KERNEL_GROUP_X_REG 0x00002215 1423static inline uint32_t REG_A3XX_HLSQ_CL_KERNEL_GROUP(uint32_t i0) { return 0x00002215 + 0x1*i0; }
1424
1425static inline uint32_t REG_A3XX_HLSQ_CL_KERNEL_GROUP_RATIO(uint32_t i0) { return 0x00002215 + 0x1*i0; }
1327 1426
1328#define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Y_REG 0x00002216 1427#define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Y_REG 0x00002216
1329 1428
@@ -1438,6 +1537,12 @@ static inline uint32_t A3XX_VFD_DECODE_INSTR_REGID(uint32_t val)
1438{ 1537{
1439 return ((val) << A3XX_VFD_DECODE_INSTR_REGID__SHIFT) & A3XX_VFD_DECODE_INSTR_REGID__MASK; 1538 return ((val) << A3XX_VFD_DECODE_INSTR_REGID__SHIFT) & A3XX_VFD_DECODE_INSTR_REGID__MASK;
1440} 1539}
1540#define A3XX_VFD_DECODE_INSTR_SWAP__MASK 0x00c00000
1541#define A3XX_VFD_DECODE_INSTR_SWAP__SHIFT 22
1542static inline uint32_t A3XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
1543{
1544 return ((val) << A3XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A3XX_VFD_DECODE_INSTR_SWAP__MASK;
1545}
1441#define A3XX_VFD_DECODE_INSTR_SHIFTCNT__MASK 0x1f000000 1546#define A3XX_VFD_DECODE_INSTR_SHIFTCNT__MASK 0x1f000000
1442#define A3XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT 24 1547#define A3XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT 24
1443static inline uint32_t A3XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val) 1548static inline uint32_t A3XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val)
@@ -1462,12 +1567,13 @@ static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(uint32_t val
1462} 1567}
1463 1568
1464#define REG_A3XX_VPC_ATTR 0x00002280 1569#define REG_A3XX_VPC_ATTR 0x00002280
1465#define A3XX_VPC_ATTR_TOTALATTR__MASK 0x00000fff 1570#define A3XX_VPC_ATTR_TOTALATTR__MASK 0x000001ff
1466#define A3XX_VPC_ATTR_TOTALATTR__SHIFT 0 1571#define A3XX_VPC_ATTR_TOTALATTR__SHIFT 0
1467static inline uint32_t A3XX_VPC_ATTR_TOTALATTR(uint32_t val) 1572static inline uint32_t A3XX_VPC_ATTR_TOTALATTR(uint32_t val)
1468{ 1573{
1469 return ((val) << A3XX_VPC_ATTR_TOTALATTR__SHIFT) & A3XX_VPC_ATTR_TOTALATTR__MASK; 1574 return ((val) << A3XX_VPC_ATTR_TOTALATTR__SHIFT) & A3XX_VPC_ATTR_TOTALATTR__MASK;
1470} 1575}
1576#define A3XX_VPC_ATTR_PSIZE 0x00000200
1471#define A3XX_VPC_ATTR_THRDASSIGN__MASK 0x0ffff000 1577#define A3XX_VPC_ATTR_THRDASSIGN__MASK 0x0ffff000
1472#define A3XX_VPC_ATTR_THRDASSIGN__SHIFT 12 1578#define A3XX_VPC_ATTR_THRDASSIGN__SHIFT 12
1473static inline uint32_t A3XX_VPC_ATTR_THRDASSIGN(uint32_t val) 1579static inline uint32_t A3XX_VPC_ATTR_THRDASSIGN(uint32_t val)
@@ -1522,11 +1628,11 @@ static inline uint32_t A3XX_SP_SP_CTRL_REG_SLEEPMODE(uint32_t val)
1522{ 1628{
1523 return ((val) << A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT) & A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK; 1629 return ((val) << A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT) & A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK;
1524} 1630}
1525#define A3XX_SP_SP_CTRL_REG_LOMODE__MASK 0x00c00000 1631#define A3XX_SP_SP_CTRL_REG_L0MODE__MASK 0x00c00000
1526#define A3XX_SP_SP_CTRL_REG_LOMODE__SHIFT 22 1632#define A3XX_SP_SP_CTRL_REG_L0MODE__SHIFT 22
1527static inline uint32_t A3XX_SP_SP_CTRL_REG_LOMODE(uint32_t val) 1633static inline uint32_t A3XX_SP_SP_CTRL_REG_L0MODE(uint32_t val)
1528{ 1634{
1529 return ((val) << A3XX_SP_SP_CTRL_REG_LOMODE__SHIFT) & A3XX_SP_SP_CTRL_REG_LOMODE__MASK; 1635 return ((val) << A3XX_SP_SP_CTRL_REG_L0MODE__SHIFT) & A3XX_SP_SP_CTRL_REG_L0MODE__MASK;
1530} 1636}
1531 1637
1532#define REG_A3XX_SP_VS_CTRL_REG0 0x000022c4 1638#define REG_A3XX_SP_VS_CTRL_REG0 0x000022c4
@@ -1569,6 +1675,7 @@ static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
1569} 1675}
1570#define A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE 0x00200000 1676#define A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE 0x00200000
1571#define A3XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00400000 1677#define A3XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00400000
1678#define A3XX_SP_VS_CTRL_REG0_COMPUTEMODE 0x00800000
1572#define A3XX_SP_VS_CTRL_REG0_LENGTH__MASK 0xff000000 1679#define A3XX_SP_VS_CTRL_REG0_LENGTH__MASK 0xff000000
1573#define A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT 24 1680#define A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT 24
1574static inline uint32_t A3XX_SP_VS_CTRL_REG0_LENGTH(uint32_t val) 1681static inline uint32_t A3XX_SP_VS_CTRL_REG0_LENGTH(uint32_t val)
@@ -1742,6 +1849,7 @@ static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
1742} 1849}
1743#define A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE 0x00200000 1850#define A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE 0x00200000
1744#define A3XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00400000 1851#define A3XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00400000
1852#define A3XX_SP_FS_CTRL_REG0_COMPUTEMODE 0x00800000
1745#define A3XX_SP_FS_CTRL_REG0_LENGTH__MASK 0xff000000 1853#define A3XX_SP_FS_CTRL_REG0_LENGTH__MASK 0xff000000
1746#define A3XX_SP_FS_CTRL_REG0_LENGTH__SHIFT 24 1854#define A3XX_SP_FS_CTRL_REG0_LENGTH__SHIFT 24
1747static inline uint32_t A3XX_SP_FS_CTRL_REG0_LENGTH(uint32_t val) 1855static inline uint32_t A3XX_SP_FS_CTRL_REG0_LENGTH(uint32_t val)
@@ -1802,6 +1910,13 @@ static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
1802#define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_1 0x000022e9 1910#define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_1 0x000022e9
1803 1911
1804#define REG_A3XX_SP_FS_OUTPUT_REG 0x000022ec 1912#define REG_A3XX_SP_FS_OUTPUT_REG 0x000022ec
1913#define A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE 0x00000080
1914#define A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK 0x0000ff00
1915#define A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT 8
1916static inline uint32_t A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val)
1917{
1918 return ((val) << A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK;
1919}
1805 1920
1806static inline uint32_t REG_A3XX_SP_FS_MRT(uint32_t i0) { return 0x000022f0 + 0x1*i0; } 1921static inline uint32_t REG_A3XX_SP_FS_MRT(uint32_t i0) { return 0x000022f0 + 0x1*i0; }
1807 1922
@@ -1914,6 +2029,42 @@ static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(uint32_t val)
1914 2029
1915#define REG_A3XX_VBIF_OUT_AXI_AOOO 0x0000305f 2030#define REG_A3XX_VBIF_OUT_AXI_AOOO 0x0000305f
1916 2031
2032#define REG_A3XX_VBIF_PERF_CNT_EN 0x00003070
2033#define A3XX_VBIF_PERF_CNT_EN_CNT0 0x00000001
2034#define A3XX_VBIF_PERF_CNT_EN_CNT1 0x00000002
2035#define A3XX_VBIF_PERF_CNT_EN_PWRCNT0 0x00000004
2036#define A3XX_VBIF_PERF_CNT_EN_PWRCNT1 0x00000008
2037#define A3XX_VBIF_PERF_CNT_EN_PWRCNT2 0x00000010
2038
2039#define REG_A3XX_VBIF_PERF_CNT_CLR 0x00003071
2040#define A3XX_VBIF_PERF_CNT_CLR_CNT0 0x00000001
2041#define A3XX_VBIF_PERF_CNT_CLR_CNT1 0x00000002
2042#define A3XX_VBIF_PERF_CNT_CLR_PWRCNT0 0x00000004
2043#define A3XX_VBIF_PERF_CNT_CLR_PWRCNT1 0x00000008
2044#define A3XX_VBIF_PERF_CNT_CLR_PWRCNT2 0x00000010
2045
2046#define REG_A3XX_VBIF_PERF_CNT_SEL 0x00003072
2047
2048#define REG_A3XX_VBIF_PERF_CNT0_LO 0x00003073
2049
2050#define REG_A3XX_VBIF_PERF_CNT0_HI 0x00003074
2051
2052#define REG_A3XX_VBIF_PERF_CNT1_LO 0x00003075
2053
2054#define REG_A3XX_VBIF_PERF_CNT1_HI 0x00003076
2055
2056#define REG_A3XX_VBIF_PERF_PWR_CNT0_LO 0x00003077
2057
2058#define REG_A3XX_VBIF_PERF_PWR_CNT0_HI 0x00003078
2059
2060#define REG_A3XX_VBIF_PERF_PWR_CNT1_LO 0x00003079
2061
2062#define REG_A3XX_VBIF_PERF_PWR_CNT1_HI 0x0000307a
2063
2064#define REG_A3XX_VBIF_PERF_PWR_CNT2_LO 0x0000307b
2065
2066#define REG_A3XX_VBIF_PERF_PWR_CNT2_HI 0x0000307c
2067
1917#define REG_A3XX_VSC_BIN_SIZE 0x00000c01 2068#define REG_A3XX_VSC_BIN_SIZE 0x00000c01
1918#define A3XX_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f 2069#define A3XX_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f
1919#define A3XX_VSC_BIN_SIZE_WIDTH__SHIFT 0 2070#define A3XX_VSC_BIN_SIZE_WIDTH__SHIFT 0
@@ -2080,6 +2231,8 @@ static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(enum a3xx_cache_op
2080} 2231}
2081#define A3XX_UCHE_CACHE_INVALIDATE1_REG_ENTIRE_CACHE 0x80000000 2232#define A3XX_UCHE_CACHE_INVALIDATE1_REG_ENTIRE_CACHE 0x80000000
2082 2233
2234#define REG_A3XX_UNKNOWN_0EA6 0x00000ea6
2235
2083#define REG_A3XX_SP_PERFCOUNTER0_SELECT 0x00000ec4 2236#define REG_A3XX_SP_PERFCOUNTER0_SELECT 0x00000ec4
2084 2237
2085#define REG_A3XX_SP_PERFCOUNTER1_SELECT 0x00000ec5 2238#define REG_A3XX_SP_PERFCOUNTER1_SELECT 0x00000ec5
@@ -2117,6 +2270,39 @@ static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(enum a3xx_cache_op
2117#define REG_A3XX_VGT_EVENT_INITIATOR 0x000021f9 2270#define REG_A3XX_VGT_EVENT_INITIATOR 0x000021f9
2118 2271
2119#define REG_A3XX_VGT_DRAW_INITIATOR 0x000021fc 2272#define REG_A3XX_VGT_DRAW_INITIATOR 0x000021fc
2273#define A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f
2274#define A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT 0
2275static inline uint32_t A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val)
2276{
2277 return ((val) << A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK;
2278}
2279#define A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK 0x000000c0
2280#define A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT 6
2281static inline uint32_t A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val)
2282{
2283 return ((val) << A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK;
2284}
2285#define A3XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK 0x00000600
2286#define A3XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT 9
2287static inline uint32_t A3XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val)
2288{
2289 return ((val) << A3XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT) & A3XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK;
2290}
2291#define A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK 0x00000800
2292#define A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT 11
2293static inline uint32_t A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val)
2294{
2295 return ((val) << A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK;
2296}
2297#define A3XX_VGT_DRAW_INITIATOR_NOT_EOP 0x00001000
2298#define A3XX_VGT_DRAW_INITIATOR_SMALL_INDEX 0x00002000
2299#define A3XX_VGT_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE 0x00004000
2300#define A3XX_VGT_DRAW_INITIATOR_NUM_INDICES__MASK 0xffff0000
2301#define A3XX_VGT_DRAW_INITIATOR_NUM_INDICES__SHIFT 16
2302static inline uint32_t A3XX_VGT_DRAW_INITIATOR_NUM_INDICES(uint32_t val)
2303{
2304 return ((val) << A3XX_VGT_DRAW_INITIATOR_NUM_INDICES__SHIFT) & A3XX_VGT_DRAW_INITIATOR_NUM_INDICES__MASK;
2305}
2120 2306
2121#define REG_A3XX_VGT_IMMED_DATA 0x000021fd 2307#define REG_A3XX_VGT_IMMED_DATA 0x000021fd
2122 2308
@@ -2152,6 +2338,12 @@ static inline uint32_t A3XX_TEX_SAMP_0_WRAP_R(enum a3xx_tex_clamp val)
2152{ 2338{
2153 return ((val) << A3XX_TEX_SAMP_0_WRAP_R__SHIFT) & A3XX_TEX_SAMP_0_WRAP_R__MASK; 2339 return ((val) << A3XX_TEX_SAMP_0_WRAP_R__SHIFT) & A3XX_TEX_SAMP_0_WRAP_R__MASK;
2154} 2340}
2341#define A3XX_TEX_SAMP_0_COMPARE_FUNC__MASK 0x00700000
2342#define A3XX_TEX_SAMP_0_COMPARE_FUNC__SHIFT 20
2343static inline uint32_t A3XX_TEX_SAMP_0_COMPARE_FUNC(enum adreno_compare_func val)
2344{
2345 return ((val) << A3XX_TEX_SAMP_0_COMPARE_FUNC__SHIFT) & A3XX_TEX_SAMP_0_COMPARE_FUNC__MASK;
2346}
2155#define A3XX_TEX_SAMP_0_UNNORM_COORDS 0x80000000 2347#define A3XX_TEX_SAMP_0_UNNORM_COORDS 0x80000000
2156 2348
2157#define REG_A3XX_TEX_SAMP_1 0x00000001 2349#define REG_A3XX_TEX_SAMP_1 0x00000001
@@ -2170,6 +2362,7 @@ static inline uint32_t A3XX_TEX_SAMP_1_MIN_LOD(float val)
2170 2362
2171#define REG_A3XX_TEX_CONST_0 0x00000000 2363#define REG_A3XX_TEX_CONST_0 0x00000000
2172#define A3XX_TEX_CONST_0_TILED 0x00000001 2364#define A3XX_TEX_CONST_0_TILED 0x00000001
2365#define A3XX_TEX_CONST_0_SRGB 0x00000004
2173#define A3XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070 2366#define A3XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070
2174#define A3XX_TEX_CONST_0_SWIZ_X__SHIFT 4 2367#define A3XX_TEX_CONST_0_SWIZ_X__SHIFT 4
2175static inline uint32_t A3XX_TEX_CONST_0_SWIZ_X(enum a3xx_tex_swiz val) 2368static inline uint32_t A3XX_TEX_CONST_0_SWIZ_X(enum a3xx_tex_swiz val)
@@ -2206,6 +2399,7 @@ static inline uint32_t A3XX_TEX_CONST_0_FMT(enum a3xx_tex_fmt val)
2206{ 2399{
2207 return ((val) << A3XX_TEX_CONST_0_FMT__SHIFT) & A3XX_TEX_CONST_0_FMT__MASK; 2400 return ((val) << A3XX_TEX_CONST_0_FMT__SHIFT) & A3XX_TEX_CONST_0_FMT__MASK;
2208} 2401}
2402#define A3XX_TEX_CONST_0_NOCONVERT 0x20000000
2209#define A3XX_TEX_CONST_0_TYPE__MASK 0xc0000000 2403#define A3XX_TEX_CONST_0_TYPE__MASK 0xc0000000
2210#define A3XX_TEX_CONST_0_TYPE__SHIFT 30 2404#define A3XX_TEX_CONST_0_TYPE__SHIFT 30
2211static inline uint32_t A3XX_TEX_CONST_0_TYPE(enum a3xx_tex_type val) 2405static inline uint32_t A3XX_TEX_CONST_0_TYPE(enum a3xx_tex_type val)
diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.h b/drivers/gpu/drm/msm/adreno/a3xx_gpu.h
index bb9a8ca0507b..85ff66cbddd6 100644
--- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.h
@@ -19,6 +19,11 @@
19#define __A3XX_GPU_H__ 19#define __A3XX_GPU_H__
20 20
21#include "adreno_gpu.h" 21#include "adreno_gpu.h"
22
23/* arrg, somehow fb.h is getting pulled in: */
24#undef ROP_COPY
25#undef ROP_XOR
26
22#include "a3xx.xml.h" 27#include "a3xx.xml.h"
23 28
24struct a3xx_gpu { 29struct a3xx_gpu {
diff --git a/drivers/gpu/drm/msm/adreno/adreno_common.xml.h b/drivers/gpu/drm/msm/adreno/adreno_common.xml.h
index d6e6ce2d1abd..9de19ac2e86c 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_common.xml.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_common.xml.h
@@ -10,13 +10,13 @@ git clone https://github.com/freedreno/envytools.git
10The rules-ng-ng source files this header was generated from are: 10The rules-ng-ng source files this header was generated from are:
11- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2013-11-30 14:47:15) 11- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2013-11-30 14:47:15)
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
13- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32814 bytes, from 2013-11-30 15:07:33) 13- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2014-06-02 15:21:30)
14- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 8900 bytes, from 2013-10-22 23:57:49) 14- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 9859 bytes, from 2014-06-02 15:21:30)
15- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 10574 bytes, from 2013-11-13 05:44:45) 15- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14477 bytes, from 2014-05-16 11:51:57)
16- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 53644 bytes, from 2013-11-30 15:07:33) 16- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 58020 bytes, from 2014-06-25 12:57:16)
17- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 8344 bytes, from 2013-11-30 14:49:47) 17- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 26602 bytes, from 2014-06-25 12:57:16)
18 18
19Copyright (C) 2013 by the following authors: 19Copyright (C) 2013-2014 by the following authors:
20- Rob Clark <robdclark@gmail.com> (robclark) 20- Rob Clark <robdclark@gmail.com> (robclark)
21 21
22Permission is hereby granted, free of charge, to any person obtaining 22Permission is hereby granted, free of charge, to any person obtaining
@@ -87,15 +87,6 @@ enum adreno_rb_blend_factor {
87 FACTOR_SRC_ALPHA_SATURATE = 16, 87 FACTOR_SRC_ALPHA_SATURATE = 16,
88}; 88};
89 89
90enum adreno_rb_blend_opcode {
91 BLEND_DST_PLUS_SRC = 0,
92 BLEND_SRC_MINUS_DST = 1,
93 BLEND_MIN_DST_SRC = 2,
94 BLEND_MAX_DST_SRC = 3,
95 BLEND_DST_MINUS_SRC = 4,
96 BLEND_DST_PLUS_SRC_BIAS = 5,
97};
98
99enum adreno_rb_surface_endian { 90enum adreno_rb_surface_endian {
100 ENDIAN_NONE = 0, 91 ENDIAN_NONE = 0,
101 ENDIAN_8IN16 = 1, 92 ENDIAN_8IN16 = 1,
@@ -116,6 +107,39 @@ enum adreno_rb_depth_format {
116 DEPTHX_24_8 = 1, 107 DEPTHX_24_8 = 1,
117}; 108};
118 109
110enum adreno_rb_copy_control_mode {
111 RB_COPY_RESOLVE = 1,
112 RB_COPY_CLEAR = 2,
113 RB_COPY_DEPTH_STENCIL = 5,
114};
115
116enum a3xx_render_mode {
117 RB_RENDERING_PASS = 0,
118 RB_TILING_PASS = 1,
119 RB_RESOLVE_PASS = 2,
120 RB_COMPUTE_PASS = 3,
121};
122
123enum a3xx_msaa_samples {
124 MSAA_ONE = 0,
125 MSAA_TWO = 1,
126 MSAA_FOUR = 2,
127};
128
129enum a3xx_threadmode {
130 MULTI = 0,
131 SINGLE = 1,
132};
133
134enum a3xx_instrbuffermode {
135 BUFFER = 1,
136};
137
138enum a3xx_threadsize {
139 TWO_QUADS = 0,
140 FOUR_QUADS = 1,
141};
142
119#define REG_AXXX_CP_RB_BASE 0x000001c0 143#define REG_AXXX_CP_RB_BASE 0x000001c0
120 144
121#define REG_AXXX_CP_RB_CNTL 0x000001c1 145#define REG_AXXX_CP_RB_CNTL 0x000001c1
@@ -264,6 +288,8 @@ static inline uint32_t AXXX_SCRATCH_UMSK_SWAP(uint32_t val)
264#define REG_AXXX_CP_INT_ACK 0x000001f4 288#define REG_AXXX_CP_INT_ACK 0x000001f4
265 289
266#define REG_AXXX_CP_ME_CNTL 0x000001f6 290#define REG_AXXX_CP_ME_CNTL 0x000001f6
291#define AXXX_CP_ME_CNTL_BUSY 0x20000000
292#define AXXX_CP_ME_CNTL_HALT 0x10000000
267 293
268#define REG_AXXX_CP_ME_STATUS 0x000001f7 294#define REG_AXXX_CP_ME_STATUS 0x000001f7
269 295
diff --git a/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h b/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
index ae992c71703f..4eee0ec8f069 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
@@ -10,13 +10,13 @@ git clone https://github.com/freedreno/envytools.git
10The rules-ng-ng source files this header was generated from are: 10The rules-ng-ng source files this header was generated from are:
11- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2013-11-30 14:47:15) 11- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2013-11-30 14:47:15)
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
13- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32814 bytes, from 2013-11-30 15:07:33) 13- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2014-06-02 15:21:30)
14- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 8900 bytes, from 2013-10-22 23:57:49) 14- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 9859 bytes, from 2014-06-02 15:21:30)
15- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 10574 bytes, from 2013-11-13 05:44:45) 15- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14477 bytes, from 2014-05-16 11:51:57)
16- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 53644 bytes, from 2013-11-30 15:07:33) 16- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 58020 bytes, from 2014-06-25 12:57:16)
17- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 8344 bytes, from 2013-11-30 14:49:47) 17- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 26602 bytes, from 2014-06-25 12:57:16)
18 18
19Copyright (C) 2013 by the following authors: 19Copyright (C) 2013-2014 by the following authors:
20- Rob Clark <robdclark@gmail.com> (robclark) 20- Rob Clark <robdclark@gmail.com> (robclark)
21 21
22Permission is hereby granted, free of charge, to any person obtaining 22Permission is hereby granted, free of charge, to any person obtaining
@@ -105,6 +105,7 @@ enum pc_di_index_size {
105 105
106enum pc_di_vis_cull_mode { 106enum pc_di_vis_cull_mode {
107 IGNORE_VISIBILITY = 0, 107 IGNORE_VISIBILITY = 0,
108 USE_VISIBILITY = 1,
108}; 109};
109 110
110enum adreno_pm4_packet_type { 111enum adreno_pm4_packet_type {
@@ -163,6 +164,11 @@ enum adreno_pm4_type3_packets {
163 CP_SET_BIN = 76, 164 CP_SET_BIN = 76,
164 CP_TEST_TWO_MEMS = 113, 165 CP_TEST_TWO_MEMS = 113,
165 CP_WAIT_FOR_ME = 19, 166 CP_WAIT_FOR_ME = 19,
167 CP_SET_DRAW_STATE = 67,
168 CP_DRAW_INDX_OFFSET = 56,
169 CP_DRAW_INDIRECT = 40,
170 CP_DRAW_INDX_INDIRECT = 41,
171 CP_DRAW_AUTO = 36,
166 IN_IB_PREFETCH_END = 23, 172 IN_IB_PREFETCH_END = 23,
167 IN_SUBBLK_PREFETCH = 31, 173 IN_SUBBLK_PREFETCH = 31,
168 IN_INSTR_PREFETCH = 32, 174 IN_INSTR_PREFETCH = 32,
@@ -232,6 +238,211 @@ static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val)
232 return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK; 238 return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK;
233} 239}
234 240
241#define REG_CP_DRAW_INDX_0 0x00000000
242#define CP_DRAW_INDX_0_VIZ_QUERY__MASK 0xffffffff
243#define CP_DRAW_INDX_0_VIZ_QUERY__SHIFT 0
244static inline uint32_t CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val)
245{
246 return ((val) << CP_DRAW_INDX_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_0_VIZ_QUERY__MASK;
247}
248
249#define REG_CP_DRAW_INDX_1 0x00000001
250#define CP_DRAW_INDX_1_PRIM_TYPE__MASK 0x0000003f
251#define CP_DRAW_INDX_1_PRIM_TYPE__SHIFT 0
252static inline uint32_t CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val)
253{
254 return ((val) << CP_DRAW_INDX_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_1_PRIM_TYPE__MASK;
255}
256#define CP_DRAW_INDX_1_SOURCE_SELECT__MASK 0x000000c0
257#define CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT 6
258static inline uint32_t CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val)
259{
260 return ((val) << CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_1_SOURCE_SELECT__MASK;
261}
262#define CP_DRAW_INDX_1_VIS_CULL__MASK 0x00000600
263#define CP_DRAW_INDX_1_VIS_CULL__SHIFT 9
264static inline uint32_t CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val)
265{
266 return ((val) << CP_DRAW_INDX_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_1_VIS_CULL__MASK;
267}
268#define CP_DRAW_INDX_1_INDEX_SIZE__MASK 0x00000800
269#define CP_DRAW_INDX_1_INDEX_SIZE__SHIFT 11
270static inline uint32_t CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val)
271{
272 return ((val) << CP_DRAW_INDX_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_1_INDEX_SIZE__MASK;
273}
274#define CP_DRAW_INDX_1_NOT_EOP 0x00001000
275#define CP_DRAW_INDX_1_SMALL_INDEX 0x00002000
276#define CP_DRAW_INDX_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000
277#define CP_DRAW_INDX_1_NUM_INDICES__MASK 0xffff0000
278#define CP_DRAW_INDX_1_NUM_INDICES__SHIFT 16
279static inline uint32_t CP_DRAW_INDX_1_NUM_INDICES(uint32_t val)
280{
281 return ((val) << CP_DRAW_INDX_1_NUM_INDICES__SHIFT) & CP_DRAW_INDX_1_NUM_INDICES__MASK;
282}
283
284#define REG_CP_DRAW_INDX_2 0x00000002
285#define CP_DRAW_INDX_2_NUM_INDICES__MASK 0xffffffff
286#define CP_DRAW_INDX_2_NUM_INDICES__SHIFT 0
287static inline uint32_t CP_DRAW_INDX_2_NUM_INDICES(uint32_t val)
288{
289 return ((val) << CP_DRAW_INDX_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_NUM_INDICES__MASK;
290}
291
292#define REG_CP_DRAW_INDX_2 0x00000002
293#define CP_DRAW_INDX_2_INDX_BASE__MASK 0xffffffff
294#define CP_DRAW_INDX_2_INDX_BASE__SHIFT 0
295static inline uint32_t CP_DRAW_INDX_2_INDX_BASE(uint32_t val)
296{
297 return ((val) << CP_DRAW_INDX_2_INDX_BASE__SHIFT) & CP_DRAW_INDX_2_INDX_BASE__MASK;
298}
299
300#define REG_CP_DRAW_INDX_2 0x00000002
301#define CP_DRAW_INDX_2_INDX_SIZE__MASK 0xffffffff
302#define CP_DRAW_INDX_2_INDX_SIZE__SHIFT 0
303static inline uint32_t CP_DRAW_INDX_2_INDX_SIZE(uint32_t val)
304{
305 return ((val) << CP_DRAW_INDX_2_INDX_SIZE__SHIFT) & CP_DRAW_INDX_2_INDX_SIZE__MASK;
306}
307
308#define REG_CP_DRAW_INDX_2_0 0x00000000
309#define CP_DRAW_INDX_2_0_VIZ_QUERY__MASK 0xffffffff
310#define CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT 0
311static inline uint32_t CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val)
312{
313 return ((val) << CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_2_0_VIZ_QUERY__MASK;
314}
315
316#define REG_CP_DRAW_INDX_2_1 0x00000001
317#define CP_DRAW_INDX_2_1_PRIM_TYPE__MASK 0x0000003f
318#define CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT 0
319static inline uint32_t CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val)
320{
321 return ((val) << CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_2_1_PRIM_TYPE__MASK;
322}
323#define CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK 0x000000c0
324#define CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT 6
325static inline uint32_t CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val)
326{
327 return ((val) << CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK;
328}
329#define CP_DRAW_INDX_2_1_VIS_CULL__MASK 0x00000600
330#define CP_DRAW_INDX_2_1_VIS_CULL__SHIFT 9
331static inline uint32_t CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val)
332{
333 return ((val) << CP_DRAW_INDX_2_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_2_1_VIS_CULL__MASK;
334}
335#define CP_DRAW_INDX_2_1_INDEX_SIZE__MASK 0x00000800
336#define CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT 11
337static inline uint32_t CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val)
338{
339 return ((val) << CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_2_1_INDEX_SIZE__MASK;
340}
341#define CP_DRAW_INDX_2_1_NOT_EOP 0x00001000
342#define CP_DRAW_INDX_2_1_SMALL_INDEX 0x00002000
343#define CP_DRAW_INDX_2_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000
344#define CP_DRAW_INDX_2_1_NUM_INDICES__MASK 0xffff0000
345#define CP_DRAW_INDX_2_1_NUM_INDICES__SHIFT 16
346static inline uint32_t CP_DRAW_INDX_2_1_NUM_INDICES(uint32_t val)
347{
348 return ((val) << CP_DRAW_INDX_2_1_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_1_NUM_INDICES__MASK;
349}
350
351#define REG_CP_DRAW_INDX_2_2 0x00000002
352#define CP_DRAW_INDX_2_2_NUM_INDICES__MASK 0xffffffff
353#define CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT 0
354static inline uint32_t CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val)
355{
356 return ((val) << CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_2_NUM_INDICES__MASK;
357}
358
359#define REG_CP_DRAW_INDX_OFFSET_0 0x00000000
360#define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK 0x0000003f
361#define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT 0
362static inline uint32_t CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val)
363{
364 return ((val) << CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK;
365}
366#define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK 0x000000c0
367#define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT 6
368static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val)
369{
370 return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK;
371}
372#define CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK 0x00000700
373#define CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT 8
374static inline uint32_t CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val)
375{
376 return ((val) << CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT) & CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK;
377}
378#define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK 0x00000800
379#define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT 11
380static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum pc_di_index_size val)
381{
382 return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK;
383}
384#define CP_DRAW_INDX_OFFSET_0_NOT_EOP 0x00001000
385#define CP_DRAW_INDX_OFFSET_0_SMALL_INDEX 0x00002000
386#define CP_DRAW_INDX_OFFSET_0_PRE_DRAW_INITIATOR_ENABLE 0x00004000
387#define CP_DRAW_INDX_OFFSET_0_NUM_INDICES__MASK 0xffff0000
388#define CP_DRAW_INDX_OFFSET_0_NUM_INDICES__SHIFT 16
389static inline uint32_t CP_DRAW_INDX_OFFSET_0_NUM_INDICES(uint32_t val)
390{
391 return ((val) << CP_DRAW_INDX_OFFSET_0_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_0_NUM_INDICES__MASK;
392}
393
394#define REG_CP_DRAW_INDX_OFFSET_1 0x00000001
395
396#define REG_CP_DRAW_INDX_OFFSET_2 0x00000002
397#define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK 0xffffffff
398#define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT 0
399static inline uint32_t CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val)
400{
401 return ((val) << CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK;
402}
403
404#define REG_CP_DRAW_INDX_OFFSET_2 0x00000002
405#define CP_DRAW_INDX_OFFSET_2_INDX_BASE__MASK 0xffffffff
406#define CP_DRAW_INDX_OFFSET_2_INDX_BASE__SHIFT 0
407static inline uint32_t CP_DRAW_INDX_OFFSET_2_INDX_BASE(uint32_t val)
408{
409 return ((val) << CP_DRAW_INDX_OFFSET_2_INDX_BASE__SHIFT) & CP_DRAW_INDX_OFFSET_2_INDX_BASE__MASK;
410}
411
412#define REG_CP_DRAW_INDX_OFFSET_2 0x00000002
413#define CP_DRAW_INDX_OFFSET_2_INDX_SIZE__MASK 0xffffffff
414#define CP_DRAW_INDX_OFFSET_2_INDX_SIZE__SHIFT 0
415static inline uint32_t CP_DRAW_INDX_OFFSET_2_INDX_SIZE(uint32_t val)
416{
417 return ((val) << CP_DRAW_INDX_OFFSET_2_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_2_INDX_SIZE__MASK;
418}
419
420#define REG_CP_SET_DRAW_STATE_0 0x00000000
421#define CP_SET_DRAW_STATE_0_COUNT__MASK 0x0000ffff
422#define CP_SET_DRAW_STATE_0_COUNT__SHIFT 0
423static inline uint32_t CP_SET_DRAW_STATE_0_COUNT(uint32_t val)
424{
425 return ((val) << CP_SET_DRAW_STATE_0_COUNT__SHIFT) & CP_SET_DRAW_STATE_0_COUNT__MASK;
426}
427#define CP_SET_DRAW_STATE_0_DIRTY 0x00010000
428#define CP_SET_DRAW_STATE_0_DISABLE 0x00020000
429#define CP_SET_DRAW_STATE_0_DISABLE_ALL_GROUPS 0x00040000
430#define CP_SET_DRAW_STATE_0_LOAD_IMMED 0x00080000
431#define CP_SET_DRAW_STATE_0_GROUP_ID__MASK 0x1f000000
432#define CP_SET_DRAW_STATE_0_GROUP_ID__SHIFT 24
433static inline uint32_t CP_SET_DRAW_STATE_0_GROUP_ID(uint32_t val)
434{
435 return ((val) << CP_SET_DRAW_STATE_0_GROUP_ID__SHIFT) & CP_SET_DRAW_STATE_0_GROUP_ID__MASK;
436}
437
438#define REG_CP_SET_DRAW_STATE_1 0x00000001
439#define CP_SET_DRAW_STATE_1_ADDR__MASK 0xffffffff
440#define CP_SET_DRAW_STATE_1_ADDR__SHIFT 0
441static inline uint32_t CP_SET_DRAW_STATE_1_ADDR(uint32_t val)
442{
443 return ((val) << CP_SET_DRAW_STATE_1_ADDR__SHIFT) & CP_SET_DRAW_STATE_1_ADDR__MASK;
444}
445
235#define REG_CP_SET_BIN_0 0x00000000 446#define REG_CP_SET_BIN_0 0x00000000
236 447
237#define REG_CP_SET_BIN_1 0x00000001 448#define REG_CP_SET_BIN_1 0x00000001
@@ -262,5 +473,21 @@ static inline uint32_t CP_SET_BIN_2_Y2(uint32_t val)
262 return ((val) << CP_SET_BIN_2_Y2__SHIFT) & CP_SET_BIN_2_Y2__MASK; 473 return ((val) << CP_SET_BIN_2_Y2__SHIFT) & CP_SET_BIN_2_Y2__MASK;
263} 474}
264 475
476#define REG_CP_SET_BIN_DATA_0 0x00000000
477#define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK 0xffffffff
478#define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT 0
479static inline uint32_t CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val)
480{
481 return ((val) << CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT) & CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK;
482}
483
484#define REG_CP_SET_BIN_DATA_1 0x00000001
485#define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK 0xffffffff
486#define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT 0
487static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val)
488{
489 return ((val) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK;
490}
491
265 492
266#endif /* ADRENO_PM4_XML */ 493#endif /* ADRENO_PM4_XML */
diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h b/drivers/gpu/drm/msm/dsi/dsi.xml.h
index 87be647e3825..0f1f5b9459a5 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.xml.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h
@@ -12,12 +12,12 @@ The rules-ng-ng source files this header was generated from are:
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 17996 bytes, from 2013-12-01 19:10:31) 13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 17996 bytes, from 2013-12-01 19:10:31)
14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 1615 bytes, from 2013-11-30 15:00:52) 14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 1615 bytes, from 2013-11-30 15:00:52)
15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2013-12-03 20:59:13) 15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2014-06-25 12:55:02)
16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43) 16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43)
17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32) 17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05) 18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05)
19- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12) 19- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
20- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 20932 bytes, from 2013-12-01 15:13:04) 20- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 23613 bytes, from 2014-06-25 12:53:44)
21 21
22Copyright (C) 2013 by the following authors: 22Copyright (C) 2013 by the following authors:
23- Rob Clark <robdclark@gmail.com> (robclark) 23- Rob Clark <robdclark@gmail.com> (robclark)
diff --git a/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h b/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h
index 747a6ef4211f..d468f86f637c 100644
--- a/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h
+++ b/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h
@@ -12,12 +12,12 @@ The rules-ng-ng source files this header was generated from are:
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 17996 bytes, from 2013-12-01 19:10:31) 13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 17996 bytes, from 2013-12-01 19:10:31)
14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 1615 bytes, from 2013-11-30 15:00:52) 14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 1615 bytes, from 2013-11-30 15:00:52)
15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2013-12-03 20:59:13) 15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2014-06-25 12:55:02)
16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43) 16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43)
17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32) 17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05) 18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05)
19- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12) 19- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
20- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 20932 bytes, from 2013-12-01 15:13:04) 20- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 23613 bytes, from 2014-06-25 12:53:44)
21 21
22Copyright (C) 2013 by the following authors: 22Copyright (C) 2013 by the following authors:
23- Rob Clark <robdclark@gmail.com> (robclark) 23- Rob Clark <robdclark@gmail.com> (robclark)
diff --git a/drivers/gpu/drm/msm/dsi/sfpb.xml.h b/drivers/gpu/drm/msm/dsi/sfpb.xml.h
index 48e03acf19bf..da8740054cdf 100644
--- a/drivers/gpu/drm/msm/dsi/sfpb.xml.h
+++ b/drivers/gpu/drm/msm/dsi/sfpb.xml.h
@@ -12,12 +12,12 @@ The rules-ng-ng source files this header was generated from are:
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 17996 bytes, from 2013-12-01 19:10:31) 13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 17996 bytes, from 2013-12-01 19:10:31)
14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 1615 bytes, from 2013-11-30 15:00:52) 14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 1615 bytes, from 2013-11-30 15:00:52)
15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2013-12-03 20:59:13) 15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2014-06-25 12:55:02)
16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43) 16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43)
17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32) 17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05) 18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05)
19- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12) 19- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
20- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 20932 bytes, from 2013-12-01 15:13:04) 20- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 23613 bytes, from 2014-06-25 12:53:44)
21 21
22Copyright (C) 2013 by the following authors: 22Copyright (C) 2013 by the following authors:
23- Rob Clark <robdclark@gmail.com> (robclark) 23- Rob Clark <robdclark@gmail.com> (robclark)
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.xml.h b/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
index e2636582cfd7..e89fe053d375 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
+++ b/drivers/gpu/drm/msm/hdmi/hdmi.xml.h
@@ -12,14 +12,14 @@ The rules-ng-ng source files this header was generated from are:
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 17996 bytes, from 2013-12-01 19:10:31) 13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 17996 bytes, from 2013-12-01 19:10:31)
14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 1615 bytes, from 2013-11-30 15:00:52) 14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 1615 bytes, from 2013-11-30 15:00:52)
15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2013-12-03 20:59:13) 15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2014-06-25 12:55:02)
16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43) 16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43)
17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32) 17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05) 18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05)
19- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12) 19- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
20- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 20932 bytes, from 2013-12-01 15:13:04) 20- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 23613 bytes, from 2014-06-25 12:53:44)
21 21
22Copyright (C) 2013 by the following authors: 22Copyright (C) 2013-2014 by the following authors:
23- Rob Clark <robdclark@gmail.com> (robclark) 23- Rob Clark <robdclark@gmail.com> (robclark)
24 24
25Permission is hereby granted, free of charge, to any person obtaining 25Permission is hereby granted, free of charge, to any person obtaining
@@ -148,9 +148,9 @@ static inline uint32_t REG_HDMI_GENERIC0(uint32_t i0) { return 0x00000088 + 0x4*
148 148
149static inline uint32_t REG_HDMI_GENERIC1(uint32_t i0) { return 0x000000a8 + 0x4*i0; } 149static inline uint32_t REG_HDMI_GENERIC1(uint32_t i0) { return 0x000000a8 + 0x4*i0; }
150 150
151static inline uint32_t REG_HDMI_ACR(uint32_t i0) { return 0x000000c4 + 0x8*i0; } 151static inline uint32_t REG_HDMI_ACR(enum hdmi_acr_cts i0) { return 0x000000c4 + 0x8*i0; }
152 152
153static inline uint32_t REG_HDMI_ACR_0(uint32_t i0) { return 0x000000c4 + 0x8*i0; } 153static inline uint32_t REG_HDMI_ACR_0(enum hdmi_acr_cts i0) { return 0x000000c4 + 0x8*i0; }
154#define HDMI_ACR_0_CTS__MASK 0xfffff000 154#define HDMI_ACR_0_CTS__MASK 0xfffff000
155#define HDMI_ACR_0_CTS__SHIFT 12 155#define HDMI_ACR_0_CTS__SHIFT 12
156static inline uint32_t HDMI_ACR_0_CTS(uint32_t val) 156static inline uint32_t HDMI_ACR_0_CTS(uint32_t val)
@@ -158,7 +158,7 @@ static inline uint32_t HDMI_ACR_0_CTS(uint32_t val)
158 return ((val) << HDMI_ACR_0_CTS__SHIFT) & HDMI_ACR_0_CTS__MASK; 158 return ((val) << HDMI_ACR_0_CTS__SHIFT) & HDMI_ACR_0_CTS__MASK;
159} 159}
160 160
161static inline uint32_t REG_HDMI_ACR_1(uint32_t i0) { return 0x000000c8 + 0x8*i0; } 161static inline uint32_t REG_HDMI_ACR_1(enum hdmi_acr_cts i0) { return 0x000000c8 + 0x8*i0; }
162#define HDMI_ACR_1_N__MASK 0xffffffff 162#define HDMI_ACR_1_N__MASK 0xffffffff
163#define HDMI_ACR_1_N__SHIFT 0 163#define HDMI_ACR_1_N__SHIFT 0
164static inline uint32_t HDMI_ACR_1_N(uint32_t val) 164static inline uint32_t HDMI_ACR_1_N(uint32_t val)
@@ -552,6 +552,103 @@ static inline uint32_t HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(uint32_t val)
552#define REG_HDMI_8960_PHY_REG11 0x0000042c 552#define REG_HDMI_8960_PHY_REG11 0x0000042c
553 553
554#define REG_HDMI_8960_PHY_REG12 0x00000430 554#define REG_HDMI_8960_PHY_REG12 0x00000430
555#define HDMI_8960_PHY_REG12_SW_RESET 0x00000020
556#define HDMI_8960_PHY_REG12_PWRDN_B 0x00000080
557
558#define REG_HDMI_8960_PHY_REG_BIST_CFG 0x00000434
559
560#define REG_HDMI_8960_PHY_DEBUG_BUS_SEL 0x00000438
561
562#define REG_HDMI_8960_PHY_REG_MISC0 0x0000043c
563
564#define REG_HDMI_8960_PHY_REG13 0x00000440
565
566#define REG_HDMI_8960_PHY_REG14 0x00000444
567
568#define REG_HDMI_8960_PHY_REG15 0x00000448
569
570#define REG_HDMI_8960_PHY_PLL_REFCLK_CFG 0x00000500
571
572#define REG_HDMI_8960_PHY_PLL_CHRG_PUMP_CFG 0x00000504
573
574#define REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG0 0x00000508
575
576#define REG_HDMI_8960_PHY_PLL_LOOP_FLT_CFG1 0x0000050c
577
578#define REG_HDMI_8960_PHY_PLL_IDAC_ADJ_CFG 0x00000510
579
580#define REG_HDMI_8960_PHY_PLL_I_VI_KVCO_CFG 0x00000514
581
582#define REG_HDMI_8960_PHY_PLL_PWRDN_B 0x00000518
583#define HDMI_8960_PHY_PLL_PWRDN_B_PD_PLL 0x00000002
584#define HDMI_8960_PHY_PLL_PWRDN_B_PLL_PWRDN_B 0x00000008
585
586#define REG_HDMI_8960_PHY_PLL_SDM_CFG0 0x0000051c
587
588#define REG_HDMI_8960_PHY_PLL_SDM_CFG1 0x00000520
589
590#define REG_HDMI_8960_PHY_PLL_SDM_CFG2 0x00000524
591
592#define REG_HDMI_8960_PHY_PLL_SDM_CFG3 0x00000528
593
594#define REG_HDMI_8960_PHY_PLL_SDM_CFG4 0x0000052c
595
596#define REG_HDMI_8960_PHY_PLL_SSC_CFG0 0x00000530
597
598#define REG_HDMI_8960_PHY_PLL_SSC_CFG1 0x00000534
599
600#define REG_HDMI_8960_PHY_PLL_SSC_CFG2 0x00000538
601
602#define REG_HDMI_8960_PHY_PLL_SSC_CFG3 0x0000053c
603
604#define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG0 0x00000540
605
606#define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG1 0x00000544
607
608#define REG_HDMI_8960_PHY_PLL_LOCKDET_CFG2 0x00000548
609
610#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG0 0x0000054c
611
612#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG1 0x00000550
613
614#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG2 0x00000554
615
616#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG3 0x00000558
617
618#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG4 0x0000055c
619
620#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG5 0x00000560
621
622#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG6 0x00000564
623
624#define REG_HDMI_8960_PHY_PLL_VCOCAL_CFG7 0x00000568
625
626#define REG_HDMI_8960_PHY_PLL_DEBUG_SEL 0x0000056c
627
628#define REG_HDMI_8960_PHY_PLL_MISC0 0x00000570
629
630#define REG_HDMI_8960_PHY_PLL_MISC1 0x00000574
631
632#define REG_HDMI_8960_PHY_PLL_MISC2 0x00000578
633
634#define REG_HDMI_8960_PHY_PLL_MISC3 0x0000057c
635
636#define REG_HDMI_8960_PHY_PLL_MISC4 0x00000580
637
638#define REG_HDMI_8960_PHY_PLL_MISC5 0x00000584
639
640#define REG_HDMI_8960_PHY_PLL_MISC6 0x00000588
641
642#define REG_HDMI_8960_PHY_PLL_DEBUG_BUS0 0x0000058c
643
644#define REG_HDMI_8960_PHY_PLL_DEBUG_BUS1 0x00000590
645
646#define REG_HDMI_8960_PHY_PLL_DEBUG_BUS2 0x00000594
647
648#define REG_HDMI_8960_PHY_PLL_STATUS0 0x00000598
649#define HDMI_8960_PHY_PLL_STATUS0_PLL_LOCK 0x00000001
650
651#define REG_HDMI_8960_PHY_PLL_STATUS1 0x0000059c
555 652
556#define REG_HDMI_8x74_ANA_CFG0 0x00000000 653#define REG_HDMI_8x74_ANA_CFG0 0x00000000
557 654
diff --git a/drivers/gpu/drm/msm/hdmi/qfprom.xml.h b/drivers/gpu/drm/msm/hdmi/qfprom.xml.h
index d591567173c4..bd81db6a7829 100644
--- a/drivers/gpu/drm/msm/hdmi/qfprom.xml.h
+++ b/drivers/gpu/drm/msm/hdmi/qfprom.xml.h
@@ -12,12 +12,12 @@ The rules-ng-ng source files this header was generated from are:
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 17996 bytes, from 2013-12-01 19:10:31) 13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 17996 bytes, from 2013-12-01 19:10:31)
14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 1615 bytes, from 2013-11-30 15:00:52) 14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 1615 bytes, from 2013-11-30 15:00:52)
15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2013-12-03 20:59:13) 15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2014-06-25 12:55:02)
16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43) 16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43)
17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32) 17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05) 18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05)
19- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12) 19- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
20- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 20932 bytes, from 2013-12-01 15:13:04) 20- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 23613 bytes, from 2014-06-25 12:53:44)
21 21
22Copyright (C) 2013 by the following authors: 22Copyright (C) 2013 by the following authors:
23- Rob Clark <robdclark@gmail.com> (robclark) 23- Rob Clark <robdclark@gmail.com> (robclark)
diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h b/drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h
index 416a26e1e58d..122208e8a2ee 100644
--- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h
+++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h
@@ -12,12 +12,12 @@ The rules-ng-ng source files this header was generated from are:
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 17996 bytes, from 2013-12-01 19:10:31) 13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 17996 bytes, from 2013-12-01 19:10:31)
14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 1615 bytes, from 2013-11-30 15:00:52) 14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 1615 bytes, from 2013-11-30 15:00:52)
15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2013-12-03 20:59:13) 15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2014-06-25 12:55:02)
16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43) 16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43)
17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32) 17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05) 18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05)
19- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12) 19- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
20- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 20932 bytes, from 2013-12-01 15:13:04) 20- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 23613 bytes, from 2014-06-25 12:53:44)
21 21
22Copyright (C) 2013 by the following authors: 22Copyright (C) 2013 by the following authors:
23- Rob Clark <robdclark@gmail.com> (robclark) 23- Rob Clark <robdclark@gmail.com> (robclark)
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
index 0aa51517f826..d501bacda4b6 100644
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
@@ -12,14 +12,14 @@ The rules-ng-ng source files this header was generated from are:
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 17996 bytes, from 2013-12-01 19:10:31) 13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 17996 bytes, from 2013-12-01 19:10:31)
14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 1615 bytes, from 2013-11-30 15:00:52) 14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 1615 bytes, from 2013-11-30 15:00:52)
15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2013-12-03 20:59:13) 15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2014-06-25 12:55:02)
16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43) 16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43)
17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32) 17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05) 18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05)
19- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12) 19- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
20- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 20932 bytes, from 2013-12-01 15:13:04) 20- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 23613 bytes, from 2014-06-25 12:53:44)
21 21
22Copyright (C) 2013 by the following authors: 22Copyright (C) 2013-2014 by the following authors:
23- Rob Clark <robdclark@gmail.com> (robclark) 23- Rob Clark <robdclark@gmail.com> (robclark)
24 24
25Permission is hereby granted, free of charge, to any person obtaining 25Permission is hereby granted, free of charge, to any person obtaining
diff --git a/drivers/gpu/drm/msm/mdp/mdp_common.xml.h b/drivers/gpu/drm/msm/mdp/mdp_common.xml.h
index a9629b85b983..64c1afd6030a 100644
--- a/drivers/gpu/drm/msm/mdp/mdp_common.xml.h
+++ b/drivers/gpu/drm/msm/mdp/mdp_common.xml.h
@@ -12,12 +12,12 @@ The rules-ng-ng source files this header was generated from are:
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) 12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 17996 bytes, from 2013-12-01 19:10:31) 13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 17996 bytes, from 2013-12-01 19:10:31)
14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 1615 bytes, from 2013-11-30 15:00:52) 14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 1615 bytes, from 2013-11-30 15:00:52)
15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2013-12-03 20:59:13) 15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2014-06-25 12:55:02)
16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43) 16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43)
17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32) 17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05) 18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05)
19- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12) 19- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
20- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 20932 bytes, from 2013-12-01 15:13:04) 20- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 23613 bytes, from 2014-06-25 12:53:44)
21 21
22Copyright (C) 2013 by the following authors: 22Copyright (C) 2013 by the following authors:
23- Rob Clark <robdclark@gmail.com> (robclark) 23- Rob Clark <robdclark@gmail.com> (robclark)
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-24 09:10:04 -0500