6 files changed, 322 insertions, 29 deletions

diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index a3afac4be734..cbe7a2fb779f 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -299,11 +299,11 @@ config I2C_AT91
           unless your system can cope with those limitations.
 
 config I2C_AU1550
-        tristate "Au1550/Au1200 SMBus interface"
+        tristate "Au1550/Au1200/Au1300 SMBus interface"
         depends on MIPS_ALCHEMY
         help
           If you say yes to this option, support will be included for the
-          Au1550 and Au1200 SMBus interface.
+          Au1550/Au1200/Au1300 SMBus interface.
 
           This driver can also be built as a module.  If so, the module
           will be called i2c-au1550.
diff --git a/drivers/mmc/host/au1xmmc.c b/drivers/mmc/host/au1xmmc.c
index 5d3b9ae64523..dbd0c8a4e98a 100644
--- a/drivers/mmc/host/au1xmmc.c
+++ b/drivers/mmc/host/au1xmmc.c
@@ -153,6 +153,7 @@ static inline int has_dbdma(void)
 {
         switch (alchemy_get_cputype()) {
         case ALCHEMY_CPU_AU1200:
+        case ALCHEMY_CPU_AU1300:
                 return 1;
         default:
                 return 0;
@@ -768,11 +769,15 @@ static void au1xmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 
         config2 = au_readl(HOST_CONFIG2(host));
         switch (ios->bus_width) {
+        case MMC_BUS_WIDTH_8:
+                config2 |= SD_CONFIG2_BB;
+                break;
         case MMC_BUS_WIDTH_4:
+                config2 &= ~SD_CONFIG2_BB;
                 config2 |= SD_CONFIG2_WB;
                 break;
         case MMC_BUS_WIDTH_1:
-                config2 &= ~SD_CONFIG2_WB;
+                config2 &= ~(SD_CONFIG2_WB | SD_CONFIG2_BB);
                 break;
         }
         au_writel(config2, HOST_CONFIG2(host));
@@ -943,7 +948,7 @@ static int __devinit au1xmmc_probe(struct platform_device *pdev)
         struct mmc_host *mmc;
         struct au1xmmc_host *host;
         struct resource *r;
-        int ret;
+        int ret, iflag;
 
         mmc = mmc_alloc_host(sizeof(struct au1xmmc_host), &pdev->dev);
         if (!mmc) {
@@ -982,37 +987,43 @@ static int __devinit au1xmmc_probe(struct platform_device *pdev)
                 dev_err(&pdev->dev, "no IRQ defined\n");
                 goto out3;
         }
-
         host->irq = r->start;
-        /* IRQ is shared among both SD controllers */
-        ret = request_irq(host->irq, au1xmmc_irq, IRQF_SHARED,
-                          DRIVER_NAME, host);
-        if (ret) {
-                dev_err(&pdev->dev, "cannot grab IRQ\n");
-                goto out3;
-        }
 
         mmc->ops = &au1xmmc_ops;
 
         mmc->f_min =   450000;
         mmc->f_max = 24000000;
 
+        mmc->max_blk_size = 2048;
+        mmc->max_blk_count = 512;
+
+        mmc->ocr_avail = AU1XMMC_OCR;
+        mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
+        mmc->max_segs = AU1XMMC_DESCRIPTOR_COUNT;
+
+        iflag = IRQF_SHARED;    /* Au1100/Au1200: one int for both ctrls */
+
         switch (alchemy_get_cputype()) {
         case ALCHEMY_CPU_AU1100:
                 mmc->max_seg_size = AU1100_MMC_DESCRIPTOR_SIZE;
-                mmc->max_segs = AU1XMMC_DESCRIPTOR_COUNT;
                 break;
         case ALCHEMY_CPU_AU1200:
                 mmc->max_seg_size = AU1200_MMC_DESCRIPTOR_SIZE;
-                mmc->max_segs = AU1XMMC_DESCRIPTOR_COUNT;
+                break;
+        case ALCHEMY_CPU_AU1300:
+                iflag = 0;      /* nothing is shared */
+                mmc->max_seg_size = AU1200_MMC_DESCRIPTOR_SIZE;
+                mmc->f_max = 52000000;
+                if (host->ioarea->start == AU1100_SD0_PHYS_ADDR)
+                        mmc->caps |= MMC_CAP_8_BIT_DATA;
                 break;
         }
 
-        mmc->max_blk_size = 2048;
-        mmc->max_blk_count = 512;
-
-        mmc->ocr_avail = AU1XMMC_OCR;
-        mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
+        ret = request_irq(host->irq, au1xmmc_irq, iflag, DRIVER_NAME, host);
+        if (ret) {
+                dev_err(&pdev->dev, "cannot grab IRQ\n");
+                goto out3;
+        }
 
         host->status = HOST_S_IDLE;
 
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index a1fd73df5416..369e092bf3d5 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -87,12 +87,12 @@ config SPI_BFIN_SPORT
           Enable support for a SPI bus via the Blackfin SPORT peripheral.
 
 config SPI_AU1550
-        tristate "Au1550/Au12x0 SPI Controller"
+        tristate "Au1550/Au1200/Au1300 SPI Controller"
         depends on MIPS_ALCHEMY && EXPERIMENTAL
         select SPI_BITBANG
         help
           If you say yes to this option, support will be included for the
-          Au1550 SPI controller (may also work with Au1200,Au1210,Au1250).
+          PSC SPI controller found on Au1550, Au1200 and Au1300 series.
 
 config SPI_BITBANG
         tristate "Utilities for Bitbanging SPI masters"
diff --git a/drivers/usb/host/alchemy-common.c b/drivers/usb/host/alchemy-common.c
index b4192c964d0d..936af8359fb2 100644
--- a/drivers/usb/host/alchemy-common.c
+++ b/drivers/usb/host/alchemy-common.c
@@ -52,9 +52,263 @@
                                  USBCFG_EBE | USBCFG_EME | USBCFG_OBE |        \
                                  USBCFG_OME)
 
+/* Au1300 USB config registers */
+#define USB_DWC_CTRL1           0x00
+#define USB_DWC_CTRL2           0x04
+#define USB_VBUS_TIMER          0x10
+#define USB_SBUS_CTRL           0x14
+#define USB_MSR_ERR             0x18
+#define USB_DWC_CTRL3           0x1C
+#define USB_DWC_CTRL4           0x20
+#define USB_OTG_STATUS          0x28
+#define USB_DWC_CTRL5           0x2C
+#define USB_DWC_CTRL6           0x30
+#define USB_DWC_CTRL7           0x34
+#define USB_PHY_STATUS          0xC0
+#define USB_INT_STATUS          0xC4
+#define USB_INT_ENABLE          0xC8
+
+#define USB_DWC_CTRL1_OTGD      0x04 /* set to DISable OTG */
+#define USB_DWC_CTRL1_HSTRS     0x02 /* set to ENable EHCI */
+#define USB_DWC_CTRL1_DCRS      0x01 /* set to ENable UDC */
+
+#define USB_DWC_CTRL2_PHY1RS    0x04 /* set to enable PHY1 */
+#define USB_DWC_CTRL2_PHY0RS    0x02 /* set to enable PHY0 */
+#define USB_DWC_CTRL2_PHYRS     0x01 /* set to enable PHY */
+
+#define USB_DWC_CTRL3_OHCI1_CKEN        (1 << 19)
+#define USB_DWC_CTRL3_OHCI0_CKEN        (1 << 18)
+#define USB_DWC_CTRL3_EHCI0_CKEN        (1 << 17)
+#define USB_DWC_CTRL3_OTG0_CKEN         (1 << 16)
+
+#define USB_SBUS_CTRL_SBCA              0x04 /* coherent access */
+
+#define USB_INTEN_FORCE                 0x20
+#define USB_INTEN_PHY                   0x10
+#define USB_INTEN_UDC                   0x08
+#define USB_INTEN_EHCI                  0x04
+#define USB_INTEN_OHCI1                 0x02
+#define USB_INTEN_OHCI0                 0x01
 
 static DEFINE_SPINLOCK(alchemy_usb_lock);
 
+static inline void __au1300_usb_phyctl(void __iomem *base, int enable)
+{
+        unsigned long r, s;
+
+        r = __raw_readl(base + USB_DWC_CTRL2);
+        s = __raw_readl(base + USB_DWC_CTRL3);
+
+        s &= USB_DWC_CTRL3_OHCI1_CKEN | USB_DWC_CTRL3_OHCI0_CKEN |
+                USB_DWC_CTRL3_EHCI0_CKEN | USB_DWC_CTRL3_OTG0_CKEN;
+
+        if (enable) {
+                /* simply enable all PHYs */
+                r |= USB_DWC_CTRL2_PHY1RS | USB_DWC_CTRL2_PHY0RS |
+                     USB_DWC_CTRL2_PHYRS;
+                __raw_writel(r, base + USB_DWC_CTRL2);
+                wmb();
+        } else if (!s) {
+                /* no USB block active, do disable all PHYs */
+                r &= ~(USB_DWC_CTRL2_PHY1RS | USB_DWC_CTRL2_PHY0RS |
+                       USB_DWC_CTRL2_PHYRS);
+                __raw_writel(r, base + USB_DWC_CTRL2);
+                wmb();
+        }
+}
+
+static inline void __au1300_ohci_control(void __iomem *base, int enable, int id)
+{
+        unsigned long r;
+
+        if (enable) {
+                __raw_writel(1, base + USB_DWC_CTRL7);  /* start OHCI clock */
+                wmb();
+
+                r = __raw_readl(base + USB_DWC_CTRL3);  /* enable OHCI block */
+                r |= (id == 0) ? USB_DWC_CTRL3_OHCI0_CKEN
+                               : USB_DWC_CTRL3_OHCI1_CKEN;
+                __raw_writel(r, base + USB_DWC_CTRL3);
+                wmb();
+
+                __au1300_usb_phyctl(base, enable);      /* power up the PHYs */
+
+                r = __raw_readl(base + USB_INT_ENABLE);
+                r |= (id == 0) ? USB_INTEN_OHCI0 : USB_INTEN_OHCI1;
+                __raw_writel(r, base + USB_INT_ENABLE);
+                wmb();
+
+                /* reset the OHCI start clock bit */
+                __raw_writel(0, base + USB_DWC_CTRL7);
+                wmb();
+        } else {
+                r = __raw_readl(base + USB_INT_ENABLE);
+                r &= ~((id == 0) ? USB_INTEN_OHCI0 : USB_INTEN_OHCI1);
+                __raw_writel(r, base + USB_INT_ENABLE);
+                wmb();
+
+                r = __raw_readl(base + USB_DWC_CTRL3);
+                r &= ~((id == 0) ? USB_DWC_CTRL3_OHCI0_CKEN
+                                 : USB_DWC_CTRL3_OHCI1_CKEN);
+                __raw_writel(r, base + USB_DWC_CTRL3);
+                wmb();
+
+                __au1300_usb_phyctl(base, enable);
+        }
+}
+
+static inline void __au1300_ehci_control(void __iomem *base, int enable)
+{
+        unsigned long r;
+
+        if (enable) {
+                r = __raw_readl(base + USB_DWC_CTRL3);
+                r |= USB_DWC_CTRL3_EHCI0_CKEN;
+                __raw_writel(r, base + USB_DWC_CTRL3);
+                wmb();
+
+                r = __raw_readl(base + USB_DWC_CTRL1);
+                r |= USB_DWC_CTRL1_HSTRS;
+                __raw_writel(r, base + USB_DWC_CTRL1);
+                wmb();
+
+                __au1300_usb_phyctl(base, enable);
+
+                r = __raw_readl(base + USB_INT_ENABLE);
+                r |= USB_INTEN_EHCI;
+                __raw_writel(r, base + USB_INT_ENABLE);
+                wmb();
+        } else {
+                r = __raw_readl(base + USB_INT_ENABLE);
+                r &= ~USB_INTEN_EHCI;
+                __raw_writel(r, base + USB_INT_ENABLE);
+                wmb();
+
+                r = __raw_readl(base + USB_DWC_CTRL1);
+                r &= ~USB_DWC_CTRL1_HSTRS;
+                __raw_writel(r, base + USB_DWC_CTRL1);
+                wmb();
+
+                r = __raw_readl(base + USB_DWC_CTRL3);
+                r &= ~USB_DWC_CTRL3_EHCI0_CKEN;
+                __raw_writel(r, base + USB_DWC_CTRL3);
+                wmb();
+
+                __au1300_usb_phyctl(base, enable);
+        }
+}
+
+static inline void __au1300_udc_control(void __iomem *base, int enable)
+{
+        unsigned long r;
+
+        if (enable) {
+                r = __raw_readl(base + USB_DWC_CTRL1);
+                r |= USB_DWC_CTRL1_DCRS;
+                __raw_writel(r, base + USB_DWC_CTRL1);
+                wmb();
+
+                __au1300_usb_phyctl(base, enable);
+
+                r = __raw_readl(base + USB_INT_ENABLE);
+                r |= USB_INTEN_UDC;
+                __raw_writel(r, base + USB_INT_ENABLE);
+                wmb();
+        } else {
+                r = __raw_readl(base + USB_INT_ENABLE);
+                r &= ~USB_INTEN_UDC;
+                __raw_writel(r, base + USB_INT_ENABLE);
+                wmb();
+
+                r = __raw_readl(base + USB_DWC_CTRL1);
+                r &= ~USB_DWC_CTRL1_DCRS;
+                __raw_writel(r, base + USB_DWC_CTRL1);
+                wmb();
+
+                __au1300_usb_phyctl(base, enable);
+        }
+}
+
+static inline void __au1300_otg_control(void __iomem *base, int enable)
+{
+        unsigned long r;
+        if (enable) {
+                r = __raw_readl(base + USB_DWC_CTRL3);
+                r |= USB_DWC_CTRL3_OTG0_CKEN;
+                __raw_writel(r, base + USB_DWC_CTRL3);
+                wmb();
+
+                r = __raw_readl(base + USB_DWC_CTRL1);
+                r &= ~USB_DWC_CTRL1_OTGD;
+                __raw_writel(r, base + USB_DWC_CTRL1);
+                wmb();
+
+                __au1300_usb_phyctl(base, enable);
+        } else {
+                r = __raw_readl(base + USB_DWC_CTRL1);
+                r |= USB_DWC_CTRL1_OTGD;
+                __raw_writel(r, base + USB_DWC_CTRL1);
+                wmb();
+
+                r = __raw_readl(base + USB_DWC_CTRL3);
+                r &= ~USB_DWC_CTRL3_OTG0_CKEN;
+                __raw_writel(r, base + USB_DWC_CTRL3);
+                wmb();
+
+                __au1300_usb_phyctl(base, enable);
+        }
+}
+
+static inline int au1300_usb_control(int block, int enable)
+{
+        void __iomem *base =
+                (void __iomem *)KSEG1ADDR(AU1300_USB_CTL_PHYS_ADDR);
+        int ret = 0;
+
+        switch (block) {
+        case ALCHEMY_USB_OHCI0:
+                __au1300_ohci_control(base, enable, 0);
+                break;
+        case ALCHEMY_USB_OHCI1:
+                __au1300_ohci_control(base, enable, 1);
+                break;
+        case ALCHEMY_USB_EHCI0:
+                __au1300_ehci_control(base, enable);
+                break;
+        case ALCHEMY_USB_UDC0:
+                __au1300_udc_control(base, enable);
+                break;
+        case ALCHEMY_USB_OTG0:
+                __au1300_otg_control(base, enable);
+                break;
+        default:
+                ret = -ENODEV;
+        }
+        return ret;
+}
+
+static inline void au1300_usb_init(void)
+{
+        void __iomem *base =
+                (void __iomem *)KSEG1ADDR(AU1300_USB_CTL_PHYS_ADDR);
+
+        /* set some sane defaults.  Note: we don't fiddle with DWC_CTRL4
+         * here at all: Port 2 routing (EHCI or UDC) must be set either
+         * by boot firmware or platform init code; I can't autodetect
+         * a sane setting.
+         */
+        __raw_writel(0, base + USB_INT_ENABLE); /* disable all USB irqs */
+        wmb();
+        __raw_writel(0, base + USB_DWC_CTRL3); /* disable all clocks */
+        wmb();
+        __raw_writel(~0, base + USB_MSR_ERR); /* clear all errors */
+        wmb();
+        __raw_writel(~0, base + USB_INT_STATUS); /* clear int status */
+        wmb();
+        /* set coherent access bit */
+        __raw_writel(USB_SBUS_CTRL_SBCA, base + USB_SBUS_CTRL);
+        wmb();
+}
 
 static inline void __au1200_ohci_control(void __iomem *base, int enable)
 {
@@ -233,6 +487,9 @@ int alchemy_usb_control(int block, int enable)
         case ALCHEMY_CPU_AU1200:
                 ret = au1200_usb_control(block, enable);
                 break;
+        case ALCHEMY_CPU_AU1300:
+                ret = au1300_usb_control(block, enable);
+                break;
         default:
                 ret = -ENODEV;
         }
@@ -281,6 +538,20 @@ static void au1200_usb_pm(int susp)
         }
 }
 
+static void au1300_usb_pm(int susp)
+{
+        void __iomem *base =
+                        (void __iomem *)KSEG1ADDR(AU1300_USB_CTL_PHYS_ADDR);
+        /* remember Port2 routing */
+        if (susp) {
+                alchemy_usb_pmdata[0] = __raw_readl(base + USB_DWC_CTRL4);
+        } else {
+                au1300_usb_init();
+                __raw_writel(alchemy_usb_pmdata[0], base + USB_DWC_CTRL4);
+                wmb();
+        }
+}
+
 static void alchemy_usb_pm(int susp)
 {
         switch (alchemy_get_cputype()) {
@@ -295,6 +566,9 @@ static void alchemy_usb_pm(int susp)
         case ALCHEMY_CPU_AU1200:
                 au1200_usb_pm(susp);
                 break;
+        case ALCHEMY_CPU_AU1300:
+                au1300_usb_pm(susp);
+                break;
         }
 }
 
@@ -328,6 +602,9 @@ static int __init alchemy_usb_init(void)
         case ALCHEMY_CPU_AU1200:
                 au1200_usb_init();
                 break;
+        case ALCHEMY_CPU_AU1300:
+                au1300_usb_init();
+                break;
         }
 
         register_syscore_ops(&alchemy_usb_pm_ops);
diff --git a/drivers/usb/host/ohci-au1xxx.c b/drivers/usb/host/ohci-au1xxx.c
index 9b66df8278f3..95d1a71dccad 100644
--- a/drivers/usb/host/ohci-au1xxx.c
+++ b/drivers/usb/host/ohci-au1xxx.c
@@ -89,7 +89,7 @@ static const struct hc_driver ohci_au1xxx_hc_driver = {
 
 static int ohci_hcd_au1xxx_drv_probe(struct platform_device *pdev)
 {
-        int ret;
+        int ret, unit;
         struct usb_hcd *hcd;
 
         if (usb_disabled())
@@ -120,7 +120,9 @@ static int ohci_hcd_au1xxx_drv_probe(struct platform_device *pdev)
                 goto err2;
         }
 
-        if (alchemy_usb_control(ALCHEMY_USB_OHCI0, 1)) {
+        unit = (hcd->rsrc_start == AU1300_USB_OHCI1_PHYS_ADDR) ?
+                        ALCHEMY_USB_OHCI1 : ALCHEMY_USB_OHCI0;
+        if (alchemy_usb_control(unit, 1)) {
                 printk(KERN_INFO "%s: controller init failed!\n", pdev->name);
                 ret = -ENODEV;
                 goto err3;
@@ -135,7 +137,7 @@ static int ohci_hcd_au1xxx_drv_probe(struct platform_device *pdev)
                 return ret;
         }
 
-        alchemy_usb_control(ALCHEMY_USB_OHCI0, 0);
+        alchemy_usb_control(unit, 0);
 err3:
         iounmap(hcd->regs);
 err2:
@@ -148,9 +150,12 @@ err1:
 static int ohci_hcd_au1xxx_drv_remove(struct platform_device *pdev)
 {
         struct usb_hcd *hcd = platform_get_drvdata(pdev);
+        int unit;
 
+        unit = (hcd->rsrc_start == AU1300_USB_OHCI1_PHYS_ADDR) ?
+                        ALCHEMY_USB_OHCI1 : ALCHEMY_USB_OHCI0;
         usb_remove_hcd(hcd);
-        alchemy_usb_control(ALCHEMY_USB_OHCI0, 0);
+        alchemy_usb_control(unit, 0);
         iounmap(hcd->regs);
         release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
         usb_put_hcd(hcd);
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index d83e967e4e15..acd4ba555e3a 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -1763,16 +1763,16 @@ config FB_AU1100
           au1100fb:panel=<name>.
 
 config FB_AU1200
-        bool "Au1200 LCD Driver"
+        bool "Au1200/Au1300 LCD Driver"
         depends on (FB = y) && MIPS_ALCHEMY
         select FB_SYS_FILLRECT
         select FB_SYS_COPYAREA
         select FB_SYS_IMAGEBLIT
         select FB_SYS_FOPS
         help
-          This is the framebuffer driver for the AMD Au1200 SOC.  It can drive
-          various panels and CRTs by passing in kernel cmd line option
-          au1200fb:panel=<name>.
+          This is the framebuffer driver for the Au1200/Au1300 SOCs.
+          It can drive various panels and CRTs by passing in kernel cmd line
+          option au1200fb:panel=<name>.
 
 config FB_VT8500
         bool "VT8500 LCD Driver"