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-rw-r--r--drivers/i2c/busses/Kconfig10
-rw-r--r--drivers/i2c/busses/Makefile1
-rw-r--r--drivers/i2c/busses/i2c-at91.c338
-rw-r--r--drivers/i2c/busses/i2c-cbus-gpio.c300
-rw-r--r--drivers/i2c/busses/i2c-gpio.c6
-rw-r--r--drivers/i2c/busses/i2c-mxs.c2
-rw-r--r--drivers/i2c/busses/i2c-nomadik.c14
-rw-r--r--drivers/i2c/busses/i2c-ocores.c164
-rw-r--r--drivers/i2c/busses/i2c-omap.c226
-rw-r--r--drivers/i2c/busses/i2c-rcar.c6
-rw-r--r--drivers/i2c/busses/i2c-s3c2410.c211
-rw-r--r--drivers/i2c/busses/i2c-sh_mobile.c150
-rw-r--r--drivers/i2c/muxes/i2c-mux-gpio.c145
13 files changed, 1236 insertions, 337 deletions
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index c7bff51fe524..bdca5111eb9d 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -337,6 +337,16 @@ config I2C_BLACKFIN_TWI_CLK_KHZ
337 help 337 help
338 The unit of the TWI clock is kHz. 338 The unit of the TWI clock is kHz.
339 339
340config I2C_CBUS_GPIO
341 tristate "CBUS I2C driver"
342 depends on GENERIC_GPIO
343 help
344 Support for CBUS access using I2C API. Mostly relevant for Nokia
345 Internet Tablets (770, N800 and N810).
346
347 This driver can also be built as a module. If so, the module
348 will be called i2c-cbus-gpio.
349
340config I2C_CPM 350config I2C_CPM
341 tristate "Freescale CPM1 or CPM2 (MPC8xx/826x)" 351 tristate "Freescale CPM1 or CPM2 (MPC8xx/826x)"
342 depends on (CPM1 || CPM2) && OF_I2C 352 depends on (CPM1 || CPM2) && OF_I2C
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index e5cb209d276c..6181f3ff263f 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_I2C_POWERMAC) += i2c-powermac.o
31obj-$(CONFIG_I2C_AT91) += i2c-at91.o 31obj-$(CONFIG_I2C_AT91) += i2c-at91.o
32obj-$(CONFIG_I2C_AU1550) += i2c-au1550.o 32obj-$(CONFIG_I2C_AU1550) += i2c-au1550.o
33obj-$(CONFIG_I2C_BLACKFIN_TWI) += i2c-bfin-twi.o 33obj-$(CONFIG_I2C_BLACKFIN_TWI) += i2c-bfin-twi.o
34obj-$(CONFIG_I2C_CBUS_GPIO) += i2c-cbus-gpio.o
34obj-$(CONFIG_I2C_CPM) += i2c-cpm.o 35obj-$(CONFIG_I2C_CPM) += i2c-cpm.o
35obj-$(CONFIG_I2C_DAVINCI) += i2c-davinci.o 36obj-$(CONFIG_I2C_DAVINCI) += i2c-davinci.o
36obj-$(CONFIG_I2C_DESIGNWARE_CORE) += i2c-designware-core.o 37obj-$(CONFIG_I2C_DESIGNWARE_CORE) += i2c-designware-core.o
diff --git a/drivers/i2c/busses/i2c-at91.c b/drivers/i2c/busses/i2c-at91.c
index c02bf208084f..b4575ee4bdf3 100644
--- a/drivers/i2c/busses/i2c-at91.c
+++ b/drivers/i2c/busses/i2c-at91.c
@@ -19,6 +19,8 @@
19 19
20#include <linux/clk.h> 20#include <linux/clk.h>
21#include <linux/completion.h> 21#include <linux/completion.h>
22#include <linux/dma-mapping.h>
23#include <linux/dmaengine.h>
22#include <linux/err.h> 24#include <linux/err.h>
23#include <linux/i2c.h> 25#include <linux/i2c.h>
24#include <linux/interrupt.h> 26#include <linux/interrupt.h>
@@ -29,9 +31,11 @@
29#include <linux/of_i2c.h> 31#include <linux/of_i2c.h>
30#include <linux/platform_device.h> 32#include <linux/platform_device.h>
31#include <linux/slab.h> 33#include <linux/slab.h>
34#include <linux/platform_data/dma-atmel.h>
32 35
33#define TWI_CLK_HZ 100000 /* max 400 Kbits/s */ 36#define TWI_CLK_HZ 100000 /* max 400 Kbits/s */
34#define AT91_I2C_TIMEOUT msecs_to_jiffies(100) /* transfer timeout */ 37#define AT91_I2C_TIMEOUT msecs_to_jiffies(100) /* transfer timeout */
38#define AT91_I2C_DMA_THRESHOLD 8 /* enable DMA if transfer size is bigger than this threshold */
35 39
36/* AT91 TWI register definitions */ 40/* AT91 TWI register definitions */
37#define AT91_TWI_CR 0x0000 /* Control Register */ 41#define AT91_TWI_CR 0x0000 /* Control Register */
@@ -66,24 +70,39 @@
66#define AT91_TWI_THR 0x0034 /* Transmit Holding Register */ 70#define AT91_TWI_THR 0x0034 /* Transmit Holding Register */
67 71
68struct at91_twi_pdata { 72struct at91_twi_pdata {
69 unsigned clk_max_div; 73 unsigned clk_max_div;
70 unsigned clk_offset; 74 unsigned clk_offset;
71 bool has_unre_flag; 75 bool has_unre_flag;
76 bool has_dma_support;
77 struct at_dma_slave dma_slave;
78};
79
80struct at91_twi_dma {
81 struct dma_chan *chan_rx;
82 struct dma_chan *chan_tx;
83 struct scatterlist sg;
84 struct dma_async_tx_descriptor *data_desc;
85 enum dma_data_direction direction;
86 bool buf_mapped;
87 bool xfer_in_progress;
72}; 88};
73 89
74struct at91_twi_dev { 90struct at91_twi_dev {
75 struct device *dev; 91 struct device *dev;
76 void __iomem *base; 92 void __iomem *base;
77 struct completion cmd_complete; 93 struct completion cmd_complete;
78 struct clk *clk; 94 struct clk *clk;
79 u8 *buf; 95 u8 *buf;
80 size_t buf_len; 96 size_t buf_len;
81 struct i2c_msg *msg; 97 struct i2c_msg *msg;
82 int irq; 98 int irq;
83 unsigned transfer_status; 99 unsigned imr;
84 struct i2c_adapter adapter; 100 unsigned transfer_status;
85 unsigned twi_cwgr_reg; 101 struct i2c_adapter adapter;
86 struct at91_twi_pdata *pdata; 102 unsigned twi_cwgr_reg;
103 struct at91_twi_pdata *pdata;
104 bool use_dma;
105 struct at91_twi_dma dma;
87}; 106};
88 107
89static unsigned at91_twi_read(struct at91_twi_dev *dev, unsigned reg) 108static unsigned at91_twi_read(struct at91_twi_dev *dev, unsigned reg)
@@ -102,6 +121,17 @@ static void at91_disable_twi_interrupts(struct at91_twi_dev *dev)
102 AT91_TWI_TXCOMP | AT91_TWI_RXRDY | AT91_TWI_TXRDY); 121 AT91_TWI_TXCOMP | AT91_TWI_RXRDY | AT91_TWI_TXRDY);
103} 122}
104 123
124static void at91_twi_irq_save(struct at91_twi_dev *dev)
125{
126 dev->imr = at91_twi_read(dev, AT91_TWI_IMR) & 0x7;
127 at91_disable_twi_interrupts(dev);
128}
129
130static void at91_twi_irq_restore(struct at91_twi_dev *dev)
131{
132 at91_twi_write(dev, AT91_TWI_IER, dev->imr);
133}
134
105static void at91_init_twi_bus(struct at91_twi_dev *dev) 135static void at91_init_twi_bus(struct at91_twi_dev *dev)
106{ 136{
107 at91_disable_twi_interrupts(dev); 137 at91_disable_twi_interrupts(dev);
@@ -138,6 +168,28 @@ static void __devinit at91_calc_twi_clock(struct at91_twi_dev *dev, int twi_clk)
138 dev_dbg(dev->dev, "cdiv %d ckdiv %d\n", cdiv, ckdiv); 168 dev_dbg(dev->dev, "cdiv %d ckdiv %d\n", cdiv, ckdiv);
139} 169}
140 170
171static void at91_twi_dma_cleanup(struct at91_twi_dev *dev)
172{
173 struct at91_twi_dma *dma = &dev->dma;
174
175 at91_twi_irq_save(dev);
176
177 if (dma->xfer_in_progress) {
178 if (dma->direction == DMA_FROM_DEVICE)
179 dmaengine_terminate_all(dma->chan_rx);
180 else
181 dmaengine_terminate_all(dma->chan_tx);
182 dma->xfer_in_progress = false;
183 }
184 if (dma->buf_mapped) {
185 dma_unmap_single(dev->dev, sg_dma_address(&dma->sg),
186 dev->buf_len, dma->direction);
187 dma->buf_mapped = false;
188 }
189
190 at91_twi_irq_restore(dev);
191}
192
141static void at91_twi_write_next_byte(struct at91_twi_dev *dev) 193static void at91_twi_write_next_byte(struct at91_twi_dev *dev)
142{ 194{
143 if (dev->buf_len <= 0) 195 if (dev->buf_len <= 0)
@@ -154,6 +206,60 @@ static void at91_twi_write_next_byte(struct at91_twi_dev *dev)
154 ++dev->buf; 206 ++dev->buf;
155} 207}
156 208
209static void at91_twi_write_data_dma_callback(void *data)
210{
211 struct at91_twi_dev *dev = (struct at91_twi_dev *)data;
212
213 dma_unmap_single(dev->dev, sg_dma_address(&dev->dma.sg),
214 dev->buf_len, DMA_MEM_TO_DEV);
215
216 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP);
217}
218
219static void at91_twi_write_data_dma(struct at91_twi_dev *dev)
220{
221 dma_addr_t dma_addr;
222 struct dma_async_tx_descriptor *txdesc;
223 struct at91_twi_dma *dma = &dev->dma;
224 struct dma_chan *chan_tx = dma->chan_tx;
225
226 if (dev->buf_len <= 0)
227 return;
228
229 dma->direction = DMA_TO_DEVICE;
230
231 at91_twi_irq_save(dev);
232 dma_addr = dma_map_single(dev->dev, dev->buf, dev->buf_len,
233 DMA_TO_DEVICE);
234 if (dma_mapping_error(dev->dev, dma_addr)) {
235 dev_err(dev->dev, "dma map failed\n");
236 return;
237 }
238 dma->buf_mapped = true;
239 at91_twi_irq_restore(dev);
240 sg_dma_len(&dma->sg) = dev->buf_len;
241 sg_dma_address(&dma->sg) = dma_addr;
242
243 txdesc = dmaengine_prep_slave_sg(chan_tx, &dma->sg, 1, DMA_MEM_TO_DEV,
244 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
245 if (!txdesc) {
246 dev_err(dev->dev, "dma prep slave sg failed\n");
247 goto error;
248 }
249
250 txdesc->callback = at91_twi_write_data_dma_callback;
251 txdesc->callback_param = dev;
252
253 dma->xfer_in_progress = true;
254 dmaengine_submit(txdesc);
255 dma_async_issue_pending(chan_tx);
256
257 return;
258
259error:
260 at91_twi_dma_cleanup(dev);
261}
262
157static void at91_twi_read_next_byte(struct at91_twi_dev *dev) 263static void at91_twi_read_next_byte(struct at91_twi_dev *dev)
158{ 264{
159 if (dev->buf_len <= 0) 265 if (dev->buf_len <= 0)
@@ -179,6 +285,61 @@ static void at91_twi_read_next_byte(struct at91_twi_dev *dev)
179 ++dev->buf; 285 ++dev->buf;
180} 286}
181 287
288static void at91_twi_read_data_dma_callback(void *data)
289{
290 struct at91_twi_dev *dev = (struct at91_twi_dev *)data;
291
292 dma_unmap_single(dev->dev, sg_dma_address(&dev->dma.sg),
293 dev->buf_len, DMA_DEV_TO_MEM);
294
295 /* The last two bytes have to be read without using dma */
296 dev->buf += dev->buf_len - 2;
297 dev->buf_len = 2;
298 at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_RXRDY);
299}
300
301static void at91_twi_read_data_dma(struct at91_twi_dev *dev)
302{
303 dma_addr_t dma_addr;
304 struct dma_async_tx_descriptor *rxdesc;
305 struct at91_twi_dma *dma = &dev->dma;
306 struct dma_chan *chan_rx = dma->chan_rx;
307
308 dma->direction = DMA_FROM_DEVICE;
309
310 /* Keep in mind that we won't use dma to read the last two bytes */
311 at91_twi_irq_save(dev);
312 dma_addr = dma_map_single(dev->dev, dev->buf, dev->buf_len - 2,
313 DMA_FROM_DEVICE);
314 if (dma_mapping_error(dev->dev, dma_addr)) {
315 dev_err(dev->dev, "dma map failed\n");
316 return;
317 }
318 dma->buf_mapped = true;
319 at91_twi_irq_restore(dev);
320 dma->sg.dma_address = dma_addr;
321 sg_dma_len(&dma->sg) = dev->buf_len - 2;
322
323 rxdesc = dmaengine_prep_slave_sg(chan_rx, &dma->sg, 1, DMA_DEV_TO_MEM,
324 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
325 if (!rxdesc) {
326 dev_err(dev->dev, "dma prep slave sg failed\n");
327 goto error;
328 }
329
330 rxdesc->callback = at91_twi_read_data_dma_callback;
331 rxdesc->callback_param = dev;
332
333 dma->xfer_in_progress = true;
334 dmaengine_submit(rxdesc);
335 dma_async_issue_pending(dma->chan_rx);
336
337 return;
338
339error:
340 at91_twi_dma_cleanup(dev);
341}
342
182static irqreturn_t atmel_twi_interrupt(int irq, void *dev_id) 343static irqreturn_t atmel_twi_interrupt(int irq, void *dev_id)
183{ 344{
184 struct at91_twi_dev *dev = dev_id; 345 struct at91_twi_dev *dev = dev_id;
@@ -229,12 +390,36 @@ static int at91_do_twi_transfer(struct at91_twi_dev *dev)
229 if (dev->buf_len <= 1 && !(dev->msg->flags & I2C_M_RECV_LEN)) 390 if (dev->buf_len <= 1 && !(dev->msg->flags & I2C_M_RECV_LEN))
230 start_flags |= AT91_TWI_STOP; 391 start_flags |= AT91_TWI_STOP;
231 at91_twi_write(dev, AT91_TWI_CR, start_flags); 392 at91_twi_write(dev, AT91_TWI_CR, start_flags);
232 at91_twi_write(dev, AT91_TWI_IER, 393 /*
394 * When using dma, the last byte has to be read manually in
395 * order to not send the stop command too late and then
396 * to receive extra data. In practice, there are some issues
397 * if you use the dma to read n-1 bytes because of latency.
398 * Reading n-2 bytes with dma and the two last ones manually
399 * seems to be the best solution.
400 */
401 if (dev->use_dma && (dev->buf_len > AT91_I2C_DMA_THRESHOLD)) {
402 at91_twi_read_data_dma(dev);
403 /*
404 * It is important to enable TXCOMP irq here because
405 * doing it only when transferring the last two bytes
406 * will mask NACK errors since TXCOMP is set when a
407 * NACK occurs.
408 */
409 at91_twi_write(dev, AT91_TWI_IER,
410 AT91_TWI_TXCOMP);
411 } else
412 at91_twi_write(dev, AT91_TWI_IER,
233 AT91_TWI_TXCOMP | AT91_TWI_RXRDY); 413 AT91_TWI_TXCOMP | AT91_TWI_RXRDY);
234 } else { 414 } else {
235 at91_twi_write_next_byte(dev); 415 if (dev->use_dma && (dev->buf_len > AT91_I2C_DMA_THRESHOLD)) {
236 at91_twi_write(dev, AT91_TWI_IER, 416 at91_twi_write_data_dma(dev);
237 AT91_TWI_TXCOMP | AT91_TWI_TXRDY); 417 at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP);
418 } else {
419 at91_twi_write_next_byte(dev);
420 at91_twi_write(dev, AT91_TWI_IER,
421 AT91_TWI_TXCOMP | AT91_TWI_TXRDY);
422 }
238 } 423 }
239 424
240 ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete, 425 ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete,
@@ -242,23 +427,31 @@ static int at91_do_twi_transfer(struct at91_twi_dev *dev)
242 if (ret == 0) { 427 if (ret == 0) {
243 dev_err(dev->dev, "controller timed out\n"); 428 dev_err(dev->dev, "controller timed out\n");
244 at91_init_twi_bus(dev); 429 at91_init_twi_bus(dev);
245 return -ETIMEDOUT; 430 ret = -ETIMEDOUT;
431 goto error;
246 } 432 }
247 if (dev->transfer_status & AT91_TWI_NACK) { 433 if (dev->transfer_status & AT91_TWI_NACK) {
248 dev_dbg(dev->dev, "received nack\n"); 434 dev_dbg(dev->dev, "received nack\n");
249 return -EREMOTEIO; 435 ret = -EREMOTEIO;
436 goto error;
250 } 437 }
251 if (dev->transfer_status & AT91_TWI_OVRE) { 438 if (dev->transfer_status & AT91_TWI_OVRE) {
252 dev_err(dev->dev, "overrun while reading\n"); 439 dev_err(dev->dev, "overrun while reading\n");
253 return -EIO; 440 ret = -EIO;
441 goto error;
254 } 442 }
255 if (has_unre_flag && dev->transfer_status & AT91_TWI_UNRE) { 443 if (has_unre_flag && dev->transfer_status & AT91_TWI_UNRE) {
256 dev_err(dev->dev, "underrun while writing\n"); 444 dev_err(dev->dev, "underrun while writing\n");
257 return -EIO; 445 ret = -EIO;
446 goto error;
258 } 447 }
259 dev_dbg(dev->dev, "transfer complete\n"); 448 dev_dbg(dev->dev, "transfer complete\n");
260 449
261 return 0; 450 return 0;
451
452error:
453 at91_twi_dma_cleanup(dev);
454 return ret;
262} 455}
263 456
264static int at91_twi_xfer(struct i2c_adapter *adap, struct i2c_msg *msg, int num) 457static int at91_twi_xfer(struct i2c_adapter *adap, struct i2c_msg *msg, int num)
@@ -329,36 +522,42 @@ static struct at91_twi_pdata at91rm9200_config = {
329 .clk_max_div = 5, 522 .clk_max_div = 5,
330 .clk_offset = 3, 523 .clk_offset = 3,
331 .has_unre_flag = true, 524 .has_unre_flag = true,
525 .has_dma_support = false,
332}; 526};
333 527
334static struct at91_twi_pdata at91sam9261_config = { 528static struct at91_twi_pdata at91sam9261_config = {
335 .clk_max_div = 5, 529 .clk_max_div = 5,
336 .clk_offset = 4, 530 .clk_offset = 4,
337 .has_unre_flag = false, 531 .has_unre_flag = false,
532 .has_dma_support = false,
338}; 533};
339 534
340static struct at91_twi_pdata at91sam9260_config = { 535static struct at91_twi_pdata at91sam9260_config = {
341 .clk_max_div = 7, 536 .clk_max_div = 7,
342 .clk_offset = 4, 537 .clk_offset = 4,
343 .has_unre_flag = false, 538 .has_unre_flag = false,
539 .has_dma_support = false,
344}; 540};
345 541
346static struct at91_twi_pdata at91sam9g20_config = { 542static struct at91_twi_pdata at91sam9g20_config = {
347 .clk_max_div = 7, 543 .clk_max_div = 7,
348 .clk_offset = 4, 544 .clk_offset = 4,
349 .has_unre_flag = false, 545 .has_unre_flag = false,
546 .has_dma_support = false,
350}; 547};
351 548
352static struct at91_twi_pdata at91sam9g10_config = { 549static struct at91_twi_pdata at91sam9g10_config = {
353 .clk_max_div = 7, 550 .clk_max_div = 7,
354 .clk_offset = 4, 551 .clk_offset = 4,
355 .has_unre_flag = false, 552 .has_unre_flag = false,
553 .has_dma_support = false,
356}; 554};
357 555
358static struct at91_twi_pdata at91sam9x5_config = { 556static struct at91_twi_pdata at91sam9x5_config = {
359 .clk_max_div = 7, 557 .clk_max_div = 7,
360 .clk_offset = 4, 558 .clk_offset = 4,
361 .has_unre_flag = false, 559 .has_unre_flag = false,
560 .has_dma_support = true,
362}; 561};
363 562
364static const struct platform_device_id at91_twi_devtypes[] = { 563static const struct platform_device_id at91_twi_devtypes[] = {
@@ -405,6 +604,90 @@ MODULE_DEVICE_TABLE(of, atmel_twi_dt_ids);
405#define atmel_twi_dt_ids NULL 604#define atmel_twi_dt_ids NULL
406#endif 605#endif
407 606
607static bool __devinit filter(struct dma_chan *chan, void *slave)
608{
609 struct at_dma_slave *sl = slave;
610
611 if (sl->dma_dev == chan->device->dev) {
612 chan->private = sl;
613 return true;
614 } else {
615 return false;
616 }
617}
618
619static int __devinit at91_twi_configure_dma(struct at91_twi_dev *dev, u32 phy_addr)
620{
621 int ret = 0;
622 struct at_dma_slave *sdata;
623 struct dma_slave_config slave_config;
624 struct at91_twi_dma *dma = &dev->dma;
625
626 sdata = &dev->pdata->dma_slave;
627
628 memset(&slave_config, 0, sizeof(slave_config));
629 slave_config.src_addr = (dma_addr_t)phy_addr + AT91_TWI_RHR;
630 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
631 slave_config.src_maxburst = 1;
632 slave_config.dst_addr = (dma_addr_t)phy_addr + AT91_TWI_THR;
633 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
634 slave_config.dst_maxburst = 1;
635 slave_config.device_fc = false;
636
637 if (sdata && sdata->dma_dev) {
638 dma_cap_mask_t mask;
639
640 dma_cap_zero(mask);
641 dma_cap_set(DMA_SLAVE, mask);
642 dma->chan_tx = dma_request_channel(mask, filter, sdata);
643 if (!dma->chan_tx) {
644 dev_err(dev->dev, "no DMA channel available for tx\n");
645 ret = -EBUSY;
646 goto error;
647 }
648 dma->chan_rx = dma_request_channel(mask, filter, sdata);
649 if (!dma->chan_rx) {
650 dev_err(dev->dev, "no DMA channel available for rx\n");
651 ret = -EBUSY;
652 goto error;
653 }
654 } else {
655 ret = -EINVAL;
656 goto error;
657 }
658
659 slave_config.direction = DMA_MEM_TO_DEV;
660 if (dmaengine_slave_config(dma->chan_tx, &slave_config)) {
661 dev_err(dev->dev, "failed to configure tx channel\n");
662 ret = -EINVAL;
663 goto error;
664 }
665
666 slave_config.direction = DMA_DEV_TO_MEM;
667 if (dmaengine_slave_config(dma->chan_rx, &slave_config)) {
668 dev_err(dev->dev, "failed to configure rx channel\n");
669 ret = -EINVAL;
670 goto error;
671 }
672
673 sg_init_table(&dma->sg, 1);
674 dma->buf_mapped = false;
675 dma->xfer_in_progress = false;
676
677 dev_info(dev->dev, "using %s (tx) and %s (rx) for DMA transfers\n",
678 dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx));
679
680 return ret;
681
682error:
683 dev_info(dev->dev, "can't use DMA\n");
684 if (dma->chan_rx)
685 dma_release_channel(dma->chan_rx);
686 if (dma->chan_tx)
687 dma_release_channel(dma->chan_tx);
688 return ret;
689}
690
408static struct at91_twi_pdata * __devinit at91_twi_get_driver_data( 691static struct at91_twi_pdata * __devinit at91_twi_get_driver_data(
409 struct platform_device *pdev) 692 struct platform_device *pdev)
410{ 693{
@@ -413,7 +696,7 @@ static struct at91_twi_pdata * __devinit at91_twi_get_driver_data(
413 match = of_match_node(atmel_twi_dt_ids, pdev->dev.of_node); 696 match = of_match_node(atmel_twi_dt_ids, pdev->dev.of_node);
414 if (!match) 697 if (!match)
415 return NULL; 698 return NULL;
416 return match->data; 699 return (struct at91_twi_pdata *)match->data;
417 } 700 }
418 return (struct at91_twi_pdata *) platform_get_device_id(pdev)->driver_data; 701 return (struct at91_twi_pdata *) platform_get_device_id(pdev)->driver_data;
419} 702}
@@ -423,6 +706,7 @@ static int __devinit at91_twi_probe(struct platform_device *pdev)
423 struct at91_twi_dev *dev; 706 struct at91_twi_dev *dev;
424 struct resource *mem; 707 struct resource *mem;
425 int rc; 708 int rc;
709 u32 phy_addr;
426 710
427 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); 711 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
428 if (!dev) 712 if (!dev)
@@ -433,6 +717,7 @@ static int __devinit at91_twi_probe(struct platform_device *pdev)
433 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 717 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
434 if (!mem) 718 if (!mem)
435 return -ENODEV; 719 return -ENODEV;
720 phy_addr = mem->start;
436 721
437 dev->pdata = at91_twi_get_driver_data(pdev); 722 dev->pdata = at91_twi_get_driver_data(pdev);
438 if (!dev->pdata) 723 if (!dev->pdata)
@@ -462,6 +747,11 @@ static int __devinit at91_twi_probe(struct platform_device *pdev)
462 } 747 }
463 clk_prepare_enable(dev->clk); 748 clk_prepare_enable(dev->clk);
464 749
750 if (dev->pdata->has_dma_support) {
751 if (at91_twi_configure_dma(dev, phy_addr) == 0)
752 dev->use_dma = true;
753 }
754
465 at91_calc_twi_clock(dev, TWI_CLK_HZ); 755 at91_calc_twi_clock(dev, TWI_CLK_HZ);
466 at91_init_twi_bus(dev); 756 at91_init_twi_bus(dev);
467 757
diff --git a/drivers/i2c/busses/i2c-cbus-gpio.c b/drivers/i2c/busses/i2c-cbus-gpio.c
new file mode 100644
index 000000000000..98386d659318
--- /dev/null
+++ b/drivers/i2c/busses/i2c-cbus-gpio.c
@@ -0,0 +1,300 @@
1/*
2 * CBUS I2C driver for Nokia Internet Tablets.
3 *
4 * Copyright (C) 2004-2010 Nokia Corporation
5 *
6 * Based on code written by Juha Yrjölä, David Weinehall, Mikko Ylinen and
7 * Felipe Balbi. Converted to I2C driver by Aaro Koskinen.
8 *
9 * This file is subject to the terms and conditions of the GNU General
10 * Public License. See the file "COPYING" in the main directory of this
11 * archive for more details.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/io.h>
20#include <linux/i2c.h>
21#include <linux/gpio.h>
22#include <linux/init.h>
23#include <linux/slab.h>
24#include <linux/delay.h>
25#include <linux/errno.h>
26#include <linux/kernel.h>
27#include <linux/module.h>
28#include <linux/of_gpio.h>
29#include <linux/interrupt.h>
30#include <linux/platform_device.h>
31#include <linux/platform_data/i2c-cbus-gpio.h>
32
33/*
34 * Bit counts are derived from Nokia implementation. These should be checked
35 * if other CBUS implementations appear.
36 */
37#define CBUS_ADDR_BITS 3
38#define CBUS_REG_BITS 5
39
40struct cbus_host {
41 spinlock_t lock; /* host lock */
42 struct device *dev;
43 int clk_gpio;
44 int dat_gpio;
45 int sel_gpio;
46};
47
48/**
49 * cbus_send_bit - sends one bit over the bus
50 * @host: the host we're using
51 * @bit: one bit of information to send
52 */
53static void cbus_send_bit(struct cbus_host *host, unsigned bit)
54{
55 gpio_set_value(host->dat_gpio, bit ? 1 : 0);
56 gpio_set_value(host->clk_gpio, 1);
57 gpio_set_value(host->clk_gpio, 0);
58}
59
60/**
61 * cbus_send_data - sends @len amount of data over the bus
62 * @host: the host we're using
63 * @data: the data to send
64 * @len: size of the transfer
65 */
66static void cbus_send_data(struct cbus_host *host, unsigned data, unsigned len)
67{
68 int i;
69
70 for (i = len; i > 0; i--)
71 cbus_send_bit(host, data & (1 << (i - 1)));
72}
73
74/**
75 * cbus_receive_bit - receives one bit from the bus
76 * @host: the host we're using
77 */
78static int cbus_receive_bit(struct cbus_host *host)
79{
80 int ret;
81
82 gpio_set_value(host->clk_gpio, 1);
83 ret = gpio_get_value(host->dat_gpio);
84 gpio_set_value(host->clk_gpio, 0);
85 return ret;
86}
87
88/**
89 * cbus_receive_word - receives 16-bit word from the bus
90 * @host: the host we're using
91 */
92static int cbus_receive_word(struct cbus_host *host)
93{
94 int ret = 0;
95 int i;
96
97 for (i = 16; i > 0; i--) {
98 int bit = cbus_receive_bit(host);
99
100 if (bit < 0)
101 return bit;
102
103 if (bit)
104 ret |= 1 << (i - 1);
105 }
106 return ret;
107}
108
109/**
110 * cbus_transfer - transfers data over the bus
111 * @host: the host we're using
112 * @rw: read/write flag
113 * @dev: device address
114 * @reg: register address
115 * @data: if @rw == I2C_SBUS_WRITE data to send otherwise 0
116 */
117static int cbus_transfer(struct cbus_host *host, char rw, unsigned dev,
118 unsigned reg, unsigned data)
119{
120 unsigned long flags;
121 int ret;
122
123 /* We don't want interrupts disturbing our transfer */
124 spin_lock_irqsave(&host->lock, flags);
125
126 /* Reset state and start of transfer, SEL stays down during transfer */
127 gpio_set_value(host->sel_gpio, 0);
128
129 /* Set the DAT pin to output */
130 gpio_direction_output(host->dat_gpio, 1);
131
132 /* Send the device address */
133 cbus_send_data(host, dev, CBUS_ADDR_BITS);
134
135 /* Send the rw flag */
136 cbus_send_bit(host, rw == I2C_SMBUS_READ);
137
138 /* Send the register address */
139 cbus_send_data(host, reg, CBUS_REG_BITS);
140
141 if (rw == I2C_SMBUS_WRITE) {
142 cbus_send_data(host, data, 16);
143 ret = 0;
144 } else {
145 ret = gpio_direction_input(host->dat_gpio);
146 if (ret) {
147 dev_dbg(host->dev, "failed setting direction\n");
148 goto out;
149 }
150 gpio_set_value(host->clk_gpio, 1);
151
152 ret = cbus_receive_word(host);
153 if (ret < 0) {
154 dev_dbg(host->dev, "failed receiving data\n");
155 goto out;
156 }
157 }
158
159 /* Indicate end of transfer, SEL goes up until next transfer */
160 gpio_set_value(host->sel_gpio, 1);
161 gpio_set_value(host->clk_gpio, 1);
162 gpio_set_value(host->clk_gpio, 0);
163
164out:
165 spin_unlock_irqrestore(&host->lock, flags);
166
167 return ret;
168}
169
170static int cbus_i2c_smbus_xfer(struct i2c_adapter *adapter,
171 u16 addr,
172 unsigned short flags,
173 char read_write,
174 u8 command,
175 int size,
176 union i2c_smbus_data *data)
177{
178 struct cbus_host *chost = i2c_get_adapdata(adapter);
179 int ret;
180
181 if (size != I2C_SMBUS_WORD_DATA)
182 return -EINVAL;
183
184 ret = cbus_transfer(chost, read_write == I2C_SMBUS_READ, addr,
185 command, data->word);
186 if (ret < 0)
187 return ret;
188
189 if (read_write == I2C_SMBUS_READ)
190 data->word = ret;
191
192 return 0;
193}
194
195static u32 cbus_i2c_func(struct i2c_adapter *adapter)
196{
197 return I2C_FUNC_SMBUS_READ_WORD_DATA | I2C_FUNC_SMBUS_WRITE_WORD_DATA;
198}
199
200static const struct i2c_algorithm cbus_i2c_algo = {
201 .smbus_xfer = cbus_i2c_smbus_xfer,
202 .functionality = cbus_i2c_func,
203};
204
205static int cbus_i2c_remove(struct platform_device *pdev)
206{
207 struct i2c_adapter *adapter = platform_get_drvdata(pdev);
208
209 return i2c_del_adapter(adapter);
210}
211
212static int cbus_i2c_probe(struct platform_device *pdev)
213{
214 struct i2c_adapter *adapter;
215 struct cbus_host *chost;
216 int ret;
217
218 adapter = devm_kzalloc(&pdev->dev, sizeof(struct i2c_adapter),
219 GFP_KERNEL);
220 if (!adapter)
221 return -ENOMEM;
222
223 chost = devm_kzalloc(&pdev->dev, sizeof(*chost), GFP_KERNEL);
224 if (!chost)
225 return -ENOMEM;
226
227 if (pdev->dev.of_node) {
228 struct device_node *dnode = pdev->dev.of_node;
229 if (of_gpio_count(dnode) != 3)
230 return -ENODEV;
231 chost->clk_gpio = of_get_gpio(dnode, 0);
232 chost->dat_gpio = of_get_gpio(dnode, 1);
233 chost->sel_gpio = of_get_gpio(dnode, 2);
234 } else if (pdev->dev.platform_data) {
235 struct i2c_cbus_platform_data *pdata = pdev->dev.platform_data;
236 chost->clk_gpio = pdata->clk_gpio;
237 chost->dat_gpio = pdata->dat_gpio;
238 chost->sel_gpio = pdata->sel_gpio;
239 } else {
240 return -ENODEV;
241 }
242
243 adapter->owner = THIS_MODULE;
244 adapter->class = I2C_CLASS_HWMON;
245 adapter->dev.parent = &pdev->dev;
246 adapter->nr = pdev->id;
247 adapter->timeout = HZ;
248 adapter->algo = &cbus_i2c_algo;
249 strlcpy(adapter->name, "CBUS I2C adapter", sizeof(adapter->name));
250
251 spin_lock_init(&chost->lock);
252 chost->dev = &pdev->dev;
253
254 ret = devm_gpio_request_one(&pdev->dev, chost->clk_gpio,
255 GPIOF_OUT_INIT_LOW, "CBUS clk");
256 if (ret)
257 return ret;
258
259 ret = devm_gpio_request_one(&pdev->dev, chost->dat_gpio, GPIOF_IN,
260 "CBUS data");
261 if (ret)
262 return ret;
263
264 ret = devm_gpio_request_one(&pdev->dev, chost->sel_gpio,
265 GPIOF_OUT_INIT_HIGH, "CBUS sel");
266 if (ret)
267 return ret;
268
269 i2c_set_adapdata(adapter, chost);
270 platform_set_drvdata(pdev, adapter);
271
272 return i2c_add_numbered_adapter(adapter);
273}
274
275#if defined(CONFIG_OF)
276static const struct of_device_id i2c_cbus_dt_ids[] = {
277 { .compatible = "i2c-cbus-gpio", },
278 { }
279};
280MODULE_DEVICE_TABLE(of, i2c_cbus_dt_ids);
281#endif
282
283static struct platform_driver cbus_i2c_driver = {
284 .probe = cbus_i2c_probe,
285 .remove = cbus_i2c_remove,
286 .driver = {
287 .owner = THIS_MODULE,
288 .name = "i2c-cbus-gpio",
289 },
290};
291module_platform_driver(cbus_i2c_driver);
292
293MODULE_ALIAS("platform:i2c-cbus-gpio");
294MODULE_DESCRIPTION("CBUS I2C driver");
295MODULE_AUTHOR("Juha Yrjölä");
296MODULE_AUTHOR("David Weinehall");
297MODULE_AUTHOR("Mikko Ylinen");
298MODULE_AUTHOR("Felipe Balbi");
299MODULE_AUTHOR("Aaro Koskinen <aaro.koskinen@iki.fi>");
300MODULE_LICENSE("GPL");
diff --git a/drivers/i2c/busses/i2c-gpio.c b/drivers/i2c/busses/i2c-gpio.c
index e62d2d938628..257299a92df3 100644
--- a/drivers/i2c/busses/i2c-gpio.c
+++ b/drivers/i2c/busses/i2c-gpio.c
@@ -184,7 +184,11 @@ static int __devinit i2c_gpio_probe(struct platform_device *pdev)
184 bit_data->data = pdata; 184 bit_data->data = pdata;
185 185
186 adap->owner = THIS_MODULE; 186 adap->owner = THIS_MODULE;
187 snprintf(adap->name, sizeof(adap->name), "i2c-gpio%d", pdev->id); 187 if (pdev->dev.of_node)
188 strlcpy(adap->name, dev_name(&pdev->dev), sizeof(adap->name));
189 else
190 snprintf(adap->name, sizeof(adap->name), "i2c-gpio%d", pdev->id);
191
188 adap->algo_data = bit_data; 192 adap->algo_data = bit_data;
189 adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 193 adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
190 adap->dev.parent = &pdev->dev; 194 adap->dev.parent = &pdev->dev;
diff --git a/drivers/i2c/busses/i2c-mxs.c b/drivers/i2c/busses/i2c-mxs.c
index 0670da79ee5e..6ed53da9e1f4 100644
--- a/drivers/i2c/busses/i2c-mxs.c
+++ b/drivers/i2c/busses/i2c-mxs.c
@@ -359,7 +359,7 @@ static int mxs_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
359 359
360static u32 mxs_i2c_func(struct i2c_adapter *adap) 360static u32 mxs_i2c_func(struct i2c_adapter *adap)
361{ 361{
362 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); 362 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
363} 363}
364 364
365static irqreturn_t mxs_i2c_isr(int this_irq, void *dev_id) 365static irqreturn_t mxs_i2c_isr(int this_irq, void *dev_id)
diff --git a/drivers/i2c/busses/i2c-nomadik.c b/drivers/i2c/busses/i2c-nomadik.c
index 02c3115a2dfa..8b2ffcf45322 100644
--- a/drivers/i2c/busses/i2c-nomadik.c
+++ b/drivers/i2c/busses/i2c-nomadik.c
@@ -435,13 +435,6 @@ static int read_i2c(struct nmk_i2c_dev *dev, u16 flags)
435 timeout = wait_for_completion_timeout( 435 timeout = wait_for_completion_timeout(
436 &dev->xfer_complete, dev->adap.timeout); 436 &dev->xfer_complete, dev->adap.timeout);
437 437
438 if (timeout < 0) {
439 dev_err(&dev->adev->dev,
440 "wait_for_completion_timeout "
441 "returned %d waiting for event\n", timeout);
442 status = timeout;
443 }
444
445 if (timeout == 0) { 438 if (timeout == 0) {
446 /* Controller timed out */ 439 /* Controller timed out */
447 dev_err(&dev->adev->dev, "read from slave 0x%x timed out\n", 440 dev_err(&dev->adev->dev, "read from slave 0x%x timed out\n",
@@ -523,13 +516,6 @@ static int write_i2c(struct nmk_i2c_dev *dev, u16 flags)
523 timeout = wait_for_completion_timeout( 516 timeout = wait_for_completion_timeout(
524 &dev->xfer_complete, dev->adap.timeout); 517 &dev->xfer_complete, dev->adap.timeout);
525 518
526 if (timeout < 0) {
527 dev_err(&dev->adev->dev,
528 "wait_for_completion_timeout "
529 "returned %d waiting for event\n", timeout);
530 status = timeout;
531 }
532
533 if (timeout == 0) { 519 if (timeout == 0) {
534 /* Controller timed out */ 520 /* Controller timed out */
535 dev_err(&dev->adev->dev, "write to slave 0x%x timed out\n", 521 dev_err(&dev->adev->dev, "write to slave 0x%x timed out\n",
diff --git a/drivers/i2c/busses/i2c-ocores.c b/drivers/i2c/busses/i2c-ocores.c
index 15da1ac7cf9e..9b35c9fbb2fe 100644
--- a/drivers/i2c/busses/i2c-ocores.c
+++ b/drivers/i2c/busses/i2c-ocores.c
@@ -4,6 +4,9 @@
4 * 4 *
5 * Peter Korsgaard <jacmet@sunsite.dk> 5 * Peter Korsgaard <jacmet@sunsite.dk>
6 * 6 *
7 * Support for the GRLIB port of the controller by
8 * Andreas Larsson <andreas@gaisler.com>
9 *
7 * This file is licensed under the terms of the GNU General Public License 10 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any 11 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied. 12 * kind, whether express or implied.
@@ -34,6 +37,8 @@ struct ocores_i2c {
34 int nmsgs; 37 int nmsgs;
35 int state; /* see STATE_ */ 38 int state; /* see STATE_ */
36 int clock_khz; 39 int clock_khz;
40 void (*setreg)(struct ocores_i2c *i2c, int reg, u8 value);
41 u8 (*getreg)(struct ocores_i2c *i2c, int reg);
37}; 42};
38 43
39/* registers */ 44/* registers */
@@ -67,24 +72,47 @@ struct ocores_i2c {
67#define STATE_READ 3 72#define STATE_READ 3
68#define STATE_ERROR 4 73#define STATE_ERROR 4
69 74
75#define TYPE_OCORES 0
76#define TYPE_GRLIB 1
77
78static void oc_setreg_8(struct ocores_i2c *i2c, int reg, u8 value)
79{
80 iowrite8(value, i2c->base + (reg << i2c->reg_shift));
81}
82
83static void oc_setreg_16(struct ocores_i2c *i2c, int reg, u8 value)
84{
85 iowrite16(value, i2c->base + (reg << i2c->reg_shift));
86}
87
88static void oc_setreg_32(struct ocores_i2c *i2c, int reg, u8 value)
89{
90 iowrite32(value, i2c->base + (reg << i2c->reg_shift));
91}
92
93static inline u8 oc_getreg_8(struct ocores_i2c *i2c, int reg)
94{
95 return ioread8(i2c->base + (reg << i2c->reg_shift));
96}
97
98static inline u8 oc_getreg_16(struct ocores_i2c *i2c, int reg)
99{
100 return ioread16(i2c->base + (reg << i2c->reg_shift));
101}
102
103static inline u8 oc_getreg_32(struct ocores_i2c *i2c, int reg)
104{
105 return ioread32(i2c->base + (reg << i2c->reg_shift));
106}
107
70static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value) 108static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value)
71{ 109{
72 if (i2c->reg_io_width == 4) 110 i2c->setreg(i2c, reg, value);
73 iowrite32(value, i2c->base + (reg << i2c->reg_shift));
74 else if (i2c->reg_io_width == 2)
75 iowrite16(value, i2c->base + (reg << i2c->reg_shift));
76 else
77 iowrite8(value, i2c->base + (reg << i2c->reg_shift));
78} 111}
79 112
80static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg) 113static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg)
81{ 114{
82 if (i2c->reg_io_width == 4) 115 return i2c->getreg(i2c, reg);
83 return ioread32(i2c->base + (reg << i2c->reg_shift));
84 else if (i2c->reg_io_width == 2)
85 return ioread16(i2c->base + (reg << i2c->reg_shift));
86 else
87 return ioread8(i2c->base + (reg << i2c->reg_shift));
88} 116}
89 117
90static void ocores_process(struct ocores_i2c *i2c) 118static void ocores_process(struct ocores_i2c *i2c)
@@ -223,11 +251,59 @@ static struct i2c_adapter ocores_adapter = {
223 .algo = &ocores_algorithm, 251 .algo = &ocores_algorithm,
224}; 252};
225 253
254static struct of_device_id ocores_i2c_match[] = {
255 {
256 .compatible = "opencores,i2c-ocores",
257 .data = (void *)TYPE_OCORES,
258 },
259 {
260 .compatible = "aeroflexgaisler,i2cmst",
261 .data = (void *)TYPE_GRLIB,
262 },
263 {},
264};
265MODULE_DEVICE_TABLE(of, ocores_i2c_match);
266
226#ifdef CONFIG_OF 267#ifdef CONFIG_OF
268/* Read and write functions for the GRLIB port of the controller. Registers are
269 * 32-bit big endian and the PRELOW and PREHIGH registers are merged into one
270 * register. The subsequent registers has their offset decreased accordingly. */
271static u8 oc_getreg_grlib(struct ocores_i2c *i2c, int reg)
272{
273 u32 rd;
274 int rreg = reg;
275 if (reg != OCI2C_PRELOW)
276 rreg--;
277 rd = ioread32be(i2c->base + (rreg << i2c->reg_shift));
278 if (reg == OCI2C_PREHIGH)
279 return (u8)(rd >> 8);
280 else
281 return (u8)rd;
282}
283
284static void oc_setreg_grlib(struct ocores_i2c *i2c, int reg, u8 value)
285{
286 u32 curr, wr;
287 int rreg = reg;
288 if (reg != OCI2C_PRELOW)
289 rreg--;
290 if (reg == OCI2C_PRELOW || reg == OCI2C_PREHIGH) {
291 curr = ioread32be(i2c->base + (rreg << i2c->reg_shift));
292 if (reg == OCI2C_PRELOW)
293 wr = (curr & 0xff00) | value;
294 else
295 wr = (((u32)value) << 8) | (curr & 0xff);
296 } else {
297 wr = value;
298 }
299 iowrite32be(wr, i2c->base + (rreg << i2c->reg_shift));
300}
301
227static int ocores_i2c_of_probe(struct platform_device *pdev, 302static int ocores_i2c_of_probe(struct platform_device *pdev,
228 struct ocores_i2c *i2c) 303 struct ocores_i2c *i2c)
229{ 304{
230 struct device_node *np = pdev->dev.of_node; 305 struct device_node *np = pdev->dev.of_node;
306 const struct of_device_id *match;
231 u32 val; 307 u32 val;
232 308
233 if (of_property_read_u32(np, "reg-shift", &i2c->reg_shift)) { 309 if (of_property_read_u32(np, "reg-shift", &i2c->reg_shift)) {
@@ -253,6 +329,14 @@ static int ocores_i2c_of_probe(struct platform_device *pdev,
253 329
254 of_property_read_u32(pdev->dev.of_node, "reg-io-width", 330 of_property_read_u32(pdev->dev.of_node, "reg-io-width",
255 &i2c->reg_io_width); 331 &i2c->reg_io_width);
332
333 match = of_match_node(ocores_i2c_match, pdev->dev.of_node);
334 if (match && (int)match->data == TYPE_GRLIB) {
335 dev_dbg(&pdev->dev, "GRLIB variant of i2c-ocores\n");
336 i2c->setreg = oc_setreg_grlib;
337 i2c->getreg = oc_getreg_grlib;
338 }
339
256 return 0; 340 return 0;
257} 341}
258#else 342#else
@@ -263,7 +347,8 @@ static int __devinit ocores_i2c_probe(struct platform_device *pdev)
263{ 347{
264 struct ocores_i2c *i2c; 348 struct ocores_i2c *i2c;
265 struct ocores_i2c_platform_data *pdata; 349 struct ocores_i2c_platform_data *pdata;
266 struct resource *res, *res2; 350 struct resource *res;
351 int irq;
267 int ret; 352 int ret;
268 int i; 353 int i;
269 354
@@ -271,26 +356,17 @@ static int __devinit ocores_i2c_probe(struct platform_device *pdev)
271 if (!res) 356 if (!res)
272 return -ENODEV; 357 return -ENODEV;
273 358
274 res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 359 irq = platform_get_irq(pdev, 0);
275 if (!res2) 360 if (irq < 0)
276 return -ENODEV; 361 return irq;
277 362
278 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); 363 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
279 if (!i2c) 364 if (!i2c)
280 return -ENOMEM; 365 return -ENOMEM;
281 366
282 if (!devm_request_mem_region(&pdev->dev, res->start, 367 i2c->base = devm_request_and_ioremap(&pdev->dev, res);
283 resource_size(res), pdev->name)) { 368 if (!i2c->base)
284 dev_err(&pdev->dev, "Memory region busy\n"); 369 return -EADDRNOTAVAIL;
285 return -EBUSY;
286 }
287
288 i2c->base = devm_ioremap_nocache(&pdev->dev, res->start,
289 resource_size(res));
290 if (!i2c->base) {
291 dev_err(&pdev->dev, "Unable to map registers\n");
292 return -EIO;
293 }
294 370
295 pdata = pdev->dev.platform_data; 371 pdata = pdev->dev.platform_data;
296 if (pdata) { 372 if (pdata) {
@@ -306,10 +382,34 @@ static int __devinit ocores_i2c_probe(struct platform_device *pdev)
306 if (i2c->reg_io_width == 0) 382 if (i2c->reg_io_width == 0)
307 i2c->reg_io_width = 1; /* Set to default value */ 383 i2c->reg_io_width = 1; /* Set to default value */
308 384
385 if (!i2c->setreg || !i2c->getreg) {
386 switch (i2c->reg_io_width) {
387 case 1:
388 i2c->setreg = oc_setreg_8;
389 i2c->getreg = oc_getreg_8;
390 break;
391
392 case 2:
393 i2c->setreg = oc_setreg_16;
394 i2c->getreg = oc_getreg_16;
395 break;
396
397 case 4:
398 i2c->setreg = oc_setreg_32;
399 i2c->getreg = oc_getreg_32;
400 break;
401
402 default:
403 dev_err(&pdev->dev, "Unsupported I/O width (%d)\n",
404 i2c->reg_io_width);
405 return -EINVAL;
406 }
407 }
408
309 ocores_init(i2c); 409 ocores_init(i2c);
310 410
311 init_waitqueue_head(&i2c->wait); 411 init_waitqueue_head(&i2c->wait);
312 ret = devm_request_irq(&pdev->dev, res2->start, ocores_isr, 0, 412 ret = devm_request_irq(&pdev->dev, irq, ocores_isr, 0,
313 pdev->name, i2c); 413 pdev->name, i2c);
314 if (ret) { 414 if (ret) {
315 dev_err(&pdev->dev, "Cannot claim IRQ\n"); 415 dev_err(&pdev->dev, "Cannot claim IRQ\n");
@@ -383,12 +483,6 @@ static SIMPLE_DEV_PM_OPS(ocores_i2c_pm, ocores_i2c_suspend, ocores_i2c_resume);
383#define OCORES_I2C_PM NULL 483#define OCORES_I2C_PM NULL
384#endif 484#endif
385 485
386static struct of_device_id ocores_i2c_match[] = {
387 { .compatible = "opencores,i2c-ocores", },
388 {},
389};
390MODULE_DEVICE_TABLE(of, ocores_i2c_match);
391
392static struct platform_driver ocores_i2c_driver = { 486static struct platform_driver ocores_i2c_driver = {
393 .probe = ocores_i2c_probe, 487 .probe = ocores_i2c_probe,
394 .remove = __devexit_p(ocores_i2c_remove), 488 .remove = __devexit_p(ocores_i2c_remove),
diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c
index 3525c9e62cb0..7a62acb7d262 100644
--- a/drivers/i2c/busses/i2c-omap.c
+++ b/drivers/i2c/busses/i2c-omap.c
@@ -43,14 +43,16 @@
43#include <linux/slab.h> 43#include <linux/slab.h>
44#include <linux/i2c-omap.h> 44#include <linux/i2c-omap.h>
45#include <linux/pm_runtime.h> 45#include <linux/pm_runtime.h>
46#include <linux/pinctrl/consumer.h>
46 47
47/* I2C controller revisions */ 48/* I2C controller revisions */
48#define OMAP_I2C_OMAP1_REV_2 0x20 49#define OMAP_I2C_OMAP1_REV_2 0x20
49 50
50/* I2C controller revisions present on specific hardware */ 51/* I2C controller revisions present on specific hardware */
51#define OMAP_I2C_REV_ON_2430 0x36 52#define OMAP_I2C_REV_ON_2430 0x00000036
52#define OMAP_I2C_REV_ON_3430_3530 0x3C 53#define OMAP_I2C_REV_ON_3430_3530 0x0000003C
53#define OMAP_I2C_REV_ON_3630_4430 0x40 54#define OMAP_I2C_REV_ON_3630 0x00000040
55#define OMAP_I2C_REV_ON_4430_PLUS 0x50400002
54 56
55/* timeout waiting for the controller to respond */ 57/* timeout waiting for the controller to respond */
56#define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000)) 58#define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
@@ -190,7 +192,6 @@ struct omap_i2c_dev {
190 void (*set_mpu_wkup_lat)(struct device *dev, 192 void (*set_mpu_wkup_lat)(struct device *dev,
191 long latency); 193 long latency);
192 u32 speed; /* Speed of bus in kHz */ 194 u32 speed; /* Speed of bus in kHz */
193 u32 dtrev; /* extra revision from DT */
194 u32 flags; 195 u32 flags;
195 u16 cmd_err; 196 u16 cmd_err;
196 u8 *buf; 197 u8 *buf;
@@ -202,17 +203,18 @@ struct omap_i2c_dev {
202 * fifo_size==0 implies no fifo 203 * fifo_size==0 implies no fifo
203 * if set, should be trsh+1 204 * if set, should be trsh+1
204 */ 205 */
205 u8 rev; 206 u32 rev;
206 unsigned b_hw:1; /* bad h/w fixes */ 207 unsigned b_hw:1; /* bad h/w fixes */
207 unsigned receiver:1; /* true when we're in receiver mode */ 208 unsigned receiver:1; /* true when we're in receiver mode */
208 u16 iestate; /* Saved interrupt register */ 209 u16 iestate; /* Saved interrupt register */
209 u16 pscstate; 210 u16 pscstate;
210 u16 scllstate; 211 u16 scllstate;
211 u16 sclhstate; 212 u16 sclhstate;
212 u16 bufstate;
213 u16 syscstate; 213 u16 syscstate;
214 u16 westate; 214 u16 westate;
215 u16 errata; 215 u16 errata;
216
217 struct pinctrl *pins;
216}; 218};
217 219
218static const u8 reg_map_ip_v1[] = { 220static const u8 reg_map_ip_v1[] = {
@@ -275,16 +277,39 @@ static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
275 (i2c_dev->regs[reg] << i2c_dev->reg_shift)); 277 (i2c_dev->regs[reg] << i2c_dev->reg_shift));
276} 278}
277 279
278static int omap_i2c_init(struct omap_i2c_dev *dev) 280static void __omap_i2c_init(struct omap_i2c_dev *dev)
281{
282
283 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
284
285 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
286 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate);
287
288 /* SCL low and high time values */
289 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, dev->scllstate);
290 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, dev->sclhstate);
291 if (dev->rev >= OMAP_I2C_REV_ON_3430_3530)
292 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate);
293
294 /* Take the I2C module out of reset: */
295 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
296
297 /*
298 * Don't write to this register if the IE state is 0 as it can
299 * cause deadlock.
300 */
301 if (dev->iestate)
302 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
303}
304
305static int omap_i2c_reset(struct omap_i2c_dev *dev)
279{ 306{
280 u16 psc = 0, scll = 0, sclh = 0, buf = 0;
281 u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
282 unsigned long fclk_rate = 12000000;
283 unsigned long timeout; 307 unsigned long timeout;
284 unsigned long internal_clk = 0; 308 u16 sysc;
285 struct clk *fclk;
286 309
287 if (dev->rev >= OMAP_I2C_OMAP1_REV_2) { 310 if (dev->rev >= OMAP_I2C_OMAP1_REV_2) {
311 sysc = omap_i2c_read_reg(dev, OMAP_I2C_SYSC_REG);
312
288 /* Disable I2C controller before soft reset */ 313 /* Disable I2C controller before soft reset */
289 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 314 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
290 omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) & 315 omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) &
@@ -306,32 +331,28 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
306 } 331 }
307 332
308 /* SYSC register is cleared by the reset; rewrite it */ 333 /* SYSC register is cleared by the reset; rewrite it */
309 if (dev->rev == OMAP_I2C_REV_ON_2430) { 334 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, sysc);
310 335
311 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, 336 }
312 SYSC_AUTOIDLE_MASK); 337 return 0;
313 338}
314 } else if (dev->rev >= OMAP_I2C_REV_ON_3430_3530) { 339
315 dev->syscstate = SYSC_AUTOIDLE_MASK; 340static int omap_i2c_init(struct omap_i2c_dev *dev)
316 dev->syscstate |= SYSC_ENAWAKEUP_MASK; 341{
317 dev->syscstate |= (SYSC_IDLEMODE_SMART << 342 u16 psc = 0, scll = 0, sclh = 0;
318 __ffs(SYSC_SIDLEMODE_MASK)); 343 u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
319 dev->syscstate |= (SYSC_CLOCKACTIVITY_FCLK << 344 unsigned long fclk_rate = 12000000;
320 __ffs(SYSC_CLOCKACTIVITY_MASK)); 345 unsigned long internal_clk = 0;
321 346 struct clk *fclk;
322 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, 347
323 dev->syscstate); 348 if (dev->rev >= OMAP_I2C_REV_ON_3430_3530) {
324 /* 349 /*
325 * Enabling all wakup sources to stop I2C freezing on 350 * Enabling all wakup sources to stop I2C freezing on
326 * WFI instruction. 351 * WFI instruction.
327 * REVISIT: Some wkup sources might not be needed. 352 * REVISIT: Some wkup sources might not be needed.
328 */ 353 */
329 dev->westate = OMAP_I2C_WE_ALL; 354 dev->westate = OMAP_I2C_WE_ALL;
330 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG,
331 dev->westate);
332 }
333 } 355 }
334 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
335 356
336 if (dev->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) { 357 if (dev->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) {
337 /* 358 /*
@@ -416,28 +437,17 @@ static int omap_i2c_init(struct omap_i2c_dev *dev)
416 sclh = fclk_rate / (dev->speed * 2) - 7 + psc; 437 sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
417 } 438 }
418 439
419 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
420 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
421
422 /* SCL low and high time values */
423 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
424 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
425
426 /* Take the I2C module out of reset: */
427 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
428
429 /* Enable interrupts */
430 dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY | 440 dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
431 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK | 441 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
432 OMAP_I2C_IE_AL) | ((dev->fifo_size) ? 442 OMAP_I2C_IE_AL) | ((dev->fifo_size) ?
433 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0); 443 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0);
434 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate); 444
435 if (dev->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) { 445 dev->pscstate = psc;
436 dev->pscstate = psc; 446 dev->scllstate = scll;
437 dev->scllstate = scll; 447 dev->sclhstate = sclh;
438 dev->sclhstate = sclh; 448
439 dev->bufstate = buf; 449 __omap_i2c_init(dev);
440 } 450
441 return 0; 451 return 0;
442} 452}
443 453
@@ -490,7 +500,7 @@ static void omap_i2c_resize_fifo(struct omap_i2c_dev *dev, u8 size, bool is_rx)
490 500
491 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf); 501 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf);
492 502
493 if (dev->rev < OMAP_I2C_REV_ON_3630_4430) 503 if (dev->rev < OMAP_I2C_REV_ON_3630)
494 dev->b_hw = 1; /* Enable hardware fixes */ 504 dev->b_hw = 1; /* Enable hardware fixes */
495 505
496 /* calculate wakeup latency constraint for MPU */ 506 /* calculate wakeup latency constraint for MPU */
@@ -586,7 +596,8 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
586 OMAP_I2C_TIMEOUT); 596 OMAP_I2C_TIMEOUT);
587 if (timeout == 0) { 597 if (timeout == 0) {
588 dev_err(dev->dev, "controller timed out\n"); 598 dev_err(dev->dev, "controller timed out\n");
589 omap_i2c_init(dev); 599 omap_i2c_reset(dev);
600 __omap_i2c_init(dev);
590 return -ETIMEDOUT; 601 return -ETIMEDOUT;
591 } 602 }
592 603
@@ -596,7 +607,8 @@ static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
596 /* We have an error */ 607 /* We have an error */
597 if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR | 608 if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
598 OMAP_I2C_STAT_XUDF)) { 609 OMAP_I2C_STAT_XUDF)) {
599 omap_i2c_init(dev); 610 omap_i2c_reset(dev);
611 __omap_i2c_init(dev);
600 return -EIO; 612 return -EIO;
601 } 613 }
602 614
@@ -642,13 +654,14 @@ omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
642 break; 654 break;
643 } 655 }
644 656
645 if (dev->set_mpu_wkup_lat != NULL)
646 dev->set_mpu_wkup_lat(dev->dev, -1);
647
648 if (r == 0) 657 if (r == 0)
649 r = num; 658 r = num;
650 659
651 omap_i2c_wait_for_bb(dev); 660 omap_i2c_wait_for_bb(dev);
661
662 if (dev->set_mpu_wkup_lat != NULL)
663 dev->set_mpu_wkup_lat(dev->dev, -1);
664
652out: 665out:
653 pm_runtime_mark_last_busy(dev->dev); 666 pm_runtime_mark_last_busy(dev->dev);
654 pm_runtime_put_autosuspend(dev->dev); 667 pm_runtime_put_autosuspend(dev->dev);
@@ -1025,9 +1038,7 @@ static const struct i2c_algorithm omap_i2c_algo = {
1025#ifdef CONFIG_OF 1038#ifdef CONFIG_OF
1026static struct omap_i2c_bus_platform_data omap3_pdata = { 1039static struct omap_i2c_bus_platform_data omap3_pdata = {
1027 .rev = OMAP_I2C_IP_VERSION_1, 1040 .rev = OMAP_I2C_IP_VERSION_1,
1028 .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 | 1041 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
1029 OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
1030 OMAP_I2C_FLAG_BUS_SHIFT_2,
1031}; 1042};
1032 1043
1033static struct omap_i2c_bus_platform_data omap4_pdata = { 1044static struct omap_i2c_bus_platform_data omap4_pdata = {
@@ -1048,6 +1059,16 @@ static const struct of_device_id omap_i2c_of_match[] = {
1048MODULE_DEVICE_TABLE(of, omap_i2c_of_match); 1059MODULE_DEVICE_TABLE(of, omap_i2c_of_match);
1049#endif 1060#endif
1050 1061
1062#define OMAP_I2C_SCHEME(rev) ((rev & 0xc000) >> 14)
1063
1064#define OMAP_I2C_REV_SCHEME_0_MAJOR(rev) (rev >> 4)
1065#define OMAP_I2C_REV_SCHEME_0_MINOR(rev) (rev & 0xf)
1066
1067#define OMAP_I2C_REV_SCHEME_1_MAJOR(rev) ((rev & 0x0700) >> 7)
1068#define OMAP_I2C_REV_SCHEME_1_MINOR(rev) (rev & 0x1f)
1069#define OMAP_I2C_SCHEME_0 0
1070#define OMAP_I2C_SCHEME_1 1
1071
1051static int __devinit 1072static int __devinit
1052omap_i2c_probe(struct platform_device *pdev) 1073omap_i2c_probe(struct platform_device *pdev)
1053{ 1074{
@@ -1060,6 +1081,8 @@ omap_i2c_probe(struct platform_device *pdev)
1060 const struct of_device_id *match; 1081 const struct of_device_id *match;
1061 int irq; 1082 int irq;
1062 int r; 1083 int r;
1084 u32 rev;
1085 u16 minor, major, scheme;
1063 1086
1064 /* NOTE: driver uses the static register mapping */ 1087 /* NOTE: driver uses the static register mapping */
1065 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1088 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -1091,7 +1114,6 @@ omap_i2c_probe(struct platform_device *pdev)
1091 u32 freq = 100000; /* default to 100000 Hz */ 1114 u32 freq = 100000; /* default to 100000 Hz */
1092 1115
1093 pdata = match->data; 1116 pdata = match->data;
1094 dev->dtrev = pdata->rev;
1095 dev->flags = pdata->flags; 1117 dev->flags = pdata->flags;
1096 1118
1097 of_property_read_u32(node, "clock-frequency", &freq); 1119 of_property_read_u32(node, "clock-frequency", &freq);
@@ -1101,7 +1123,16 @@ omap_i2c_probe(struct platform_device *pdev)
1101 dev->speed = pdata->clkrate; 1123 dev->speed = pdata->clkrate;
1102 dev->flags = pdata->flags; 1124 dev->flags = pdata->flags;
1103 dev->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat; 1125 dev->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat;
1104 dev->dtrev = pdata->rev; 1126 }
1127
1128 dev->pins = devm_pinctrl_get_select_default(&pdev->dev);
1129 if (IS_ERR(dev->pins)) {
1130 if (PTR_ERR(dev->pins) == -EPROBE_DEFER)
1131 return -EPROBE_DEFER;
1132
1133 dev_warn(&pdev->dev, "did not get pins for i2c error: %li\n",
1134 PTR_ERR(dev->pins));
1135 dev->pins = NULL;
1105 } 1136 }
1106 1137
1107 dev->dev = &pdev->dev; 1138 dev->dev = &pdev->dev;
@@ -1114,11 +1145,6 @@ omap_i2c_probe(struct platform_device *pdev)
1114 1145
1115 dev->reg_shift = (dev->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3; 1146 dev->reg_shift = (dev->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3;
1116 1147
1117 if (dev->dtrev == OMAP_I2C_IP_VERSION_2)
1118 dev->regs = (u8 *)reg_map_ip_v2;
1119 else
1120 dev->regs = (u8 *)reg_map_ip_v1;
1121
1122 pm_runtime_enable(dev->dev); 1148 pm_runtime_enable(dev->dev);
1123 pm_runtime_set_autosuspend_delay(dev->dev, OMAP_I2C_PM_TIMEOUT); 1149 pm_runtime_set_autosuspend_delay(dev->dev, OMAP_I2C_PM_TIMEOUT);
1124 pm_runtime_use_autosuspend(dev->dev); 1150 pm_runtime_use_autosuspend(dev->dev);
@@ -1127,11 +1153,37 @@ omap_i2c_probe(struct platform_device *pdev)
1127 if (IS_ERR_VALUE(r)) 1153 if (IS_ERR_VALUE(r))
1128 goto err_free_mem; 1154 goto err_free_mem;
1129 1155
1130 dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff; 1156 /*
1157 * Read the Rev hi bit-[15:14] ie scheme this is 1 indicates ver2.
1158 * On omap1/3/2 Offset 4 is IE Reg the bit [15:14] is 0 at reset.
1159 * Also since the omap_i2c_read_reg uses reg_map_ip_* a
1160 * raw_readw is done.
1161 */
1162 rev = __raw_readw(dev->base + 0x04);
1163
1164 scheme = OMAP_I2C_SCHEME(rev);
1165 switch (scheme) {
1166 case OMAP_I2C_SCHEME_0:
1167 dev->regs = (u8 *)reg_map_ip_v1;
1168 dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG);
1169 minor = OMAP_I2C_REV_SCHEME_0_MAJOR(dev->rev);
1170 major = OMAP_I2C_REV_SCHEME_0_MAJOR(dev->rev);
1171 break;
1172 case OMAP_I2C_SCHEME_1:
1173 /* FALLTHROUGH */
1174 default:
1175 dev->regs = (u8 *)reg_map_ip_v2;
1176 rev = (rev << 16) |
1177 omap_i2c_read_reg(dev, OMAP_I2C_IP_V2_REVNB_LO);
1178 minor = OMAP_I2C_REV_SCHEME_1_MINOR(rev);
1179 major = OMAP_I2C_REV_SCHEME_1_MAJOR(rev);
1180 dev->rev = rev;
1181 }
1131 1182
1132 dev->errata = 0; 1183 dev->errata = 0;
1133 1184
1134 if (dev->flags & OMAP_I2C_FLAG_APPLY_ERRATA_I207) 1185 if (dev->rev >= OMAP_I2C_REV_ON_2430 &&
1186 dev->rev < OMAP_I2C_REV_ON_4430_PLUS)
1135 dev->errata |= I2C_OMAP_ERRATA_I207; 1187 dev->errata |= I2C_OMAP_ERRATA_I207;
1136 1188
1137 if (dev->rev <= OMAP_I2C_REV_ON_3430_3530) 1189 if (dev->rev <= OMAP_I2C_REV_ON_3430_3530)
@@ -1152,7 +1204,7 @@ omap_i2c_probe(struct platform_device *pdev)
1152 1204
1153 dev->fifo_size = (dev->fifo_size / 2); 1205 dev->fifo_size = (dev->fifo_size / 2);
1154 1206
1155 if (dev->rev < OMAP_I2C_REV_ON_3630_4430) 1207 if (dev->rev < OMAP_I2C_REV_ON_3630)
1156 dev->b_hw = 1; /* Enable hardware fixes */ 1208 dev->b_hw = 1; /* Enable hardware fixes */
1157 1209
1158 /* calculate wakeup latency constraint for MPU */ 1210 /* calculate wakeup latency constraint for MPU */
@@ -1195,8 +1247,8 @@ omap_i2c_probe(struct platform_device *pdev)
1195 goto err_unuse_clocks; 1247 goto err_unuse_clocks;
1196 } 1248 }
1197 1249
1198 dev_info(dev->dev, "bus %d rev%d.%d.%d at %d kHz\n", adap->nr, 1250 dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n", adap->nr,
1199 dev->dtrev, dev->rev >> 4, dev->rev & 0xf, dev->speed); 1251 major, minor, dev->speed);
1200 1252
1201 of_i2c_register_devices(adap); 1253 of_i2c_register_devices(adap);
1202 1254
@@ -1239,14 +1291,13 @@ static int omap_i2c_runtime_suspend(struct device *dev)
1239{ 1291{
1240 struct platform_device *pdev = to_platform_device(dev); 1292 struct platform_device *pdev = to_platform_device(dev);
1241 struct omap_i2c_dev *_dev = platform_get_drvdata(pdev); 1293 struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
1242 u16 iv;
1243 1294
1244 _dev->iestate = omap_i2c_read_reg(_dev, OMAP_I2C_IE_REG); 1295 _dev->iestate = omap_i2c_read_reg(_dev, OMAP_I2C_IE_REG);
1245 1296
1246 omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, 0); 1297 omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, 0);
1247 1298
1248 if (_dev->rev < OMAP_I2C_OMAP1_REV_2) { 1299 if (_dev->rev < OMAP_I2C_OMAP1_REV_2) {
1249 iv = omap_i2c_read_reg(_dev, OMAP_I2C_IV_REG); /* Read clears */ 1300 omap_i2c_read_reg(_dev, OMAP_I2C_IV_REG); /* Read clears */
1250 } else { 1301 } else {
1251 omap_i2c_write_reg(_dev, OMAP_I2C_STAT_REG, _dev->iestate); 1302 omap_i2c_write_reg(_dev, OMAP_I2C_STAT_REG, _dev->iestate);
1252 1303
@@ -1262,23 +1313,10 @@ static int omap_i2c_runtime_resume(struct device *dev)
1262 struct platform_device *pdev = to_platform_device(dev); 1313 struct platform_device *pdev = to_platform_device(dev);
1263 struct omap_i2c_dev *_dev = platform_get_drvdata(pdev); 1314 struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
1264 1315
1265 if (_dev->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) { 1316 if (!_dev->regs)
1266 omap_i2c_write_reg(_dev, OMAP_I2C_CON_REG, 0); 1317 return 0;
1267 omap_i2c_write_reg(_dev, OMAP_I2C_PSC_REG, _dev->pscstate);
1268 omap_i2c_write_reg(_dev, OMAP_I2C_SCLL_REG, _dev->scllstate);
1269 omap_i2c_write_reg(_dev, OMAP_I2C_SCLH_REG, _dev->sclhstate);
1270 omap_i2c_write_reg(_dev, OMAP_I2C_BUF_REG, _dev->bufstate);
1271 omap_i2c_write_reg(_dev, OMAP_I2C_SYSC_REG, _dev->syscstate);
1272 omap_i2c_write_reg(_dev, OMAP_I2C_WE_REG, _dev->westate);
1273 omap_i2c_write_reg(_dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
1274 }
1275 1318
1276 /* 1319 __omap_i2c_init(_dev);
1277 * Don't write to this register if the IE state is 0 as it can
1278 * cause deadlock.
1279 */
1280 if (_dev->iestate)
1281 omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, _dev->iestate);
1282 1320
1283 return 0; 1321 return 0;
1284} 1322}
diff --git a/drivers/i2c/busses/i2c-rcar.c b/drivers/i2c/busses/i2c-rcar.c
index f9399d163af2..72a8071a5556 100644
--- a/drivers/i2c/busses/i2c-rcar.c
+++ b/drivers/i2c/busses/i2c-rcar.c
@@ -642,7 +642,7 @@ static int __devinit rcar_i2c_probe(struct platform_device *pdev)
642 if (ret < 0) 642 if (ret < 0)
643 return ret; 643 return ret;
644 644
645 priv->io = devm_ioremap(dev, res->start, resource_size(res)); 645 priv->io = devm_request_and_ioremap(dev, res);
646 if (!priv->io) { 646 if (!priv->io) {
647 dev_err(dev, "cannot ioremap\n"); 647 dev_err(dev, "cannot ioremap\n");
648 return -ENODEV; 648 return -ENODEV;
@@ -693,7 +693,7 @@ static int __devexit rcar_i2c_remove(struct platform_device *pdev)
693 return 0; 693 return 0;
694} 694}
695 695
696static struct platform_driver rcar_i2c_drv = { 696static struct platform_driver rcar_i2c_driver = {
697 .driver = { 697 .driver = {
698 .name = "i2c-rcar", 698 .name = "i2c-rcar",
699 .owner = THIS_MODULE, 699 .owner = THIS_MODULE,
@@ -702,7 +702,7 @@ static struct platform_driver rcar_i2c_drv = {
702 .remove = __devexit_p(rcar_i2c_remove), 702 .remove = __devexit_p(rcar_i2c_remove),
703}; 703};
704 704
705module_platform_driver(rcar_i2c_drv); 705module_platform_driver(rcar_i2c_driver);
706 706
707MODULE_LICENSE("GPL"); 707MODULE_LICENSE("GPL");
708MODULE_DESCRIPTION("Renesas R-Car I2C bus driver"); 708MODULE_DESCRIPTION("Renesas R-Car I2C bus driver");
diff --git a/drivers/i2c/busses/i2c-s3c2410.c b/drivers/i2c/busses/i2c-s3c2410.c
index b33d95ebc890..a290d089ceaf 100644
--- a/drivers/i2c/busses/i2c-s3c2410.c
+++ b/drivers/i2c/busses/i2c-s3c2410.c
@@ -38,6 +38,7 @@
38#include <linux/io.h> 38#include <linux/io.h>
39#include <linux/of_i2c.h> 39#include <linux/of_i2c.h>
40#include <linux/of_gpio.h> 40#include <linux/of_gpio.h>
41#include <linux/pinctrl/consumer.h>
41 42
42#include <asm/irq.h> 43#include <asm/irq.h>
43 44
@@ -49,6 +50,9 @@
49#define QUIRK_HDMIPHY (1 << 1) 50#define QUIRK_HDMIPHY (1 << 1)
50#define QUIRK_NO_GPIO (1 << 2) 51#define QUIRK_NO_GPIO (1 << 2)
51 52
53/* Max time to wait for bus to become idle after a xfer (in us) */
54#define S3C2410_IDLE_TIMEOUT 5000
55
52/* i2c controller state */ 56/* i2c controller state */
53enum s3c24xx_i2c_state { 57enum s3c24xx_i2c_state {
54 STATE_IDLE, 58 STATE_IDLE,
@@ -59,7 +63,6 @@ enum s3c24xx_i2c_state {
59}; 63};
60 64
61struct s3c24xx_i2c { 65struct s3c24xx_i2c {
62 spinlock_t lock;
63 wait_queue_head_t wait; 66 wait_queue_head_t wait;
64 unsigned int quirks; 67 unsigned int quirks;
65 unsigned int suspended:1; 68 unsigned int suspended:1;
@@ -78,11 +81,11 @@ struct s3c24xx_i2c {
78 void __iomem *regs; 81 void __iomem *regs;
79 struct clk *clk; 82 struct clk *clk;
80 struct device *dev; 83 struct device *dev;
81 struct resource *ioarea;
82 struct i2c_adapter adap; 84 struct i2c_adapter adap;
83 85
84 struct s3c2410_platform_i2c *pdata; 86 struct s3c2410_platform_i2c *pdata;
85 int gpios[2]; 87 int gpios[2];
88 struct pinctrl *pctrl;
86#ifdef CONFIG_CPU_FREQ 89#ifdef CONFIG_CPU_FREQ
87 struct notifier_block freq_transition; 90 struct notifier_block freq_transition;
88#endif 91#endif
@@ -235,8 +238,47 @@ static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret)
235 238
236 dev_dbg(i2c->dev, "STOP\n"); 239 dev_dbg(i2c->dev, "STOP\n");
237 240
238 /* stop the transfer */ 241 /*
239 iicstat &= ~S3C2410_IICSTAT_START; 242 * The datasheet says that the STOP sequence should be:
243 * 1) I2CSTAT.5 = 0 - Clear BUSY (or 'generate STOP')
244 * 2) I2CCON.4 = 0 - Clear IRQPEND
245 * 3) Wait until the stop condition takes effect.
246 * 4*) I2CSTAT.4 = 0 - Clear TXRXEN
247 *
248 * Where, step "4*" is only for buses with the "HDMIPHY" quirk.
249 *
250 * However, after much experimentation, it appears that:
251 * a) normal buses automatically clear BUSY and transition from
252 * Master->Slave when they complete generating a STOP condition.
253 * Therefore, step (3) can be done in doxfer() by polling I2CCON.4
254 * after starting the STOP generation here.
255 * b) HDMIPHY bus does neither, so there is no way to do step 3.
256 * There is no indication when this bus has finished generating
257 * STOP.
258 *
259 * In fact, we have found that as soon as the IRQPEND bit is cleared in
260 * step 2, the HDMIPHY bus generates the STOP condition, and then
261 * immediately starts transferring another data byte, even though the
262 * bus is supposedly stopped. This is presumably because the bus is
263 * still in "Master" mode, and its BUSY bit is still set.
264 *
265 * To avoid these extra post-STOP transactions on HDMI phy devices, we
266 * just disable Serial Output on the bus (I2CSTAT.4 = 0) directly,
267 * instead of first generating a proper STOP condition. This should
268 * float SDA & SCK terminating the transfer. Subsequent transfers
269 * start with a proper START condition, and proceed normally.
270 *
271 * The HDMIPHY bus is an internal bus that always has exactly two
272 * devices, the host as Master and the HDMIPHY device as the slave.
273 * Skipping the STOP condition has been tested on this bus and works.
274 */
275 if (i2c->quirks & QUIRK_HDMIPHY) {
276 /* Stop driving the I2C pins */
277 iicstat &= ~S3C2410_IICSTAT_TXRXEN;
278 } else {
279 /* stop the transfer */
280 iicstat &= ~S3C2410_IICSTAT_START;
281 }
240 writel(iicstat, i2c->regs + S3C2410_IICSTAT); 282 writel(iicstat, i2c->regs + S3C2410_IICSTAT);
241 283
242 i2c->state = STATE_STOP; 284 i2c->state = STATE_STOP;
@@ -490,13 +532,6 @@ static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c)
490 unsigned long iicstat; 532 unsigned long iicstat;
491 int timeout = 400; 533 int timeout = 400;
492 534
493 /* the timeout for HDMIPHY is reduced to 10 ms because
494 * the hangup is expected to happen, so waiting 400 ms
495 * causes only unnecessary system hangup
496 */
497 if (i2c->quirks & QUIRK_HDMIPHY)
498 timeout = 10;
499
500 while (timeout-- > 0) { 535 while (timeout-- > 0) {
501 iicstat = readl(i2c->regs + S3C2410_IICSTAT); 536 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
502 537
@@ -506,16 +541,61 @@ static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c)
506 msleep(1); 541 msleep(1);
507 } 542 }
508 543
509 /* hang-up of bus dedicated for HDMIPHY occurred, resetting */ 544 return -ETIMEDOUT;
510 if (i2c->quirks & QUIRK_HDMIPHY) { 545}
511 writel(0, i2c->regs + S3C2410_IICCON);
512 writel(0, i2c->regs + S3C2410_IICSTAT);
513 writel(0, i2c->regs + S3C2410_IICDS);
514 546
515 return 0; 547/* s3c24xx_i2c_wait_idle
548 *
549 * wait for the i2c bus to become idle.
550*/
551
552static void s3c24xx_i2c_wait_idle(struct s3c24xx_i2c *i2c)
553{
554 unsigned long iicstat;
555 ktime_t start, now;
556 unsigned long delay;
557 int spins;
558
559 /* ensure the stop has been through the bus */
560
561 dev_dbg(i2c->dev, "waiting for bus idle\n");
562
563 start = now = ktime_get();
564
565 /*
566 * Most of the time, the bus is already idle within a few usec of the
567 * end of a transaction. However, really slow i2c devices can stretch
568 * the clock, delaying STOP generation.
569 *
570 * On slower SoCs this typically happens within a very small number of
571 * instructions so busy wait briefly to avoid scheduling overhead.
572 */
573 spins = 3;
574 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
575 while ((iicstat & S3C2410_IICSTAT_START) && --spins) {
576 cpu_relax();
577 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
516 } 578 }
517 579
518 return -ETIMEDOUT; 580 /*
581 * If we do get an appreciable delay as a compromise between idle
582 * detection latency for the normal, fast case, and system load in the
583 * slow device case, use an exponential back off in the polling loop,
584 * up to 1/10th of the total timeout, then continue to poll at a
585 * constant rate up to the timeout.
586 */
587 delay = 1;
588 while ((iicstat & S3C2410_IICSTAT_START) &&
589 ktime_us_delta(now, start) < S3C2410_IDLE_TIMEOUT) {
590 usleep_range(delay, 2 * delay);
591 if (delay < S3C2410_IDLE_TIMEOUT / 10)
592 delay <<= 1;
593 now = ktime_get();
594 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
595 }
596
597 if (iicstat & S3C2410_IICSTAT_START)
598 dev_warn(i2c->dev, "timeout waiting for bus idle\n");
519} 599}
520 600
521/* s3c24xx_i2c_doxfer 601/* s3c24xx_i2c_doxfer
@@ -526,8 +606,7 @@ static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c)
526static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c, 606static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
527 struct i2c_msg *msgs, int num) 607 struct i2c_msg *msgs, int num)
528{ 608{
529 unsigned long iicstat, timeout; 609 unsigned long timeout;
530 int spins = 20;
531 int ret; 610 int ret;
532 611
533 if (i2c->suspended) 612 if (i2c->suspended)
@@ -540,8 +619,6 @@ static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
540 goto out; 619 goto out;
541 } 620 }
542 621
543 spin_lock_irq(&i2c->lock);
544
545 i2c->msg = msgs; 622 i2c->msg = msgs;
546 i2c->msg_num = num; 623 i2c->msg_num = num;
547 i2c->msg_ptr = 0; 624 i2c->msg_ptr = 0;
@@ -550,7 +627,6 @@ static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
550 627
551 s3c24xx_i2c_enable_irq(i2c); 628 s3c24xx_i2c_enable_irq(i2c);
552 s3c24xx_i2c_message_start(i2c, msgs); 629 s3c24xx_i2c_message_start(i2c, msgs);
553 spin_unlock_irq(&i2c->lock);
554 630
555 timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5); 631 timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
556 632
@@ -564,24 +640,11 @@ static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
564 else if (ret != num) 640 else if (ret != num)
565 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret); 641 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
566 642
567 /* ensure the stop has been through the bus */ 643 /* For QUIRK_HDMIPHY, bus is already disabled */
568 644 if (i2c->quirks & QUIRK_HDMIPHY)
569 dev_dbg(i2c->dev, "waiting for bus idle\n"); 645 goto out;
570
571 /* first, try busy waiting briefly */
572 do {
573 cpu_relax();
574 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
575 } while ((iicstat & S3C2410_IICSTAT_START) && --spins);
576
577 /* if that timed out sleep */
578 if (!spins) {
579 msleep(1);
580 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
581 }
582 646
583 if (iicstat & S3C2410_IICSTAT_START) 647 s3c24xx_i2c_wait_idle(i2c);
584 dev_warn(i2c->dev, "timeout waiting for bus idle\n");
585 648
586 out: 649 out:
587 return ret; 650 return ret;
@@ -740,7 +803,6 @@ static int s3c24xx_i2c_cpufreq_transition(struct notifier_block *nb,
740 unsigned long val, void *data) 803 unsigned long val, void *data)
741{ 804{
742 struct s3c24xx_i2c *i2c = freq_to_i2c(nb); 805 struct s3c24xx_i2c *i2c = freq_to_i2c(nb);
743 unsigned long flags;
744 unsigned int got; 806 unsigned int got;
745 int delta_f; 807 int delta_f;
746 int ret; 808 int ret;
@@ -754,9 +816,9 @@ static int s3c24xx_i2c_cpufreq_transition(struct notifier_block *nb,
754 816
755 if ((val == CPUFREQ_POSTCHANGE && delta_f < 0) || 817 if ((val == CPUFREQ_POSTCHANGE && delta_f < 0) ||
756 (val == CPUFREQ_PRECHANGE && delta_f > 0)) { 818 (val == CPUFREQ_PRECHANGE && delta_f > 0)) {
757 spin_lock_irqsave(&i2c->lock, flags); 819 i2c_lock_adapter(&i2c->adap);
758 ret = s3c24xx_i2c_clockrate(i2c, &got); 820 ret = s3c24xx_i2c_clockrate(i2c, &got);
759 spin_unlock_irqrestore(&i2c->lock, flags); 821 i2c_unlock_adapter(&i2c->adap);
760 822
761 if (ret < 0) 823 if (ret < 0)
762 dev_err(i2c->dev, "cannot find frequency\n"); 824 dev_err(i2c->dev, "cannot find frequency\n");
@@ -858,14 +920,6 @@ static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c)
858 920
859 pdata = i2c->pdata; 921 pdata = i2c->pdata;
860 922
861 /* inititalise the gpio */
862
863 if (pdata->cfg_gpio)
864 pdata->cfg_gpio(to_platform_device(i2c->dev));
865 else
866 if (s3c24xx_i2c_parse_dt_gpio(i2c))
867 return -EINVAL;
868
869 /* write slave address */ 923 /* write slave address */
870 924
871 writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD); 925 writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD);
@@ -963,7 +1017,6 @@ static int s3c24xx_i2c_probe(struct platform_device *pdev)
963 i2c->adap.class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 1017 i2c->adap.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
964 i2c->tx_setup = 50; 1018 i2c->tx_setup = 50;
965 1019
966 spin_lock_init(&i2c->lock);
967 init_waitqueue_head(&i2c->wait); 1020 init_waitqueue_head(&i2c->wait);
968 1021
969 /* find the clock and enable it */ 1022 /* find the clock and enable it */
@@ -989,36 +1042,38 @@ static int s3c24xx_i2c_probe(struct platform_device *pdev)
989 goto err_clk; 1042 goto err_clk;
990 } 1043 }
991 1044
992 i2c->ioarea = request_mem_region(res->start, resource_size(res), 1045 i2c->regs = devm_request_and_ioremap(&pdev->dev, res);
993 pdev->name);
994
995 if (i2c->ioarea == NULL) {
996 dev_err(&pdev->dev, "cannot request IO\n");
997 ret = -ENXIO;
998 goto err_clk;
999 }
1000
1001 i2c->regs = ioremap(res->start, resource_size(res));
1002 1046
1003 if (i2c->regs == NULL) { 1047 if (i2c->regs == NULL) {
1004 dev_err(&pdev->dev, "cannot map IO\n"); 1048 dev_err(&pdev->dev, "cannot map IO\n");
1005 ret = -ENXIO; 1049 ret = -ENXIO;
1006 goto err_ioarea; 1050 goto err_clk;
1007 } 1051 }
1008 1052
1009 dev_dbg(&pdev->dev, "registers %p (%p, %p)\n", 1053 dev_dbg(&pdev->dev, "registers %p (%p)\n",
1010 i2c->regs, i2c->ioarea, res); 1054 i2c->regs, res);
1011 1055
1012 /* setup info block for the i2c core */ 1056 /* setup info block for the i2c core */
1013 1057
1014 i2c->adap.algo_data = i2c; 1058 i2c->adap.algo_data = i2c;
1015 i2c->adap.dev.parent = &pdev->dev; 1059 i2c->adap.dev.parent = &pdev->dev;
1016 1060
1061 i2c->pctrl = devm_pinctrl_get_select_default(i2c->dev);
1062
1063 /* inititalise the i2c gpio lines */
1064
1065 if (i2c->pdata->cfg_gpio) {
1066 i2c->pdata->cfg_gpio(to_platform_device(i2c->dev));
1067 } else if (IS_ERR(i2c->pctrl) && s3c24xx_i2c_parse_dt_gpio(i2c)) {
1068 ret = -EINVAL;
1069 goto err_clk;
1070 }
1071
1017 /* initialise the i2c controller */ 1072 /* initialise the i2c controller */
1018 1073
1019 ret = s3c24xx_i2c_init(i2c); 1074 ret = s3c24xx_i2c_init(i2c);
1020 if (ret != 0) 1075 if (ret != 0)
1021 goto err_iomap; 1076 goto err_clk;
1022 1077
1023 /* find the IRQ for this unit (note, this relies on the init call to 1078 /* find the IRQ for this unit (note, this relies on the init call to
1024 * ensure no current IRQs pending 1079 * ensure no current IRQs pending
@@ -1027,7 +1082,7 @@ static int s3c24xx_i2c_probe(struct platform_device *pdev)
1027 i2c->irq = ret = platform_get_irq(pdev, 0); 1082 i2c->irq = ret = platform_get_irq(pdev, 0);
1028 if (ret <= 0) { 1083 if (ret <= 0) {
1029 dev_err(&pdev->dev, "cannot find IRQ\n"); 1084 dev_err(&pdev->dev, "cannot find IRQ\n");
1030 goto err_iomap; 1085 goto err_clk;
1031 } 1086 }
1032 1087
1033 ret = request_irq(i2c->irq, s3c24xx_i2c_irq, 0, 1088 ret = request_irq(i2c->irq, s3c24xx_i2c_irq, 0,
@@ -1035,7 +1090,7 @@ static int s3c24xx_i2c_probe(struct platform_device *pdev)
1035 1090
1036 if (ret != 0) { 1091 if (ret != 0) {
1037 dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq); 1092 dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
1038 goto err_iomap; 1093 goto err_clk;
1039 } 1094 }
1040 1095
1041 ret = s3c24xx_i2c_register_cpufreq(i2c); 1096 ret = s3c24xx_i2c_register_cpufreq(i2c);
@@ -1075,13 +1130,6 @@ static int s3c24xx_i2c_probe(struct platform_device *pdev)
1075 err_irq: 1130 err_irq:
1076 free_irq(i2c->irq, i2c); 1131 free_irq(i2c->irq, i2c);
1077 1132
1078 err_iomap:
1079 iounmap(i2c->regs);
1080
1081 err_ioarea:
1082 release_resource(i2c->ioarea);
1083 kfree(i2c->ioarea);
1084
1085 err_clk: 1133 err_clk:
1086 clk_disable_unprepare(i2c->clk); 1134 clk_disable_unprepare(i2c->clk);
1087 clk_put(i2c->clk); 1135 clk_put(i2c->clk);
@@ -1110,16 +1158,13 @@ static int s3c24xx_i2c_remove(struct platform_device *pdev)
1110 clk_disable_unprepare(i2c->clk); 1158 clk_disable_unprepare(i2c->clk);
1111 clk_put(i2c->clk); 1159 clk_put(i2c->clk);
1112 1160
1113 iounmap(i2c->regs); 1161 if (pdev->dev.of_node && IS_ERR(i2c->pctrl))
1114 1162 s3c24xx_i2c_dt_gpio_free(i2c);
1115 release_resource(i2c->ioarea);
1116 s3c24xx_i2c_dt_gpio_free(i2c);
1117 kfree(i2c->ioarea);
1118 1163
1119 return 0; 1164 return 0;
1120} 1165}
1121 1166
1122#ifdef CONFIG_PM 1167#ifdef CONFIG_PM_SLEEP
1123static int s3c24xx_i2c_suspend_noirq(struct device *dev) 1168static int s3c24xx_i2c_suspend_noirq(struct device *dev)
1124{ 1169{
1125 struct platform_device *pdev = to_platform_device(dev); 1170 struct platform_device *pdev = to_platform_device(dev);
@@ -1142,10 +1187,14 @@ static int s3c24xx_i2c_resume(struct device *dev)
1142 1187
1143 return 0; 1188 return 0;
1144} 1189}
1190#endif
1145 1191
1192#ifdef CONFIG_PM
1146static const struct dev_pm_ops s3c24xx_i2c_dev_pm_ops = { 1193static const struct dev_pm_ops s3c24xx_i2c_dev_pm_ops = {
1194#ifdef CONFIG_PM_SLEEP
1147 .suspend_noirq = s3c24xx_i2c_suspend_noirq, 1195 .suspend_noirq = s3c24xx_i2c_suspend_noirq,
1148 .resume = s3c24xx_i2c_resume, 1196 .resume = s3c24xx_i2c_resume,
1197#endif
1149}; 1198};
1150 1199
1151#define S3C24XX_DEV_PM_OPS (&s3c24xx_i2c_dev_pm_ops) 1200#define S3C24XX_DEV_PM_OPS (&s3c24xx_i2c_dev_pm_ops)
diff --git a/drivers/i2c/busses/i2c-sh_mobile.c b/drivers/i2c/busses/i2c-sh_mobile.c
index 8110ca45f342..9411c1b892c0 100644
--- a/drivers/i2c/busses/i2c-sh_mobile.c
+++ b/drivers/i2c/busses/i2c-sh_mobile.c
@@ -120,11 +120,12 @@ struct sh_mobile_i2c_data {
120 void __iomem *reg; 120 void __iomem *reg;
121 struct i2c_adapter adap; 121 struct i2c_adapter adap;
122 unsigned long bus_speed; 122 unsigned long bus_speed;
123 unsigned int clks_per_count;
123 struct clk *clk; 124 struct clk *clk;
124 u_int8_t icic; 125 u_int8_t icic;
125 u_int8_t iccl;
126 u_int8_t icch;
127 u_int8_t flags; 126 u_int8_t flags;
127 u_int16_t iccl;
128 u_int16_t icch;
128 129
129 spinlock_t lock; 130 spinlock_t lock;
130 wait_queue_head_t wait; 131 wait_queue_head_t wait;
@@ -135,7 +136,8 @@ struct sh_mobile_i2c_data {
135 136
136#define IIC_FLAG_HAS_ICIC67 (1 << 0) 137#define IIC_FLAG_HAS_ICIC67 (1 << 0)
137 138
138#define NORMAL_SPEED 100000 /* FAST_SPEED 400000 */ 139#define STANDARD_MODE 100000
140#define FAST_MODE 400000
139 141
140/* Register offsets */ 142/* Register offsets */
141#define ICDR 0x00 143#define ICDR 0x00
@@ -187,57 +189,90 @@ static void iic_set_clr(struct sh_mobile_i2c_data *pd, int offs,
187 iic_wr(pd, offs, (iic_rd(pd, offs) | set) & ~clr); 189 iic_wr(pd, offs, (iic_rd(pd, offs) | set) & ~clr);
188} 190}
189 191
190static void activate_ch(struct sh_mobile_i2c_data *pd) 192static u32 sh_mobile_i2c_iccl(unsigned long count_khz, u32 tLOW, u32 tf, int offset)
191{ 193{
192 unsigned long i2c_clk; 194 /*
193 u_int32_t num; 195 * Conditional expression:
194 u_int32_t denom; 196 * ICCL >= COUNT_CLK * (tLOW + tf)
195 u_int32_t tmp; 197 *
196 198 * SH-Mobile IIC hardware starts counting the LOW period of
197 /* Wake up device and enable clock */ 199 * the SCL signal (tLOW) as soon as it pulls the SCL line.
198 pm_runtime_get_sync(pd->dev); 200 * In order to meet the tLOW timing spec, we need to take into
199 clk_enable(pd->clk); 201 * account the fall time of SCL signal (tf). Default tf value
200 202 * should be 0.3 us, for safety.
201 /* Get clock rate after clock is enabled */ 203 */
202 i2c_clk = clk_get_rate(pd->clk); 204 return (((count_khz * (tLOW + tf)) + 5000) / 10000) + offset;
205}
203 206
204 /* Calculate the value for iccl. From the data sheet: 207static u32 sh_mobile_i2c_icch(unsigned long count_khz, u32 tHIGH, u32 tf, int offset)
205 * iccl = (p clock / transfer rate) * (L / (L + H)) 208{
206 * where L and H are the SCL low/high ratio (5/4 in this case). 209 /*
207 * We also round off the result. 210 * Conditional expression:
211 * ICCH >= COUNT_CLK * (tHIGH + tf)
212 *
213 * SH-Mobile IIC hardware is aware of SCL transition period 'tr',
214 * and can ignore it. SH-Mobile IIC controller starts counting
215 * the HIGH period of the SCL signal (tHIGH) after the SCL input
216 * voltage increases at VIH.
217 *
218 * Afterward it turned out calculating ICCH using only tHIGH spec
219 * will result in violation of the tHD;STA timing spec. We need
220 * to take into account the fall time of SDA signal (tf) at START
221 * condition, in order to meet both tHIGH and tHD;STA specs.
208 */ 222 */
209 num = i2c_clk * 5; 223 return (((count_khz * (tHIGH + tf)) + 5000) / 10000) + offset;
210 denom = pd->bus_speed * 9; 224}
211 tmp = num * 10 / denom;
212 if (tmp % 10 >= 5)
213 pd->iccl = (u_int8_t)((num/denom) + 1);
214 else
215 pd->iccl = (u_int8_t)(num/denom);
216 225
217 /* one more bit of ICCL in ICIC */ 226static void sh_mobile_i2c_init(struct sh_mobile_i2c_data *pd)
218 if (pd->flags & IIC_FLAG_HAS_ICIC67) { 227{
219 if ((num/denom) > 0xff) 228 unsigned long i2c_clk_khz;
220 pd->icic |= ICIC_ICCLB8; 229 u32 tHIGH, tLOW, tf;
221 else 230 int offset;
222 pd->icic &= ~ICIC_ICCLB8; 231
232 /* Get clock rate after clock is enabled */
233 clk_enable(pd->clk);
234 i2c_clk_khz = clk_get_rate(pd->clk) / 1000;
235 i2c_clk_khz /= pd->clks_per_count;
236
237 if (pd->bus_speed == STANDARD_MODE) {
238 tLOW = 47; /* tLOW = 4.7 us */
239 tHIGH = 40; /* tHD;STA = tHIGH = 4.0 us */
240 tf = 3; /* tf = 0.3 us */
241 offset = 0; /* No offset */
242 } else if (pd->bus_speed == FAST_MODE) {
243 tLOW = 13; /* tLOW = 1.3 us */
244 tHIGH = 6; /* tHD;STA = tHIGH = 0.6 us */
245 tf = 3; /* tf = 0.3 us */
246 offset = 0; /* No offset */
247 } else {
248 dev_err(pd->dev, "unrecognized bus speed %lu Hz\n",
249 pd->bus_speed);
250 goto out;
223 } 251 }
224 252
225 /* Calculate the value for icch. From the data sheet: 253 pd->iccl = sh_mobile_i2c_iccl(i2c_clk_khz, tLOW, tf, offset);
226 icch = (p clock / transfer rate) * (H / (L + H)) */ 254 /* one more bit of ICCL in ICIC */
227 num = i2c_clk * 4; 255 if ((pd->iccl > 0xff) && (pd->flags & IIC_FLAG_HAS_ICIC67))
228 tmp = num * 10 / denom; 256 pd->icic |= ICIC_ICCLB8;
229 if (tmp % 10 >= 5)
230 pd->icch = (u_int8_t)((num/denom) + 1);
231 else 257 else
232 pd->icch = (u_int8_t)(num/denom); 258 pd->icic &= ~ICIC_ICCLB8;
233 259
260 pd->icch = sh_mobile_i2c_icch(i2c_clk_khz, tHIGH, tf, offset);
234 /* one more bit of ICCH in ICIC */ 261 /* one more bit of ICCH in ICIC */
235 if (pd->flags & IIC_FLAG_HAS_ICIC67) { 262 if ((pd->icch > 0xff) && (pd->flags & IIC_FLAG_HAS_ICIC67))
236 if ((num/denom) > 0xff) 263 pd->icic |= ICIC_ICCHB8;
237 pd->icic |= ICIC_ICCHB8; 264 else
238 else 265 pd->icic &= ~ICIC_ICCHB8;
239 pd->icic &= ~ICIC_ICCHB8; 266
240 } 267out:
268 clk_disable(pd->clk);
269}
270
271static void activate_ch(struct sh_mobile_i2c_data *pd)
272{
273 /* Wake up device and enable clock */
274 pm_runtime_get_sync(pd->dev);
275 clk_enable(pd->clk);
241 276
242 /* Enable channel and configure rx ack */ 277 /* Enable channel and configure rx ack */
243 iic_set_clr(pd, ICCR, ICCR_ICE, 0); 278 iic_set_clr(pd, ICCR, ICCR_ICE, 0);
@@ -246,8 +281,8 @@ static void activate_ch(struct sh_mobile_i2c_data *pd)
246 iic_wr(pd, ICIC, 0); 281 iic_wr(pd, ICIC, 0);
247 282
248 /* Set the clock */ 283 /* Set the clock */
249 iic_wr(pd, ICCL, pd->iccl); 284 iic_wr(pd, ICCL, pd->iccl & 0xff);
250 iic_wr(pd, ICCH, pd->icch); 285 iic_wr(pd, ICCH, pd->icch & 0xff);
251} 286}
252 287
253static void deactivate_ch(struct sh_mobile_i2c_data *pd) 288static void deactivate_ch(struct sh_mobile_i2c_data *pd)
@@ -434,6 +469,9 @@ static irqreturn_t sh_mobile_i2c_isr(int irq, void *dev_id)
434 wake_up(&pd->wait); 469 wake_up(&pd->wait);
435 } 470 }
436 471
472 /* defeat write posting to avoid spurious WAIT interrupts */
473 iic_rd(pd, ICSR);
474
437 return IRQ_HANDLED; 475 return IRQ_HANDLED;
438} 476}
439 477
@@ -451,8 +489,8 @@ static int start_ch(struct sh_mobile_i2c_data *pd, struct i2c_msg *usr_msg)
451 iic_set_clr(pd, ICCR, ICCR_ICE, 0); 489 iic_set_clr(pd, ICCR, ICCR_ICE, 0);
452 490
453 /* Set the clock */ 491 /* Set the clock */
454 iic_wr(pd, ICCL, pd->iccl); 492 iic_wr(pd, ICCL, pd->iccl & 0xff);
455 iic_wr(pd, ICCH, pd->icch); 493 iic_wr(pd, ICCH, pd->icch & 0xff);
456 494
457 pd->msg = usr_msg; 495 pd->msg = usr_msg;
458 pd->pos = -1; 496 pd->pos = -1;
@@ -621,10 +659,13 @@ static int sh_mobile_i2c_probe(struct platform_device *dev)
621 goto err_irq; 659 goto err_irq;
622 } 660 }
623 661
624 /* Use platformd data bus speed or NORMAL_SPEED */ 662 /* Use platform data bus speed or STANDARD_MODE */
625 pd->bus_speed = NORMAL_SPEED; 663 pd->bus_speed = STANDARD_MODE;
626 if (pdata && pdata->bus_speed) 664 if (pdata && pdata->bus_speed)
627 pd->bus_speed = pdata->bus_speed; 665 pd->bus_speed = pdata->bus_speed;
666 pd->clks_per_count = 1;
667 if (pdata && pdata->clks_per_count)
668 pd->clks_per_count = pdata->clks_per_count;
628 669
629 /* The IIC blocks on SH-Mobile ARM processors 670 /* The IIC blocks on SH-Mobile ARM processors
630 * come with two new bits in ICIC. 671 * come with two new bits in ICIC.
@@ -632,6 +673,8 @@ static int sh_mobile_i2c_probe(struct platform_device *dev)
632 if (size > 0x17) 673 if (size > 0x17)
633 pd->flags |= IIC_FLAG_HAS_ICIC67; 674 pd->flags |= IIC_FLAG_HAS_ICIC67;
634 675
676 sh_mobile_i2c_init(pd);
677
635 /* Enable Runtime PM for this device. 678 /* Enable Runtime PM for this device.
636 * 679 *
637 * Also tell the Runtime PM core to ignore children 680 * Also tell the Runtime PM core to ignore children
@@ -667,8 +710,9 @@ static int sh_mobile_i2c_probe(struct platform_device *dev)
667 goto err_all; 710 goto err_all;
668 } 711 }
669 712
670 dev_info(&dev->dev, "I2C adapter %d with bus speed %lu Hz\n", 713 dev_info(&dev->dev,
671 adap->nr, pd->bus_speed); 714 "I2C adapter %d with bus speed %lu Hz (L/H=%x/%x)\n",
715 adap->nr, pd->bus_speed, pd->iccl, pd->icch);
672 716
673 of_i2c_register_devices(adap); 717 of_i2c_register_devices(adap);
674 return 0; 718 return 0;
diff --git a/drivers/i2c/muxes/i2c-mux-gpio.c b/drivers/i2c/muxes/i2c-mux-gpio.c
index 566a6757a33d..3b7bc06fe8a6 100644
--- a/drivers/i2c/muxes/i2c-mux-gpio.c
+++ b/drivers/i2c/muxes/i2c-mux-gpio.c
@@ -16,6 +16,8 @@
16#include <linux/module.h> 16#include <linux/module.h>
17#include <linux/slab.h> 17#include <linux/slab.h>
18#include <linux/gpio.h> 18#include <linux/gpio.h>
19#include <linux/of_i2c.h>
20#include <linux/of_gpio.h>
19 21
20struct gpiomux { 22struct gpiomux {
21 struct i2c_adapter *parent; 23 struct i2c_adapter *parent;
@@ -57,29 +59,110 @@ static int __devinit match_gpio_chip_by_label(struct gpio_chip *chip,
57 return !strcmp(chip->label, data); 59 return !strcmp(chip->label, data);
58} 60}
59 61
62#ifdef CONFIG_OF
63static int __devinit i2c_mux_gpio_probe_dt(struct gpiomux *mux,
64 struct platform_device *pdev)
65{
66 struct device_node *np = pdev->dev.of_node;
67 struct device_node *adapter_np, *child;
68 struct i2c_adapter *adapter;
69 unsigned *values, *gpios;
70 int i = 0;
71
72 if (!np)
73 return -ENODEV;
74
75 adapter_np = of_parse_phandle(np, "i2c-parent", 0);
76 if (!adapter_np) {
77 dev_err(&pdev->dev, "Cannot parse i2c-parent\n");
78 return -ENODEV;
79 }
80 adapter = of_find_i2c_adapter_by_node(adapter_np);
81 if (!adapter) {
82 dev_err(&pdev->dev, "Cannot find parent bus\n");
83 return -ENODEV;
84 }
85 mux->data.parent = i2c_adapter_id(adapter);
86 put_device(&adapter->dev);
87
88 mux->data.n_values = of_get_child_count(np);
89
90 values = devm_kzalloc(&pdev->dev,
91 sizeof(*mux->data.values) * mux->data.n_values,
92 GFP_KERNEL);
93 if (!values) {
94 dev_err(&pdev->dev, "Cannot allocate values array");
95 return -ENOMEM;
96 }
97
98 for_each_child_of_node(np, child) {
99 of_property_read_u32(child, "reg", values + i);
100 i++;
101 }
102 mux->data.values = values;
103
104 if (of_property_read_u32(np, "idle-state", &mux->data.idle))
105 mux->data.idle = I2C_MUX_GPIO_NO_IDLE;
106
107 mux->data.n_gpios = of_gpio_named_count(np, "mux-gpios");
108 if (mux->data.n_gpios < 0) {
109 dev_err(&pdev->dev, "Missing mux-gpios property in the DT.\n");
110 return -EINVAL;
111 }
112
113 gpios = devm_kzalloc(&pdev->dev,
114 sizeof(*mux->data.gpios) * mux->data.n_gpios, GFP_KERNEL);
115 if (!gpios) {
116 dev_err(&pdev->dev, "Cannot allocate gpios array");
117 return -ENOMEM;
118 }
119
120 for (i = 0; i < mux->data.n_gpios; i++)
121 gpios[i] = of_get_named_gpio(np, "mux-gpios", i);
122
123 mux->data.gpios = gpios;
124
125 return 0;
126}
127#else
128static int __devinit i2c_mux_gpio_probe_dt(struct gpiomux *mux,
129 struct platform_device *pdev)
130{
131 return 0;
132}
133#endif
134
60static int __devinit i2c_mux_gpio_probe(struct platform_device *pdev) 135static int __devinit i2c_mux_gpio_probe(struct platform_device *pdev)
61{ 136{
62 struct gpiomux *mux; 137 struct gpiomux *mux;
63 struct i2c_mux_gpio_platform_data *pdata;
64 struct i2c_adapter *parent; 138 struct i2c_adapter *parent;
65 int (*deselect) (struct i2c_adapter *, void *, u32); 139 int (*deselect) (struct i2c_adapter *, void *, u32);
66 unsigned initial_state, gpio_base; 140 unsigned initial_state, gpio_base;
67 int i, ret; 141 int i, ret;
68 142
69 pdata = pdev->dev.platform_data; 143 mux = devm_kzalloc(&pdev->dev, sizeof(*mux), GFP_KERNEL);
70 if (!pdata) { 144 if (!mux) {
71 dev_err(&pdev->dev, "Missing platform data\n"); 145 dev_err(&pdev->dev, "Cannot allocate gpiomux structure");
72 return -ENODEV; 146 return -ENOMEM;
73 } 147 }
74 148
149 platform_set_drvdata(pdev, mux);
150
151 if (!pdev->dev.platform_data) {
152 ret = i2c_mux_gpio_probe_dt(mux, pdev);
153 if (ret < 0)
154 return ret;
155 } else
156 memcpy(&mux->data, pdev->dev.platform_data, sizeof(mux->data));
157
75 /* 158 /*
76 * If a GPIO chip name is provided, the GPIO pin numbers provided are 159 * If a GPIO chip name is provided, the GPIO pin numbers provided are
77 * relative to its base GPIO number. Otherwise they are absolute. 160 * relative to its base GPIO number. Otherwise they are absolute.
78 */ 161 */
79 if (pdata->gpio_chip) { 162 if (mux->data.gpio_chip) {
80 struct gpio_chip *gpio; 163 struct gpio_chip *gpio;
81 164
82 gpio = gpiochip_find(pdata->gpio_chip, 165 gpio = gpiochip_find(mux->data.gpio_chip,
83 match_gpio_chip_by_label); 166 match_gpio_chip_by_label);
84 if (!gpio) 167 if (!gpio)
85 return -EPROBE_DEFER; 168 return -EPROBE_DEFER;
@@ -89,49 +172,44 @@ static int __devinit i2c_mux_gpio_probe(struct platform_device *pdev)
89 gpio_base = 0; 172 gpio_base = 0;
90 } 173 }
91 174
92 parent = i2c_get_adapter(pdata->parent); 175 parent = i2c_get_adapter(mux->data.parent);
93 if (!parent) { 176 if (!parent) {
94 dev_err(&pdev->dev, "Parent adapter (%d) not found\n", 177 dev_err(&pdev->dev, "Parent adapter (%d) not found\n",
95 pdata->parent); 178 mux->data.parent);
96 return -ENODEV; 179 return -ENODEV;
97 } 180 }
98 181
99 mux = devm_kzalloc(&pdev->dev, sizeof(*mux), GFP_KERNEL);
100 if (!mux) {
101 ret = -ENOMEM;
102 goto alloc_failed;
103 }
104
105 mux->parent = parent; 182 mux->parent = parent;
106 mux->data = *pdata;
107 mux->gpio_base = gpio_base; 183 mux->gpio_base = gpio_base;
184
108 mux->adap = devm_kzalloc(&pdev->dev, 185 mux->adap = devm_kzalloc(&pdev->dev,
109 sizeof(*mux->adap) * pdata->n_values, 186 sizeof(*mux->adap) * mux->data.n_values,
110 GFP_KERNEL); 187 GFP_KERNEL);
111 if (!mux->adap) { 188 if (!mux->adap) {
189 dev_err(&pdev->dev, "Cannot allocate i2c_adapter structure");
112 ret = -ENOMEM; 190 ret = -ENOMEM;
113 goto alloc_failed; 191 goto alloc_failed;
114 } 192 }
115 193
116 if (pdata->idle != I2C_MUX_GPIO_NO_IDLE) { 194 if (mux->data.idle != I2C_MUX_GPIO_NO_IDLE) {
117 initial_state = pdata->idle; 195 initial_state = mux->data.idle;
118 deselect = i2c_mux_gpio_deselect; 196 deselect = i2c_mux_gpio_deselect;
119 } else { 197 } else {
120 initial_state = pdata->values[0]; 198 initial_state = mux->data.values[0];
121 deselect = NULL; 199 deselect = NULL;
122 } 200 }
123 201
124 for (i = 0; i < pdata->n_gpios; i++) { 202 for (i = 0; i < mux->data.n_gpios; i++) {
125 ret = gpio_request(gpio_base + pdata->gpios[i], "i2c-mux-gpio"); 203 ret = gpio_request(gpio_base + mux->data.gpios[i], "i2c-mux-gpio");
126 if (ret) 204 if (ret)
127 goto err_request_gpio; 205 goto err_request_gpio;
128 gpio_direction_output(gpio_base + pdata->gpios[i], 206 gpio_direction_output(gpio_base + mux->data.gpios[i],
129 initial_state & (1 << i)); 207 initial_state & (1 << i));
130 } 208 }
131 209
132 for (i = 0; i < pdata->n_values; i++) { 210 for (i = 0; i < mux->data.n_values; i++) {
133 u32 nr = pdata->base_nr ? (pdata->base_nr + i) : 0; 211 u32 nr = mux->data.base_nr ? (mux->data.base_nr + i) : 0;
134 unsigned int class = pdata->classes ? pdata->classes[i] : 0; 212 unsigned int class = mux->data.classes ? mux->data.classes[i] : 0;
135 213
136 mux->adap[i] = i2c_add_mux_adapter(parent, &pdev->dev, mux, nr, 214 mux->adap[i] = i2c_add_mux_adapter(parent, &pdev->dev, mux, nr,
137 i, class, 215 i, class,
@@ -144,19 +222,17 @@ static int __devinit i2c_mux_gpio_probe(struct platform_device *pdev)
144 } 222 }
145 223
146 dev_info(&pdev->dev, "%d port mux on %s adapter\n", 224 dev_info(&pdev->dev, "%d port mux on %s adapter\n",
147 pdata->n_values, parent->name); 225 mux->data.n_values, parent->name);
148
149 platform_set_drvdata(pdev, mux);
150 226
151 return 0; 227 return 0;
152 228
153add_adapter_failed: 229add_adapter_failed:
154 for (; i > 0; i--) 230 for (; i > 0; i--)
155 i2c_del_mux_adapter(mux->adap[i - 1]); 231 i2c_del_mux_adapter(mux->adap[i - 1]);
156 i = pdata->n_gpios; 232 i = mux->data.n_gpios;
157err_request_gpio: 233err_request_gpio:
158 for (; i > 0; i--) 234 for (; i > 0; i--)
159 gpio_free(gpio_base + pdata->gpios[i - 1]); 235 gpio_free(gpio_base + mux->data.gpios[i - 1]);
160alloc_failed: 236alloc_failed:
161 i2c_put_adapter(parent); 237 i2c_put_adapter(parent);
162 238
@@ -180,12 +256,19 @@ static int __devexit i2c_mux_gpio_remove(struct platform_device *pdev)
180 return 0; 256 return 0;
181} 257}
182 258
259static const struct of_device_id i2c_mux_gpio_of_match[] __devinitconst = {
260 { .compatible = "i2c-mux-gpio", },
261 {},
262};
263MODULE_DEVICE_TABLE(of, i2c_mux_gpio_of_match);
264
183static struct platform_driver i2c_mux_gpio_driver = { 265static struct platform_driver i2c_mux_gpio_driver = {
184 .probe = i2c_mux_gpio_probe, 266 .probe = i2c_mux_gpio_probe,
185 .remove = __devexit_p(i2c_mux_gpio_remove), 267 .remove = __devexit_p(i2c_mux_gpio_remove),
186 .driver = { 268 .driver = {
187 .owner = THIS_MODULE, 269 .owner = THIS_MODULE,
188 .name = "i2c-mux-gpio", 270 .name = "i2c-mux-gpio",
271 .of_match_table = of_match_ptr(i2c_mux_gpio_of_match),
189 }, 272 },
190}; 273};
191 274
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-12 00:46:28 -0500