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-rw-r--r--drivers/dma/omap-dma.c2
-rw-r--r--drivers/gpio/gpio-omap.c15
-rw-r--r--drivers/gpio/gpio-samsung.c40
-rw-r--r--drivers/gpio/gpio-tegra.c3
-rw-r--r--drivers/gpio/gpio-twl4030.c15
-rw-r--r--drivers/i2c/busses/Kconfig2
-rw-r--r--drivers/i2c/busses/i2c-iop3xx.c121
-rw-r--r--drivers/input/keyboard/Kconfig2
-rw-r--r--drivers/input/keyboard/omap-keypad.c156
-rw-r--r--drivers/input/mouse/rpcmouse.c2
-rw-r--r--drivers/input/serio/ams_delta_serio.c2
-rw-r--r--drivers/media/video/omap/omap_vout.c1
-rw-r--r--drivers/media/video/omap3isp/isp.c2
-rw-r--r--drivers/mfd/twl-core.c54
-rw-r--r--drivers/mmc/host/omap.c2
-rw-r--r--drivers/mmc/host/omap_hsmmc.c1
-rw-r--r--drivers/mmc/host/sdhci-tegra.c1
-rw-r--r--drivers/mtd/nand/ams-delta.c10
-rw-r--r--drivers/mtd/nand/bcm_umi_nand.c12
-rw-r--r--drivers/mtd/nand/nand_bcm_umi.h73
-rw-r--r--drivers/mtd/nand/omap2.c303
-rw-r--r--drivers/mtd/onenand/omap2.c34
-rw-r--r--drivers/net/ethernet/seeq/ether3.c4
-rw-r--r--drivers/pcmcia/omap_cf.c2
-rw-r--r--drivers/pinctrl/pinctrl-coh901.c220
-rw-r--r--drivers/power/avs/smartreflex.c2
-rw-r--r--drivers/remoteproc/omap_remoteproc.c2
-rw-r--r--drivers/scsi/arm/eesox.c2
-rw-r--r--drivers/spi/Kconfig2
-rw-r--r--drivers/spi/spi-omap-uwire.c5
-rw-r--r--drivers/spi/spi-omap2-mcspi.c2
-rw-r--r--drivers/spi/spi-tegra.c55
-rw-r--r--drivers/staging/tidspbridge/core/dsp-clock.c2
-rw-r--r--drivers/staging/tidspbridge/core/tiomap3430.c2
-rw-r--r--drivers/staging/tidspbridge/core/tiomap3430_pwr.c2
-rw-r--r--drivers/staging/tidspbridge/core/tiomap_io.c2
-rw-r--r--drivers/staging/tidspbridge/core/wdt.c2
-rw-r--r--drivers/staging/tidspbridge/rmgr/drv_interface.c2
-rw-r--r--drivers/tty/serial/serial_ks8695.c4
-rw-r--r--drivers/usb/Kconfig1
-rw-r--r--drivers/usb/host/Kconfig2
-rw-r--r--drivers/usb/host/ohci-hcd.c2
-rw-r--r--drivers/usb/host/ohci-nxp.c84
-rw-r--r--drivers/usb/host/ohci-omap.c2
-rw-r--r--drivers/usb/musb/tusb6010_omap.c1
-rw-r--r--drivers/usb/otg/isp1301_omap.c2
-rw-r--r--drivers/video/backlight/omap1_bl.c4
-rw-r--r--drivers/video/da8xx-fb.c8
-rw-r--r--drivers/video/omap/lcd_ams_delta.c3
-rw-r--r--drivers/video/omap/lcd_mipid.c2
-rw-r--r--drivers/video/omap/lcd_osk.c2
-rw-r--r--drivers/video/omap2/dss/dispc.c1
-rw-r--r--drivers/video/omap2/omapfb/omapfb-main.c1
-rw-r--r--drivers/watchdog/Kconfig6
-rw-r--r--drivers/watchdog/ks8695_wdt.c14
-rw-r--r--drivers/watchdog/omap_wdt.c5
56 files changed, 547 insertions, 758 deletions
diff --git a/drivers/dma/omap-dma.c b/drivers/dma/omap-dma.c
index ae0561826137..2e1662777661 100644
--- a/drivers/dma/omap-dma.c
+++ b/drivers/dma/omap-dma.c
@@ -18,6 +18,8 @@
18#include <linux/spinlock.h> 18#include <linux/spinlock.h>
19 19
20#include "virt-dma.h" 20#include "virt-dma.h"
21
22#include <plat/cpu.h>
21#include <plat/dma.h> 23#include <plat/dma.h>
22 24
23struct omap_dmadev { 25struct omap_dmadev {
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 0725d181581f..94cbc842fbc3 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -25,11 +25,9 @@
25#include <linux/of.h> 25#include <linux/of.h>
26#include <linux/of_device.h> 26#include <linux/of_device.h>
27#include <linux/irqdomain.h> 27#include <linux/irqdomain.h>
28#include <linux/gpio.h>
29#include <linux/platform_data/gpio-omap.h>
28 30
29#include <mach/hardware.h>
30#include <asm/irq.h>
31#include <mach/irqs.h>
32#include <asm/gpio.h>
33#include <asm/mach/irq.h> 31#include <asm/mach/irq.h>
34 32
35#define OFF_MODE 1 33#define OFF_MODE 1
@@ -385,13 +383,16 @@ static int _set_gpio_triggering(struct gpio_bank *bank, int gpio,
385static int gpio_irq_type(struct irq_data *d, unsigned type) 383static int gpio_irq_type(struct irq_data *d, unsigned type)
386{ 384{
387 struct gpio_bank *bank = irq_data_get_irq_chip_data(d); 385 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
388 unsigned gpio; 386 unsigned gpio = 0;
389 int retval; 387 int retval;
390 unsigned long flags; 388 unsigned long flags;
391 389
392 if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE) 390#ifdef CONFIG_ARCH_OMAP1
391 if (d->irq > IH_MPUIO_BASE)
393 gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE); 392 gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
394 else 393#endif
394
395 if (!gpio)
395 gpio = irq_to_gpio(bank, d->irq); 396 gpio = irq_to_gpio(bank, d->irq);
396 397
397 if (type & ~IRQ_TYPE_SENSE_MASK) 398 if (type & ~IRQ_TYPE_SENSE_MASK)
diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index ba126cc04073..1c169324e357 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -3131,46 +3131,6 @@ samsung_gpio_pull_t s3c_gpio_getpull(unsigned int pin)
3131} 3131}
3132EXPORT_SYMBOL(s3c_gpio_getpull); 3132EXPORT_SYMBOL(s3c_gpio_getpull);
3133 3133
3134/* gpiolib wrappers until these are totally eliminated */
3135
3136void s3c2410_gpio_pullup(unsigned int pin, unsigned int to)
3137{
3138 int ret;
3139
3140 WARN_ON(to); /* should be none of these left */
3141
3142 if (!to) {
3143 /* if pull is enabled, try first with up, and if that
3144 * fails, try using down */
3145
3146 ret = s3c_gpio_setpull(pin, S3C_GPIO_PULL_UP);
3147 if (ret)
3148 s3c_gpio_setpull(pin, S3C_GPIO_PULL_DOWN);
3149 } else {
3150 s3c_gpio_setpull(pin, S3C_GPIO_PULL_NONE);
3151 }
3152}
3153EXPORT_SYMBOL(s3c2410_gpio_pullup);
3154
3155void s3c2410_gpio_setpin(unsigned int pin, unsigned int to)
3156{
3157 /* do this via gpiolib until all users removed */
3158
3159 gpio_request(pin, "temporary");
3160 gpio_set_value(pin, to);
3161 gpio_free(pin);
3162}
3163EXPORT_SYMBOL(s3c2410_gpio_setpin);
3164
3165unsigned int s3c2410_gpio_getpin(unsigned int pin)
3166{
3167 struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin);
3168 unsigned long offs = pin - chip->chip.base;
3169
3170 return __raw_readl(chip->base + 0x04) & (1 << offs);
3171}
3172EXPORT_SYMBOL(s3c2410_gpio_getpin);
3173
3174#ifdef CONFIG_S5P_GPIO_DRVSTR 3134#ifdef CONFIG_S5P_GPIO_DRVSTR
3175s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin) 3135s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin)
3176{ 3136{
diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c
index dc5184d57892..d982593d7563 100644
--- a/drivers/gpio/gpio-tegra.c
+++ b/drivers/gpio/gpio-tegra.c
@@ -30,9 +30,6 @@
30 30
31#include <asm/mach/irq.h> 31#include <asm/mach/irq.h>
32 32
33#include <mach/iomap.h>
34#include <mach/suspend.h>
35
36#define GPIO_BANK(x) ((x) >> 5) 33#define GPIO_BANK(x) ((x) >> 5)
37#define GPIO_PORT(x) (((x) >> 3) & 0x3) 34#define GPIO_PORT(x) (((x) >> 3) & 0x3)
38#define GPIO_BIT(x) ((x) & 0x7) 35#define GPIO_BIT(x) ((x) & 0x7)
diff --git a/drivers/gpio/gpio-twl4030.c b/drivers/gpio/gpio-twl4030.c
index 94256fe7bf36..f030880bc9bb 100644
--- a/drivers/gpio/gpio-twl4030.c
+++ b/drivers/gpio/gpio-twl4030.c
@@ -51,6 +51,7 @@
51 51
52 52
53static struct gpio_chip twl_gpiochip; 53static struct gpio_chip twl_gpiochip;
54static int twl4030_gpio_base;
54static int twl4030_gpio_irq_base; 55static int twl4030_gpio_irq_base;
55 56
56/* genirq interfaces are not available to modules */ 57/* genirq interfaces are not available to modules */
@@ -428,8 +429,6 @@ no_irqs:
428 twl_gpiochip.dev = &pdev->dev; 429 twl_gpiochip.dev = &pdev->dev;
429 430
430 if (pdata) { 431 if (pdata) {
431 twl_gpiochip.base = pdata->gpio_base;
432
433 /* 432 /*
434 * NOTE: boards may waste power if they don't set pullups 433 * NOTE: boards may waste power if they don't set pullups
435 * and pulldowns correctly ... default for non-ULPI pins is 434 * and pulldowns correctly ... default for non-ULPI pins is
@@ -461,15 +460,21 @@ no_irqs:
461 dev_err(&pdev->dev, "could not register gpiochip, %d\n", ret); 460 dev_err(&pdev->dev, "could not register gpiochip, %d\n", ret);
462 twl_gpiochip.ngpio = 0; 461 twl_gpiochip.ngpio = 0;
463 gpio_twl4030_remove(pdev); 462 gpio_twl4030_remove(pdev);
464 } else if (pdata && pdata->setup) { 463 goto out;
464 }
465
466 twl4030_gpio_base = twl_gpiochip.base;
467
468 if (pdata && pdata->setup) {
465 int status; 469 int status;
466 470
467 status = pdata->setup(&pdev->dev, 471 status = pdata->setup(&pdev->dev,
468 pdata->gpio_base, TWL4030_GPIO_MAX); 472 twl4030_gpio_base, TWL4030_GPIO_MAX);
469 if (status) 473 if (status)
470 dev_dbg(&pdev->dev, "setup --> %d\n", status); 474 dev_dbg(&pdev->dev, "setup --> %d\n", status);
471 } 475 }
472 476
477out:
473 return ret; 478 return ret;
474} 479}
475 480
@@ -481,7 +486,7 @@ static int gpio_twl4030_remove(struct platform_device *pdev)
481 486
482 if (pdata && pdata->teardown) { 487 if (pdata && pdata->teardown) {
483 status = pdata->teardown(&pdev->dev, 488 status = pdata->teardown(&pdev->dev,
484 pdata->gpio_base, TWL4030_GPIO_MAX); 489 twl4030_gpio_base, TWL4030_GPIO_MAX);
485 if (status) { 490 if (status) {
486 dev_dbg(&pdev->dev, "teardown --> %d\n", status); 491 dev_dbg(&pdev->dev, "teardown --> %d\n", status);
487 return status; 492 return status;
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 970a1612e795..42d9fdd63de0 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -551,7 +551,7 @@ config I2C_PMCMSP
551 551
552config I2C_PNX 552config I2C_PNX
553 tristate "I2C bus support for Philips PNX and NXP LPC targets" 553 tristate "I2C bus support for Philips PNX and NXP LPC targets"
554 depends on ARCH_PNX4008 || ARCH_LPC32XX 554 depends on ARCH_LPC32XX
555 help 555 help
556 This driver supports the Philips IP3204 I2C IP block master and/or 556 This driver supports the Philips IP3204 I2C IP block master and/or
557 slave controller 557 slave controller
diff --git a/drivers/i2c/busses/i2c-iop3xx.c b/drivers/i2c/busses/i2c-iop3xx.c
index 93f147a96b62..2f99613fd677 100644
--- a/drivers/i2c/busses/i2c-iop3xx.c
+++ b/drivers/i2c/busses/i2c-iop3xx.c
@@ -4,13 +4,13 @@
4/* Copyright (C) 2003 Peter Milne, D-TACQ Solutions Ltd 4/* Copyright (C) 2003 Peter Milne, D-TACQ Solutions Ltd
5 * <Peter dot Milne at D hyphen TACQ dot com> 5 * <Peter dot Milne at D hyphen TACQ dot com>
6 * 6 *
7 * With acknowledgements to i2c-algo-ibm_ocp.c by 7 * With acknowledgements to i2c-algo-ibm_ocp.c by
8 * Ian DaSilva, MontaVista Software, Inc. idasilva@mvista.com 8 * Ian DaSilva, MontaVista Software, Inc. idasilva@mvista.com
9 * 9 *
10 * And i2c-algo-pcf.c, which was created by Simon G. Vogl and Hans Berglund: 10 * And i2c-algo-pcf.c, which was created by Simon G. Vogl and Hans Berglund:
11 * 11 *
12 * Copyright (C) 1995-1997 Simon G. Vogl, 1998-2000 Hans Berglund 12 * Copyright (C) 1995-1997 Simon G. Vogl, 1998-2000 Hans Berglund
13 * 13 *
14 * And which acknowledged Kyösti Mälkki <kmalkki@cc.hut.fi>, 14 * And which acknowledged Kyösti Mälkki <kmalkki@cc.hut.fi>,
15 * Frodo Looijaard <frodol@dds.nl>, Martin Bailey<mbailey@littlefeet-inc.com> 15 * Frodo Looijaard <frodol@dds.nl>, Martin Bailey<mbailey@littlefeet-inc.com>
16 * 16 *
@@ -39,14 +39,15 @@
39#include <linux/platform_device.h> 39#include <linux/platform_device.h>
40#include <linux/i2c.h> 40#include <linux/i2c.h>
41#include <linux/io.h> 41#include <linux/io.h>
42#include <linux/gpio.h>
42 43
43#include "i2c-iop3xx.h" 44#include "i2c-iop3xx.h"
44 45
45/* global unit counter */ 46/* global unit counter */
46static int i2c_id; 47static int i2c_id;
47 48
48static inline unsigned char 49static inline unsigned char
49iic_cook_addr(struct i2c_msg *msg) 50iic_cook_addr(struct i2c_msg *msg)
50{ 51{
51 unsigned char addr; 52 unsigned char addr;
52 53
@@ -55,38 +56,38 @@ iic_cook_addr(struct i2c_msg *msg)
55 if (msg->flags & I2C_M_RD) 56 if (msg->flags & I2C_M_RD)
56 addr |= 1; 57 addr |= 1;
57 58
58 return addr; 59 return addr;
59} 60}
60 61
61static void 62static void
62iop3xx_i2c_reset(struct i2c_algo_iop3xx_data *iop3xx_adap) 63iop3xx_i2c_reset(struct i2c_algo_iop3xx_data *iop3xx_adap)
63{ 64{
64 /* Follows devman 9.3 */ 65 /* Follows devman 9.3 */
65 __raw_writel(IOP3XX_ICR_UNIT_RESET, iop3xx_adap->ioaddr + CR_OFFSET); 66 __raw_writel(IOP3XX_ICR_UNIT_RESET, iop3xx_adap->ioaddr + CR_OFFSET);
66 __raw_writel(IOP3XX_ISR_CLEARBITS, iop3xx_adap->ioaddr + SR_OFFSET); 67 __raw_writel(IOP3XX_ISR_CLEARBITS, iop3xx_adap->ioaddr + SR_OFFSET);
67 __raw_writel(0, iop3xx_adap->ioaddr + CR_OFFSET); 68 __raw_writel(0, iop3xx_adap->ioaddr + CR_OFFSET);
68} 69}
69 70
70static void 71static void
71iop3xx_i2c_enable(struct i2c_algo_iop3xx_data *iop3xx_adap) 72iop3xx_i2c_enable(struct i2c_algo_iop3xx_data *iop3xx_adap)
72{ 73{
73 u32 cr = IOP3XX_ICR_GCD | IOP3XX_ICR_SCLEN | IOP3XX_ICR_UE; 74 u32 cr = IOP3XX_ICR_GCD | IOP3XX_ICR_SCLEN | IOP3XX_ICR_UE;
74 75
75 /* 76 /*
76 * Every time unit enable is asserted, GPOD needs to be cleared 77 * Every time unit enable is asserted, GPOD needs to be cleared
77 * on IOP3XX to avoid data corruption on the bus. 78 * on IOP3XX to avoid data corruption on the bus.
78 */ 79 */
79#if defined(CONFIG_ARCH_IOP32X) || defined(CONFIG_ARCH_IOP33X) 80#if defined(CONFIG_ARCH_IOP32X) || defined(CONFIG_ARCH_IOP33X)
80 if (iop3xx_adap->id == 0) { 81 if (iop3xx_adap->id == 0) {
81 gpio_line_set(IOP3XX_GPIO_LINE(7), GPIO_LOW); 82 gpio_set_value(7, 0);
82 gpio_line_set(IOP3XX_GPIO_LINE(6), GPIO_LOW); 83 gpio_set_value(6, 0);
83 } else { 84 } else {
84 gpio_line_set(IOP3XX_GPIO_LINE(5), GPIO_LOW); 85 gpio_set_value(5, 0);
85 gpio_line_set(IOP3XX_GPIO_LINE(4), GPIO_LOW); 86 gpio_set_value(4, 0);
86 } 87 }
87#endif 88#endif
88 /* NB SR bits not same position as CR IE bits :-( */ 89 /* NB SR bits not same position as CR IE bits :-( */
89 iop3xx_adap->SR_enabled = 90 iop3xx_adap->SR_enabled =
90 IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD | 91 IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD |
91 IOP3XX_ISR_RXFULL | IOP3XX_ISR_TXEMPTY; 92 IOP3XX_ISR_RXFULL | IOP3XX_ISR_TXEMPTY;
92 93
@@ -96,23 +97,23 @@ iop3xx_i2c_enable(struct i2c_algo_iop3xx_data *iop3xx_adap)
96 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET); 97 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
97} 98}
98 99
99static void 100static void
100iop3xx_i2c_transaction_cleanup(struct i2c_algo_iop3xx_data *iop3xx_adap) 101iop3xx_i2c_transaction_cleanup(struct i2c_algo_iop3xx_data *iop3xx_adap)
101{ 102{
102 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET); 103 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
103 104
104 cr &= ~(IOP3XX_ICR_MSTART | IOP3XX_ICR_TBYTE | 105 cr &= ~(IOP3XX_ICR_MSTART | IOP3XX_ICR_TBYTE |
105 IOP3XX_ICR_MSTOP | IOP3XX_ICR_SCLEN); 106 IOP3XX_ICR_MSTOP | IOP3XX_ICR_SCLEN);
106 107
107 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET); 108 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
108} 109}
109 110
110/* 111/*
111 * NB: the handler has to clear the source of the interrupt! 112 * NB: the handler has to clear the source of the interrupt!
112 * Then it passes the SR flags of interest to BH via adap data 113 * Then it passes the SR flags of interest to BH via adap data
113 */ 114 */
114static irqreturn_t 115static irqreturn_t
115iop3xx_i2c_irq_handler(int this_irq, void *dev_id) 116iop3xx_i2c_irq_handler(int this_irq, void *dev_id)
116{ 117{
117 struct i2c_algo_iop3xx_data *iop3xx_adap = dev_id; 118 struct i2c_algo_iop3xx_data *iop3xx_adap = dev_id;
118 u32 sr = __raw_readl(iop3xx_adap->ioaddr + SR_OFFSET); 119 u32 sr = __raw_readl(iop3xx_adap->ioaddr + SR_OFFSET);
@@ -126,7 +127,7 @@ iop3xx_i2c_irq_handler(int this_irq, void *dev_id)
126} 127}
127 128
128/* check all error conditions, clear them , report most important */ 129/* check all error conditions, clear them , report most important */
129static int 130static int
130iop3xx_i2c_error(u32 sr) 131iop3xx_i2c_error(u32 sr)
131{ 132{
132 int rc = 0; 133 int rc = 0;
@@ -135,12 +136,12 @@ iop3xx_i2c_error(u32 sr)
135 if ( !rc ) rc = -I2C_ERR_BERR; 136 if ( !rc ) rc = -I2C_ERR_BERR;
136 } 137 }
137 if ((sr & IOP3XX_ISR_ALD)) { 138 if ((sr & IOP3XX_ISR_ALD)) {
138 if ( !rc ) rc = -I2C_ERR_ALD; 139 if ( !rc ) rc = -I2C_ERR_ALD;
139 } 140 }
140 return rc; 141 return rc;
141} 142}
142 143
143static inline u32 144static inline u32
144iop3xx_i2c_get_srstat(struct i2c_algo_iop3xx_data *iop3xx_adap) 145iop3xx_i2c_get_srstat(struct i2c_algo_iop3xx_data *iop3xx_adap)
145{ 146{
146 unsigned long flags; 147 unsigned long flags;
@@ -161,8 +162,8 @@ iop3xx_i2c_get_srstat(struct i2c_algo_iop3xx_data *iop3xx_adap)
161typedef int (* compare_func)(unsigned test, unsigned mask); 162typedef int (* compare_func)(unsigned test, unsigned mask);
162/* returns 1 on correct comparison */ 163/* returns 1 on correct comparison */
163 164
164static int 165static int
165iop3xx_i2c_wait_event(struct i2c_algo_iop3xx_data *iop3xx_adap, 166iop3xx_i2c_wait_event(struct i2c_algo_iop3xx_data *iop3xx_adap,
166 unsigned flags, unsigned* status, 167 unsigned flags, unsigned* status,
167 compare_func compare) 168 compare_func compare)
168{ 169{
@@ -192,47 +193,47 @@ iop3xx_i2c_wait_event(struct i2c_algo_iop3xx_data *iop3xx_adap,
192} 193}
193 194
194/* 195/*
195 * Concrete compare_funcs 196 * Concrete compare_funcs
196 */ 197 */
197static int 198static int
198all_bits_clear(unsigned test, unsigned mask) 199all_bits_clear(unsigned test, unsigned mask)
199{ 200{
200 return (test & mask) == 0; 201 return (test & mask) == 0;
201} 202}
202 203
203static int 204static int
204any_bits_set(unsigned test, unsigned mask) 205any_bits_set(unsigned test, unsigned mask)
205{ 206{
206 return (test & mask) != 0; 207 return (test & mask) != 0;
207} 208}
208 209
209static int 210static int
210iop3xx_i2c_wait_tx_done(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status) 211iop3xx_i2c_wait_tx_done(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status)
211{ 212{
212 return iop3xx_i2c_wait_event( 213 return iop3xx_i2c_wait_event(
213 iop3xx_adap, 214 iop3xx_adap,
214 IOP3XX_ISR_TXEMPTY | IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD, 215 IOP3XX_ISR_TXEMPTY | IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD,
215 status, any_bits_set); 216 status, any_bits_set);
216} 217}
217 218
218static int 219static int
219iop3xx_i2c_wait_rx_done(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status) 220iop3xx_i2c_wait_rx_done(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status)
220{ 221{
221 return iop3xx_i2c_wait_event( 222 return iop3xx_i2c_wait_event(
222 iop3xx_adap, 223 iop3xx_adap,
223 IOP3XX_ISR_RXFULL | IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD, 224 IOP3XX_ISR_RXFULL | IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD,
224 status, any_bits_set); 225 status, any_bits_set);
225} 226}
226 227
227static int 228static int
228iop3xx_i2c_wait_idle(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status) 229iop3xx_i2c_wait_idle(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status)
229{ 230{
230 return iop3xx_i2c_wait_event( 231 return iop3xx_i2c_wait_event(
231 iop3xx_adap, IOP3XX_ISR_UNITBUSY, status, all_bits_clear); 232 iop3xx_adap, IOP3XX_ISR_UNITBUSY, status, all_bits_clear);
232} 233}
233 234
234static int 235static int
235iop3xx_i2c_send_target_addr(struct i2c_algo_iop3xx_data *iop3xx_adap, 236iop3xx_i2c_send_target_addr(struct i2c_algo_iop3xx_data *iop3xx_adap,
236 struct i2c_msg* msg) 237 struct i2c_msg* msg)
237{ 238{
238 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET); 239 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
@@ -247,7 +248,7 @@ iop3xx_i2c_send_target_addr(struct i2c_algo_iop3xx_data *iop3xx_adap,
247 } 248 }
248 249
249 __raw_writel(iic_cook_addr(msg), iop3xx_adap->ioaddr + DBR_OFFSET); 250 __raw_writel(iic_cook_addr(msg), iop3xx_adap->ioaddr + DBR_OFFSET);
250 251
251 cr &= ~(IOP3XX_ICR_MSTOP | IOP3XX_ICR_NACK); 252 cr &= ~(IOP3XX_ICR_MSTOP | IOP3XX_ICR_NACK);
252 cr |= IOP3XX_ICR_MSTART | IOP3XX_ICR_TBYTE; 253 cr |= IOP3XX_ICR_MSTART | IOP3XX_ICR_TBYTE;
253 254
@@ -257,8 +258,8 @@ iop3xx_i2c_send_target_addr(struct i2c_algo_iop3xx_data *iop3xx_adap,
257 return rc; 258 return rc;
258} 259}
259 260
260static int 261static int
261iop3xx_i2c_write_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char byte, 262iop3xx_i2c_write_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char byte,
262 int stop) 263 int stop)
263{ 264{
264 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET); 265 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
@@ -277,10 +278,10 @@ iop3xx_i2c_write_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char byte,
277 rc = iop3xx_i2c_wait_tx_done(iop3xx_adap, &status); 278 rc = iop3xx_i2c_wait_tx_done(iop3xx_adap, &status);
278 279
279 return rc; 280 return rc;
280} 281}
281 282
282static int 283static int
283iop3xx_i2c_read_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char* byte, 284iop3xx_i2c_read_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char* byte,
284 int stop) 285 int stop)
285{ 286{
286 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET); 287 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
@@ -304,19 +305,19 @@ iop3xx_i2c_read_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char* byte,
304 return rc; 305 return rc;
305} 306}
306 307
307static int 308static int
308iop3xx_i2c_writebytes(struct i2c_adapter *i2c_adap, const char *buf, int count) 309iop3xx_i2c_writebytes(struct i2c_adapter *i2c_adap, const char *buf, int count)
309{ 310{
310 struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data; 311 struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
311 int ii; 312 int ii;
312 int rc = 0; 313 int rc = 0;
313 314
314 for (ii = 0; rc == 0 && ii != count; ++ii) 315 for (ii = 0; rc == 0 && ii != count; ++ii)
315 rc = iop3xx_i2c_write_byte(iop3xx_adap, buf[ii], ii==count-1); 316 rc = iop3xx_i2c_write_byte(iop3xx_adap, buf[ii], ii==count-1);
316 return rc; 317 return rc;
317} 318}
318 319
319static int 320static int
320iop3xx_i2c_readbytes(struct i2c_adapter *i2c_adap, char *buf, int count) 321iop3xx_i2c_readbytes(struct i2c_adapter *i2c_adap, char *buf, int count)
321{ 322{
322 struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data; 323 struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
@@ -325,7 +326,7 @@ iop3xx_i2c_readbytes(struct i2c_adapter *i2c_adap, char *buf, int count)
325 326
326 for (ii = 0; rc == 0 && ii != count; ++ii) 327 for (ii = 0; rc == 0 && ii != count; ++ii)
327 rc = iop3xx_i2c_read_byte(iop3xx_adap, &buf[ii], ii==count-1); 328 rc = iop3xx_i2c_read_byte(iop3xx_adap, &buf[ii], ii==count-1);
328 329
329 return rc; 330 return rc;
330} 331}
331 332
@@ -336,8 +337,8 @@ iop3xx_i2c_readbytes(struct i2c_adapter *i2c_adap, char *buf, int count)
336 * Each transfer (i.e. a read or a write) is separated by a repeated start 337 * Each transfer (i.e. a read or a write) is separated by a repeated start
337 * condition. 338 * condition.
338 */ 339 */
339static int 340static int
340iop3xx_i2c_handle_msg(struct i2c_adapter *i2c_adap, struct i2c_msg* pmsg) 341iop3xx_i2c_handle_msg(struct i2c_adapter *i2c_adap, struct i2c_msg* pmsg)
341{ 342{
342 struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data; 343 struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
343 int rc; 344 int rc;
@@ -357,8 +358,8 @@ iop3xx_i2c_handle_msg(struct i2c_adapter *i2c_adap, struct i2c_msg* pmsg)
357/* 358/*
358 * master_xfer() - main read/write entry 359 * master_xfer() - main read/write entry
359 */ 360 */
360static int 361static int
361iop3xx_i2c_master_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs, 362iop3xx_i2c_master_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
362 int num) 363 int num)
363{ 364{
364 struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data; 365 struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
@@ -375,14 +376,14 @@ iop3xx_i2c_master_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
375 } 376 }
376 377
377 iop3xx_i2c_transaction_cleanup(iop3xx_adap); 378 iop3xx_i2c_transaction_cleanup(iop3xx_adap);
378 379
379 if(ret) 380 if(ret)
380 return ret; 381 return ret;
381 382
382 return im; 383 return im;
383} 384}
384 385
385static u32 386static u32
386iop3xx_i2c_func(struct i2c_adapter *adap) 387iop3xx_i2c_func(struct i2c_adapter *adap)
387{ 388{
388 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 389 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
@@ -393,11 +394,11 @@ static const struct i2c_algorithm iop3xx_i2c_algo = {
393 .functionality = iop3xx_i2c_func, 394 .functionality = iop3xx_i2c_func,
394}; 395};
395 396
396static int 397static int
397iop3xx_i2c_remove(struct platform_device *pdev) 398iop3xx_i2c_remove(struct platform_device *pdev)
398{ 399{
399 struct i2c_adapter *padapter = platform_get_drvdata(pdev); 400 struct i2c_adapter *padapter = platform_get_drvdata(pdev);
400 struct i2c_algo_iop3xx_data *adapter_data = 401 struct i2c_algo_iop3xx_data *adapter_data =
401 (struct i2c_algo_iop3xx_data *)padapter->algo_data; 402 (struct i2c_algo_iop3xx_data *)padapter->algo_data;
402 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 403 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
403 unsigned long cr = __raw_readl(adapter_data->ioaddr + CR_OFFSET); 404 unsigned long cr = __raw_readl(adapter_data->ioaddr + CR_OFFSET);
@@ -419,7 +420,7 @@ iop3xx_i2c_remove(struct platform_device *pdev)
419 return 0; 420 return 0;
420} 421}
421 422
422static int 423static int
423iop3xx_i2c_probe(struct platform_device *pdev) 424iop3xx_i2c_probe(struct platform_device *pdev)
424{ 425{
425 struct resource *res; 426 struct resource *res;
diff --git a/drivers/input/keyboard/Kconfig b/drivers/input/keyboard/Kconfig
index c50fa75416f8..b4b65af8612a 100644
--- a/drivers/input/keyboard/Kconfig
+++ b/drivers/input/keyboard/Kconfig
@@ -533,7 +533,7 @@ config KEYBOARD_DAVINCI
533 533
534config KEYBOARD_OMAP 534config KEYBOARD_OMAP
535 tristate "TI OMAP keypad support" 535 tristate "TI OMAP keypad support"
536 depends on (ARCH_OMAP1 || ARCH_OMAP2) 536 depends on ARCH_OMAP1
537 select INPUT_MATRIXKMAP 537 select INPUT_MATRIXKMAP
538 help 538 help
539 Say Y here if you want to use the OMAP keypad. 539 Say Y here if you want to use the OMAP keypad.
diff --git a/drivers/input/keyboard/omap-keypad.c b/drivers/input/keyboard/omap-keypad.c
index a0222db4dc86..6d6b1427ae12 100644
--- a/drivers/input/keyboard/omap-keypad.c
+++ b/drivers/input/keyboard/omap-keypad.c
@@ -35,13 +35,9 @@
35#include <linux/mutex.h> 35#include <linux/mutex.h>
36#include <linux/errno.h> 36#include <linux/errno.h>
37#include <linux/slab.h> 37#include <linux/slab.h>
38#include <asm/gpio.h> 38#include <linux/gpio.h>
39#include <plat/keypad.h> 39#include <linux/platform_data/gpio-omap.h>
40#include <plat/menelaus.h> 40#include <linux/platform_data/keypad-omap.h>
41#include <asm/irq.h>
42#include <mach/hardware.h>
43#include <asm/io.h>
44#include <plat/mux.h>
45 41
46#undef NEW_BOARD_LEARNING_MODE 42#undef NEW_BOARD_LEARNING_MODE
47 43
@@ -96,28 +92,8 @@ static u8 get_row_gpio_val(struct omap_kp *omap_kp)
96 92
97static irqreturn_t omap_kp_interrupt(int irq, void *dev_id) 93static irqreturn_t omap_kp_interrupt(int irq, void *dev_id)
98{ 94{
99 struct omap_kp *omap_kp = dev_id;
100
101 /* disable keyboard interrupt and schedule for handling */ 95 /* disable keyboard interrupt and schedule for handling */
102 if (cpu_is_omap24xx()) { 96 omap_writew(1, OMAP1_MPUIO_BASE + OMAP_MPUIO_KBD_MASKIT);
103 int i;
104
105 for (i = 0; i < omap_kp->rows; i++) {
106 int gpio_irq = gpio_to_irq(row_gpios[i]);
107 /*
108 * The interrupt which we're currently handling should
109 * be disabled _nosync() to avoid deadlocks waiting
110 * for this handler to complete. All others should
111 * be disabled the regular way for SMP safety.
112 */
113 if (gpio_irq == irq)
114 disable_irq_nosync(gpio_irq);
115 else
116 disable_irq(gpio_irq);
117 }
118 } else
119 /* disable keyboard interrupt and schedule for handling */
120 omap_writew(1, OMAP1_MPUIO_BASE + OMAP_MPUIO_KBD_MASKIT);
121 97
122 tasklet_schedule(&kp_tasklet); 98 tasklet_schedule(&kp_tasklet);
123 99
@@ -133,33 +109,22 @@ static void omap_kp_scan_keypad(struct omap_kp *omap_kp, unsigned char *state)
133{ 109{
134 int col = 0; 110 int col = 0;
135 111
136 /* read the keypad status */ 112 /* disable keyboard interrupt and schedule for handling */
137 if (cpu_is_omap24xx()) { 113 omap_writew(1, OMAP1_MPUIO_BASE + OMAP_MPUIO_KBD_MASKIT);
138 /* read the keypad status */
139 for (col = 0; col < omap_kp->cols; col++) {
140 set_col_gpio_val(omap_kp, ~(1 << col));
141 state[col] = ~(get_row_gpio_val(omap_kp)) & 0xff;
142 }
143 set_col_gpio_val(omap_kp, 0);
144
145 } else {
146 /* disable keyboard interrupt and schedule for handling */
147 omap_writew(1, OMAP1_MPUIO_BASE + OMAP_MPUIO_KBD_MASKIT);
148 114
149 /* read the keypad status */ 115 /* read the keypad status */
150 omap_writew(0xff, OMAP1_MPUIO_BASE + OMAP_MPUIO_KBC); 116 omap_writew(0xff, OMAP1_MPUIO_BASE + OMAP_MPUIO_KBC);
151 for (col = 0; col < omap_kp->cols; col++) { 117 for (col = 0; col < omap_kp->cols; col++) {
152 omap_writew(~(1 << col) & 0xff, 118 omap_writew(~(1 << col) & 0xff,
153 OMAP1_MPUIO_BASE + OMAP_MPUIO_KBC); 119 OMAP1_MPUIO_BASE + OMAP_MPUIO_KBC);
154 120
155 udelay(omap_kp->delay); 121 udelay(omap_kp->delay);
156 122
157 state[col] = ~omap_readw(OMAP1_MPUIO_BASE + 123 state[col] = ~omap_readw(OMAP1_MPUIO_BASE +
158 OMAP_MPUIO_KBR_LATCH) & 0xff; 124 OMAP_MPUIO_KBR_LATCH) & 0xff;
159 }
160 omap_writew(0x00, OMAP1_MPUIO_BASE + OMAP_MPUIO_KBC);
161 udelay(2);
162 } 125 }
126 omap_writew(0x00, OMAP1_MPUIO_BASE + OMAP_MPUIO_KBC);
127 udelay(2);
163} 128}
164 129
165static void omap_kp_tasklet(unsigned long data) 130static void omap_kp_tasklet(unsigned long data)
@@ -222,14 +187,8 @@ static void omap_kp_tasklet(unsigned long data)
222 mod_timer(&omap_kp_data->timer, jiffies + delay); 187 mod_timer(&omap_kp_data->timer, jiffies + delay);
223 } else { 188 } else {
224 /* enable interrupts */ 189 /* enable interrupts */
225 if (cpu_is_omap24xx()) { 190 omap_writew(0, OMAP1_MPUIO_BASE + OMAP_MPUIO_KBD_MASKIT);
226 int i; 191 kp_cur_group = -1;
227 for (i = 0; i < omap_kp_data->rows; i++)
228 enable_irq(gpio_to_irq(row_gpios[i]));
229 } else {
230 omap_writew(0, OMAP1_MPUIO_BASE + OMAP_MPUIO_KBD_MASKIT);
231 kp_cur_group = -1;
232 }
233 } 192 }
234} 193}
235 194
@@ -242,6 +201,7 @@ static ssize_t omap_kp_enable_show(struct device *dev,
242static ssize_t omap_kp_enable_store(struct device *dev, struct device_attribute *attr, 201static ssize_t omap_kp_enable_store(struct device *dev, struct device_attribute *attr,
243 const char *buf, size_t count) 202 const char *buf, size_t count)
244{ 203{
204 struct omap_kp *omap_kp = dev_get_drvdata(dev);
245 int state; 205 int state;
246 206
247 if (sscanf(buf, "%u", &state) != 1) 207 if (sscanf(buf, "%u", &state) != 1)
@@ -253,9 +213,9 @@ static ssize_t omap_kp_enable_store(struct device *dev, struct device_attribute
253 mutex_lock(&kp_enable_mutex); 213 mutex_lock(&kp_enable_mutex);
254 if (state != kp_enable) { 214 if (state != kp_enable) {
255 if (state) 215 if (state)
256 enable_irq(INT_KEYBOARD); 216 enable_irq(omap_kp->irq);
257 else 217 else
258 disable_irq(INT_KEYBOARD); 218 disable_irq(omap_kp->irq);
259 kp_enable = state; 219 kp_enable = state;
260 } 220 }
261 mutex_unlock(&kp_enable_mutex); 221 mutex_unlock(&kp_enable_mutex);
@@ -289,7 +249,7 @@ static int __devinit omap_kp_probe(struct platform_device *pdev)
289 struct omap_kp *omap_kp; 249 struct omap_kp *omap_kp;
290 struct input_dev *input_dev; 250 struct input_dev *input_dev;
291 struct omap_kp_platform_data *pdata = pdev->dev.platform_data; 251 struct omap_kp_platform_data *pdata = pdev->dev.platform_data;
292 int i, col_idx, row_idx, irq_idx, ret; 252 int i, col_idx, row_idx, ret;
293 unsigned int row_shift, keycodemax; 253 unsigned int row_shift, keycodemax;
294 254
295 if (!pdata->rows || !pdata->cols || !pdata->keymap_data) { 255 if (!pdata->rows || !pdata->cols || !pdata->keymap_data) {
@@ -314,8 +274,7 @@ static int __devinit omap_kp_probe(struct platform_device *pdev)
314 omap_kp->input = input_dev; 274 omap_kp->input = input_dev;
315 275
316 /* Disable the interrupt for the MPUIO keyboard */ 276 /* Disable the interrupt for the MPUIO keyboard */
317 if (!cpu_is_omap24xx()) 277 omap_writew(1, OMAP1_MPUIO_BASE + OMAP_MPUIO_KBD_MASKIT);
318 omap_writew(1, OMAP1_MPUIO_BASE + OMAP_MPUIO_KBD_MASKIT);
319 278
320 if (pdata->delay) 279 if (pdata->delay)
321 omap_kp->delay = pdata->delay; 280 omap_kp->delay = pdata->delay;
@@ -328,31 +287,8 @@ static int __devinit omap_kp_probe(struct platform_device *pdev)
328 omap_kp->rows = pdata->rows; 287 omap_kp->rows = pdata->rows;
329 omap_kp->cols = pdata->cols; 288 omap_kp->cols = pdata->cols;
330 289
331 if (cpu_is_omap24xx()) { 290 col_idx = 0;
332 /* Cols: outputs */ 291 row_idx = 0;
333 for (col_idx = 0; col_idx < omap_kp->cols; col_idx++) {
334 if (gpio_request(col_gpios[col_idx], "omap_kp_col") < 0) {
335 printk(KERN_ERR "Failed to request"
336 "GPIO%d for keypad\n",
337 col_gpios[col_idx]);
338 goto err1;
339 }
340 gpio_direction_output(col_gpios[col_idx], 0);
341 }
342 /* Rows: inputs */
343 for (row_idx = 0; row_idx < omap_kp->rows; row_idx++) {
344 if (gpio_request(row_gpios[row_idx], "omap_kp_row") < 0) {
345 printk(KERN_ERR "Failed to request"
346 "GPIO%d for keypad\n",
347 row_gpios[row_idx]);
348 goto err2;
349 }
350 gpio_direction_input(row_gpios[row_idx]);
351 }
352 } else {
353 col_idx = 0;
354 row_idx = 0;
355 }
356 292
357 setup_timer(&omap_kp->timer, omap_kp_timer, (unsigned long)omap_kp); 293 setup_timer(&omap_kp->timer, omap_kp_timer, (unsigned long)omap_kp);
358 294
@@ -394,27 +330,16 @@ static int __devinit omap_kp_probe(struct platform_device *pdev)
394 330
395 /* scan current status and enable interrupt */ 331 /* scan current status and enable interrupt */
396 omap_kp_scan_keypad(omap_kp, keypad_state); 332 omap_kp_scan_keypad(omap_kp, keypad_state);
397 if (!cpu_is_omap24xx()) { 333 omap_kp->irq = platform_get_irq(pdev, 0);
398 omap_kp->irq = platform_get_irq(pdev, 0); 334 if (omap_kp->irq >= 0) {
399 if (omap_kp->irq >= 0) { 335 if (request_irq(omap_kp->irq, omap_kp_interrupt, 0,
400 if (request_irq(omap_kp->irq, omap_kp_interrupt, 0, 336 "omap-keypad", omap_kp) < 0)
401 "omap-keypad", omap_kp) < 0) 337 goto err4;
402 goto err4;
403 }
404 omap_writew(0, OMAP1_MPUIO_BASE + OMAP_MPUIO_KBD_MASKIT);
405 } else {
406 for (irq_idx = 0; irq_idx < omap_kp->rows; irq_idx++) {
407 if (request_irq(gpio_to_irq(row_gpios[irq_idx]),
408 omap_kp_interrupt,
409 IRQF_TRIGGER_FALLING,
410 "omap-keypad", omap_kp) < 0)
411 goto err5;
412 }
413 } 338 }
339 omap_writew(0, OMAP1_MPUIO_BASE + OMAP_MPUIO_KBD_MASKIT);
340
414 return 0; 341 return 0;
415err5: 342
416 for (i = irq_idx - 1; i >=0; i--)
417 free_irq(row_gpios[i], omap_kp);
418err4: 343err4:
419 input_unregister_device(omap_kp->input); 344 input_unregister_device(omap_kp->input);
420 input_dev = NULL; 345 input_dev = NULL;
@@ -423,7 +348,6 @@ err3:
423err2: 348err2:
424 for (i = row_idx - 1; i >=0; i--) 349 for (i = row_idx - 1; i >=0; i--)
425 gpio_free(row_gpios[i]); 350 gpio_free(row_gpios[i]);
426err1:
427 for (i = col_idx - 1; i >=0; i--) 351 for (i = col_idx - 1; i >=0; i--)
428 gpio_free(col_gpios[i]); 352 gpio_free(col_gpios[i]);
429 353
@@ -439,18 +363,8 @@ static int __devexit omap_kp_remove(struct platform_device *pdev)
439 363
440 /* disable keypad interrupt handling */ 364 /* disable keypad interrupt handling */
441 tasklet_disable(&kp_tasklet); 365 tasklet_disable(&kp_tasklet);
442 if (cpu_is_omap24xx()) { 366 omap_writew(1, OMAP1_MPUIO_BASE + OMAP_MPUIO_KBD_MASKIT);
443 int i; 367 free_irq(omap_kp->irq, omap_kp);
444 for (i = 0; i < omap_kp->cols; i++)
445 gpio_free(col_gpios[i]);
446 for (i = 0; i < omap_kp->rows; i++) {
447 gpio_free(row_gpios[i]);
448 free_irq(gpio_to_irq(row_gpios[i]), omap_kp);
449 }
450 } else {
451 omap_writew(1, OMAP1_MPUIO_BASE + OMAP_MPUIO_KBD_MASKIT);
452 free_irq(omap_kp->irq, omap_kp);
453 }
454 368
455 del_timer_sync(&omap_kp->timer); 369 del_timer_sync(&omap_kp->timer);
456 tasklet_kill(&kp_tasklet); 370 tasklet_kill(&kp_tasklet);
diff --git a/drivers/input/mouse/rpcmouse.c b/drivers/input/mouse/rpcmouse.c
index 272deddc8db6..21c60fea5d31 100644
--- a/drivers/input/mouse/rpcmouse.c
+++ b/drivers/input/mouse/rpcmouse.c
@@ -42,7 +42,7 @@ static irqreturn_t rpcmouse_irq(int irq, void *dev_id)
42 42
43 x = (short) iomd_readl(IOMD_MOUSEX); 43 x = (short) iomd_readl(IOMD_MOUSEX);
44 y = (short) iomd_readl(IOMD_MOUSEY); 44 y = (short) iomd_readl(IOMD_MOUSEY);
45 b = (short) (__raw_readl(0xe0310000) ^ 0x70); 45 b = (short) (__raw_readl(IOMEM(0xe0310000)) ^ 0x70);
46 46
47 dx = x - rpcmouse_lastx; 47 dx = x - rpcmouse_lastx;
48 dy = y - rpcmouse_lasty; 48 dy = y - rpcmouse_lasty;
diff --git a/drivers/input/serio/ams_delta_serio.c b/drivers/input/serio/ams_delta_serio.c
index f5fbdf94de3b..45887e31242a 100644
--- a/drivers/input/serio/ams_delta_serio.c
+++ b/drivers/input/serio/ams_delta_serio.c
@@ -27,7 +27,7 @@
27#include <linux/module.h> 27#include <linux/module.h>
28 28
29#include <asm/mach-types.h> 29#include <asm/mach-types.h>
30#include <plat/board-ams-delta.h> 30#include <mach/board-ams-delta.h>
31 31
32#include <mach/ams-delta-fiq.h> 32#include <mach/ams-delta-fiq.h>
33 33
diff --git a/drivers/media/video/omap/omap_vout.c b/drivers/media/video/omap/omap_vout.c
index 88cf9d952631..409da0f8e5cf 100644
--- a/drivers/media/video/omap/omap_vout.c
+++ b/drivers/media/video/omap/omap_vout.c
@@ -44,6 +44,7 @@
44#include <media/v4l2-device.h> 44#include <media/v4l2-device.h>
45#include <media/v4l2-ioctl.h> 45#include <media/v4l2-ioctl.h>
46 46
47#include <plat/cpu.h>
47#include <plat/dma.h> 48#include <plat/dma.h>
48#include <plat/vrfb.h> 49#include <plat/vrfb.h>
49#include <video/omapdss.h> 50#include <video/omapdss.h>
diff --git a/drivers/media/video/omap3isp/isp.c b/drivers/media/video/omap3isp/isp.c
index 1c347633e663..43e61fe5df50 100644
--- a/drivers/media/video/omap3isp/isp.c
+++ b/drivers/media/video/omap3isp/isp.c
@@ -70,6 +70,8 @@
70#include <media/v4l2-common.h> 70#include <media/v4l2-common.h>
71#include <media/v4l2-device.h> 71#include <media/v4l2-device.h>
72 72
73#include <plat/cpu.h>
74
73#include "isp.h" 75#include "isp.h"
74#include "ispreg.h" 76#include "ispreg.h"
75#include "ispccdc.h" 77#include "ispccdc.h"
diff --git a/drivers/mfd/twl-core.c b/drivers/mfd/twl-core.c
index 1c32afed28aa..9d3a0bc1a65f 100644
--- a/drivers/mfd/twl-core.c
+++ b/drivers/mfd/twl-core.c
@@ -1132,12 +1132,7 @@ static void clocks_init(struct device *dev,
1132 u32 rate; 1132 u32 rate;
1133 u8 ctrl = HFCLK_FREQ_26_MHZ; 1133 u8 ctrl = HFCLK_FREQ_26_MHZ;
1134 1134
1135#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) 1135 osc = clk_get(dev, "fck");
1136 if (cpu_is_omap2430())
1137 osc = clk_get(dev, "osc_ck");
1138 else
1139 osc = clk_get(dev, "osc_sys_ck");
1140
1141 if (IS_ERR(osc)) { 1136 if (IS_ERR(osc)) {
1142 printk(KERN_WARNING "Skipping twl internal clock init and " 1137 printk(KERN_WARNING "Skipping twl internal clock init and "
1143 "using bootloader value (unknown osc rate)\n"); 1138 "using bootloader value (unknown osc rate)\n");
@@ -1147,18 +1142,6 @@ static void clocks_init(struct device *dev,
1147 rate = clk_get_rate(osc); 1142 rate = clk_get_rate(osc);
1148 clk_put(osc); 1143 clk_put(osc);
1149 1144
1150#else
1151 /* REVISIT for non-OMAP systems, pass the clock rate from
1152 * board init code, using platform_data.
1153 */
1154 osc = ERR_PTR(-EIO);
1155
1156 printk(KERN_WARNING "Skipping twl internal clock init and "
1157 "using bootloader value (unknown osc rate)\n");
1158
1159 return;
1160#endif
1161
1162 switch (rate) { 1145 switch (rate) {
1163 case 19200000: 1146 case 19200000:
1164 ctrl = HFCLK_FREQ_19p2_MHZ; 1147 ctrl = HFCLK_FREQ_19p2_MHZ;
@@ -1220,10 +1203,23 @@ twl_probe(struct i2c_client *client, const struct i2c_device_id *id)
1220{ 1203{
1221 struct twl4030_platform_data *pdata = client->dev.platform_data; 1204 struct twl4030_platform_data *pdata = client->dev.platform_data;
1222 struct device_node *node = client->dev.of_node; 1205 struct device_node *node = client->dev.of_node;
1206 struct platform_device *pdev;
1223 int irq_base = 0; 1207 int irq_base = 0;
1224 int status; 1208 int status;
1225 unsigned i, num_slaves; 1209 unsigned i, num_slaves;
1226 1210
1211 pdev = platform_device_alloc(DRIVER_NAME, -1);
1212 if (!pdev) {
1213 dev_err(&client->dev, "can't alloc pdev\n");
1214 return -ENOMEM;
1215 }
1216
1217 status = platform_device_add(pdev);
1218 if (status) {
1219 platform_device_put(pdev);
1220 return status;
1221 }
1222
1227 if (node && !pdata) { 1223 if (node && !pdata) {
1228 /* 1224 /*
1229 * XXX: Temporary pdata until the information is correctly 1225 * XXX: Temporary pdata until the information is correctly
@@ -1232,23 +1228,30 @@ twl_probe(struct i2c_client *client, const struct i2c_device_id *id)
1232 pdata = devm_kzalloc(&client->dev, 1228 pdata = devm_kzalloc(&client->dev,
1233 sizeof(struct twl4030_platform_data), 1229 sizeof(struct twl4030_platform_data),
1234 GFP_KERNEL); 1230 GFP_KERNEL);
1235 if (!pdata) 1231 if (!pdata) {
1236 return -ENOMEM; 1232 status = -ENOMEM;
1233 goto free;
1234 }
1237 } 1235 }
1238 1236
1239 if (!pdata) { 1237 if (!pdata) {
1240 dev_dbg(&client->dev, "no platform data?\n"); 1238 dev_dbg(&client->dev, "no platform data?\n");
1241 return -EINVAL; 1239 status = -EINVAL;
1240 goto free;
1242 } 1241 }
1243 1242
1243 platform_set_drvdata(pdev, pdata);
1244
1244 if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C) == 0) { 1245 if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C) == 0) {
1245 dev_dbg(&client->dev, "can't talk I2C?\n"); 1246 dev_dbg(&client->dev, "can't talk I2C?\n");
1246 return -EIO; 1247 status = -EIO;
1248 goto free;
1247 } 1249 }
1248 1250
1249 if (inuse) { 1251 if (inuse) {
1250 dev_dbg(&client->dev, "driver is already in use\n"); 1252 dev_dbg(&client->dev, "driver is already in use\n");
1251 return -EBUSY; 1253 status = -EBUSY;
1254 goto free;
1252 } 1255 }
1253 1256
1254 if ((id->driver_data) & TWL6030_CLASS) { 1257 if ((id->driver_data) & TWL6030_CLASS) {
@@ -1283,7 +1286,7 @@ twl_probe(struct i2c_client *client, const struct i2c_device_id *id)
1283 inuse = true; 1286 inuse = true;
1284 1287
1285 /* setup clock framework */ 1288 /* setup clock framework */
1286 clocks_init(&client->dev, pdata->clock); 1289 clocks_init(&pdev->dev, pdata->clock);
1287 1290
1288 /* read TWL IDCODE Register */ 1291 /* read TWL IDCODE Register */
1289 if (twl_id == TWL4030_CLASS_ID) { 1292 if (twl_id == TWL4030_CLASS_ID) {
@@ -1333,6 +1336,9 @@ twl_probe(struct i2c_client *client, const struct i2c_device_id *id)
1333fail: 1336fail:
1334 if (status < 0) 1337 if (status < 0)
1335 twl_remove(client); 1338 twl_remove(client);
1339free:
1340 if (status < 0)
1341 platform_device_unregister(pdev);
1336 1342
1337 return status; 1343 return status;
1338} 1344}
diff --git a/drivers/mmc/host/omap.c b/drivers/mmc/host/omap.c
index a5999a74496a..c6259a829544 100644
--- a/drivers/mmc/host/omap.c
+++ b/drivers/mmc/host/omap.c
@@ -33,11 +33,9 @@
33#include <asm/io.h> 33#include <asm/io.h>
34#include <asm/irq.h> 34#include <asm/irq.h>
35 35
36#include <plat/board.h>
37#include <plat/mmc.h> 36#include <plat/mmc.h>
38#include <asm/gpio.h> 37#include <asm/gpio.h>
39#include <plat/dma.h> 38#include <plat/dma.h>
40#include <plat/mux.h>
41#include <plat/fpga.h> 39#include <plat/fpga.h>
42 40
43#define OMAP_MMC_REG_CMD 0x00 41#define OMAP_MMC_REG_CMD 0x00
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 8e2d81f1ee4b..38adc330c007 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -40,7 +40,6 @@
40#include <linux/regulator/consumer.h> 40#include <linux/regulator/consumer.h>
41#include <linux/pm_runtime.h> 41#include <linux/pm_runtime.h>
42#include <mach/hardware.h> 42#include <mach/hardware.h>
43#include <plat/board.h>
44#include <plat/mmc.h> 43#include <plat/mmc.h>
45#include <plat/cpu.h> 44#include <plat/cpu.h>
46 45
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index 0810ccc23d7e..5393c64de3c8 100644
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -27,7 +27,6 @@
27 27
28#include <asm/gpio.h> 28#include <asm/gpio.h>
29 29
30#include <mach/gpio-tegra.h>
31#include <mach/sdhci.h> 30#include <mach/sdhci.h>
32 31
33#include "sdhci-pltfm.h" 32#include "sdhci-pltfm.h"
diff --git a/drivers/mtd/nand/ams-delta.c b/drivers/mtd/nand/ams-delta.c
index 861ca8f7e47d..a7040af08536 100644
--- a/drivers/mtd/nand/ams-delta.c
+++ b/drivers/mtd/nand/ams-delta.c
@@ -23,11 +23,15 @@
23#include <linux/mtd/mtd.h> 23#include <linux/mtd/mtd.h>
24#include <linux/mtd/nand.h> 24#include <linux/mtd/nand.h>
25#include <linux/mtd/partitions.h> 25#include <linux/mtd/partitions.h>
26#include <linux/gpio.h>
27#include <linux/platform_data/gpio-omap.h>
28
26#include <asm/io.h> 29#include <asm/io.h>
27#include <mach/hardware.h>
28#include <asm/sizes.h> 30#include <asm/sizes.h>
29#include <linux/gpio.h> 31
30#include <plat/board-ams-delta.h> 32#include <mach/board-ams-delta.h>
33
34#include <mach/hardware.h>
31 35
32/* 36/*
33 * MTD structure for E3 (Delta) 37 * MTD structure for E3 (Delta)
diff --git a/drivers/mtd/nand/bcm_umi_nand.c b/drivers/mtd/nand/bcm_umi_nand.c
index c855e7cd337b..d0d1bd4d0e7d 100644
--- a/drivers/mtd/nand/bcm_umi_nand.c
+++ b/drivers/mtd/nand/bcm_umi_nand.c
@@ -249,20 +249,20 @@ static int nand_dev_ready(struct mtd_info *mtd)
249int bcm_umi_nand_inithw(void) 249int bcm_umi_nand_inithw(void)
250{ 250{
251 /* Configure nand timing parameters */ 251 /* Configure nand timing parameters */
252 REG_UMI_NAND_TCR &= ~0x7ffff; 252 writel(readl(&REG_UMI_NAND_TCR) & ~0x7ffff, &REG_UMI_NAND_TCR);
253 REG_UMI_NAND_TCR |= HW_CFG_NAND_TCR; 253 writel(readl(&REG_UMI_NAND_TCR) | HW_CFG_NAND_TCR, &REG_UMI_NAND_TCR);
254 254
255#if !defined(CONFIG_MTD_NAND_BCM_UMI_HWCS) 255#if !defined(CONFIG_MTD_NAND_BCM_UMI_HWCS)
256 /* enable software control of CS */ 256 /* enable software control of CS */
257 REG_UMI_NAND_TCR |= REG_UMI_NAND_TCR_CS_SWCTRL; 257 writel(readl(&REG_UMI_NAND_TCR) | REG_UMI_NAND_TCR_CS_SWCTRL, &REG_UMI_NAND_TCR);
258#endif 258#endif
259 259
260 /* keep NAND chip select asserted */ 260 /* keep NAND chip select asserted */
261 REG_UMI_NAND_RCSR |= REG_UMI_NAND_RCSR_CS_ASSERTED; 261 writel(readl(&REG_UMI_NAND_RCSR) | REG_UMI_NAND_RCSR_CS_ASSERTED, &REG_UMI_NAND_RCSR);
262 262
263 REG_UMI_NAND_TCR &= ~REG_UMI_NAND_TCR_WORD16; 263 writel(readl(&REG_UMI_NAND_TCR) & ~REG_UMI_NAND_TCR_WORD16, &REG_UMI_NAND_TCR);
264 /* enable writes to flash */ 264 /* enable writes to flash */
265 REG_UMI_MMD_ICR |= REG_UMI_MMD_ICR_FLASH_WP; 265 writel(readl(&REG_UMI_MMD_ICR) | REG_UMI_MMD_ICR_FLASH_WP, &REG_UMI_MMD_ICR);
266 266
267 writel(NAND_CMD_RESET, bcm_umi_io_base + REG_NAND_CMD_OFFSET); 267 writel(NAND_CMD_RESET, bcm_umi_io_base + REG_NAND_CMD_OFFSET);
268 nand_bcm_umi_wait_till_ready(); 268 nand_bcm_umi_wait_till_ready();
diff --git a/drivers/mtd/nand/nand_bcm_umi.h b/drivers/mtd/nand/nand_bcm_umi.h
index 198b304d6f72..d90186684db8 100644
--- a/drivers/mtd/nand/nand_bcm_umi.h
+++ b/drivers/mtd/nand/nand_bcm_umi.h
@@ -17,7 +17,7 @@
17/* ---- Include Files ---------------------------------------------------- */ 17/* ---- Include Files ---------------------------------------------------- */
18#include <mach/reg_umi.h> 18#include <mach/reg_umi.h>
19#include <mach/reg_nand.h> 19#include <mach/reg_nand.h>
20#include <cfg_global.h> 20#include <mach/cfg_global.h>
21 21
22/* ---- Constants and Types ---------------------------------------------- */ 22/* ---- Constants and Types ---------------------------------------------- */
23#if (CFG_GLOBAL_CHIP_FAMILY == CFG_GLOBAL_CHIP_FAMILY_BCMRING) 23#if (CFG_GLOBAL_CHIP_FAMILY == CFG_GLOBAL_CHIP_FAMILY_BCMRING)
@@ -48,7 +48,7 @@ int nand_bcm_umi_bch_correct_page(uint8_t *datap, uint8_t *readEccData,
48/* Check in device is ready */ 48/* Check in device is ready */
49static inline int nand_bcm_umi_dev_ready(void) 49static inline int nand_bcm_umi_dev_ready(void)
50{ 50{
51 return REG_UMI_NAND_RCSR & REG_UMI_NAND_RCSR_RDY; 51 return readl(&REG_UMI_NAND_RCSR) & REG_UMI_NAND_RCSR_RDY;
52} 52}
53 53
54/* Wait until device is ready */ 54/* Wait until device is ready */
@@ -62,10 +62,11 @@ static inline void nand_bcm_umi_wait_till_ready(void)
62static inline void nand_bcm_umi_hamming_enable_hwecc(void) 62static inline void nand_bcm_umi_hamming_enable_hwecc(void)
63{ 63{
64 /* disable and reset ECC, 512 byte page */ 64 /* disable and reset ECC, 512 byte page */
65 REG_UMI_NAND_ECC_CSR &= ~(REG_UMI_NAND_ECC_CSR_ECC_ENABLE | 65 writel(readl(&REG_UMI_NAND_ECC_CSR) & ~(REG_UMI_NAND_ECC_CSR_ECC_ENABLE |
66 REG_UMI_NAND_ECC_CSR_256BYTE); 66 REG_UMI_NAND_ECC_CSR_256BYTE), &REG_UMI_NAND_ECC_CSR);
67 /* enable ECC */ 67 /* enable ECC */
68 REG_UMI_NAND_ECC_CSR |= REG_UMI_NAND_ECC_CSR_ECC_ENABLE; 68 writel(readl(&REG_UMI_NAND_ECC_CSR) | REG_UMI_NAND_ECC_CSR_ECC_ENABLE,
69 &REG_UMI_NAND_ECC_CSR);
69} 70}
70 71
71#if NAND_ECC_BCH 72#if NAND_ECC_BCH
@@ -76,18 +77,18 @@ static inline void nand_bcm_umi_hamming_enable_hwecc(void)
76static inline void nand_bcm_umi_bch_enable_read_hwecc(void) 77static inline void nand_bcm_umi_bch_enable_read_hwecc(void)
77{ 78{
78 /* disable and reset ECC */ 79 /* disable and reset ECC */
79 REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID; 80 writel(REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID, &REG_UMI_BCH_CTRL_STATUS);
80 /* Turn on ECC */ 81 /* Turn on ECC */
81 REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN; 82 writel(REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN, &REG_UMI_BCH_CTRL_STATUS);
82} 83}
83 84
84/* Enable BCH Write ECC */ 85/* Enable BCH Write ECC */
85static inline void nand_bcm_umi_bch_enable_write_hwecc(void) 86static inline void nand_bcm_umi_bch_enable_write_hwecc(void)
86{ 87{
87 /* disable and reset ECC */ 88 /* disable and reset ECC */
88 REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID; 89 writel(REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID, &REG_UMI_BCH_CTRL_STATUS);
89 /* Turn on ECC */ 90 /* Turn on ECC */
90 REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_WR_EN; 91 writel(REG_UMI_BCH_CTRL_STATUS_ECC_WR_EN, &REG_UMI_BCH_CTRL_STATUS);
91} 92}
92 93
93/* Config number of BCH ECC bytes */ 94/* Config number of BCH ECC bytes */
@@ -99,9 +100,9 @@ static inline void nand_bcm_umi_bch_config_ecc(uint8_t numEccBytes)
99 uint32_t numBits = numEccBytes * 8; 100 uint32_t numBits = numEccBytes * 8;
100 101
101 /* disable and reset ECC */ 102 /* disable and reset ECC */
102 REG_UMI_BCH_CTRL_STATUS = 103 writel(REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID |
103 REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID | 104 REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID,
104 REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID; 105 &REG_UMI_BCH_CTRL_STATUS);
105 106
106 /* Every correctible bit requires 13 ECC bits */ 107 /* Every correctible bit requires 13 ECC bits */
107 tValue = (uint32_t) (numBits / ECC_BITS_PER_CORRECTABLE_BIT); 108 tValue = (uint32_t) (numBits / ECC_BITS_PER_CORRECTABLE_BIT);
@@ -113,23 +114,21 @@ static inline void nand_bcm_umi_bch_config_ecc(uint8_t numEccBytes)
113 kValue = nValue - (tValue * ECC_BITS_PER_CORRECTABLE_BIT); 114 kValue = nValue - (tValue * ECC_BITS_PER_CORRECTABLE_BIT);
114 115
115 /* Write the settings */ 116 /* Write the settings */
116 REG_UMI_BCH_N = nValue; 117 writel(nValue, &REG_UMI_BCH_N);
117 REG_UMI_BCH_T = tValue; 118 writel(tValue, &REG_UMI_BCH_T);
118 REG_UMI_BCH_K = kValue; 119 writel(kValue, &REG_UMI_BCH_K);
119} 120}
120 121
121/* Pause during ECC read calculation to skip bytes in OOB */ 122/* Pause during ECC read calculation to skip bytes in OOB */
122static inline void nand_bcm_umi_bch_pause_read_ecc_calc(void) 123static inline void nand_bcm_umi_bch_pause_read_ecc_calc(void)
123{ 124{
124 REG_UMI_BCH_CTRL_STATUS = 125 writel(REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN | REG_UMI_BCH_CTRL_STATUS_PAUSE_ECC_DEC, &REG_UMI_BCH_CTRL_STATUS);
125 REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN |
126 REG_UMI_BCH_CTRL_STATUS_PAUSE_ECC_DEC;
127} 126}
128 127
129/* Resume during ECC read calculation after skipping bytes in OOB */ 128/* Resume during ECC read calculation after skipping bytes in OOB */
130static inline void nand_bcm_umi_bch_resume_read_ecc_calc(void) 129static inline void nand_bcm_umi_bch_resume_read_ecc_calc(void)
131{ 130{
132 REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN; 131 writel(REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN, &REG_UMI_BCH_CTRL_STATUS);
133} 132}
134 133
135/* Poll read ECC calc to check when hardware completes */ 134/* Poll read ECC calc to check when hardware completes */
@@ -139,7 +138,7 @@ static inline uint32_t nand_bcm_umi_bch_poll_read_ecc_calc(void)
139 138
140 do { 139 do {
141 /* wait for ECC to be valid */ 140 /* wait for ECC to be valid */
142 regVal = REG_UMI_BCH_CTRL_STATUS; 141 regVal = readl(&REG_UMI_BCH_CTRL_STATUS);
143 } while ((regVal & REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID) == 0); 142 } while ((regVal & REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID) == 0);
144 143
145 return regVal; 144 return regVal;
@@ -149,7 +148,7 @@ static inline uint32_t nand_bcm_umi_bch_poll_read_ecc_calc(void)
149static inline void nand_bcm_umi_bch_poll_write_ecc_calc(void) 148static inline void nand_bcm_umi_bch_poll_write_ecc_calc(void)
150{ 149{
151 /* wait for ECC to be valid */ 150 /* wait for ECC to be valid */
152 while ((REG_UMI_BCH_CTRL_STATUS & REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID) 151 while ((readl(&REG_UMI_BCH_CTRL_STATUS) & REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID)
153 == 0) 152 == 0)
154 ; 153 ;
155} 154}
@@ -170,9 +169,9 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
170 if (pageSize != NAND_DATA_ACCESS_SIZE) { 169 if (pageSize != NAND_DATA_ACCESS_SIZE) {
171 /* skip BI */ 170 /* skip BI */
172#if defined(__KERNEL__) && !defined(STANDALONE) 171#if defined(__KERNEL__) && !defined(STANDALONE)
173 *oobp++ = REG_NAND_DATA8; 172 *oobp++ = readb(&REG_NAND_DATA8);
174#else 173#else
175 REG_NAND_DATA8; 174 readb(&REG_NAND_DATA8);
176#endif 175#endif
177 numToRead--; 176 numToRead--;
178 } 177 }
@@ -180,9 +179,9 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
180 while (numToRead > numEccBytes) { 179 while (numToRead > numEccBytes) {
181 /* skip free oob region */ 180 /* skip free oob region */
182#if defined(__KERNEL__) && !defined(STANDALONE) 181#if defined(__KERNEL__) && !defined(STANDALONE)
183 *oobp++ = REG_NAND_DATA8; 182 *oobp++ = readb(&REG_NAND_DATA8);
184#else 183#else
185 REG_NAND_DATA8; 184 readb(&REG_NAND_DATA8);
186#endif 185#endif
187 numToRead--; 186 numToRead--;
188 } 187 }
@@ -193,11 +192,11 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
193 192
194 while (numToRead > 11) { 193 while (numToRead > 11) {
195#if defined(__KERNEL__) && !defined(STANDALONE) 194#if defined(__KERNEL__) && !defined(STANDALONE)
196 *oobp = REG_NAND_DATA8; 195 *oobp = readb(&REG_NAND_DATA8);
197 eccCalc[eccPos++] = *oobp; 196 eccCalc[eccPos++] = *oobp;
198 oobp++; 197 oobp++;
199#else 198#else
200 eccCalc[eccPos++] = REG_NAND_DATA8; 199 eccCalc[eccPos++] = readb(&REG_NAND_DATA8);
201#endif 200#endif
202 numToRead--; 201 numToRead--;
203 } 202 }
@@ -207,9 +206,9 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
207 if (numToRead == 11) { 206 if (numToRead == 11) {
208 /* read BI */ 207 /* read BI */
209#if defined(__KERNEL__) && !defined(STANDALONE) 208#if defined(__KERNEL__) && !defined(STANDALONE)
210 *oobp++ = REG_NAND_DATA8; 209 *oobp++ = readb(&REG_NAND_DATA8);
211#else 210#else
212 REG_NAND_DATA8; 211 readb(&REG_NAND_DATA8);
213#endif 212#endif
214 numToRead--; 213 numToRead--;
215 } 214 }
@@ -219,11 +218,11 @@ static inline void nand_bcm_umi_bch_read_oobEcc(uint32_t pageSize,
219 nand_bcm_umi_bch_resume_read_ecc_calc(); 218 nand_bcm_umi_bch_resume_read_ecc_calc();
220 while (numToRead) { 219 while (numToRead) {
221#if defined(__KERNEL__) && !defined(STANDALONE) 220#if defined(__KERNEL__) && !defined(STANDALONE)
222 *oobp = REG_NAND_DATA8; 221 *oobp = readb(&REG_NAND_DATA8);
223 eccCalc[eccPos++] = *oobp; 222 eccCalc[eccPos++] = *oobp;
224 oobp++; 223 oobp++;
225#else 224#else
226 eccCalc[eccPos++] = REG_NAND_DATA8; 225 eccCalc[eccPos++] = readb(&REG_NAND_DATA8);
227#endif 226#endif
228 numToRead--; 227 numToRead--;
229 } 228 }
@@ -255,7 +254,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
255 if (pageSize == NAND_DATA_ACCESS_SIZE) { 254 if (pageSize == NAND_DATA_ACCESS_SIZE) {
256 /* Now fill in the ECC bytes */ 255 /* Now fill in the ECC bytes */
257 if (numEccBytes >= 13) 256 if (numEccBytes >= 13)
258 eccVal = REG_UMI_BCH_WR_ECC_3; 257 eccVal = readl(&REG_UMI_BCH_WR_ECC_3);
259 258
260 /* Usually we skip CM in oob[0,1] */ 259 /* Usually we skip CM in oob[0,1] */
261 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 15, &oobp[0], 260 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 15, &oobp[0],
@@ -268,7 +267,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
268 eccVal & 0xff); /* ECC 12 */ 267 eccVal & 0xff); /* ECC 12 */
269 268
270 if (numEccBytes >= 9) 269 if (numEccBytes >= 9)
271 eccVal = REG_UMI_BCH_WR_ECC_2; 270 eccVal = readl(&REG_UMI_BCH_WR_ECC_2);
272 271
273 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 12, &oobp[3], 272 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 12, &oobp[3],
274 (eccVal >> 24) & 0xff); /* ECC11 */ 273 (eccVal >> 24) & 0xff); /* ECC11 */
@@ -281,7 +280,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
281 280
282 /* Now fill in the ECC bytes */ 281 /* Now fill in the ECC bytes */
283 if (numEccBytes >= 13) 282 if (numEccBytes >= 13)
284 eccVal = REG_UMI_BCH_WR_ECC_3; 283 eccVal = readl(&REG_UMI_BCH_WR_ECC_3);
285 284
286 /* Usually skip CM in oob[1,2] */ 285 /* Usually skip CM in oob[1,2] */
287 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 15, &oobp[1], 286 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 15, &oobp[1],
@@ -294,7 +293,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
294 eccVal & 0xff); /* ECC12 */ 293 eccVal & 0xff); /* ECC12 */
295 294
296 if (numEccBytes >= 9) 295 if (numEccBytes >= 9)
297 eccVal = REG_UMI_BCH_WR_ECC_2; 296 eccVal = readl(&REG_UMI_BCH_WR_ECC_2);
298 297
299 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 12, &oobp[4], 298 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 12, &oobp[4],
300 (eccVal >> 24) & 0xff); /* ECC11 */ 299 (eccVal >> 24) & 0xff); /* ECC11 */
@@ -309,7 +308,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
309 eccVal & 0xff); /* ECC8 */ 308 eccVal & 0xff); /* ECC8 */
310 309
311 if (numEccBytes >= 5) 310 if (numEccBytes >= 5)
312 eccVal = REG_UMI_BCH_WR_ECC_1; 311 eccVal = readl(&REG_UMI_BCH_WR_ECC_1);
313 312
314 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 8, &oobp[8], 313 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 8, &oobp[8],
315 (eccVal >> 24) & 0xff); /* ECC7 */ 314 (eccVal >> 24) & 0xff); /* ECC7 */
@@ -321,7 +320,7 @@ static inline void nand_bcm_umi_bch_write_oobEcc(uint32_t pageSize,
321 eccVal & 0xff); /* ECC4 */ 320 eccVal & 0xff); /* ECC4 */
322 321
323 if (numEccBytes >= 1) 322 if (numEccBytes >= 1)
324 eccVal = REG_UMI_BCH_WR_ECC_0; 323 eccVal = readl(&REG_UMI_BCH_WR_ECC_0);
325 324
326 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 4, &oobp[12], 325 NAND_BCM_UMI_ECC_WRITE(numEccBytes, 4, &oobp[12],
327 (eccVal >> 24) & 0xff); /* ECC3 */ 326 (eccVal >> 24) & 0xff); /* ECC3 */
diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c
index ac4fd756eda3..fc8111278d12 100644
--- a/drivers/mtd/nand/omap2.c
+++ b/drivers/mtd/nand/omap2.c
@@ -29,7 +29,7 @@
29 29
30#include <plat/dma.h> 30#include <plat/dma.h>
31#include <plat/gpmc.h> 31#include <plat/gpmc.h>
32#include <plat/nand.h> 32#include <linux/platform_data/mtd-nand-omap2.h>
33 33
34#define DRIVER_NAME "omap2-nand" 34#define DRIVER_NAME "omap2-nand"
35#define OMAP_NAND_TIMEOUT_MS 5000 35#define OMAP_NAND_TIMEOUT_MS 5000
@@ -101,6 +101,16 @@
101#define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0) 101#define P4e_s(a) (TF(a & NAND_Ecc_P4e) << 0)
102#define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1) 102#define P4o_s(a) (TF(a & NAND_Ecc_P4o) << 1)
103 103
104#define PREFETCH_CONFIG1_CS_SHIFT 24
105#define ECC_CONFIG_CS_SHIFT 1
106#define CS_MASK 0x7
107#define ENABLE_PREFETCH (0x1 << 7)
108#define DMA_MPU_MODE_SHIFT 2
109#define ECCSIZE1_SHIFT 22
110#define ECC1RESULTSIZE 0x1
111#define ECCCLEAR 0x100
112#define ECC1 0x1
113
104/* oob info generated runtime depending on ecc algorithm and layout selected */ 114/* oob info generated runtime depending on ecc algorithm and layout selected */
105static struct nand_ecclayout omap_oobinfo; 115static struct nand_ecclayout omap_oobinfo;
106/* Define some generic bad / good block scan pattern which are used 116/* Define some generic bad / good block scan pattern which are used
@@ -124,15 +134,18 @@ struct omap_nand_info {
124 134
125 int gpmc_cs; 135 int gpmc_cs;
126 unsigned long phys_base; 136 unsigned long phys_base;
137 unsigned long mem_size;
127 struct completion comp; 138 struct completion comp;
128 struct dma_chan *dma; 139 struct dma_chan *dma;
129 int gpmc_irq; 140 int gpmc_irq_fifo;
141 int gpmc_irq_count;
130 enum { 142 enum {
131 OMAP_NAND_IO_READ = 0, /* read */ 143 OMAP_NAND_IO_READ = 0, /* read */
132 OMAP_NAND_IO_WRITE, /* write */ 144 OMAP_NAND_IO_WRITE, /* write */
133 } iomode; 145 } iomode;
134 u_char *buf; 146 u_char *buf;
135 int buf_len; 147 int buf_len;
148 struct gpmc_nand_regs reg;
136 149
137#ifdef CONFIG_MTD_NAND_OMAP_BCH 150#ifdef CONFIG_MTD_NAND_OMAP_BCH
138 struct bch_control *bch; 151 struct bch_control *bch;
@@ -141,6 +154,63 @@ struct omap_nand_info {
141}; 154};
142 155
143/** 156/**
157 * omap_prefetch_enable - configures and starts prefetch transfer
158 * @cs: cs (chip select) number
159 * @fifo_th: fifo threshold to be used for read/ write
160 * @dma_mode: dma mode enable (1) or disable (0)
161 * @u32_count: number of bytes to be transferred
162 * @is_write: prefetch read(0) or write post(1) mode
163 */
164static int omap_prefetch_enable(int cs, int fifo_th, int dma_mode,
165 unsigned int u32_count, int is_write, struct omap_nand_info *info)
166{
167 u32 val;
168
169 if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX)
170 return -1;
171
172 if (readl(info->reg.gpmc_prefetch_control))
173 return -EBUSY;
174
175 /* Set the amount of bytes to be prefetched */
176 writel(u32_count, info->reg.gpmc_prefetch_config2);
177
178 /* Set dma/mpu mode, the prefetch read / post write and
179 * enable the engine. Set which cs is has requested for.
180 */
181 val = ((cs << PREFETCH_CONFIG1_CS_SHIFT) |
182 PREFETCH_FIFOTHRESHOLD(fifo_th) | ENABLE_PREFETCH |
183 (dma_mode << DMA_MPU_MODE_SHIFT) | (0x1 & is_write));
184 writel(val, info->reg.gpmc_prefetch_config1);
185
186 /* Start the prefetch engine */
187 writel(0x1, info->reg.gpmc_prefetch_control);
188
189 return 0;
190}
191
192/**
193 * omap_prefetch_reset - disables and stops the prefetch engine
194 */
195static int omap_prefetch_reset(int cs, struct omap_nand_info *info)
196{
197 u32 config1;
198
199 /* check if the same module/cs is trying to reset */
200 config1 = readl(info->reg.gpmc_prefetch_config1);
201 if (((config1 >> PREFETCH_CONFIG1_CS_SHIFT) & CS_MASK) != cs)
202 return -EINVAL;
203
204 /* Stop the PFPW engine */
205 writel(0x0, info->reg.gpmc_prefetch_control);
206
207 /* Reset/disable the PFPW engine */
208 writel(0x0, info->reg.gpmc_prefetch_config1);
209
210 return 0;
211}
212
213/**
144 * omap_hwcontrol - hardware specific access to control-lines 214 * omap_hwcontrol - hardware specific access to control-lines
145 * @mtd: MTD device structure 215 * @mtd: MTD device structure
146 * @cmd: command to device 216 * @cmd: command to device
@@ -158,13 +228,13 @@ static void omap_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
158 228
159 if (cmd != NAND_CMD_NONE) { 229 if (cmd != NAND_CMD_NONE) {
160 if (ctrl & NAND_CLE) 230 if (ctrl & NAND_CLE)
161 gpmc_nand_write(info->gpmc_cs, GPMC_NAND_COMMAND, cmd); 231 writeb(cmd, info->reg.gpmc_nand_command);
162 232
163 else if (ctrl & NAND_ALE) 233 else if (ctrl & NAND_ALE)
164 gpmc_nand_write(info->gpmc_cs, GPMC_NAND_ADDRESS, cmd); 234 writeb(cmd, info->reg.gpmc_nand_address);
165 235
166 else /* NAND_NCE */ 236 else /* NAND_NCE */
167 gpmc_nand_write(info->gpmc_cs, GPMC_NAND_DATA, cmd); 237 writeb(cmd, info->reg.gpmc_nand_data);
168 } 238 }
169} 239}
170 240
@@ -198,7 +268,8 @@ static void omap_write_buf8(struct mtd_info *mtd, const u_char *buf, int len)
198 iowrite8(*p++, info->nand.IO_ADDR_W); 268 iowrite8(*p++, info->nand.IO_ADDR_W);
199 /* wait until buffer is available for write */ 269 /* wait until buffer is available for write */
200 do { 270 do {
201 status = gpmc_read_status(GPMC_STATUS_BUFFER); 271 status = readl(info->reg.gpmc_status) &
272 GPMC_STATUS_BUFF_EMPTY;
202 } while (!status); 273 } while (!status);
203 } 274 }
204} 275}
@@ -235,7 +306,8 @@ static void omap_write_buf16(struct mtd_info *mtd, const u_char * buf, int len)
235 iowrite16(*p++, info->nand.IO_ADDR_W); 306 iowrite16(*p++, info->nand.IO_ADDR_W);
236 /* wait until buffer is available for write */ 307 /* wait until buffer is available for write */
237 do { 308 do {
238 status = gpmc_read_status(GPMC_STATUS_BUFFER); 309 status = readl(info->reg.gpmc_status) &
310 GPMC_STATUS_BUFF_EMPTY;
239 } while (!status); 311 } while (!status);
240 } 312 }
241} 313}
@@ -265,8 +337,8 @@ static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
265 } 337 }
266 338
267 /* configure and start prefetch transfer */ 339 /* configure and start prefetch transfer */
268 ret = gpmc_prefetch_enable(info->gpmc_cs, 340 ret = omap_prefetch_enable(info->gpmc_cs,
269 PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0); 341 PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x0, info);
270 if (ret) { 342 if (ret) {
271 /* PFPW engine is busy, use cpu copy method */ 343 /* PFPW engine is busy, use cpu copy method */
272 if (info->nand.options & NAND_BUSWIDTH_16) 344 if (info->nand.options & NAND_BUSWIDTH_16)
@@ -275,14 +347,15 @@ static void omap_read_buf_pref(struct mtd_info *mtd, u_char *buf, int len)
275 omap_read_buf8(mtd, (u_char *)p, len); 347 omap_read_buf8(mtd, (u_char *)p, len);
276 } else { 348 } else {
277 do { 349 do {
278 r_count = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT); 350 r_count = readl(info->reg.gpmc_prefetch_status);
351 r_count = GPMC_PREFETCH_STATUS_FIFO_CNT(r_count);
279 r_count = r_count >> 2; 352 r_count = r_count >> 2;
280 ioread32_rep(info->nand.IO_ADDR_R, p, r_count); 353 ioread32_rep(info->nand.IO_ADDR_R, p, r_count);
281 p += r_count; 354 p += r_count;
282 len -= r_count << 2; 355 len -= r_count << 2;
283 } while (len); 356 } while (len);
284 /* disable and stop the PFPW engine */ 357 /* disable and stop the PFPW engine */
285 gpmc_prefetch_reset(info->gpmc_cs); 358 omap_prefetch_reset(info->gpmc_cs, info);
286 } 359 }
287} 360}
288 361
@@ -301,6 +374,7 @@ static void omap_write_buf_pref(struct mtd_info *mtd,
301 int i = 0, ret = 0; 374 int i = 0, ret = 0;
302 u16 *p = (u16 *)buf; 375 u16 *p = (u16 *)buf;
303 unsigned long tim, limit; 376 unsigned long tim, limit;
377 u32 val;
304 378
305 /* take care of subpage writes */ 379 /* take care of subpage writes */
306 if (len % 2 != 0) { 380 if (len % 2 != 0) {
@@ -310,8 +384,8 @@ static void omap_write_buf_pref(struct mtd_info *mtd,
310 } 384 }
311 385
312 /* configure and start prefetch transfer */ 386 /* configure and start prefetch transfer */
313 ret = gpmc_prefetch_enable(info->gpmc_cs, 387 ret = omap_prefetch_enable(info->gpmc_cs,
314 PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1); 388 PREFETCH_FIFOTHRESHOLD_MAX, 0x0, len, 0x1, info);
315 if (ret) { 389 if (ret) {
316 /* PFPW engine is busy, use cpu copy method */ 390 /* PFPW engine is busy, use cpu copy method */
317 if (info->nand.options & NAND_BUSWIDTH_16) 391 if (info->nand.options & NAND_BUSWIDTH_16)
@@ -320,7 +394,8 @@ static void omap_write_buf_pref(struct mtd_info *mtd,
320 omap_write_buf8(mtd, (u_char *)p, len); 394 omap_write_buf8(mtd, (u_char *)p, len);
321 } else { 395 } else {
322 while (len) { 396 while (len) {
323 w_count = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT); 397 w_count = readl(info->reg.gpmc_prefetch_status);
398 w_count = GPMC_PREFETCH_STATUS_FIFO_CNT(w_count);
324 w_count = w_count >> 1; 399 w_count = w_count >> 1;
325 for (i = 0; (i < w_count) && len; i++, len -= 2) 400 for (i = 0; (i < w_count) && len; i++, len -= 2)
326 iowrite16(*p++, info->nand.IO_ADDR_W); 401 iowrite16(*p++, info->nand.IO_ADDR_W);
@@ -329,11 +404,14 @@ static void omap_write_buf_pref(struct mtd_info *mtd,
329 tim = 0; 404 tim = 0;
330 limit = (loops_per_jiffy * 405 limit = (loops_per_jiffy *
331 msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); 406 msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
332 while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit)) 407 do {
333 cpu_relax(); 408 cpu_relax();
409 val = readl(info->reg.gpmc_prefetch_status);
410 val = GPMC_PREFETCH_STATUS_COUNT(val);
411 } while (val && (tim++ < limit));
334 412
335 /* disable and stop the PFPW engine */ 413 /* disable and stop the PFPW engine */
336 gpmc_prefetch_reset(info->gpmc_cs); 414 omap_prefetch_reset(info->gpmc_cs, info);
337 } 415 }
338} 416}
339 417
@@ -365,6 +443,7 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
365 unsigned long tim, limit; 443 unsigned long tim, limit;
366 unsigned n; 444 unsigned n;
367 int ret; 445 int ret;
446 u32 val;
368 447
369 if (addr >= high_memory) { 448 if (addr >= high_memory) {
370 struct page *p1; 449 struct page *p1;
@@ -396,9 +475,9 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
396 tx->callback_param = &info->comp; 475 tx->callback_param = &info->comp;
397 dmaengine_submit(tx); 476 dmaengine_submit(tx);
398 477
399 /* configure and start prefetch transfer */ 478 /* configure and start prefetch transfer */
400 ret = gpmc_prefetch_enable(info->gpmc_cs, 479 ret = omap_prefetch_enable(info->gpmc_cs,
401 PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write); 480 PREFETCH_FIFOTHRESHOLD_MAX, 0x1, len, is_write, info);
402 if (ret) 481 if (ret)
403 /* PFPW engine is busy, use cpu copy method */ 482 /* PFPW engine is busy, use cpu copy method */
404 goto out_copy_unmap; 483 goto out_copy_unmap;
@@ -410,11 +489,15 @@ static inline int omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
410 wait_for_completion(&info->comp); 489 wait_for_completion(&info->comp);
411 tim = 0; 490 tim = 0;
412 limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); 491 limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
413 while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit)) 492
493 do {
414 cpu_relax(); 494 cpu_relax();
495 val = readl(info->reg.gpmc_prefetch_status);
496 val = GPMC_PREFETCH_STATUS_COUNT(val);
497 } while (val && (tim++ < limit));
415 498
416 /* disable and stop the PFPW engine */ 499 /* disable and stop the PFPW engine */
417 gpmc_prefetch_reset(info->gpmc_cs); 500 omap_prefetch_reset(info->gpmc_cs, info);
418 501
419 dma_unmap_sg(info->dma->device->dev, &sg, 1, dir); 502 dma_unmap_sg(info->dma->device->dev, &sg, 1, dir);
420 return 0; 503 return 0;
@@ -471,13 +554,12 @@ static irqreturn_t omap_nand_irq(int this_irq, void *dev)
471{ 554{
472 struct omap_nand_info *info = (struct omap_nand_info *) dev; 555 struct omap_nand_info *info = (struct omap_nand_info *) dev;
473 u32 bytes; 556 u32 bytes;
474 u32 irq_stat;
475 557
476 irq_stat = gpmc_read_status(GPMC_GET_IRQ_STATUS); 558 bytes = readl(info->reg.gpmc_prefetch_status);
477 bytes = gpmc_read_status(GPMC_PREFETCH_FIFO_CNT); 559 bytes = GPMC_PREFETCH_STATUS_FIFO_CNT(bytes);
478 bytes = bytes & 0xFFFC; /* io in multiple of 4 bytes */ 560 bytes = bytes & 0xFFFC; /* io in multiple of 4 bytes */
479 if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */ 561 if (info->iomode == OMAP_NAND_IO_WRITE) { /* checks for write io */
480 if (irq_stat & 0x2) 562 if (this_irq == info->gpmc_irq_count)
481 goto done; 563 goto done;
482 564
483 if (info->buf_len && (info->buf_len < bytes)) 565 if (info->buf_len && (info->buf_len < bytes))
@@ -494,20 +576,17 @@ static irqreturn_t omap_nand_irq(int this_irq, void *dev)
494 (u32 *)info->buf, bytes >> 2); 576 (u32 *)info->buf, bytes >> 2);
495 info->buf = info->buf + bytes; 577 info->buf = info->buf + bytes;
496 578
497 if (irq_stat & 0x2) 579 if (this_irq == info->gpmc_irq_count)
498 goto done; 580 goto done;
499 } 581 }
500 gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat);
501 582
502 return IRQ_HANDLED; 583 return IRQ_HANDLED;
503 584
504done: 585done:
505 complete(&info->comp); 586 complete(&info->comp);
506 /* disable irq */
507 gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ, 0);
508 587
509 /* clear status */ 588 disable_irq_nosync(info->gpmc_irq_fifo);
510 gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, irq_stat); 589 disable_irq_nosync(info->gpmc_irq_count);
511 590
512 return IRQ_HANDLED; 591 return IRQ_HANDLED;
513} 592}
@@ -534,22 +613,22 @@ static void omap_read_buf_irq_pref(struct mtd_info *mtd, u_char *buf, int len)
534 init_completion(&info->comp); 613 init_completion(&info->comp);
535 614
536 /* configure and start prefetch transfer */ 615 /* configure and start prefetch transfer */
537 ret = gpmc_prefetch_enable(info->gpmc_cs, 616 ret = omap_prefetch_enable(info->gpmc_cs,
538 PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0); 617 PREFETCH_FIFOTHRESHOLD_MAX/2, 0x0, len, 0x0, info);
539 if (ret) 618 if (ret)
540 /* PFPW engine is busy, use cpu copy method */ 619 /* PFPW engine is busy, use cpu copy method */
541 goto out_copy; 620 goto out_copy;
542 621
543 info->buf_len = len; 622 info->buf_len = len;
544 /* enable irq */ 623
545 gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ, 624 enable_irq(info->gpmc_irq_count);
546 (GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT)); 625 enable_irq(info->gpmc_irq_fifo);
547 626
548 /* waiting for read to complete */ 627 /* waiting for read to complete */
549 wait_for_completion(&info->comp); 628 wait_for_completion(&info->comp);
550 629
551 /* disable and stop the PFPW engine */ 630 /* disable and stop the PFPW engine */
552 gpmc_prefetch_reset(info->gpmc_cs); 631 omap_prefetch_reset(info->gpmc_cs, info);
553 return; 632 return;
554 633
555out_copy: 634out_copy:
@@ -572,6 +651,7 @@ static void omap_write_buf_irq_pref(struct mtd_info *mtd,
572 struct omap_nand_info, mtd); 651 struct omap_nand_info, mtd);
573 int ret = 0; 652 int ret = 0;
574 unsigned long tim, limit; 653 unsigned long tim, limit;
654 u32 val;
575 655
576 if (len <= mtd->oobsize) { 656 if (len <= mtd->oobsize) {
577 omap_write_buf_pref(mtd, buf, len); 657 omap_write_buf_pref(mtd, buf, len);
@@ -583,27 +663,31 @@ static void omap_write_buf_irq_pref(struct mtd_info *mtd,
583 init_completion(&info->comp); 663 init_completion(&info->comp);
584 664
585 /* configure and start prefetch transfer : size=24 */ 665 /* configure and start prefetch transfer : size=24 */
586 ret = gpmc_prefetch_enable(info->gpmc_cs, 666 ret = omap_prefetch_enable(info->gpmc_cs,
587 (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1); 667 (PREFETCH_FIFOTHRESHOLD_MAX * 3) / 8, 0x0, len, 0x1, info);
588 if (ret) 668 if (ret)
589 /* PFPW engine is busy, use cpu copy method */ 669 /* PFPW engine is busy, use cpu copy method */
590 goto out_copy; 670 goto out_copy;
591 671
592 info->buf_len = len; 672 info->buf_len = len;
593 /* enable irq */ 673
594 gpmc_cs_configure(info->gpmc_cs, GPMC_ENABLE_IRQ, 674 enable_irq(info->gpmc_irq_count);
595 (GPMC_IRQ_FIFOEVENTENABLE | GPMC_IRQ_COUNT_EVENT)); 675 enable_irq(info->gpmc_irq_fifo);
596 676
597 /* waiting for write to complete */ 677 /* waiting for write to complete */
598 wait_for_completion(&info->comp); 678 wait_for_completion(&info->comp);
679
599 /* wait for data to flushed-out before reset the prefetch */ 680 /* wait for data to flushed-out before reset the prefetch */
600 tim = 0; 681 tim = 0;
601 limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS)); 682 limit = (loops_per_jiffy * msecs_to_jiffies(OMAP_NAND_TIMEOUT_MS));
602 while (gpmc_read_status(GPMC_PREFETCH_COUNT) && (tim++ < limit)) 683 do {
684 val = readl(info->reg.gpmc_prefetch_status);
685 val = GPMC_PREFETCH_STATUS_COUNT(val);
603 cpu_relax(); 686 cpu_relax();
687 } while (val && (tim++ < limit));
604 688
605 /* disable and stop the PFPW engine */ 689 /* disable and stop the PFPW engine */
606 gpmc_prefetch_reset(info->gpmc_cs); 690 omap_prefetch_reset(info->gpmc_cs, info);
607 return; 691 return;
608 692
609out_copy: 693out_copy:
@@ -843,7 +927,20 @@ static int omap_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
843{ 927{
844 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, 928 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
845 mtd); 929 mtd);
846 return gpmc_calculate_ecc(info->gpmc_cs, dat, ecc_code); 930 u32 val;
931
932 val = readl(info->reg.gpmc_ecc_config);
933 if (((val >> ECC_CONFIG_CS_SHIFT) & ~CS_MASK) != info->gpmc_cs)
934 return -EINVAL;
935
936 /* read ecc result */
937 val = readl(info->reg.gpmc_ecc1_result);
938 *ecc_code++ = val; /* P128e, ..., P1e */
939 *ecc_code++ = val >> 16; /* P128o, ..., P1o */
940 /* P2048o, P1024o, P512o, P256o, P2048e, P1024e, P512e, P256e */
941 *ecc_code++ = ((val >> 8) & 0x0f) | ((val >> 20) & 0xf0);
942
943 return 0;
847} 944}
848 945
849/** 946/**
@@ -857,8 +954,34 @@ static void omap_enable_hwecc(struct mtd_info *mtd, int mode)
857 mtd); 954 mtd);
858 struct nand_chip *chip = mtd->priv; 955 struct nand_chip *chip = mtd->priv;
859 unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0; 956 unsigned int dev_width = (chip->options & NAND_BUSWIDTH_16) ? 1 : 0;
957 u32 val;
958
959 /* clear ecc and enable bits */
960 val = ECCCLEAR | ECC1;
961 writel(val, info->reg.gpmc_ecc_control);
962
963 /* program ecc and result sizes */
964 val = ((((info->nand.ecc.size >> 1) - 1) << ECCSIZE1_SHIFT) |
965 ECC1RESULTSIZE);
966 writel(val, info->reg.gpmc_ecc_size_config);
860 967
861 gpmc_enable_hwecc(info->gpmc_cs, mode, dev_width, info->nand.ecc.size); 968 switch (mode) {
969 case NAND_ECC_READ:
970 case NAND_ECC_WRITE:
971 writel(ECCCLEAR | ECC1, info->reg.gpmc_ecc_control);
972 break;
973 case NAND_ECC_READSYN:
974 writel(ECCCLEAR, info->reg.gpmc_ecc_control);
975 break;
976 default:
977 dev_info(&info->pdev->dev,
978 "error: unrecognized Mode[%d]!\n", mode);
979 break;
980 }
981
982 /* (ECC 16 or 8 bit col) | ( CS ) | ECC Enable */
983 val = (dev_width << 7) | (info->gpmc_cs << 1) | (0x1);
984 writel(val, info->reg.gpmc_ecc_config);
862} 985}
863 986
864/** 987/**
@@ -886,10 +1009,9 @@ static int omap_wait(struct mtd_info *mtd, struct nand_chip *chip)
886 else 1009 else
887 timeo += (HZ * 20) / 1000; 1010 timeo += (HZ * 20) / 1000;
888 1011
889 gpmc_nand_write(info->gpmc_cs, 1012 writeb(NAND_CMD_STATUS & 0xFF, info->reg.gpmc_nand_command);
890 GPMC_NAND_COMMAND, (NAND_CMD_STATUS & 0xFF));
891 while (time_before(jiffies, timeo)) { 1013 while (time_before(jiffies, timeo)) {
892 status = gpmc_nand_read(info->gpmc_cs, GPMC_NAND_DATA); 1014 status = readb(info->reg.gpmc_nand_data);
893 if (status & NAND_STATUS_READY) 1015 if (status & NAND_STATUS_READY)
894 break; 1016 break;
895 cond_resched(); 1017 cond_resched();
@@ -909,22 +1031,13 @@ static int omap_dev_ready(struct mtd_info *mtd)
909 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, 1031 struct omap_nand_info *info = container_of(mtd, struct omap_nand_info,
910 mtd); 1032 mtd);
911 1033
912 val = gpmc_read_status(GPMC_GET_IRQ_STATUS); 1034 val = readl(info->reg.gpmc_status);
1035
913 if ((val & 0x100) == 0x100) { 1036 if ((val & 0x100) == 0x100) {
914 /* Clear IRQ Interrupt */ 1037 return 1;
915 val |= 0x100;
916 val &= ~(0x0);
917 gpmc_cs_configure(info->gpmc_cs, GPMC_SET_IRQ_STATUS, val);
918 } else { 1038 } else {
919 unsigned int cnt = 0; 1039 return 0;
920 while (cnt++ < 0x1FF) {
921 if ((val & 0x100) == 0x100)
922 return 0;
923 val = gpmc_read_status(GPMC_GET_IRQ_STATUS);
924 }
925 } 1040 }
926
927 return 1;
928} 1041}
929 1042
930#ifdef CONFIG_MTD_NAND_OMAP_BCH 1043#ifdef CONFIG_MTD_NAND_OMAP_BCH
@@ -1155,6 +1268,7 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
1155 int i, offset; 1268 int i, offset;
1156 dma_cap_mask_t mask; 1269 dma_cap_mask_t mask;
1157 unsigned sig; 1270 unsigned sig;
1271 struct resource *res;
1158 1272
1159 pdata = pdev->dev.platform_data; 1273 pdata = pdev->dev.platform_data;
1160 if (pdata == NULL) { 1274 if (pdata == NULL) {
@@ -1174,7 +1288,7 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
1174 info->pdev = pdev; 1288 info->pdev = pdev;
1175 1289
1176 info->gpmc_cs = pdata->cs; 1290 info->gpmc_cs = pdata->cs;
1177 info->phys_base = pdata->phys_base; 1291 info->reg = pdata->reg;
1178 1292
1179 info->mtd.priv = &info->nand; 1293 info->mtd.priv = &info->nand;
1180 info->mtd.name = dev_name(&pdev->dev); 1294 info->mtd.name = dev_name(&pdev->dev);
@@ -1183,16 +1297,23 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
1183 info->nand.options = pdata->devsize; 1297 info->nand.options = pdata->devsize;
1184 info->nand.options |= NAND_SKIP_BBTSCAN; 1298 info->nand.options |= NAND_SKIP_BBTSCAN;
1185 1299
1186 /* NAND write protect off */ 1300 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1187 gpmc_cs_configure(info->gpmc_cs, GPMC_CONFIG_WP, 0); 1301 if (res == NULL) {
1302 err = -EINVAL;
1303 dev_err(&pdev->dev, "error getting memory resource\n");
1304 goto out_free_info;
1305 }
1306
1307 info->phys_base = res->start;
1308 info->mem_size = resource_size(res);
1188 1309
1189 if (!request_mem_region(info->phys_base, NAND_IO_SIZE, 1310 if (!request_mem_region(info->phys_base, info->mem_size,
1190 pdev->dev.driver->name)) { 1311 pdev->dev.driver->name)) {
1191 err = -EBUSY; 1312 err = -EBUSY;
1192 goto out_free_info; 1313 goto out_free_info;
1193 } 1314 }
1194 1315
1195 info->nand.IO_ADDR_R = ioremap(info->phys_base, NAND_IO_SIZE); 1316 info->nand.IO_ADDR_R = ioremap(info->phys_base, info->mem_size);
1196 if (!info->nand.IO_ADDR_R) { 1317 if (!info->nand.IO_ADDR_R) {
1197 err = -ENOMEM; 1318 err = -ENOMEM;
1198 goto out_release_mem_region; 1319 goto out_release_mem_region;
@@ -1265,17 +1386,39 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
1265 break; 1386 break;
1266 1387
1267 case NAND_OMAP_PREFETCH_IRQ: 1388 case NAND_OMAP_PREFETCH_IRQ:
1268 err = request_irq(pdata->gpmc_irq, 1389 info->gpmc_irq_fifo = platform_get_irq(pdev, 0);
1269 omap_nand_irq, IRQF_SHARED, "gpmc-nand", info); 1390 if (info->gpmc_irq_fifo <= 0) {
1391 dev_err(&pdev->dev, "error getting fifo irq\n");
1392 err = -ENODEV;
1393 goto out_release_mem_region;
1394 }
1395 err = request_irq(info->gpmc_irq_fifo, omap_nand_irq,
1396 IRQF_SHARED, "gpmc-nand-fifo", info);
1270 if (err) { 1397 if (err) {
1271 dev_err(&pdev->dev, "requesting irq(%d) error:%d", 1398 dev_err(&pdev->dev, "requesting irq(%d) error:%d",
1272 pdata->gpmc_irq, err); 1399 info->gpmc_irq_fifo, err);
1400 info->gpmc_irq_fifo = 0;
1401 goto out_release_mem_region;
1402 }
1403
1404 info->gpmc_irq_count = platform_get_irq(pdev, 1);
1405 if (info->gpmc_irq_count <= 0) {
1406 dev_err(&pdev->dev, "error getting count irq\n");
1407 err = -ENODEV;
1408 goto out_release_mem_region;
1409 }
1410 err = request_irq(info->gpmc_irq_count, omap_nand_irq,
1411 IRQF_SHARED, "gpmc-nand-count", info);
1412 if (err) {
1413 dev_err(&pdev->dev, "requesting irq(%d) error:%d",
1414 info->gpmc_irq_count, err);
1415 info->gpmc_irq_count = 0;
1273 goto out_release_mem_region; 1416 goto out_release_mem_region;
1274 } else {
1275 info->gpmc_irq = pdata->gpmc_irq;
1276 info->nand.read_buf = omap_read_buf_irq_pref;
1277 info->nand.write_buf = omap_write_buf_irq_pref;
1278 } 1417 }
1418
1419 info->nand.read_buf = omap_read_buf_irq_pref;
1420 info->nand.write_buf = omap_write_buf_irq_pref;
1421
1279 break; 1422 break;
1280 1423
1281 default: 1424 default:
@@ -1363,7 +1506,11 @@ static int __devinit omap_nand_probe(struct platform_device *pdev)
1363out_release_mem_region: 1506out_release_mem_region:
1364 if (info->dma) 1507 if (info->dma)
1365 dma_release_channel(info->dma); 1508 dma_release_channel(info->dma);
1366 release_mem_region(info->phys_base, NAND_IO_SIZE); 1509 if (info->gpmc_irq_count > 0)
1510 free_irq(info->gpmc_irq_count, info);
1511 if (info->gpmc_irq_fifo > 0)
1512 free_irq(info->gpmc_irq_fifo, info);
1513 release_mem_region(info->phys_base, info->mem_size);
1367out_free_info: 1514out_free_info:
1368 kfree(info); 1515 kfree(info);
1369 1516
@@ -1381,8 +1528,10 @@ static int omap_nand_remove(struct platform_device *pdev)
1381 if (info->dma) 1528 if (info->dma)
1382 dma_release_channel(info->dma); 1529 dma_release_channel(info->dma);
1383 1530
1384 if (info->gpmc_irq) 1531 if (info->gpmc_irq_count > 0)
1385 free_irq(info->gpmc_irq, info); 1532 free_irq(info->gpmc_irq_count, info);
1533 if (info->gpmc_irq_fifo > 0)
1534 free_irq(info->gpmc_irq_fifo, info);
1386 1535
1387 /* Release NAND device, its internal structures and partitions */ 1536 /* Release NAND device, its internal structures and partitions */
1388 nand_release(&info->mtd); 1537 nand_release(&info->mtd);
diff --git a/drivers/mtd/onenand/omap2.c b/drivers/mtd/onenand/omap2.c
index 398a82783848..1961be985171 100644
--- a/drivers/mtd/onenand/omap2.c
+++ b/drivers/mtd/onenand/omap2.c
@@ -39,22 +39,21 @@
39 39
40#include <asm/mach/flash.h> 40#include <asm/mach/flash.h>
41#include <plat/gpmc.h> 41#include <plat/gpmc.h>
42#include <plat/onenand.h> 42#include <linux/platform_data/mtd-onenand-omap2.h>
43#include <asm/gpio.h> 43#include <asm/gpio.h>
44 44
45#include <plat/dma.h> 45#include <plat/dma.h>
46 46#include <plat/cpu.h>
47#include <plat/board.h>
48 47
49#define DRIVER_NAME "omap2-onenand" 48#define DRIVER_NAME "omap2-onenand"
50 49
51#define ONENAND_IO_SIZE SZ_128K
52#define ONENAND_BUFRAM_SIZE (1024 * 5) 50#define ONENAND_BUFRAM_SIZE (1024 * 5)
53 51
54struct omap2_onenand { 52struct omap2_onenand {
55 struct platform_device *pdev; 53 struct platform_device *pdev;
56 int gpmc_cs; 54 int gpmc_cs;
57 unsigned long phys_base; 55 unsigned long phys_base;
56 unsigned int mem_size;
58 int gpio_irq; 57 int gpio_irq;
59 struct mtd_info mtd; 58 struct mtd_info mtd;
60 struct onenand_chip onenand; 59 struct onenand_chip onenand;
@@ -626,6 +625,7 @@ static int __devinit omap2_onenand_probe(struct platform_device *pdev)
626 struct omap2_onenand *c; 625 struct omap2_onenand *c;
627 struct onenand_chip *this; 626 struct onenand_chip *this;
628 int r; 627 int r;
628 struct resource *res;
629 629
630 pdata = pdev->dev.platform_data; 630 pdata = pdev->dev.platform_data;
631 if (pdata == NULL) { 631 if (pdata == NULL) {
@@ -647,20 +647,24 @@ static int __devinit omap2_onenand_probe(struct platform_device *pdev)
647 c->gpio_irq = 0; 647 c->gpio_irq = 0;
648 } 648 }
649 649
650 r = gpmc_cs_request(c->gpmc_cs, ONENAND_IO_SIZE, &c->phys_base); 650 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
651 if (r < 0) { 651 if (res == NULL) {
652 dev_err(&pdev->dev, "Cannot request GPMC CS\n"); 652 r = -EINVAL;
653 dev_err(&pdev->dev, "error getting memory resource\n");
653 goto err_kfree; 654 goto err_kfree;
654 } 655 }
655 656
656 if (request_mem_region(c->phys_base, ONENAND_IO_SIZE, 657 c->phys_base = res->start;
658 c->mem_size = resource_size(res);
659
660 if (request_mem_region(c->phys_base, c->mem_size,
657 pdev->dev.driver->name) == NULL) { 661 pdev->dev.driver->name) == NULL) {
658 dev_err(&pdev->dev, "Cannot reserve memory region at 0x%08lx, " 662 dev_err(&pdev->dev, "Cannot reserve memory region at 0x%08lx, size: 0x%x\n",
659 "size: 0x%x\n", c->phys_base, ONENAND_IO_SIZE); 663 c->phys_base, c->mem_size);
660 r = -EBUSY; 664 r = -EBUSY;
661 goto err_free_cs; 665 goto err_kfree;
662 } 666 }
663 c->onenand.base = ioremap(c->phys_base, ONENAND_IO_SIZE); 667 c->onenand.base = ioremap(c->phys_base, c->mem_size);
664 if (c->onenand.base == NULL) { 668 if (c->onenand.base == NULL) {
665 r = -ENOMEM; 669 r = -ENOMEM;
666 goto err_release_mem_region; 670 goto err_release_mem_region;
@@ -776,9 +780,7 @@ err_release_gpio:
776err_iounmap: 780err_iounmap:
777 iounmap(c->onenand.base); 781 iounmap(c->onenand.base);
778err_release_mem_region: 782err_release_mem_region:
779 release_mem_region(c->phys_base, ONENAND_IO_SIZE); 783 release_mem_region(c->phys_base, c->mem_size);
780err_free_cs:
781 gpmc_cs_free(c->gpmc_cs);
782err_kfree: 784err_kfree:
783 kfree(c); 785 kfree(c);
784 786
@@ -800,7 +802,7 @@ static int __devexit omap2_onenand_remove(struct platform_device *pdev)
800 gpio_free(c->gpio_irq); 802 gpio_free(c->gpio_irq);
801 } 803 }
802 iounmap(c->onenand.base); 804 iounmap(c->onenand.base);
803 release_mem_region(c->phys_base, ONENAND_IO_SIZE); 805 release_mem_region(c->phys_base, c->mem_size);
804 gpmc_cs_free(c->gpmc_cs); 806 gpmc_cs_free(c->gpmc_cs);
805 kfree(c); 807 kfree(c);
806 808
diff --git a/drivers/net/ethernet/seeq/ether3.c b/drivers/net/ethernet/seeq/ether3.c
index df808ac8cb65..6a40dd03a32f 100644
--- a/drivers/net/ethernet/seeq/ether3.c
+++ b/drivers/net/ethernet/seeq/ether3.c
@@ -99,13 +99,13 @@ typedef enum {
99 * The SEEQ8005 doesn't like us writing to its registers 99 * The SEEQ8005 doesn't like us writing to its registers
100 * too quickly. 100 * too quickly.
101 */ 101 */
102static inline void ether3_outb(int v, const void __iomem *r) 102static inline void ether3_outb(int v, void __iomem *r)
103{ 103{
104 writeb(v, r); 104 writeb(v, r);
105 udelay(1); 105 udelay(1);
106} 106}
107 107
108static inline void ether3_outw(int v, const void __iomem *r) 108static inline void ether3_outw(int v, void __iomem *r)
109{ 109{
110 writew(v, r); 110 writew(v, r);
111 udelay(1); 111 udelay(1);
diff --git a/drivers/pcmcia/omap_cf.c b/drivers/pcmcia/omap_cf.c
index 0ad06a3bd562..fa74efe82206 100644
--- a/drivers/pcmcia/omap_cf.c
+++ b/drivers/pcmcia/omap_cf.c
@@ -24,7 +24,7 @@
24#include <asm/io.h> 24#include <asm/io.h>
25#include <asm/sizes.h> 25#include <asm/sizes.h>
26 26
27#include <plat/mux.h> 27#include <mach/mux.h>
28#include <plat/tc.h> 28#include <plat/tc.h>
29 29
30 30
diff --git a/drivers/pinctrl/pinctrl-coh901.c b/drivers/pinctrl/pinctrl-coh901.c
index cc0f00d73d15..b446c9641212 100644
--- a/drivers/pinctrl/pinctrl-coh901.c
+++ b/drivers/pinctrl/pinctrl-coh901.c
@@ -1,11 +1,8 @@
1/* 1/*
2 * U300 GPIO module. 2 * U300 GPIO module.
3 * 3 *
4 * Copyright (C) 2007-2011 ST-Ericsson AB 4 * Copyright (C) 2007-2012 ST-Ericsson AB
5 * License terms: GNU General Public License (GPL) version 2 5 * License terms: GNU General Public License (GPL) version 2
6 * This can driver either of the two basic GPIO cores
7 * available in the U300 platforms:
8 * COH 901 335 - Used in DB3150 (U300 1.0) and DB3200 (U330 1.0)
9 * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0) 6 * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0)
10 * Author: Linus Walleij <linus.walleij@linaro.org> 7 * Author: Linus Walleij <linus.walleij@linaro.org>
11 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> 8 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
@@ -24,19 +21,22 @@
24#include <linux/slab.h> 21#include <linux/slab.h>
25#include <linux/pinctrl/consumer.h> 22#include <linux/pinctrl/consumer.h>
26#include <linux/pinctrl/pinconf-generic.h> 23#include <linux/pinctrl/pinconf-generic.h>
27#include <mach/gpio-u300.h> 24#include <linux/platform_data/pinctrl-coh901.h>
28#include "pinctrl-coh901.h" 25#include "pinctrl-coh901.h"
29 26
27#define U300_GPIO_PORT_STRIDE (0x30)
30/* 28/*
31 * Register definitions for COH 901 335 variant 29 * Control Register 32bit (R/W)
30 * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores
31 * gives the number of GPIO pins.
32 * bit 8-2 (mask 0x000001FC) contains the core version ID.
32 */ 33 */
33#define U300_335_PORT_STRIDE (0x1C) 34#define U300_GPIO_CR (0x00)
34/* Port X Pin Data Register 32bit, this is both input and output (R/W) */ 35#define U300_GPIO_CR_SYNC_SEL_ENABLE (0x00000002UL)
35#define U300_335_PXPDIR (0x00) 36#define U300_GPIO_CR_BLOCK_CLKRQ_ENABLE (0x00000001UL)
36#define U300_335_PXPDOR (0x00) 37#define U300_GPIO_PXPDIR (0x04)
37/* Port X Pin Config Register 32bit (R/W) */ 38#define U300_GPIO_PXPDOR (0x08)
38#define U300_335_PXPCR (0x04) 39#define U300_GPIO_PXPCR (0x0C)
39/* This register layout is the same in both blocks */
40#define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK (0x0000FFFFUL) 40#define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK (0x0000FFFFUL)
41#define U300_GPIO_PXPCR_PIN_MODE_MASK (0x00000003UL) 41#define U300_GPIO_PXPCR_PIN_MODE_MASK (0x00000003UL)
42#define U300_GPIO_PXPCR_PIN_MODE_SHIFT (0x00000002UL) 42#define U300_GPIO_PXPCR_PIN_MODE_SHIFT (0x00000002UL)
@@ -44,53 +44,17 @@
44#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL (0x00000001UL) 44#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL (0x00000001UL)
45#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN (0x00000002UL) 45#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN (0x00000002UL)
46#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE (0x00000003UL) 46#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE (0x00000003UL)
47/* Port X Interrupt Event Register 32bit (R/W) */ 47#define U300_GPIO_PXPER (0x10)
48#define U300_335_PXIEV (0x08) 48#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK (0x000000FFUL)
49/* Port X Interrupt Enable Register 32bit (R/W) */ 49#define U300_GPIO_PXPER_PULL_UP_DISABLE (0x00000001UL)
50#define U300_335_PXIEN (0x0C) 50#define U300_GPIO_PXIEV (0x14)
51/* Port X Interrupt Force Register 32bit (R/W) */ 51#define U300_GPIO_PXIEN (0x18)
52#define U300_335_PXIFR (0x10) 52#define U300_GPIO_PXIFR (0x1C)
53/* Port X Interrupt Config Register 32bit (R/W) */ 53#define U300_GPIO_PXICR (0x20)
54#define U300_335_PXICR (0x14)
55/* This register layout is the same in both blocks */
56#define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK (0x000000FFUL) 54#define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK (0x000000FFUL)
57#define U300_GPIO_PXICR_IRQ_CONFIG_MASK (0x00000001UL) 55#define U300_GPIO_PXICR_IRQ_CONFIG_MASK (0x00000001UL)
58#define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE (0x00000000UL) 56#define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE (0x00000000UL)
59#define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL) 57#define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL)
60/* Port X Pull-up Enable Register 32bit (R/W) */
61#define U300_335_PXPER (0x18)
62/* This register layout is the same in both blocks */
63#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK (0x000000FFUL)
64#define U300_GPIO_PXPER_PULL_UP_DISABLE (0x00000001UL)
65/* Control Register 32bit (R/W) */
66#define U300_335_CR (0x54)
67#define U300_335_CR_BLOCK_CLOCK_ENABLE (0x00000001UL)
68
69/*
70 * Register definitions for COH 901 571 / 3 variant
71 */
72#define U300_571_PORT_STRIDE (0x30)
73/*
74 * Control Register 32bit (R/W)
75 * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores
76 * gives the number of GPIO pins.
77 * bit 8-2 (mask 0x000001FC) contains the core version ID.
78 */
79#define U300_571_CR (0x00)
80#define U300_571_CR_SYNC_SEL_ENABLE (0x00000002UL)
81#define U300_571_CR_BLOCK_CLKRQ_ENABLE (0x00000001UL)
82/*
83 * These registers have the same layout and function as the corresponding
84 * COH 901 335 registers, just at different offset.
85 */
86#define U300_571_PXPDIR (0x04)
87#define U300_571_PXPDOR (0x08)
88#define U300_571_PXPCR (0x0C)
89#define U300_571_PXPER (0x10)
90#define U300_571_PXIEV (0x14)
91#define U300_571_PXIEN (0x18)
92#define U300_571_PXIFR (0x1C)
93#define U300_571_PXICR (0x20)
94 58
95/* 8 bits per port, no version has more than 7 ports */ 59/* 8 bits per port, no version has more than 7 ports */
96#define U300_GPIO_PINS_PER_PORT 8 60#define U300_GPIO_PINS_PER_PORT 8
@@ -149,8 +113,6 @@ struct u300_gpio_confdata {
149 113
150/* BS335 has seven ports of 8 bits each = GPIO pins 0..55 */ 114/* BS335 has seven ports of 8 bits each = GPIO pins 0..55 */
151#define BS335_GPIO_NUM_PORTS 7 115#define BS335_GPIO_NUM_PORTS 7
152/* BS365 has five ports of 8 bits each = GPIO pins 0..39 */
153#define BS365_GPIO_NUM_PORTS 5
154 116
155#define U300_FLOATING_INPUT { \ 117#define U300_FLOATING_INPUT { \
156 .bias_mode = PIN_CONFIG_BIAS_HIGH_IMPEDANCE, \ 118 .bias_mode = PIN_CONFIG_BIAS_HIGH_IMPEDANCE, \
@@ -172,7 +134,6 @@ struct u300_gpio_confdata {
172 .outval = 1, \ 134 .outval = 1, \
173} 135}
174 136
175
176/* Initial configuration */ 137/* Initial configuration */
177static const struct __initconst u300_gpio_confdata 138static const struct __initconst u300_gpio_confdata
178bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = { 139bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
@@ -255,66 +216,6 @@ bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
255 } 216 }
256}; 217};
257 218
258static const struct __initconst u300_gpio_confdata
259bs365_gpio_config[BS365_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
260 /* Port 0, pins 0-7 */
261 {
262 U300_FLOATING_INPUT,
263 U300_OUTPUT_LOW,
264 U300_FLOATING_INPUT,
265 U300_OUTPUT_LOW,
266 U300_OUTPUT_LOW,
267 U300_OUTPUT_LOW,
268 U300_PULL_UP_INPUT,
269 U300_FLOATING_INPUT,
270 },
271 /* Port 1, pins 0-7 */
272 {
273 U300_OUTPUT_LOW,
274 U300_FLOATING_INPUT,
275 U300_OUTPUT_LOW,
276 U300_FLOATING_INPUT,
277 U300_FLOATING_INPUT,
278 U300_OUTPUT_HIGH,
279 U300_OUTPUT_LOW,
280 U300_OUTPUT_LOW,
281 },
282 /* Port 2, pins 0-7 */
283 {
284 U300_FLOATING_INPUT,
285 U300_PULL_UP_INPUT,
286 U300_OUTPUT_LOW,
287 U300_OUTPUT_LOW,
288 U300_PULL_UP_INPUT,
289 U300_PULL_UP_INPUT,
290 U300_PULL_UP_INPUT,
291 U300_PULL_UP_INPUT,
292 },
293 /* Port 3, pins 0-7 */
294 {
295 U300_PULL_UP_INPUT,
296 U300_PULL_UP_INPUT,
297 U300_PULL_UP_INPUT,
298 U300_PULL_UP_INPUT,
299 U300_PULL_UP_INPUT,
300 U300_PULL_UP_INPUT,
301 U300_PULL_UP_INPUT,
302 U300_PULL_UP_INPUT,
303 },
304 /* Port 4, pins 0-7 */
305 {
306 U300_PULL_UP_INPUT,
307 U300_PULL_UP_INPUT,
308 U300_PULL_UP_INPUT,
309 U300_PULL_UP_INPUT,
310 /* These 4 pins doesn't exist on DB3210 */
311 U300_OUTPUT_LOW,
312 U300_OUTPUT_LOW,
313 U300_OUTPUT_LOW,
314 U300_OUTPUT_LOW,
315 }
316};
317
318/** 219/**
319 * to_u300_gpio() - get the pointer to u300_gpio 220 * to_u300_gpio() - get the pointer to u300_gpio
320 * @chip: the gpio chip member of the structure u300_gpio 221 * @chip: the gpio chip member of the structure u300_gpio
@@ -716,13 +617,7 @@ static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio,
716 const struct u300_gpio_confdata *conf; 617 const struct u300_gpio_confdata *conf;
717 int offset = (i*8) + j; 618 int offset = (i*8) + j;
718 619
719 if (plat->variant == U300_GPIO_COH901571_3_BS335) 620 conf = &bs335_gpio_config[i][j];
720 conf = &bs335_gpio_config[i][j];
721 else if (plat->variant == U300_GPIO_COH901571_3_BS365)
722 conf = &bs365_gpio_config[i][j];
723 else
724 break;
725
726 u300_gpio_init_pin(gpio, offset, conf); 621 u300_gpio_init_pin(gpio, offset, conf);
727 } 622 }
728 } 623 }
@@ -796,50 +691,27 @@ static int __init u300_gpio_probe(struct platform_device *pdev)
796 goto err_no_ioremap; 691 goto err_no_ioremap;
797 } 692 }
798 693
799 if (plat->variant == U300_GPIO_COH901335) { 694 dev_info(gpio->dev,
800 dev_info(gpio->dev, 695 "initializing GPIO Controller COH 901 571/3\n");
801 "initializing GPIO Controller COH 901 335\n"); 696 gpio->stride = U300_GPIO_PORT_STRIDE;
802 gpio->stride = U300_335_PORT_STRIDE; 697 gpio->pcr = U300_GPIO_PXPCR;
803 gpio->pcr = U300_335_PXPCR; 698 gpio->dor = U300_GPIO_PXPDOR;
804 gpio->dor = U300_335_PXPDOR; 699 gpio->dir = U300_GPIO_PXPDIR;
805 gpio->dir = U300_335_PXPDIR; 700 gpio->per = U300_GPIO_PXPER;
806 gpio->per = U300_335_PXPER; 701 gpio->icr = U300_GPIO_PXICR;
807 gpio->icr = U300_335_PXICR; 702 gpio->ien = U300_GPIO_PXIEN;
808 gpio->ien = U300_335_PXIEN; 703 gpio->iev = U300_GPIO_PXIEV;
809 gpio->iev = U300_335_PXIEV; 704 ifr = U300_GPIO_PXIFR;
810 ifr = U300_335_PXIFR; 705
811 706 val = readl(gpio->base + U300_GPIO_CR);
812 /* Turn on the GPIO block */ 707 dev_info(gpio->dev, "COH901571/3 block version: %d, " \
813 writel(U300_335_CR_BLOCK_CLOCK_ENABLE, 708 "number of cores: %d totalling %d pins\n",
814 gpio->base + U300_335_CR); 709 ((val & 0x000001FC) >> 2),
815 } else if (plat->variant == U300_GPIO_COH901571_3_BS335 || 710 ((val & 0x0000FE00) >> 9),
816 plat->variant == U300_GPIO_COH901571_3_BS365) { 711 ((val & 0x0000FE00) >> 9) * 8);
817 dev_info(gpio->dev, 712 writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE,
818 "initializing GPIO Controller COH 901 571/3\n"); 713 gpio->base + U300_GPIO_CR);
819 gpio->stride = U300_571_PORT_STRIDE; 714 u300_gpio_init_coh901571(gpio, plat);
820 gpio->pcr = U300_571_PXPCR;
821 gpio->dor = U300_571_PXPDOR;
822 gpio->dir = U300_571_PXPDIR;
823 gpio->per = U300_571_PXPER;
824 gpio->icr = U300_571_PXICR;
825 gpio->ien = U300_571_PXIEN;
826 gpio->iev = U300_571_PXIEV;
827 ifr = U300_571_PXIFR;
828
829 val = readl(gpio->base + U300_571_CR);
830 dev_info(gpio->dev, "COH901571/3 block version: %d, " \
831 "number of cores: %d totalling %d pins\n",
832 ((val & 0x000001FC) >> 2),
833 ((val & 0x0000FE00) >> 9),
834 ((val & 0x0000FE00) >> 9) * 8);
835 writel(U300_571_CR_BLOCK_CLKRQ_ENABLE,
836 gpio->base + U300_571_CR);
837 u300_gpio_init_coh901571(gpio, plat);
838 } else {
839 dev_err(gpio->dev, "unknown block variant\n");
840 err = -ENODEV;
841 goto err_unknown_variant;
842 }
843 715
844 /* Add each port with its IRQ separately */ 716 /* Add each port with its IRQ separately */
845 INIT_LIST_HEAD(&gpio->port_list); 717 INIT_LIST_HEAD(&gpio->port_list);
@@ -906,7 +778,6 @@ err_no_pinctrl:
906err_no_chip: 778err_no_chip:
907err_no_port: 779err_no_port:
908 u300_gpio_free_ports(gpio); 780 u300_gpio_free_ports(gpio);
909err_unknown_variant:
910 iounmap(gpio->base); 781 iounmap(gpio->base);
911err_no_ioremap: 782err_no_ioremap:
912 release_mem_region(gpio->memres->start, resource_size(gpio->memres)); 783 release_mem_region(gpio->memres->start, resource_size(gpio->memres));
@@ -923,16 +794,11 @@ err_no_clk:
923 794
924static int __exit u300_gpio_remove(struct platform_device *pdev) 795static int __exit u300_gpio_remove(struct platform_device *pdev)
925{ 796{
926 struct u300_gpio_platform *plat = dev_get_platdata(&pdev->dev);
927 struct u300_gpio *gpio = platform_get_drvdata(pdev); 797 struct u300_gpio *gpio = platform_get_drvdata(pdev);
928 int err; 798 int err;
929 799
930 /* Turn off the GPIO block */ 800 /* Turn off the GPIO block */
931 if (plat->variant == U300_GPIO_COH901335) 801 writel(0x00000000U, gpio->base + U300_GPIO_CR);
932 writel(0x00000000U, gpio->base + U300_335_CR);
933 if (plat->variant == U300_GPIO_COH901571_3_BS335 ||
934 plat->variant == U300_GPIO_COH901571_3_BS365)
935 writel(0x00000000U, gpio->base + U300_571_CR);
936 802
937 err = gpiochip_remove(&gpio->chip); 803 err = gpiochip_remove(&gpio->chip);
938 if (err < 0) { 804 if (err < 0) {
diff --git a/drivers/power/avs/smartreflex.c b/drivers/power/avs/smartreflex.c
index 44efc6e202af..d4957b4edb62 100644
--- a/drivers/power/avs/smartreflex.c
+++ b/drivers/power/avs/smartreflex.c
@@ -27,6 +27,8 @@
27#include <linux/pm_runtime.h> 27#include <linux/pm_runtime.h>
28#include <linux/power/smartreflex.h> 28#include <linux/power/smartreflex.h>
29 29
30#include <plat/cpu.h>
31
30#define SMARTREFLEX_NAME_LEN 16 32#define SMARTREFLEX_NAME_LEN 16
31#define NVALUE_NAME_LEN 40 33#define NVALUE_NAME_LEN 40
32#define SR_DISABLE_TIMEOUT 200 34#define SR_DISABLE_TIMEOUT 200
diff --git a/drivers/remoteproc/omap_remoteproc.c b/drivers/remoteproc/omap_remoteproc.c
index a1f7ac1f8cf6..b54504ee61f1 100644
--- a/drivers/remoteproc/omap_remoteproc.c
+++ b/drivers/remoteproc/omap_remoteproc.c
@@ -29,7 +29,7 @@
29#include <linux/remoteproc.h> 29#include <linux/remoteproc.h>
30 30
31#include <plat/mailbox.h> 31#include <plat/mailbox.h>
32#include <plat/remoteproc.h> 32#include <linux/platform_data/remoteproc-omap.h>
33 33
34#include "omap_remoteproc.h" 34#include "omap_remoteproc.h"
35#include "remoteproc_internal.h" 35#include "remoteproc_internal.h"
diff --git a/drivers/scsi/arm/eesox.c b/drivers/scsi/arm/eesox.c
index edfd12b48c28..968d08358d20 100644
--- a/drivers/scsi/arm/eesox.c
+++ b/drivers/scsi/arm/eesox.c
@@ -273,7 +273,7 @@ static void eesoxscsi_buffer_out(void *buf, int length, void __iomem *base)
273{ 273{
274 const void __iomem *reg_fas = base + EESOX_FAS216_OFFSET; 274 const void __iomem *reg_fas = base + EESOX_FAS216_OFFSET;
275 const void __iomem *reg_dmastat = base + EESOX_DMASTAT; 275 const void __iomem *reg_dmastat = base + EESOX_DMASTAT;
276 const void __iomem *reg_dmadata = base + EESOX_DMADATA; 276 void __iomem *reg_dmadata = base + EESOX_DMADATA;
277 277
278 do { 278 do {
279 unsigned int status; 279 unsigned int status;
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 5f84b5563c2d..2d198a01a410 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -366,7 +366,7 @@ config SPI_STMP3XXX
366 366
367config SPI_TEGRA 367config SPI_TEGRA
368 tristate "Nvidia Tegra SPI controller" 368 tristate "Nvidia Tegra SPI controller"
369 depends on ARCH_TEGRA && (TEGRA_SYSTEM_DMA || TEGRA20_APB_DMA) 369 depends on ARCH_TEGRA && TEGRA20_APB_DMA
370 help 370 help
371 SPI driver for NVidia Tegra SoCs 371 SPI driver for NVidia Tegra SoCs
372 372
diff --git a/drivers/spi/spi-omap-uwire.c b/drivers/spi/spi-omap-uwire.c
index 9b0d71696039..0a94d9dc9c31 100644
--- a/drivers/spi/spi-omap-uwire.c
+++ b/drivers/spi/spi-omap-uwire.c
@@ -52,8 +52,9 @@
52#include <asm/io.h> 52#include <asm/io.h>
53#include <asm/mach-types.h> 53#include <asm/mach-types.h>
54 54
55#include <plat/mux.h> 55#include <mach/mux.h>
56#include <plat/omap7xx.h> /* OMAP7XX_IO_CONF registers */ 56
57#include <mach/omap7xx.h> /* OMAP7XX_IO_CONF registers */
57 58
58 59
59/* FIXME address is now a platform device resource, 60/* FIXME address is now a platform device resource,
diff --git a/drivers/spi/spi-omap2-mcspi.c b/drivers/spi/spi-omap2-mcspi.c
index 569714ebffe0..5d59a69a9064 100644
--- a/drivers/spi/spi-omap2-mcspi.c
+++ b/drivers/spi/spi-omap2-mcspi.c
@@ -42,7 +42,7 @@
42#include <linux/spi/spi.h> 42#include <linux/spi/spi.h>
43 43
44#include <plat/clock.h> 44#include <plat/clock.h>
45#include <plat/mcspi.h> 45#include <linux/platform_data/spi-omap2-mcspi.h>
46 46
47#define OMAP2_MCSPI_MAX_FREQ 48000000 47#define OMAP2_MCSPI_MAX_FREQ 48000000
48#define SPI_AUTOSUSPEND_TIMEOUT 2000 48#define SPI_AUTOSUSPEND_TIMEOUT 2000
diff --git a/drivers/spi/spi-tegra.c b/drivers/spi/spi-tegra.c
index ef52c1c6f5c5..488d9b6e9cbe 100644
--- a/drivers/spi/spi-tegra.c
+++ b/drivers/spi/spi-tegra.c
@@ -164,23 +164,15 @@ struct spi_tegra_data {
164 * for the generic case. 164 * for the generic case.
165 */ 165 */
166 int dma_req_len; 166 int dma_req_len;
167#if defined(CONFIG_TEGRA_SYSTEM_DMA)
168 struct tegra_dma_req rx_dma_req;
169 struct tegra_dma_channel *rx_dma;
170#else
171 struct dma_chan *rx_dma; 167 struct dma_chan *rx_dma;
172 struct dma_slave_config sconfig; 168 struct dma_slave_config sconfig;
173 struct dma_async_tx_descriptor *rx_dma_desc; 169 struct dma_async_tx_descriptor *rx_dma_desc;
174 dma_cookie_t rx_cookie; 170 dma_cookie_t rx_cookie;
175#endif
176 u32 *rx_bb; 171 u32 *rx_bb;
177 dma_addr_t rx_bb_phys; 172 dma_addr_t rx_bb_phys;
178}; 173};
179 174
180#if !defined(CONFIG_TEGRA_SYSTEM_DMA)
181static void tegra_spi_rx_dma_complete(void *args); 175static void tegra_spi_rx_dma_complete(void *args);
182#endif
183
184static inline unsigned long spi_tegra_readl(struct spi_tegra_data *tspi, 176static inline unsigned long spi_tegra_readl(struct spi_tegra_data *tspi,
185 unsigned long reg) 177 unsigned long reg)
186{ 178{
@@ -204,10 +196,6 @@ static void spi_tegra_go(struct spi_tegra_data *tspi)
204 val &= ~SLINK_DMA_BLOCK_SIZE(~0) & ~SLINK_DMA_EN; 196 val &= ~SLINK_DMA_BLOCK_SIZE(~0) & ~SLINK_DMA_EN;
205 val |= SLINK_DMA_BLOCK_SIZE(tspi->dma_req_len / 4 - 1); 197 val |= SLINK_DMA_BLOCK_SIZE(tspi->dma_req_len / 4 - 1);
206 spi_tegra_writel(tspi, val, SLINK_DMA_CTL); 198 spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
207#if defined(CONFIG_TEGRA_SYSTEM_DMA)
208 tspi->rx_dma_req.size = tspi->dma_req_len;
209 tegra_dma_enqueue_req(tspi->rx_dma, &tspi->rx_dma_req);
210#else
211 tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma, 199 tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma,
212 tspi->rx_bb_phys, tspi->dma_req_len, 200 tspi->rx_bb_phys, tspi->dma_req_len,
213 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); 201 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
@@ -219,7 +207,6 @@ static void spi_tegra_go(struct spi_tegra_data *tspi)
219 tspi->rx_dma_desc->callback_param = tspi; 207 tspi->rx_dma_desc->callback_param = tspi;
220 tspi->rx_cookie = dmaengine_submit(tspi->rx_dma_desc); 208 tspi->rx_cookie = dmaengine_submit(tspi->rx_dma_desc);
221 dma_async_issue_pending(tspi->rx_dma); 209 dma_async_issue_pending(tspi->rx_dma);
222#endif
223 210
224 val |= SLINK_DMA_EN; 211 val |= SLINK_DMA_EN;
225 spi_tegra_writel(tspi, val, SLINK_DMA_CTL); 212 spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
@@ -405,19 +392,12 @@ static void handle_spi_rx_dma_complete(struct spi_tegra_data *tspi)
405 392
406 spin_unlock_irqrestore(&tspi->lock, flags); 393 spin_unlock_irqrestore(&tspi->lock, flags);
407} 394}
408#if defined(CONFIG_TEGRA_SYSTEM_DMA) 395
409static void tegra_spi_rx_dma_complete(struct tegra_dma_req *req)
410{
411 struct spi_tegra_data *tspi = req->dev;
412 handle_spi_rx_dma_complete(tspi);
413}
414#else
415static void tegra_spi_rx_dma_complete(void *args) 396static void tegra_spi_rx_dma_complete(void *args)
416{ 397{
417 struct spi_tegra_data *tspi = args; 398 struct spi_tegra_data *tspi = args;
418 handle_spi_rx_dma_complete(tspi); 399 handle_spi_rx_dma_complete(tspi);
419} 400}
420#endif
421 401
422static int spi_tegra_setup(struct spi_device *spi) 402static int spi_tegra_setup(struct spi_device *spi)
423{ 403{
@@ -509,9 +489,7 @@ static int __devinit spi_tegra_probe(struct platform_device *pdev)
509 struct spi_tegra_data *tspi; 489 struct spi_tegra_data *tspi;
510 struct resource *r; 490 struct resource *r;
511 int ret; 491 int ret;
512#if !defined(CONFIG_TEGRA_SYSTEM_DMA)
513 dma_cap_mask_t mask; 492 dma_cap_mask_t mask;
514#endif
515 493
516 master = spi_alloc_master(&pdev->dev, sizeof *tspi); 494 master = spi_alloc_master(&pdev->dev, sizeof *tspi);
517 if (master == NULL) { 495 if (master == NULL) {
@@ -563,14 +541,6 @@ static int __devinit spi_tegra_probe(struct platform_device *pdev)
563 541
564 INIT_LIST_HEAD(&tspi->queue); 542 INIT_LIST_HEAD(&tspi->queue);
565 543
566#if defined(CONFIG_TEGRA_SYSTEM_DMA)
567 tspi->rx_dma = tegra_dma_allocate_channel(TEGRA_DMA_MODE_ONESHOT);
568 if (!tspi->rx_dma) {
569 dev_err(&pdev->dev, "can not allocate rx dma channel\n");
570 ret = -ENODEV;
571 goto err3;
572 }
573#else
574 dma_cap_zero(mask); 544 dma_cap_zero(mask);
575 dma_cap_set(DMA_SLAVE, mask); 545 dma_cap_set(DMA_SLAVE, mask);
576 tspi->rx_dma = dma_request_channel(mask, NULL, NULL); 546 tspi->rx_dma = dma_request_channel(mask, NULL, NULL);
@@ -580,8 +550,6 @@ static int __devinit spi_tegra_probe(struct platform_device *pdev)
580 goto err3; 550 goto err3;
581 } 551 }
582 552
583#endif
584
585 tspi->rx_bb = dma_alloc_coherent(&pdev->dev, sizeof(u32) * BB_LEN, 553 tspi->rx_bb = dma_alloc_coherent(&pdev->dev, sizeof(u32) * BB_LEN,
586 &tspi->rx_bb_phys, GFP_KERNEL); 554 &tspi->rx_bb_phys, GFP_KERNEL);
587 if (!tspi->rx_bb) { 555 if (!tspi->rx_bb) {
@@ -590,17 +558,6 @@ static int __devinit spi_tegra_probe(struct platform_device *pdev)
590 goto err4; 558 goto err4;
591 } 559 }
592 560
593#if defined(CONFIG_TEGRA_SYSTEM_DMA)
594 tspi->rx_dma_req.complete = tegra_spi_rx_dma_complete;
595 tspi->rx_dma_req.to_memory = 1;
596 tspi->rx_dma_req.dest_addr = tspi->rx_bb_phys;
597 tspi->rx_dma_req.dest_bus_width = 32;
598 tspi->rx_dma_req.source_addr = tspi->phys + SLINK_RX_FIFO;
599 tspi->rx_dma_req.source_bus_width = 32;
600 tspi->rx_dma_req.source_wrap = 4;
601 tspi->rx_dma_req.req_sel = spi_tegra_req_sels[pdev->id];
602 tspi->rx_dma_req.dev = tspi;
603#else
604 /* Dmaengine Dma slave config */ 561 /* Dmaengine Dma slave config */
605 tspi->sconfig.src_addr = tspi->phys + SLINK_RX_FIFO; 562 tspi->sconfig.src_addr = tspi->phys + SLINK_RX_FIFO;
606 tspi->sconfig.dst_addr = tspi->phys + SLINK_RX_FIFO; 563 tspi->sconfig.dst_addr = tspi->phys + SLINK_RX_FIFO;
@@ -616,7 +573,6 @@ static int __devinit spi_tegra_probe(struct platform_device *pdev)
616 ret); 573 ret);
617 goto err4; 574 goto err4;
618 } 575 }
619#endif
620 576
621 master->dev.of_node = pdev->dev.of_node; 577 master->dev.of_node = pdev->dev.of_node;
622 ret = spi_register_master(master); 578 ret = spi_register_master(master);
@@ -630,11 +586,7 @@ err5:
630 dma_free_coherent(&pdev->dev, sizeof(u32) * BB_LEN, 586 dma_free_coherent(&pdev->dev, sizeof(u32) * BB_LEN,
631 tspi->rx_bb, tspi->rx_bb_phys); 587 tspi->rx_bb, tspi->rx_bb_phys);
632err4: 588err4:
633#if defined(CONFIG_TEGRA_SYSTEM_DMA)
634 tegra_dma_free_channel(tspi->rx_dma);
635#else
636 dma_release_channel(tspi->rx_dma); 589 dma_release_channel(tspi->rx_dma);
637#endif
638err3: 590err3:
639 clk_put(tspi->clk); 591 clk_put(tspi->clk);
640err2: 592err2:
@@ -656,12 +608,7 @@ static int __devexit spi_tegra_remove(struct platform_device *pdev)
656 tspi = spi_master_get_devdata(master); 608 tspi = spi_master_get_devdata(master);
657 609
658 spi_unregister_master(master); 610 spi_unregister_master(master);
659#if defined(CONFIG_TEGRA_SYSTEM_DMA)
660 tegra_dma_free_channel(tspi->rx_dma);
661#else
662 dma_release_channel(tspi->rx_dma); 611 dma_release_channel(tspi->rx_dma);
663#endif
664
665 dma_free_coherent(&pdev->dev, sizeof(u32) * BB_LEN, 612 dma_free_coherent(&pdev->dev, sizeof(u32) * BB_LEN,
666 tspi->rx_bb, tspi->rx_bb_phys); 613 tspi->rx_bb, tspi->rx_bb_phys);
667 614
diff --git a/drivers/staging/tidspbridge/core/dsp-clock.c b/drivers/staging/tidspbridge/core/dsp-clock.c
index 7eac01e5fe0b..b647207928b1 100644
--- a/drivers/staging/tidspbridge/core/dsp-clock.c
+++ b/drivers/staging/tidspbridge/core/dsp-clock.c
@@ -23,7 +23,7 @@
23/* ----------------------------------- Host OS */ 23/* ----------------------------------- Host OS */
24#include <dspbridge/host_os.h> 24#include <dspbridge/host_os.h>
25#include <plat/dmtimer.h> 25#include <plat/dmtimer.h>
26#include <plat/mcbsp.h> 26#include <linux/platform_data/asoc-ti-mcbsp.h>
27 27
28/* ----------------------------------- DSP/BIOS Bridge */ 28/* ----------------------------------- DSP/BIOS Bridge */
29#include <dspbridge/dbdefs.h> 29#include <dspbridge/dbdefs.h>
diff --git a/drivers/staging/tidspbridge/core/tiomap3430.c b/drivers/staging/tidspbridge/core/tiomap3430.c
index 012c5a0cc6c8..066a3ceec65e 100644
--- a/drivers/staging/tidspbridge/core/tiomap3430.c
+++ b/drivers/staging/tidspbridge/core/tiomap3430.c
@@ -16,7 +16,7 @@
16 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. 16 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
17 */ 17 */
18 18
19#include <plat/dsp.h> 19#include <linux/platform_data/dsp-omap.h>
20 20
21#include <linux/types.h> 21#include <linux/types.h>
22/* ----------------------------------- Host OS */ 22/* ----------------------------------- Host OS */
diff --git a/drivers/staging/tidspbridge/core/tiomap3430_pwr.c b/drivers/staging/tidspbridge/core/tiomap3430_pwr.c
index 58a1d6dcf098..dafa6d9b2948 100644
--- a/drivers/staging/tidspbridge/core/tiomap3430_pwr.c
+++ b/drivers/staging/tidspbridge/core/tiomap3430_pwr.c
@@ -19,7 +19,7 @@
19/* ----------------------------------- Host OS */ 19/* ----------------------------------- Host OS */
20#include <dspbridge/host_os.h> 20#include <dspbridge/host_os.h>
21 21
22#include <plat/dsp.h> 22#include <linux/platform_data/dsp-omap.h>
23 23
24/* ----------------------------------- DSP/BIOS Bridge */ 24/* ----------------------------------- DSP/BIOS Bridge */
25#include <dspbridge/dbdefs.h> 25#include <dspbridge/dbdefs.h>
diff --git a/drivers/staging/tidspbridge/core/tiomap_io.c b/drivers/staging/tidspbridge/core/tiomap_io.c
index 7fda10c36862..f53ed98d18c1 100644
--- a/drivers/staging/tidspbridge/core/tiomap_io.c
+++ b/drivers/staging/tidspbridge/core/tiomap_io.c
@@ -16,7 +16,7 @@
16 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. 16 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
17 */ 17 */
18 18
19#include <plat/dsp.h> 19#include <linux/platform_data/dsp-omap.h>
20 20
21/* ----------------------------------- DSP/BIOS Bridge */ 21/* ----------------------------------- DSP/BIOS Bridge */
22#include <dspbridge/dbdefs.h> 22#include <dspbridge/dbdefs.h>
diff --git a/drivers/staging/tidspbridge/core/wdt.c b/drivers/staging/tidspbridge/core/wdt.c
index e5adad08f1c4..1dce36fb828f 100644
--- a/drivers/staging/tidspbridge/core/wdt.c
+++ b/drivers/staging/tidspbridge/core/wdt.c
@@ -26,7 +26,7 @@
26 26
27 27
28#define OMAP34XX_WDT3_BASE (0x49000000 + 0x30000) 28#define OMAP34XX_WDT3_BASE (0x49000000 + 0x30000)
29#define INT_34XX_WDT3_IRQ 36 29#define INT_34XX_WDT3_IRQ (36 + NR_IRQS)
30 30
31static struct dsp_wdt_setting dsp_wdt; 31static struct dsp_wdt_setting dsp_wdt;
32 32
diff --git a/drivers/staging/tidspbridge/rmgr/drv_interface.c b/drivers/staging/tidspbridge/rmgr/drv_interface.c
index 6acea2b56aa4..bddea1d3b2c3 100644
--- a/drivers/staging/tidspbridge/rmgr/drv_interface.c
+++ b/drivers/staging/tidspbridge/rmgr/drv_interface.c
@@ -16,7 +16,7 @@
16 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. 16 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
17 */ 17 */
18 18
19#include <plat/dsp.h> 19#include <linux/platform_data/dsp-omap.h>
20 20
21#include <linux/types.h> 21#include <linux/types.h>
22#include <linux/platform_device.h> 22#include <linux/platform_device.h>
diff --git a/drivers/tty/serial/serial_ks8695.c b/drivers/tty/serial/serial_ks8695.c
index 7c13639c597e..9bd004f9da89 100644
--- a/drivers/tty/serial/serial_ks8695.c
+++ b/drivers/tty/serial/serial_ks8695.c
@@ -548,8 +548,8 @@ static struct uart_ops ks8695uart_pops = {
548 548
549static struct uart_port ks8695uart_ports[SERIAL_KS8695_NR] = { 549static struct uart_port ks8695uart_ports[SERIAL_KS8695_NR] = {
550 { 550 {
551 .membase = (void *) KS8695_UART_VA, 551 .membase = KS8695_UART_VA,
552 .mapbase = KS8695_UART_VA, 552 .mapbase = KS8695_UART_PA,
553 .iotype = SERIAL_IO_MEM, 553 .iotype = SERIAL_IO_MEM,
554 .irq = KS8695_IRQ_UART_TX, 554 .irq = KS8695_IRQ_UART_TX,
555 .uartclk = KS8695_CLOCK_RATE * 16, 555 .uartclk = KS8695_CLOCK_RATE * 16,
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index 2564b546ba8a..4c90b510d016 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -13,7 +13,6 @@ config USB_ARCH_HAS_OHCI
13 default y if PXA3xx 13 default y if PXA3xx
14 default y if ARCH_EP93XX 14 default y if ARCH_EP93XX
15 default y if ARCH_AT91 15 default y if ARCH_AT91
16 default y if ARCH_PNX4008
17 default y if MFD_TC6393XB 16 default y if MFD_TC6393XB
18 default y if ARCH_W90X900 17 default y if ARCH_W90X900
19 default y if ARCH_DAVINCI_DA8XX 18 default y if ARCH_DAVINCI_DA8XX
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index b1deb0fd4197..3f1431d37e1c 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -292,7 +292,7 @@ config USB_OHCI_HCD
292 depends on USB && USB_ARCH_HAS_OHCI 292 depends on USB && USB_ARCH_HAS_OHCI
293 select ISP1301_OMAP if MACH_OMAP_H2 || MACH_OMAP_H3 293 select ISP1301_OMAP if MACH_OMAP_H2 || MACH_OMAP_H3
294 select USB_OTG_UTILS if ARCH_OMAP 294 select USB_OTG_UTILS if ARCH_OMAP
295 depends on USB_ISP1301 || !(ARCH_LPC32XX || ARCH_PNX4008) 295 depends on USB_ISP1301 || !ARCH_LPC32XX
296 ---help--- 296 ---help---
297 The Open Host Controller Interface (OHCI) is a standard for accessing 297 The Open Host Controller Interface (OHCI) is a standard for accessing
298 USB 1.1 host controller hardware. It does more in hardware than Intel's 298 USB 1.1 host controller hardware. It does more in hardware than Intel's
diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index 2b1e8d84c873..6780010e9c3c 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -1049,7 +1049,7 @@ MODULE_LICENSE ("GPL");
1049#define PLATFORM_DRIVER ohci_hcd_at91_driver 1049#define PLATFORM_DRIVER ohci_hcd_at91_driver
1050#endif 1050#endif
1051 1051
1052#if defined(CONFIG_ARCH_PNX4008) || defined(CONFIG_ARCH_LPC32XX) 1052#ifdef CONFIG_ARCH_LPC32XX
1053#include "ohci-nxp.c" 1053#include "ohci-nxp.c"
1054#define PLATFORM_DRIVER usb_hcd_nxp_driver 1054#define PLATFORM_DRIVER usb_hcd_nxp_driver
1055#endif 1055#endif
diff --git a/drivers/usb/host/ohci-nxp.c b/drivers/usb/host/ohci-nxp.c
index c60066a63606..e068f034cb9b 100644
--- a/drivers/usb/host/ohci-nxp.c
+++ b/drivers/usb/host/ohci-nxp.c
@@ -2,7 +2,6 @@
2 * driver for NXP USB Host devices 2 * driver for NXP USB Host devices
3 * 3 *
4 * Currently supported OHCI host devices: 4 * Currently supported OHCI host devices:
5 * - Philips PNX4008
6 * - NXP LPC32xx 5 * - NXP LPC32xx
7 * 6 *
8 * Authors: Dmitry Chigirev <source@mvista.com> 7 * Authors: Dmitry Chigirev <source@mvista.com>
@@ -66,38 +65,6 @@ static struct clk *usb_pll_clk;
66static struct clk *usb_dev_clk; 65static struct clk *usb_dev_clk;
67static struct clk *usb_otg_clk; 66static struct clk *usb_otg_clk;
68 67
69static void isp1301_configure_pnx4008(void)
70{
71 /* PNX4008 only supports DAT_SE0 USB mode */
72 /* PNX4008 R2A requires setting the MAX603 to output 3.6V */
73 /* Power up externel charge-pump */
74
75 i2c_smbus_write_byte_data(isp1301_i2c_client,
76 ISP1301_I2C_MODE_CONTROL_1, MC1_DAT_SE0 | MC1_SPEED_REG);
77 i2c_smbus_write_byte_data(isp1301_i2c_client,
78 ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
79 ~(MC1_DAT_SE0 | MC1_SPEED_REG));
80 i2c_smbus_write_byte_data(isp1301_i2c_client,
81 ISP1301_I2C_MODE_CONTROL_2,
82 MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL);
83 i2c_smbus_write_byte_data(isp1301_i2c_client,
84 ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR,
85 ~(MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL));
86 i2c_smbus_write_byte_data(isp1301_i2c_client,
87 ISP1301_I2C_OTG_CONTROL_1, OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN);
88 i2c_smbus_write_byte_data(isp1301_i2c_client,
89 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
90 ~(OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN));
91 i2c_smbus_write_byte_data(isp1301_i2c_client,
92 ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR, 0xFF);
93 i2c_smbus_write_byte_data(isp1301_i2c_client,
94 ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR,
95 0xFF);
96 i2c_smbus_write_byte_data(isp1301_i2c_client,
97 ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR,
98 0xFF);
99}
100
101static void isp1301_configure_lpc32xx(void) 68static void isp1301_configure_lpc32xx(void)
102{ 69{
103 /* LPC32XX only supports DAT_SE0 USB mode */ 70 /* LPC32XX only supports DAT_SE0 USB mode */
@@ -149,10 +116,7 @@ static void isp1301_configure_lpc32xx(void)
149 116
150static void isp1301_configure(void) 117static void isp1301_configure(void)
151{ 118{
152 if (machine_is_pnx4008()) 119 isp1301_configure_lpc32xx();
153 isp1301_configure_pnx4008();
154 else
155 isp1301_configure_lpc32xx();
156} 120}
157 121
158static inline void isp1301_vbus_on(void) 122static inline void isp1301_vbus_on(void)
@@ -241,47 +205,6 @@ static const struct hc_driver ohci_nxp_hc_driver = {
241 .start_port_reset = ohci_start_port_reset, 205 .start_port_reset = ohci_start_port_reset,
242}; 206};
243 207
244static void nxp_set_usb_bits(void)
245{
246 if (machine_is_pnx4008()) {
247 start_int_set_falling_edge(SE_USB_OTG_ATX_INT_N);
248 start_int_ack(SE_USB_OTG_ATX_INT_N);
249 start_int_umask(SE_USB_OTG_ATX_INT_N);
250
251 start_int_set_rising_edge(SE_USB_OTG_TIMER_INT);
252 start_int_ack(SE_USB_OTG_TIMER_INT);
253 start_int_umask(SE_USB_OTG_TIMER_INT);
254
255 start_int_set_rising_edge(SE_USB_I2C_INT);
256 start_int_ack(SE_USB_I2C_INT);
257 start_int_umask(SE_USB_I2C_INT);
258
259 start_int_set_rising_edge(SE_USB_INT);
260 start_int_ack(SE_USB_INT);
261 start_int_umask(SE_USB_INT);
262
263 start_int_set_rising_edge(SE_USB_NEED_CLK_INT);
264 start_int_ack(SE_USB_NEED_CLK_INT);
265 start_int_umask(SE_USB_NEED_CLK_INT);
266
267 start_int_set_rising_edge(SE_USB_AHB_NEED_CLK_INT);
268 start_int_ack(SE_USB_AHB_NEED_CLK_INT);
269 start_int_umask(SE_USB_AHB_NEED_CLK_INT);
270 }
271}
272
273static void nxp_unset_usb_bits(void)
274{
275 if (machine_is_pnx4008()) {
276 start_int_mask(SE_USB_OTG_ATX_INT_N);
277 start_int_mask(SE_USB_OTG_TIMER_INT);
278 start_int_mask(SE_USB_I2C_INT);
279 start_int_mask(SE_USB_INT);
280 start_int_mask(SE_USB_NEED_CLK_INT);
281 start_int_mask(SE_USB_AHB_NEED_CLK_INT);
282 }
283}
284
285static int __devinit usb_hcd_nxp_probe(struct platform_device *pdev) 208static int __devinit usb_hcd_nxp_probe(struct platform_device *pdev)
286{ 209{
287 struct usb_hcd *hcd = 0; 210 struct usb_hcd *hcd = 0;
@@ -376,9 +299,6 @@ static int __devinit usb_hcd_nxp_probe(struct platform_device *pdev)
376 goto out8; 299 goto out8;
377 } 300 }
378 301
379 /* Set all USB bits in the Start Enable register */
380 nxp_set_usb_bits();
381
382 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 302 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
383 if (!res) { 303 if (!res) {
384 dev_err(&pdev->dev, "Failed to get MEM resource\n"); 304 dev_err(&pdev->dev, "Failed to get MEM resource\n");
@@ -413,7 +333,6 @@ static int __devinit usb_hcd_nxp_probe(struct platform_device *pdev)
413 333
414 nxp_stop_hc(); 334 nxp_stop_hc();
415out8: 335out8:
416 nxp_unset_usb_bits();
417 usb_put_hcd(hcd); 336 usb_put_hcd(hcd);
418out7: 337out7:
419 clk_disable(usb_otg_clk); 338 clk_disable(usb_otg_clk);
@@ -441,7 +360,6 @@ static int usb_hcd_nxp_remove(struct platform_device *pdev)
441 nxp_stop_hc(); 360 nxp_stop_hc();
442 release_mem_region(hcd->rsrc_start, hcd->rsrc_len); 361 release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
443 usb_put_hcd(hcd); 362 usb_put_hcd(hcd);
444 nxp_unset_usb_bits();
445 clk_disable(usb_pll_clk); 363 clk_disable(usb_pll_clk);
446 clk_put(usb_pll_clk); 364 clk_put(usb_pll_clk);
447 clk_disable(usb_dev_clk); 365 clk_disable(usb_dev_clk);
diff --git a/drivers/usb/host/ohci-omap.c b/drivers/usb/host/ohci-omap.c
index f8b2d91851f7..4531d03503c3 100644
--- a/drivers/usb/host/ohci-omap.c
+++ b/drivers/usb/host/ohci-omap.c
@@ -24,7 +24,7 @@
24#include <asm/io.h> 24#include <asm/io.h>
25#include <asm/mach-types.h> 25#include <asm/mach-types.h>
26 26
27#include <plat/mux.h> 27#include <mach/mux.h>
28#include <plat/fpga.h> 28#include <plat/fpga.h>
29 29
30#include <mach/hardware.h> 30#include <mach/hardware.h>
diff --git a/drivers/usb/musb/tusb6010_omap.c b/drivers/usb/musb/tusb6010_omap.c
index 53e25968ed0c..7a62b95dac24 100644
--- a/drivers/usb/musb/tusb6010_omap.c
+++ b/drivers/usb/musb/tusb6010_omap.c
@@ -17,7 +17,6 @@
17#include <linux/dma-mapping.h> 17#include <linux/dma-mapping.h>
18#include <linux/slab.h> 18#include <linux/slab.h>
19#include <plat/dma.h> 19#include <plat/dma.h>
20#include <plat/mux.h>
21 20
22#include "musb_core.h" 21#include "musb_core.h"
23#include "tusb6010.h" 22#include "tusb6010.h"
diff --git a/drivers/usb/otg/isp1301_omap.c b/drivers/usb/otg/isp1301_omap.c
index 7a88667742b6..81f1f9a0be8f 100644
--- a/drivers/usb/otg/isp1301_omap.c
+++ b/drivers/usb/otg/isp1301_omap.c
@@ -36,7 +36,7 @@
36#include <asm/irq.h> 36#include <asm/irq.h>
37#include <asm/mach-types.h> 37#include <asm/mach-types.h>
38 38
39#include <plat/mux.h> 39#include <mach/mux.h>
40 40
41#include <mach/usb.h> 41#include <mach/usb.h>
42 42
diff --git a/drivers/video/backlight/omap1_bl.c b/drivers/video/backlight/omap1_bl.c
index bfdc5fbeaa11..9a046a4c98f5 100644
--- a/drivers/video/backlight/omap1_bl.c
+++ b/drivers/video/backlight/omap1_bl.c
@@ -27,10 +27,10 @@
27#include <linux/fb.h> 27#include <linux/fb.h>
28#include <linux/backlight.h> 28#include <linux/backlight.h>
29#include <linux/slab.h> 29#include <linux/slab.h>
30#include <linux/platform_data/omap1_bl.h>
30 31
31#include <mach/hardware.h> 32#include <mach/hardware.h>
32#include <plat/board.h> 33#include <mach/mux.h>
33#include <plat/mux.h>
34 34
35#define OMAPBL_MAX_INTENSITY 0xff 35#define OMAPBL_MAX_INTENSITY 0xff
36 36
diff --git a/drivers/video/da8xx-fb.c b/drivers/video/da8xx-fb.c
index 7ae9d53f2bf1..113d43a16f54 100644
--- a/drivers/video/da8xx-fb.c
+++ b/drivers/video/da8xx-fb.c
@@ -131,7 +131,7 @@
131#define UPPER_MARGIN 32 131#define UPPER_MARGIN 32
132#define LOWER_MARGIN 32 132#define LOWER_MARGIN 32
133 133
134static resource_size_t da8xx_fb_reg_base; 134static void __iomem *da8xx_fb_reg_base;
135static struct resource *lcdc_regs; 135static struct resource *lcdc_regs;
136static unsigned int lcd_revision; 136static unsigned int lcd_revision;
137static irq_handler_t lcdc_irq_handler; 137static irq_handler_t lcdc_irq_handler;
@@ -951,7 +951,7 @@ static int __devexit fb_remove(struct platform_device *dev)
951 clk_disable(par->lcdc_clk); 951 clk_disable(par->lcdc_clk);
952 clk_put(par->lcdc_clk); 952 clk_put(par->lcdc_clk);
953 framebuffer_release(info); 953 framebuffer_release(info);
954 iounmap((void __iomem *)da8xx_fb_reg_base); 954 iounmap(da8xx_fb_reg_base);
955 release_mem_region(lcdc_regs->start, resource_size(lcdc_regs)); 955 release_mem_region(lcdc_regs->start, resource_size(lcdc_regs));
956 956
957 } 957 }
@@ -1171,7 +1171,7 @@ static int __devinit fb_probe(struct platform_device *device)
1171 if (!lcdc_regs) 1171 if (!lcdc_regs)
1172 return -EBUSY; 1172 return -EBUSY;
1173 1173
1174 da8xx_fb_reg_base = (resource_size_t)ioremap(lcdc_regs->start, len); 1174 da8xx_fb_reg_base = ioremap(lcdc_regs->start, len);
1175 if (!da8xx_fb_reg_base) { 1175 if (!da8xx_fb_reg_base) {
1176 ret = -EBUSY; 1176 ret = -EBUSY;
1177 goto err_request_mem; 1177 goto err_request_mem;
@@ -1392,7 +1392,7 @@ err_clk_put:
1392 clk_put(fb_clk); 1392 clk_put(fb_clk);
1393 1393
1394err_ioremap: 1394err_ioremap:
1395 iounmap((void __iomem *)da8xx_fb_reg_base); 1395 iounmap(da8xx_fb_reg_base);
1396 1396
1397err_request_mem: 1397err_request_mem:
1398 release_mem_region(lcdc_regs->start, len); 1398 release_mem_region(lcdc_regs->start, len);
diff --git a/drivers/video/omap/lcd_ams_delta.c b/drivers/video/omap/lcd_ams_delta.c
index d3a311327227..ed4cad87fbcd 100644
--- a/drivers/video/omap/lcd_ams_delta.c
+++ b/drivers/video/omap/lcd_ams_delta.c
@@ -27,8 +27,7 @@
27#include <linux/lcd.h> 27#include <linux/lcd.h>
28#include <linux/gpio.h> 28#include <linux/gpio.h>
29 29
30#include <plat/board-ams-delta.h> 30#include <mach/board-ams-delta.h>
31#include <mach/hardware.h>
32 31
33#include "omapfb.h" 32#include "omapfb.h"
34 33
diff --git a/drivers/video/omap/lcd_mipid.c b/drivers/video/omap/lcd_mipid.c
index e3880c4a0bb1..b739600c51ac 100644
--- a/drivers/video/omap/lcd_mipid.c
+++ b/drivers/video/omap/lcd_mipid.c
@@ -25,7 +25,7 @@
25#include <linux/spi/spi.h> 25#include <linux/spi/spi.h>
26#include <linux/module.h> 26#include <linux/module.h>
27 27
28#include <plat/lcd_mipid.h> 28#include <linux/platform_data/lcd-mipid.h>
29 29
30#include "omapfb.h" 30#include "omapfb.h"
31 31
diff --git a/drivers/video/omap/lcd_osk.c b/drivers/video/omap/lcd_osk.c
index 5914220dfa9c..3aa62da89195 100644
--- a/drivers/video/omap/lcd_osk.c
+++ b/drivers/video/omap/lcd_osk.c
@@ -24,7 +24,7 @@
24#include <linux/platform_device.h> 24#include <linux/platform_device.h>
25 25
26#include <asm/gpio.h> 26#include <asm/gpio.h>
27#include <plat/mux.h> 27#include <mach/mux.h>
28#include "omapfb.h" 28#include "omapfb.h"
29 29
30static int osk_panel_init(struct lcd_panel *panel, struct omapfb_device *fbdev) 30static int osk_panel_init(struct lcd_panel *panel, struct omapfb_device *fbdev)
diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index 5b289c5f695b..ee9e29639dcc 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -37,6 +37,7 @@
37#include <linux/platform_device.h> 37#include <linux/platform_device.h>
38#include <linux/pm_runtime.h> 38#include <linux/pm_runtime.h>
39 39
40#include <plat/cpu.h>
40#include <plat/clock.h> 41#include <plat/clock.h>
41 42
42#include <video/omapdss.h> 43#include <video/omapdss.h>
diff --git a/drivers/video/omap2/omapfb/omapfb-main.c b/drivers/video/omap2/omapfb/omapfb-main.c
index fc671d3d8004..3c39aa8de928 100644
--- a/drivers/video/omap2/omapfb/omapfb-main.c
+++ b/drivers/video/omap2/omapfb/omapfb-main.c
@@ -31,6 +31,7 @@
31#include <linux/omapfb.h> 31#include <linux/omapfb.h>
32 32
33#include <video/omapdss.h> 33#include <video/omapdss.h>
34#include <plat/cpu.h>
34#include <plat/vram.h> 35#include <plat/vram.h>
35#include <plat/vrfb.h> 36#include <plat/vrfb.h>
36 37
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 53d75719078e..ad1bb9382a96 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -237,12 +237,12 @@ config OMAP_WATCHDOG
237 here to enable the OMAP1610/OMAP1710/OMAP2420/OMAP3430/OMAP4430 watchdog timer. 237 here to enable the OMAP1610/OMAP1710/OMAP2420/OMAP3430/OMAP4430 watchdog timer.
238 238
239config PNX4008_WATCHDOG 239config PNX4008_WATCHDOG
240 tristate "PNX4008 and LPC32XX Watchdog" 240 tristate "LPC32XX Watchdog"
241 depends on ARCH_PNX4008 || ARCH_LPC32XX 241 depends on ARCH_LPC32XX
242 select WATCHDOG_CORE 242 select WATCHDOG_CORE
243 help 243 help
244 Say Y here if to include support for the watchdog timer 244 Say Y here if to include support for the watchdog timer
245 in the PNX4008 or LPC32XX processor. 245 in the LPC32XX processor.
246 This driver can be built as a module by choosing M. The module 246 This driver can be built as a module by choosing M. The module
247 will be called pnx4008_wdt. 247 will be called pnx4008_wdt.
248 248
diff --git a/drivers/watchdog/ks8695_wdt.c b/drivers/watchdog/ks8695_wdt.c
index 59e75d9a6b7f..c1a4d3bf581d 100644
--- a/drivers/watchdog/ks8695_wdt.c
+++ b/drivers/watchdog/ks8695_wdt.c
@@ -24,7 +24,19 @@
24#include <linux/io.h> 24#include <linux/io.h>
25#include <linux/uaccess.h> 25#include <linux/uaccess.h>
26#include <mach/hardware.h> 26#include <mach/hardware.h>
27#include <mach/regs-timer.h> 27
28#define KS8695_TMR_OFFSET (0xF0000 + 0xE400)
29#define KS8695_TMR_VA (KS8695_IO_VA + KS8695_TMR_OFFSET)
30
31/*
32 * Timer registers
33 */
34#define KS8695_TMCON (0x00) /* Timer Control Register */
35#define KS8695_T0TC (0x08) /* Timer 0 Timeout Count Register */
36#define TMCON_T0EN (1 << 0) /* Timer 0 Enable */
37
38/* Timer0 Timeout Counter Register */
39#define T0TC_WATCHDOG (0xff) /* Enable watchdog mode */
28 40
29#define WDT_DEFAULT_TIME 5 /* seconds */ 41#define WDT_DEFAULT_TIME 5 /* seconds */
30#define WDT_MAX_TIME 171 /* seconds */ 42#define WDT_MAX_TIME 171 /* seconds */
diff --git a/drivers/watchdog/omap_wdt.c b/drivers/watchdog/omap_wdt.c
index fceec4f4eb7e..f5db18dbc0f9 100644
--- a/drivers/watchdog/omap_wdt.c
+++ b/drivers/watchdog/omap_wdt.c
@@ -46,6 +46,7 @@
46#include <linux/slab.h> 46#include <linux/slab.h>
47#include <linux/pm_runtime.h> 47#include <linux/pm_runtime.h>
48#include <mach/hardware.h> 48#include <mach/hardware.h>
49#include <plat/cpu.h>
49#include <plat/prcm.h> 50#include <plat/prcm.h>
50 51
51#include "omap_wdt.h" 52#include "omap_wdt.h"
@@ -218,12 +219,16 @@ static long omap_wdt_ioctl(struct file *file, unsigned int cmd,
218 case WDIOC_GETSTATUS: 219 case WDIOC_GETSTATUS:
219 return put_user(0, (int __user *)arg); 220 return put_user(0, (int __user *)arg);
220 case WDIOC_GETBOOTSTATUS: 221 case WDIOC_GETBOOTSTATUS:
222#ifdef CONFIG_ARCH_OMAP1
221 if (cpu_is_omap16xx()) 223 if (cpu_is_omap16xx())
222 return put_user(__raw_readw(ARM_SYSST), 224 return put_user(__raw_readw(ARM_SYSST),
223 (int __user *)arg); 225 (int __user *)arg);
226#endif
227#ifdef CONFIG_ARCH_OMAP2PLUS
224 if (cpu_is_omap24xx()) 228 if (cpu_is_omap24xx())
225 return put_user(omap_prcm_get_reset_sources(), 229 return put_user(omap_prcm_get_reset_sources(),
226 (int __user *)arg); 230 (int __user *)arg);
231#endif
227 return put_user(0, (int __user *)arg); 232 return put_user(0, (int __user *)arg);
228 case WDIOC_KEEPALIVE: 233 case WDIOC_KEEPALIVE:
229 spin_lock(&wdt_lock); 234 spin_lock(&wdt_lock);
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-16 04:59:22 -0400