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-rw-r--r--drivers/idle/intel_idle.c179
1 files changed, 125 insertions, 54 deletions
diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c
index 1bc0c170f12a..b0e58522780d 100644
--- a/drivers/idle/intel_idle.c
+++ b/drivers/idle/intel_idle.c
@@ -97,6 +97,8 @@ static const struct idle_cpu *icpu;
97static struct cpuidle_device __percpu *intel_idle_cpuidle_devices; 97static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
98static int intel_idle(struct cpuidle_device *dev, 98static int intel_idle(struct cpuidle_device *dev,
99 struct cpuidle_driver *drv, int index); 99 struct cpuidle_driver *drv, int index);
100static void intel_idle_freeze(struct cpuidle_device *dev,
101 struct cpuidle_driver *drv, int index);
100static int intel_idle_cpu_init(int cpu); 102static int intel_idle_cpu_init(int cpu);
101 103
102static struct cpuidle_state *cpuidle_state_table; 104static struct cpuidle_state *cpuidle_state_table;
@@ -131,28 +133,32 @@ static struct cpuidle_state nehalem_cstates[] = {
131 .flags = MWAIT2flg(0x00), 133 .flags = MWAIT2flg(0x00),
132 .exit_latency = 3, 134 .exit_latency = 3,
133 .target_residency = 6, 135 .target_residency = 6,
134 .enter = &intel_idle }, 136 .enter = &intel_idle,
137 .enter_freeze = intel_idle_freeze, },
135 { 138 {
136 .name = "C1E-NHM", 139 .name = "C1E-NHM",
137 .desc = "MWAIT 0x01", 140 .desc = "MWAIT 0x01",
138 .flags = MWAIT2flg(0x01), 141 .flags = MWAIT2flg(0x01),
139 .exit_latency = 10, 142 .exit_latency = 10,
140 .target_residency = 20, 143 .target_residency = 20,
141 .enter = &intel_idle }, 144 .enter = &intel_idle,
145 .enter_freeze = intel_idle_freeze, },
142 { 146 {
143 .name = "C3-NHM", 147 .name = "C3-NHM",
144 .desc = "MWAIT 0x10", 148 .desc = "MWAIT 0x10",
145 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, 149 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
146 .exit_latency = 20, 150 .exit_latency = 20,
147 .target_residency = 80, 151 .target_residency = 80,
148 .enter = &intel_idle }, 152 .enter = &intel_idle,
153 .enter_freeze = intel_idle_freeze, },
149 { 154 {
150 .name = "C6-NHM", 155 .name = "C6-NHM",
151 .desc = "MWAIT 0x20", 156 .desc = "MWAIT 0x20",
152 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, 157 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
153 .exit_latency = 200, 158 .exit_latency = 200,
154 .target_residency = 800, 159 .target_residency = 800,
155 .enter = &intel_idle }, 160 .enter = &intel_idle,
161 .enter_freeze = intel_idle_freeze, },
156 { 162 {
157 .enter = NULL } 163 .enter = NULL }
158}; 164};
@@ -164,35 +170,40 @@ static struct cpuidle_state snb_cstates[] = {
164 .flags = MWAIT2flg(0x00), 170 .flags = MWAIT2flg(0x00),
165 .exit_latency = 2, 171 .exit_latency = 2,
166 .target_residency = 2, 172 .target_residency = 2,
167 .enter = &intel_idle }, 173 .enter = &intel_idle,
174 .enter_freeze = intel_idle_freeze, },
168 { 175 {
169 .name = "C1E-SNB", 176 .name = "C1E-SNB",
170 .desc = "MWAIT 0x01", 177 .desc = "MWAIT 0x01",
171 .flags = MWAIT2flg(0x01), 178 .flags = MWAIT2flg(0x01),
172 .exit_latency = 10, 179 .exit_latency = 10,
173 .target_residency = 20, 180 .target_residency = 20,
174 .enter = &intel_idle }, 181 .enter = &intel_idle,
182 .enter_freeze = intel_idle_freeze, },
175 { 183 {
176 .name = "C3-SNB", 184 .name = "C3-SNB",
177 .desc = "MWAIT 0x10", 185 .desc = "MWAIT 0x10",
178 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, 186 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
179 .exit_latency = 80, 187 .exit_latency = 80,
180 .target_residency = 211, 188 .target_residency = 211,
181 .enter = &intel_idle }, 189 .enter = &intel_idle,
190 .enter_freeze = intel_idle_freeze, },
182 { 191 {
183 .name = "C6-SNB", 192 .name = "C6-SNB",
184 .desc = "MWAIT 0x20", 193 .desc = "MWAIT 0x20",
185 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, 194 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
186 .exit_latency = 104, 195 .exit_latency = 104,
187 .target_residency = 345, 196 .target_residency = 345,
188 .enter = &intel_idle }, 197 .enter = &intel_idle,
198 .enter_freeze = intel_idle_freeze, },
189 { 199 {
190 .name = "C7-SNB", 200 .name = "C7-SNB",
191 .desc = "MWAIT 0x30", 201 .desc = "MWAIT 0x30",
192 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED, 202 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
193 .exit_latency = 109, 203 .exit_latency = 109,
194 .target_residency = 345, 204 .target_residency = 345,
195 .enter = &intel_idle }, 205 .enter = &intel_idle,
206 .enter_freeze = intel_idle_freeze, },
196 { 207 {
197 .enter = NULL } 208 .enter = NULL }
198}; 209};
@@ -204,42 +215,48 @@ static struct cpuidle_state byt_cstates[] = {
204 .flags = MWAIT2flg(0x00), 215 .flags = MWAIT2flg(0x00),
205 .exit_latency = 1, 216 .exit_latency = 1,
206 .target_residency = 1, 217 .target_residency = 1,
207 .enter = &intel_idle }, 218 .enter = &intel_idle,
219 .enter_freeze = intel_idle_freeze, },
208 { 220 {
209 .name = "C1E-BYT", 221 .name = "C1E-BYT",
210 .desc = "MWAIT 0x01", 222 .desc = "MWAIT 0x01",
211 .flags = MWAIT2flg(0x01), 223 .flags = MWAIT2flg(0x01),
212 .exit_latency = 15, 224 .exit_latency = 15,
213 .target_residency = 30, 225 .target_residency = 30,
214 .enter = &intel_idle }, 226 .enter = &intel_idle,
227 .enter_freeze = intel_idle_freeze, },
215 { 228 {
216 .name = "C6N-BYT", 229 .name = "C6N-BYT",
217 .desc = "MWAIT 0x58", 230 .desc = "MWAIT 0x58",
218 .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED, 231 .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED,
219 .exit_latency = 40, 232 .exit_latency = 40,
220 .target_residency = 275, 233 .target_residency = 275,
221 .enter = &intel_idle }, 234 .enter = &intel_idle,
235 .enter_freeze = intel_idle_freeze, },
222 { 236 {
223 .name = "C6S-BYT", 237 .name = "C6S-BYT",
224 .desc = "MWAIT 0x52", 238 .desc = "MWAIT 0x52",
225 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED, 239 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
226 .exit_latency = 140, 240 .exit_latency = 140,
227 .target_residency = 560, 241 .target_residency = 560,
228 .enter = &intel_idle }, 242 .enter = &intel_idle,
243 .enter_freeze = intel_idle_freeze, },
229 { 244 {
230 .name = "C7-BYT", 245 .name = "C7-BYT",
231 .desc = "MWAIT 0x60", 246 .desc = "MWAIT 0x60",
232 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, 247 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
233 .exit_latency = 1200, 248 .exit_latency = 1200,
234 .target_residency = 1500, 249 .target_residency = 1500,
235 .enter = &intel_idle }, 250 .enter = &intel_idle,
251 .enter_freeze = intel_idle_freeze, },
236 { 252 {
237 .name = "C7S-BYT", 253 .name = "C7S-BYT",
238 .desc = "MWAIT 0x64", 254 .desc = "MWAIT 0x64",
239 .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED, 255 .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
240 .exit_latency = 10000, 256 .exit_latency = 10000,
241 .target_residency = 20000, 257 .target_residency = 20000,
242 .enter = &intel_idle }, 258 .enter = &intel_idle,
259 .enter_freeze = intel_idle_freeze, },
243 { 260 {
244 .enter = NULL } 261 .enter = NULL }
245}; 262};
@@ -251,35 +268,40 @@ static struct cpuidle_state ivb_cstates[] = {
251 .flags = MWAIT2flg(0x00), 268 .flags = MWAIT2flg(0x00),
252 .exit_latency = 1, 269 .exit_latency = 1,
253 .target_residency = 1, 270 .target_residency = 1,
254 .enter = &intel_idle }, 271 .enter = &intel_idle,
272 .enter_freeze = intel_idle_freeze, },
255 { 273 {
256 .name = "C1E-IVB", 274 .name = "C1E-IVB",
257 .desc = "MWAIT 0x01", 275 .desc = "MWAIT 0x01",
258 .flags = MWAIT2flg(0x01), 276 .flags = MWAIT2flg(0x01),
259 .exit_latency = 10, 277 .exit_latency = 10,
260 .target_residency = 20, 278 .target_residency = 20,
261 .enter = &intel_idle }, 279 .enter = &intel_idle,
280 .enter_freeze = intel_idle_freeze, },
262 { 281 {
263 .name = "C3-IVB", 282 .name = "C3-IVB",
264 .desc = "MWAIT 0x10", 283 .desc = "MWAIT 0x10",
265 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, 284 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
266 .exit_latency = 59, 285 .exit_latency = 59,
267 .target_residency = 156, 286 .target_residency = 156,
268 .enter = &intel_idle }, 287 .enter = &intel_idle,
288 .enter_freeze = intel_idle_freeze, },
269 { 289 {
270 .name = "C6-IVB", 290 .name = "C6-IVB",
271 .desc = "MWAIT 0x20", 291 .desc = "MWAIT 0x20",
272 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, 292 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
273 .exit_latency = 80, 293 .exit_latency = 80,
274 .target_residency = 300, 294 .target_residency = 300,
275 .enter = &intel_idle }, 295 .enter = &intel_idle,
296 .enter_freeze = intel_idle_freeze, },
276 { 297 {
277 .name = "C7-IVB", 298 .name = "C7-IVB",
278 .desc = "MWAIT 0x30", 299 .desc = "MWAIT 0x30",
279 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED, 300 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
280 .exit_latency = 87, 301 .exit_latency = 87,
281 .target_residency = 300, 302 .target_residency = 300,
282 .enter = &intel_idle }, 303 .enter = &intel_idle,
304 .enter_freeze = intel_idle_freeze, },
283 { 305 {
284 .enter = NULL } 306 .enter = NULL }
285}; 307};
@@ -291,28 +313,32 @@ static struct cpuidle_state ivt_cstates[] = {
291 .flags = MWAIT2flg(0x00), 313 .flags = MWAIT2flg(0x00),
292 .exit_latency = 1, 314 .exit_latency = 1,
293 .target_residency = 1, 315 .target_residency = 1,
294 .enter = &intel_idle }, 316 .enter = &intel_idle,
317 .enter_freeze = intel_idle_freeze, },
295 { 318 {
296 .name = "C1E-IVT", 319 .name = "C1E-IVT",
297 .desc = "MWAIT 0x01", 320 .desc = "MWAIT 0x01",
298 .flags = MWAIT2flg(0x01), 321 .flags = MWAIT2flg(0x01),
299 .exit_latency = 10, 322 .exit_latency = 10,
300 .target_residency = 80, 323 .target_residency = 80,
301 .enter = &intel_idle }, 324 .enter = &intel_idle,
325 .enter_freeze = intel_idle_freeze, },
302 { 326 {
303 .name = "C3-IVT", 327 .name = "C3-IVT",
304 .desc = "MWAIT 0x10", 328 .desc = "MWAIT 0x10",
305 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, 329 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
306 .exit_latency = 59, 330 .exit_latency = 59,
307 .target_residency = 156, 331 .target_residency = 156,
308 .enter = &intel_idle }, 332 .enter = &intel_idle,
333 .enter_freeze = intel_idle_freeze, },
309 { 334 {
310 .name = "C6-IVT", 335 .name = "C6-IVT",
311 .desc = "MWAIT 0x20", 336 .desc = "MWAIT 0x20",
312 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, 337 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
313 .exit_latency = 82, 338 .exit_latency = 82,
314 .target_residency = 300, 339 .target_residency = 300,
315 .enter = &intel_idle }, 340 .enter = &intel_idle,
341 .enter_freeze = intel_idle_freeze, },
316 { 342 {
317 .enter = NULL } 343 .enter = NULL }
318}; 344};
@@ -324,28 +350,32 @@ static struct cpuidle_state ivt_cstates_4s[] = {
324 .flags = MWAIT2flg(0x00), 350 .flags = MWAIT2flg(0x00),
325 .exit_latency = 1, 351 .exit_latency = 1,
326 .target_residency = 1, 352 .target_residency = 1,
327 .enter = &intel_idle }, 353 .enter = &intel_idle,
354 .enter_freeze = intel_idle_freeze, },
328 { 355 {
329 .name = "C1E-IVT-4S", 356 .name = "C1E-IVT-4S",
330 .desc = "MWAIT 0x01", 357 .desc = "MWAIT 0x01",
331 .flags = MWAIT2flg(0x01), 358 .flags = MWAIT2flg(0x01),
332 .exit_latency = 10, 359 .exit_latency = 10,
333 .target_residency = 250, 360 .target_residency = 250,
334 .enter = &intel_idle }, 361 .enter = &intel_idle,
362 .enter_freeze = intel_idle_freeze, },
335 { 363 {
336 .name = "C3-IVT-4S", 364 .name = "C3-IVT-4S",
337 .desc = "MWAIT 0x10", 365 .desc = "MWAIT 0x10",
338 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, 366 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
339 .exit_latency = 59, 367 .exit_latency = 59,
340 .target_residency = 300, 368 .target_residency = 300,
341 .enter = &intel_idle }, 369 .enter = &intel_idle,
370 .enter_freeze = intel_idle_freeze, },
342 { 371 {
343 .name = "C6-IVT-4S", 372 .name = "C6-IVT-4S",
344 .desc = "MWAIT 0x20", 373 .desc = "MWAIT 0x20",
345 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, 374 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
346 .exit_latency = 84, 375 .exit_latency = 84,
347 .target_residency = 400, 376 .target_residency = 400,
348 .enter = &intel_idle }, 377 .enter = &intel_idle,
378 .enter_freeze = intel_idle_freeze, },
349 { 379 {
350 .enter = NULL } 380 .enter = NULL }
351}; 381};
@@ -357,28 +387,32 @@ static struct cpuidle_state ivt_cstates_8s[] = {
357 .flags = MWAIT2flg(0x00), 387 .flags = MWAIT2flg(0x00),
358 .exit_latency = 1, 388 .exit_latency = 1,
359 .target_residency = 1, 389 .target_residency = 1,
360 .enter = &intel_idle }, 390 .enter = &intel_idle,
391 .enter_freeze = intel_idle_freeze, },
361 { 392 {
362 .name = "C1E-IVT-8S", 393 .name = "C1E-IVT-8S",
363 .desc = "MWAIT 0x01", 394 .desc = "MWAIT 0x01",
364 .flags = MWAIT2flg(0x01), 395 .flags = MWAIT2flg(0x01),
365 .exit_latency = 10, 396 .exit_latency = 10,
366 .target_residency = 500, 397 .target_residency = 500,
367 .enter = &intel_idle }, 398 .enter = &intel_idle,
399 .enter_freeze = intel_idle_freeze, },
368 { 400 {
369 .name = "C3-IVT-8S", 401 .name = "C3-IVT-8S",
370 .desc = "MWAIT 0x10", 402 .desc = "MWAIT 0x10",
371 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, 403 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
372 .exit_latency = 59, 404 .exit_latency = 59,
373 .target_residency = 600, 405 .target_residency = 600,
374 .enter = &intel_idle }, 406 .enter = &intel_idle,
407 .enter_freeze = intel_idle_freeze, },
375 { 408 {
376 .name = "C6-IVT-8S", 409 .name = "C6-IVT-8S",
377 .desc = "MWAIT 0x20", 410 .desc = "MWAIT 0x20",
378 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, 411 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
379 .exit_latency = 88, 412 .exit_latency = 88,
380 .target_residency = 700, 413 .target_residency = 700,
381 .enter = &intel_idle }, 414 .enter = &intel_idle,
415 .enter_freeze = intel_idle_freeze, },
382 { 416 {
383 .enter = NULL } 417 .enter = NULL }
384}; 418};
@@ -390,56 +424,64 @@ static struct cpuidle_state hsw_cstates[] = {
390 .flags = MWAIT2flg(0x00), 424 .flags = MWAIT2flg(0x00),
391 .exit_latency = 2, 425 .exit_latency = 2,
392 .target_residency = 2, 426 .target_residency = 2,
393 .enter = &intel_idle }, 427 .enter = &intel_idle,
428 .enter_freeze = intel_idle_freeze, },
394 { 429 {
395 .name = "C1E-HSW", 430 .name = "C1E-HSW",
396 .desc = "MWAIT 0x01", 431 .desc = "MWAIT 0x01",
397 .flags = MWAIT2flg(0x01), 432 .flags = MWAIT2flg(0x01),
398 .exit_latency = 10, 433 .exit_latency = 10,
399 .target_residency = 20, 434 .target_residency = 20,
400 .enter = &intel_idle }, 435 .enter = &intel_idle,
436 .enter_freeze = intel_idle_freeze, },
401 { 437 {
402 .name = "C3-HSW", 438 .name = "C3-HSW",
403 .desc = "MWAIT 0x10", 439 .desc = "MWAIT 0x10",
404 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, 440 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
405 .exit_latency = 33, 441 .exit_latency = 33,
406 .target_residency = 100, 442 .target_residency = 100,
407 .enter = &intel_idle }, 443 .enter = &intel_idle,
444 .enter_freeze = intel_idle_freeze, },
408 { 445 {
409 .name = "C6-HSW", 446 .name = "C6-HSW",
410 .desc = "MWAIT 0x20", 447 .desc = "MWAIT 0x20",
411 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, 448 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
412 .exit_latency = 133, 449 .exit_latency = 133,
413 .target_residency = 400, 450 .target_residency = 400,
414 .enter = &intel_idle }, 451 .enter = &intel_idle,
452 .enter_freeze = intel_idle_freeze, },
415 { 453 {
416 .name = "C7s-HSW", 454 .name = "C7s-HSW",
417 .desc = "MWAIT 0x32", 455 .desc = "MWAIT 0x32",
418 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED, 456 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
419 .exit_latency = 166, 457 .exit_latency = 166,
420 .target_residency = 500, 458 .target_residency = 500,
421 .enter = &intel_idle }, 459 .enter = &intel_idle,
460 .enter_freeze = intel_idle_freeze, },
422 { 461 {
423 .name = "C8-HSW", 462 .name = "C8-HSW",
424 .desc = "MWAIT 0x40", 463 .desc = "MWAIT 0x40",
425 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED, 464 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
426 .exit_latency = 300, 465 .exit_latency = 300,
427 .target_residency = 900, 466 .target_residency = 900,
428 .enter = &intel_idle }, 467 .enter = &intel_idle,
468 .enter_freeze = intel_idle_freeze, },
429 { 469 {
430 .name = "C9-HSW", 470 .name = "C9-HSW",
431 .desc = "MWAIT 0x50", 471 .desc = "MWAIT 0x50",
432 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED, 472 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
433 .exit_latency = 600, 473 .exit_latency = 600,
434 .target_residency = 1800, 474 .target_residency = 1800,
435 .enter = &intel_idle }, 475 .enter = &intel_idle,
476 .enter_freeze = intel_idle_freeze, },
436 { 477 {
437 .name = "C10-HSW", 478 .name = "C10-HSW",
438 .desc = "MWAIT 0x60", 479 .desc = "MWAIT 0x60",
439 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, 480 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
440 .exit_latency = 2600, 481 .exit_latency = 2600,
441 .target_residency = 7700, 482 .target_residency = 7700,
442 .enter = &intel_idle }, 483 .enter = &intel_idle,
484 .enter_freeze = intel_idle_freeze, },
443 { 485 {
444 .enter = NULL } 486 .enter = NULL }
445}; 487};
@@ -450,56 +492,64 @@ static struct cpuidle_state bdw_cstates[] = {
450 .flags = MWAIT2flg(0x00), 492 .flags = MWAIT2flg(0x00),
451 .exit_latency = 2, 493 .exit_latency = 2,
452 .target_residency = 2, 494 .target_residency = 2,
453 .enter = &intel_idle }, 495 .enter = &intel_idle,
496 .enter_freeze = intel_idle_freeze, },
454 { 497 {
455 .name = "C1E-BDW", 498 .name = "C1E-BDW",
456 .desc = "MWAIT 0x01", 499 .desc = "MWAIT 0x01",
457 .flags = MWAIT2flg(0x01), 500 .flags = MWAIT2flg(0x01),
458 .exit_latency = 10, 501 .exit_latency = 10,
459 .target_residency = 20, 502 .target_residency = 20,
460 .enter = &intel_idle }, 503 .enter = &intel_idle,
504 .enter_freeze = intel_idle_freeze, },
461 { 505 {
462 .name = "C3-BDW", 506 .name = "C3-BDW",
463 .desc = "MWAIT 0x10", 507 .desc = "MWAIT 0x10",
464 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED, 508 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
465 .exit_latency = 40, 509 .exit_latency = 40,
466 .target_residency = 100, 510 .target_residency = 100,
467 .enter = &intel_idle }, 511 .enter = &intel_idle,
512 .enter_freeze = intel_idle_freeze, },
468 { 513 {
469 .name = "C6-BDW", 514 .name = "C6-BDW",
470 .desc = "MWAIT 0x20", 515 .desc = "MWAIT 0x20",
471 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED, 516 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
472 .exit_latency = 133, 517 .exit_latency = 133,
473 .target_residency = 400, 518 .target_residency = 400,
474 .enter = &intel_idle }, 519 .enter = &intel_idle,
520 .enter_freeze = intel_idle_freeze, },
475 { 521 {
476 .name = "C7s-BDW", 522 .name = "C7s-BDW",
477 .desc = "MWAIT 0x32", 523 .desc = "MWAIT 0x32",
478 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED, 524 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
479 .exit_latency = 166, 525 .exit_latency = 166,
480 .target_residency = 500, 526 .target_residency = 500,
481 .enter = &intel_idle }, 527 .enter = &intel_idle,
528 .enter_freeze = intel_idle_freeze, },
482 { 529 {
483 .name = "C8-BDW", 530 .name = "C8-BDW",
484 .desc = "MWAIT 0x40", 531 .desc = "MWAIT 0x40",
485 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED, 532 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
486 .exit_latency = 300, 533 .exit_latency = 300,
487 .target_residency = 900, 534 .target_residency = 900,
488 .enter = &intel_idle }, 535 .enter = &intel_idle,
536 .enter_freeze = intel_idle_freeze, },
489 { 537 {
490 .name = "C9-BDW", 538 .name = "C9-BDW",
491 .desc = "MWAIT 0x50", 539 .desc = "MWAIT 0x50",
492 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED, 540 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
493 .exit_latency = 600, 541 .exit_latency = 600,
494 .target_residency = 1800, 542 .target_residency = 1800,
495 .enter = &intel_idle }, 543 .enter = &intel_idle,
544 .enter_freeze = intel_idle_freeze, },
496 { 545 {
497 .name = "C10-BDW", 546 .name = "C10-BDW",
498 .desc = "MWAIT 0x60", 547 .desc = "MWAIT 0x60",
499 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED, 548 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
500 .exit_latency = 2600, 549 .exit_latency = 2600,
501 .target_residency = 7700, 550 .target_residency = 7700,
502 .enter = &intel_idle }, 551 .enter = &intel_idle,
552 .enter_freeze = intel_idle_freeze, },
503 { 553 {
504 .enter = NULL } 554 .enter = NULL }
505}; 555};
@@ -511,28 +561,32 @@ static struct cpuidle_state atom_cstates[] = {
511 .flags = MWAIT2flg(0x00), 561 .flags = MWAIT2flg(0x00),
512 .exit_latency = 10, 562 .exit_latency = 10,
513 .target_residency = 20, 563 .target_residency = 20,
514 .enter = &intel_idle }, 564 .enter = &intel_idle,
565 .enter_freeze = intel_idle_freeze, },
515 { 566 {
516 .name = "C2-ATM", 567 .name = "C2-ATM",
517 .desc = "MWAIT 0x10", 568 .desc = "MWAIT 0x10",
518 .flags = MWAIT2flg(0x10), 569 .flags = MWAIT2flg(0x10),
519 .exit_latency = 20, 570 .exit_latency = 20,
520 .target_residency = 80, 571 .target_residency = 80,
521 .enter = &intel_idle }, 572 .enter = &intel_idle,
573 .enter_freeze = intel_idle_freeze, },
522 { 574 {
523 .name = "C4-ATM", 575 .name = "C4-ATM",
524 .desc = "MWAIT 0x30", 576 .desc = "MWAIT 0x30",
525 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED, 577 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
526 .exit_latency = 100, 578 .exit_latency = 100,
527 .target_residency = 400, 579 .target_residency = 400,
528 .enter = &intel_idle }, 580 .enter = &intel_idle,
581 .enter_freeze = intel_idle_freeze, },
529 { 582 {
530 .name = "C6-ATM", 583 .name = "C6-ATM",
531 .desc = "MWAIT 0x52", 584 .desc = "MWAIT 0x52",
532 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED, 585 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
533 .exit_latency = 140, 586 .exit_latency = 140,
534 .target_residency = 560, 587 .target_residency = 560,
535 .enter = &intel_idle }, 588 .enter = &intel_idle,
589 .enter_freeze = intel_idle_freeze, },
536 { 590 {
537 .enter = NULL } 591 .enter = NULL }
538}; 592};
@@ -543,14 +597,16 @@ static struct cpuidle_state avn_cstates[] = {
543 .flags = MWAIT2flg(0x00), 597 .flags = MWAIT2flg(0x00),
544 .exit_latency = 2, 598 .exit_latency = 2,
545 .target_residency = 2, 599 .target_residency = 2,
546 .enter = &intel_idle }, 600 .enter = &intel_idle,
601 .enter_freeze = intel_idle_freeze, },
547 { 602 {
548 .name = "C6-AVN", 603 .name = "C6-AVN",
549 .desc = "MWAIT 0x51", 604 .desc = "MWAIT 0x51",
550 .flags = MWAIT2flg(0x51) | CPUIDLE_FLAG_TLB_FLUSHED, 605 .flags = MWAIT2flg(0x51) | CPUIDLE_FLAG_TLB_FLUSHED,
551 .exit_latency = 15, 606 .exit_latency = 15,
552 .target_residency = 45, 607 .target_residency = 45,
553 .enter = &intel_idle }, 608 .enter = &intel_idle,
609 .enter_freeze = intel_idle_freeze, },
554 { 610 {
555 .enter = NULL } 611 .enter = NULL }
556}; 612};
@@ -592,6 +648,21 @@ static int intel_idle(struct cpuidle_device *dev,
592 return index; 648 return index;
593} 649}
594 650
651/**
652 * intel_idle_freeze - simplified "enter" callback routine for suspend-to-idle
653 * @dev: cpuidle_device
654 * @drv: cpuidle driver
655 * @index: state index
656 */
657static void intel_idle_freeze(struct cpuidle_device *dev,
658 struct cpuidle_driver *drv, int index)
659{
660 unsigned long ecx = 1; /* break on interrupt flag */
661 unsigned long eax = flg2MWAIT(drv->states[index].flags);
662
663 mwait_idle_with_hints(eax, ecx);
664}
665
595static void __setup_broadcast_timer(void *arg) 666static void __setup_broadcast_timer(void *arg)
596{ 667{
597 unsigned long reason = (unsigned long)arg; 668 unsigned long reason = (unsigned long)arg;
generated by cgit v1.2.2 (git 2.25.0) at 2026-04-20 15:34:05 -0400